CN102750980B - Phase change memory chip with configuration circuit - Google Patents
Phase change memory chip with configuration circuit Download PDFInfo
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- CN102750980B CN102750980B CN201210254293.7A CN201210254293A CN102750980B CN 102750980 B CN102750980 B CN 102750980B CN 201210254293 A CN201210254293 A CN 201210254293A CN 102750980 B CN102750980 B CN 102750980B
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Abstract
The invention provides a phase change memory chip with a configuration circuit. The phase change memory chip with the configuration circuit at least comprises a memory array, a row decoder unit, a column decoder unit, a column selector unit, a driving circuit unit, a sensitive amplifier unit, an address buffer latching unit, a data buffer latching unit, a logic control unit and a configuration circuit unit. The configuration circuit unit is used for configuration of the driving circuit unit to enable current pulses generated by the driving circuit to effectively write in a memory unit of the chip and to enable better uniformity of high resistance and low resistance of the memory unit. The configuration unit is further used for configuration of the sensitive amplifier unit to enable the sensitive amplifier unit to effectively and quickly read out the memory unit of the chip.
Description
Technical field
The present invention relates to a kind of memory chip, particularly relate to a kind of phase change memory chip with configuration circuit, belong to memory integrated circuit field.
Background technology
Phase-changing memory unit is that the conception that the phase-change thin film proposed based on beginning of the seventies late 1960s can be applied to phase change memory medium is set up, and is the memory device of a kind of low price, stable performance.Phase-changing memory unit can be made in silicon wafer substrate, and its critical material is recordable phase-change thin film, heating electrode material, thermal insulation material and extraction electrode material, and its study hotspot also just launches around device technology.The physical mechanism research of device comprises how reducing device material etc.The ultimate principle of phase-changing memory unit acts on device cell with electric impulse signal, make phase-change material, between amorphous state and polycrystalline state, reversible transition occur, low-resistance when high resistant during by differentiating amorphous state and polycrystalline state realizes the write of information, erasing and read operation.
Phase transition storage, owing to having the at a high speed advantage such as readings, high erasable number of times, non-volatile, component size is little, low in energy consumption, anti-strong motion and radioresistance, is thought the current flash memories of most possible replacement and become future memory main product and become the device of commercial product at first by international semiconductor TIA.
The reading and writing of phase transition storage and wiping operation apply voltage or the current pulse signal of different in width and height exactly on device cell: wipe operation (RESET), be elevated to after more than temperature of fusion when adding the phase-change material temperature in a short and strong pulse enable signal device cell, again through cooling fast thus realizing phase-change material polycrystalline state to amorphous conversion, namely one state is to the conversion of " 0 " state; Write operation (SET), when the long and pulse enable signal phase-change material temperature of medium tenacity of applying one is raised to after under temperature of fusion, on Tc, and keep a period of time to impel nucleus growth, thus realize the conversion of amorphous state to polycrystalline state, namely " 0 " state is to the conversion of one state; Read operation, after adding the very weak pulse signal that a state to phase-change material can not have an impact, reads its state by the resistance value of measuring element unit.
Phase transition storage is as a new technology, Ultrahigh must be clear further, the preparation technology of nanoscale storage unit also needs to solve many key issues, in the commercialization initial period, process deviation in phase transition storage monolithic wafer between the individual performance difference of storage unit and wafer can not be ignored, therefore in the peripheral circuit of phase change memory chip, configuration circuit is added, when chip powers on, configuration circuit will detect storage unit and assess, automatically configuration is optimized to interlock circuits such as driving circuits according to assessment result, chip-scale consistance and high reliability during to realize producing in batches.
Given this, how to design the configuration circuit of phase transition storage, realize storage unit Performance Evaluation accurately, and to improve chip-scale consistance and high reliability be key issue urgently to be resolved hurrily at present.
Summary of the invention
The shortcoming of prior art in view of the above, the object of the present invention is to provide a kind of phase change memory chip with configuration circuit, for solving the consistance of phase change memory chip and the problem of poor reliability in prior art.
For achieving the above object and other relevant objects, the invention provides a kind of phase change memory chip with configuration circuit, at least comprise: storage array, column decode circuitry unit, column decoder unit, column selector unit, address buffer latch units, data buffering latch units and logic control element, described phase change memory chip also comprises further:
Drive circuit unit, its first input end connects the output terminal of described data buffering latch units, for receiving data-signal; Its second input end connects the output terminal of described configuration circuit unit, for receiving configuration signal; Its 3rd input end connects the output terminal of described logic control element, for receive logic control command; Its output terminal connects the input end of described column selector unit, for by the data-signal received according to steering order provide drive current to described storage array by described column selector unit;
Sense amplifier unit, its first input end connects the output terminal of described configuration circuit unit, for receiving configuration signal; Its second input end connects the output terminal of described logic control element, for receive logic control command; Its 3rd input end connects the output terminal of described column selector unit, when read operation for receiving in the described storage array selected by described column selector unit the data-signal needing to read; Its output terminal connects the input end of described data buffering latch units, amplifies its data-signal received when read operation according to logic control instruction, and exports the data-signal after amplifying to data buffering latch units;
Configuration circuit unit, its input end connects described configuration bus, for receiving the configuration signal transmitted from configuration bus; Its first output terminal connects the second input end of described drive circuit unit, for being configured described drive circuit unit according to the configuration signal received, the drive current that described drive circuit unit is produced there is predetermined pulsewidth and arteries and veins high, to the high resistant of its storage unit during the operation of described storage array and low-resistance, there is consistance with the current impulse after this configuration; Its second output terminal connects the first input end of described sense amplifier unit, for setting and regulating this sense amplifier elements reference magnitude of voltage.
Alternatively, described phase change memory chip also has a time-multiplexed bus interface, is used for receiving configuration signal, address signal and data-signal.Described phase change memory chip also has a selection circuit unit, this selection circuit unit is coupled to described bus interface and between described address buffer latch units, described data buffering latch units and described configuration circuit unit, distribute for carrying out selection to the time division multiplex bus signal inputted by bus interface, respectively described configuration signal, address signal and data-signal are sent to described configuration circuit unit, address buffer latch units and data buffering latch units by inner configuration bus, address bus and data bus.
Alternatively, described phase change memory chip has configuration bus interface, address letter bus interface and data bus interface respectively, respectively described configuration signal, address signal and data-signal is sent to described configuration circuit unit, address buffer latch units and data buffering latch units by each this bus interface.Further alternatively, described storage array is made up of the phase-change memory cell of cross one another all row and columns.
As mentioned above, a kind of phase change memory chip with configuration circuit of the present invention, has following beneficial effect:
Configuration circuit module is added in the peripheral circuit of phase change memory chip, when chip powers on, the configuration signal preset is sent to described configuration circuit unit by time division multiplex bus interface by user, this configuration circuit unit is configured described drive circuit unit and sense amplifier unit according to the configuration signal received, the allocation optimum of the high and pulsewidth of arteries and veins is carried out in the current impulse produced described drive circuit unit, to improve stability and the reliability of chip, and set the reference voltage level of described sense amplifier unit, and within the specific limits reference voltage is regulated, make described sense amplifier can carry out quick and correct reading to described storage unit.
Accompanying drawing explanation
Fig. 1 is shown as the phase change memory chip structural representation in the embodiment of the present invention one with configuration circuit.
Fig. 2 is shown as phase change memory chip configuration input timing figure in the present invention.
Fig. 3 is shown as phase change memory chip address input timing figure in the present invention.
Fig. 4 is shown as phase change memory chip data write timing figure in the present invention.
Fig. 5 is shown as phase change memory chip data output timing diagram in the present invention.
Fig. 6 is the phase change memory chip structural representation in the embodiment of the present invention two with configuration circuit.
Element numbers explanation
10 storage arrays
11 line decoder unit
12 column decoder unit
13 column selector unit
14 address buffer latch units
15 data buffering latch units
16 drive circuit units
17 sense amplifier unit
18 configuration circuit unit
19 circuit selection units
20 time division multiplex bus
21 logic control elements
22 address buss
23 configuration bus
24 data buss
A<n:0> time division multiplex bus signal
Embodiment
Below by way of specific instantiation, embodiments of the present invention are described, those skilled in the art the content disclosed by this instructions can understand other advantages of the present invention and effect easily.The present invention can also be implemented or be applied by embodiments different in addition, and the every details in this instructions also can based on different viewpoints and application, carries out various modification or change not deviating under spirit of the present invention.
Refer to Fig. 1 to Fig. 6.It should be noted that, the diagram provided in the present embodiment only illustrates basic conception of the present invention in a schematic way, then only the assembly relevant with the present invention is shown in graphic but not component count, shape and size when implementing according to reality is drawn, it is actual when implementing, and the kenel of each assembly, quantity and ratio can be a kind of change arbitrarily, and its assembly layout kenel also may be more complicated.
Embodiment one
As shown in the figure 1, the invention provides a kind of phase change memory chip with configuration circuit, comprise storage array 10, line decoder unit 11, column decoder unit 12, column selector unit 13, drive circuit unit 16, sense amplifier unit 17, address buffer latch units 14, data buffering latch units 15, logic control element 21, configuration circuit unit 18, selection circuit unit 19 and a time-multiplexed bus interface (not shown, to connect with outside time division multiplex bus 20).
Described storage array 10 to be intersected according to certain row and column by phase-change memory cell and formed, for storing data message; Described line decoder unit 11, be coupled between described storage array 10 and described address buffer latch units 14, and decoding is carried out to the row address line inputted from described address buffer latch units 14, the row of decoding address signal out to storage array 10 is selected, and the unlatching of the wordline (WL) of control store array 10 is with closed; Described column decoder unit 12 is coupled between described column selector unit 13 and described address buffer latch units 14, decoding is carried out to the column address conductor inputted from described address buffer latch units 14, decoding address signal is out selected by the row of described column selector unit 13 to described storage array 10, controls the unlatching of described column selector unit 13 with closed; Described column selector unit 13 is configured to be connected with described drive circuit unit 16 and sense amplifier unit 17 simultaneously, and be used for the unlatching of control store array bitline (BL) with closed, it is made up of transmission gate or single nmos pass transistor.
Described drive circuit unit 16 is coupled between described column selector unit 13 and data buffering latch units 15, and by column selector unit 13 for storage array 10 provides the electric current of certain pulse height and width, the broadband of electric current and adjustable highly within the specific limits, think the drive current that the storage unit of different performance provides different, this drive current can operate thawing or the crystalline state of phase-change memory cell; Described sense amplifier unit 17 is coupled to described memory array 10 and is configured to amplify the data be stored in selected phase-change memory cell when read operation.
Further, described data buffering latch units 15, one input end is cushioned by the data-signal of data bus 24 to input and is latched, data-signal is input in described drive circuit unit 16 by the instruction of steering logic signal by another output terminal, meanwhile, described data buffering latch units 15 is configured to again the output buffer memory after described sense amplifier unit 17 amplified data signal; Described address buffer latch units 14, input end is cushioned by the address signal of address bus 22 to input and is latched, and two output terminals are connected to described line decoder unit 11 and column decoder unit 12 respectively; Described time-multiplexed bus interface is used for receiving configuration signal, address signal and the data-signal that outside time division multiplex bus 20 sends, according to steering order, selection is carried out to the time multiplexing signal that bus interface inputs distribute by described selection circuit unit 19, and respectively described configuration signal, address signal and data-signal are sent to described configuration circuit unit 18, address buffer latch units 14 and data buffering latch units 15 by each this bus; The state such as selection, write, reading of described logic control element 21 to whole phase change memory chip carries out logic control, comprises clock signal (CLK), chip enable signal (/CE), write-enable signal (/WE), reads enable signal (/OE) and address selection enable (/AE).
It should be noted that, the data bus 24 in the present embodiment is bidirectional bus, is used for stored in data-signal in described data buffering latch units 15 when write operation, or when read operation, outputting data signals from described data buffering latch units 15.
In addition, the resistance of phase-change memory cell has dispersion problem, this is the difference of the aspect such as structure and size owing to being caused by the fluctuation of technique between phase-change memory cell, the resistance of different storage unit can be caused different, even there is larger difference, if the dispersiveness of resistance causes the high value of low resistance state to be intersected, to cause storing and lose efficacy, therefore, when making phase change memory chip, first to test the distribution of resistance of storage unit in described storage array 10, can determine according to these test parameters and drive the pulsewidth of the best of the current impulse required for described phase-change memory cell and the high configuration data of arteries and veins, when utilizing the pulse current after configuration to operate described storage array 10, the high resistant of storage unit and low-resistance is made to have consistance, thus improve stability and the reliability of this chip.Configuration circuit unit 18 is introduced thus in the present invention, described configuration circuit unit 18 input end is configuration bus 23, two output terminals connect described drive circuit unit 16 and sense amplifier unit 17 respectively, can by advance according to the configuration data that test parameter provides, by this chip time division multiplex bus interface, and be dispensed to configuration bus 23 via described selection circuit unit 19, via configuration bus 23, configuration data is sent to described configuration circuit unit 18 and described drive circuit unit 16 and sense amplifier unit 17 are configured.Configuration signal is configured described drive circuit unit 16, the pulsewidth of the current impulse that drive circuit unit 16 is produced and arteries and veins is high carries out allocation optimum, to realize effectively writing the storage unit of chip, the high resistant of storage unit and low-resistance is made to have good consistance, the resistance distribution being embodied in high resistant and low-resistance is all more concentrated, and the ratio of high resistant and low-resistance is greater than more than 2 orders of magnitude; Be configured to set and regulate its reference voltage level to described sense amplifier unit 17, thus realize the quick and correct reading of described sense amplifier unit 17 pairs of storage arrays 10.It should be noted that, when chip powers on, configuration signal is sent to described configuration circuit unit 18 by time division multiplex bus interface by user, this configuration circuit unit 18 is configured described drive circuit unit 18 and sense amplifier unit 19 according to the configuration signal received, read and write operation more subsequently, thus ensure the Stability and dependability of chip.
When being configured described phase change memory chip, chip enable signal/CE is low level, when most significant digit A<n> in time division multiplex bus 20 signal A<n:0> is high level, A<n-1:0> is configured port, by time division multiplex bus interface input configuration signal, and by selection circuit unit 19, configuration signal is dispensed to configuration bus 23, then be sent in described configuration circuit unit 18 by configuration bus 23, then by this configuration circuit unit 18, configuration is optimized to this phase change memory chip.Be illustrated in figure 2 phase transition storage configuration input timing figure.
When selecting storage array 10 rank addresses of described phase change memory chip, chip enable signal/CE is low level, most significant digit A<n> in time division multiplex bus 20 signal A<n:0> bus is low level, and address selection enable signal/AE is when being low level, time division multiplex bus 20 signal A<n-1:0> input signal through selection circuit unit 19 be chosen as address signal input, address signal A<n-1:0> enters described address buffer latch units 14 through address bus 22, then row address is isolated, column address, and respectively via after line decoder unit 11 and column decoder unit 12 decoding, decoding row address out selects the row of signal to storage array 10 to select, decoding column address out selects signal to be selected by the row of described column selector unit 13 pairs of storage arrays 10.Be illustrated in figure 3 described phase change memory chip address input timing figure.
When writing data to storage array 10 unit of described phase change memory chip, chip enable signal/CE is low level, most significant digit A<n> in time division multiplex bus 20 signal A<n:0> is low level, address selection enable signal/AE is high level, and write-enable signal/WE is when being low level, the signal that time division multiplex bus 20 signal A<n-1:0> inputs is chosen as data-signal input through selection circuit unit 19.When n be greater than 9 and be less than 16 time, be 8 bit data A<7:0> input, when n is greater than 17, be 16 bit data A<15:0> input.Data-signal A<n-1:0> is sent in described data buffering latch units 15 via internal data bus 24, described drive circuit unit 16 is entered, finally by the storage unit of data-signal stored in storage array 10 rank addresses selected in Fig. 2 after buffering.Be illustrated in figure 4 the sequential chart to the storage array write data in described phase change memory chip.
When to the storage array 10 unit sense data of described phase change memory chip, chip enable signal/CE is low level, most significant digit A<n> in time division multiplex bus 20 signal A<n:0> is low level, address selection enable signal/AE is high level, and reading enable signal/OE when being low level, time division multiplex bus 20 signal A<n-1:0> is data output channel.When above-mentioned sequential meets, data-signal in the storage unit of storage array 10 rank addresses selected in Fig. 2 outputs in described data buffering latch units 15 after amplifying via described sense amplifier unit 17, after buffering, by internal bus 24, data-signal is outputted to the bus interface of phase change memory chip, and output to external bus 20 or data terminal by bus interface.Figure 5 shows that the sequential chart writing data in storage array 10 unit of described phase change memory chip.
Embodiment two
As shown in the figure 6, the invention provides the phase change memory chip that another kind has configuration circuit, being distinguished as of the present embodiment and embodiment one: this phase change memory chip has three bus interface, be respectively address bus 22 interface, data bus 24 interface and configuration bus 23 interface, do not need selection circuit unit 19, and in embodiment one, only have time-multiplexed bus 20 interface, need the input signal of selection circuit unit 19 to time division multiplex bus 20 interface and carry out selection distribution.Other structure and timing requirements identical with embodiment one, do not repeating in the present embodiment.
In sum, the present invention proposes a kind of phase change memory chip with configuration circuit, configuration circuit module is added in the peripheral circuit of phase change memory chip, when chip powers on, the configuration signal preset is sent to described configuration circuit unit by time division multiplex bus interface by user, this configuration circuit unit is configured described drive circuit unit and sense amplifier unit according to the configuration signal received, the allocation optimum of the high and pulsewidth of arteries and veins is carried out in the current impulse produced described drive circuit unit, to improve stability and the reliability of chip, and set the reference voltage level of described sense amplifier unit, and within the specific limits reference voltage is regulated, make described sense amplifier can carry out quick and correct reading to described storage unit.So the present invention effectively overcomes various shortcoming of the prior art and tool high industrial utilization.
Above-described embodiment is illustrative principle of the present invention and effect thereof only, but not for limiting the present invention.Any person skilled in the art scholar all without prejudice under spirit of the present invention and category, can modify above-described embodiment or changes.Therefore, such as have in art usually know the knowledgeable do not depart from complete under disclosed spirit and technological thought all equivalence modify or change, must be contained by claim of the present invention.
Claims (5)
1. one kind has the phase change memory chip of configuration circuit, comprise: storage array, column decode circuitry unit, column decoder unit, column selector unit, address buffer latch units, data buffering latch units and logic control element, it is characterized in that, described phase change memory chip also comprises:
Drive circuit unit, its first input end connects the output terminal of described data buffering latch units, for receiving data-signal; Its second input end connects the output terminal of described configuration circuit unit, for receiving configuration signal; Its 3rd input end connects the output terminal of described logic control element, for receive logic control command; Its output terminal connects the input end of described column selector unit, for by the data-signal received according to steering order provide drive current to described storage array by described column selector unit;
Sense amplifier unit, its first input end connects the output terminal of described configuration circuit unit, for receiving configuration signal; Its second input end connects the output terminal of described logic control element, for receive logic control command; Its 3rd input end connects the output terminal of described column selector unit, when read operation for receiving in the described storage array selected by described column selector unit the data-signal needing to read; Its output terminal connects the input end of described data buffering latch units, amplifies its data-signal received when read operation according to logic control instruction, and exports the data-signal after amplifying to data buffering latch units;
Configuration circuit unit, its input end connects configuration bus, for receiving the configuration signal transmitted from configuration bus; Its first output terminal connects the second input end of described drive circuit unit, for being configured described drive circuit unit according to the configuration signal received, the drive current that described drive circuit unit is produced there is predetermined pulsewidth and arteries and veins high, to the high resistant of its storage unit during the operation of described storage array and low-resistance, there is consistance with the current impulse after this configuration; Its second output terminal connects the first input end of described sense amplifier unit, for setting and regulating this sense amplifier elements reference magnitude of voltage.
2. the phase change memory chip with configuration circuit according to claim 1, is characterized in that: described phase change memory chip also has a time-multiplexed bus interface, is used for receiving configuration signal, address signal and data-signal.
3. the phase change memory chip with configuration circuit according to claim 2, it is characterized in that: described phase change memory chip also has a selection circuit unit, this selection circuit unit is coupled to described bus interface and described address buffer latch units, described data buffering latch units, and between described configuration circuit unit, distribute for carrying out selection to the time division multiplex bus signal inputted by bus interface, by inner configuration bus, address bus, and data bus is respectively by described configuration signal, address signal, and data-signal is sent to described configuration circuit unit, address buffer latch units, and data buffering latch units.
4. the phase change memory chip with configuration circuit according to claim 1, it is characterized in that: described phase change memory chip has configuration bus interface, address bus interface and data bus interface respectively, respectively described configuration signal, address signal and data-signal are sent to described configuration circuit unit, address buffer latch units and data buffering latch units by each this bus interface.
5. the phase change memory chip with configuration circuit according to claim 1, is characterized in that: described storage array is made up of the phase-change memory cell of cross one another row and column.
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| CN105632551B (en) * | 2015-12-18 | 2018-09-25 | 中国科学院上海微系统与信息技术研究所 | Storage array, the storage chip of storage object logical relation and method |
| CN106024054A (en) * | 2016-05-24 | 2016-10-12 | 中国科学院上海微系统与信息技术研究所 | Phase change memory with retention test function |
| CN109491596B (en) * | 2018-10-08 | 2020-07-10 | 华中科技大学 | Method for reducing data storage error rate in charge trapping type 3D flash memory |
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| US5651128A (en) * | 1994-07-20 | 1997-07-22 | Sgs-Thomson Microelectronics, S.A. | Programmable integrated circuit memory comprising emulation means |
| CN101034585A (en) * | 2006-03-08 | 2007-09-12 | 天利半导体（深圳）有限公司 | SRAM system circuit without sensitive amplifier |
| CN101281790A (en) * | 2008-02-01 | 2008-10-08 | 中国科学院上海微系统与信息技术研究所 | Method for designing control circuit capable of regulating pulse-width for read-write operation of phase transition internal memory |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5651128A (en) * | 1994-07-20 | 1997-07-22 | Sgs-Thomson Microelectronics, S.A. | Programmable integrated circuit memory comprising emulation means |
| CN101034585A (en) * | 2006-03-08 | 2007-09-12 | 天利半导体（深圳）有限公司 | SRAM system circuit without sensitive amplifier |
| CN101281790A (en) * | 2008-02-01 | 2008-10-08 | 中国科学院上海微系统与信息技术研究所 | Method for designing control circuit capable of regulating pulse-width for read-write operation of phase transition internal memory |
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