CN108665925B - Read-write method and system based on multi-level storage type phase change memory - Google Patents
Read-write method and system based on multi-level storage type phase change memory Download PDFInfo
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/004—Reading or sensing circuits or methods
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/004—Reading or sensing circuits or methods
- G11C2013/0045—Read using current through the cell
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
- G11C2013/0076—Write operation performed depending on read result
Abstract
The invention discloses a read-write method and a read-write system based on a multi-level storage type phase change memory, and belongs to the technical field of read-write control of the phase change memory. The reading and writing method comprises a reading method and a writing method, wherein two phase change storage units with multi-level storage capacity are adopted to form a reading and writing basic unit; expressing the stored 2-bit data based on the relative resistance values of two phase change memory cells thereof; the reading method is used for reading data from the reading and writing basic unit, and the writing method is used for writing data into the reading and writing basic unit. The read-write system comprises a gating circuit, a read driving circuit, a read-write basic unit, a read circuit, a data output circuit, a write operation judging circuit and a write driving circuit. The invention aims to express data by using the relative resistance value of the phase change unit in the read-write basic unit based on the multi-level storage capacity of the phase change memory unit, thereby obviously reducing the execution times of write operation, improving the read-write efficiency and realizing the low-power consumption read-write of the phase change memory under the condition of unchanged data storage density.
Description
Technical Field
The invention belongs to the technical field of read-write control of a phase change memory PCRAM, and particularly relates to a read-write method and a read-write system based on a multi-level storage type phase change memory.
Background
In 1968, Ovshinsky (Stanford Ovshinsky) published a first paper on amorphous phase transformation, which for the first time described a memory based on phase transformation theory: in the process that the material is changed from an amorphous state to a crystal and then is changed back to the amorphous state, the amorphous state and the crystal state of the material present different optical characteristics and resistance characteristics, so that information can be stored by respectively representing '0' and '1' by utilizing the amorphous state and the crystalline state, which is called as an Austenitic electronic effect. Phase change Memory (PCRAM) is an element based on the ovonic electronic effect, and is therefore also called Ovonic Unified Memory (OUM).
PCRAM is typically fabricated using chalcogenide materials, a common chalcogenide being Ge2Sb2Te5Abbreviated as GST. It utilizes reversible physical state change of material to store information, and has the advantages of non-volatility, small process size, high storage density, long cycle life and readingFast writing speed, low power consumption, radiation interference resistance and the like. The international semiconductor industry association has recognized that PCRAM will likely replace current flash memory and will become the mainstream non-volatile memory in the future.
According to the research results of Liubo, Song begonia and the like (CN200410067987.5 can be used as a phase change material for multi-level storage of a phase change memory), the PCRAM has the capacity of multi-level storage. The square resistance of the chalcogenide compound gradually decreases in the process of temperature rise, and two obvious resistance steps appear in the process of temperature rise. These two steps correspond to the transition of the material from the amorphous state to the FCC crystalline state and the transition of the FCC crystalline structure to the HCP crystalline structure, respectively. Thus PCRAMs have three more stable resistance states.
It is now common to read and write to PCRAMs by applying pulsed currents to the memory cells. In which the current for the write operation is large, and a large joule heat is generated in this process. If the write operation occurs frequently, not only is a large power consumption generated, but also the data stability of the adjacent memory cells may be adversely affected due to the serious heat accumulation. Therefore, it is necessary to research a low power consumption read/write method and system for a phase change memory based on multi-level storage to reduce the read/write power consumption of the PCRAM and optimize the performance of the PCRAM.
Disclosure of Invention
The invention provides a read-write method and a read-write system based on a multi-level storage type phase change memory, aiming at forming a read-write basic unit by adopting two phase change memory units with multi-level storage capacity based on the multi-level storage capacity of the phase change memory unit, and expressing stored 2-bit data by using the relative resistance value of the phase change unit in the read-write basic unit, thereby obviously reducing the execution times of write operation and realizing low-power consumption read-write of the phase change memory under the condition of unchanged data storage density.
In order to achieve the above object, according to one aspect of the present invention, there is provided a read/write method based on a multi-level storage type phase change memory, which is characterized in that the read/write method includes a read method and a write method, and the read/write method uses two phase change memory cells with multi-level storage capability to form a read/write basic unit; the read-write basic unit expresses stored 2-bit data based on the relative resistance values of the two phase change storage units to realize a storage function; the relative resistance values of the two phase change memory cells are the difference value of the steady-state resistance values of the two phase change memory cells; the number of the steady-state resistance values of one phase change memory cell is three or more;
the reading method is used for reading data from the reading and writing basic unit, and the writing method is used for writing data into the reading and writing basic unit.
Preferably, the reading method includes the steps of:
D1. gating one phase change storage unit in the read-write basic unit, and reading a state value, namely a first state value;
D2. gating another phase change memory cell in the read-write basic unit, and reading a state value, namely a second state value;
D3. inputting the first state value and the second state value into a data output circuit;
D4. and the data output circuit obtains a state combination according to the first state value and the second state value, and outputs corresponding data according to the state combination, wherein the data output circuit defines the relationship between the state combination and the data according to the relative resistance value.
Further preferably, step D1 is specifically:
the gating circuit receives an external address signal and gates one phase change storage unit in the read-write basic unit; the read driving circuit receives external read enable, generates pulse current and applies read excitation to the gated phase change memory unit; the gated phase change memory cell outputs a read excitation response to the read circuit, and the read circuit reads a state value, namely a first state value, of the gated phase change memory cell;
the step D2 specifically includes:
the gating circuit gates another phase change storage unit in the reading and writing basic unit; the read driving circuit receives external read enable, generates pulse current and applies read excitation to the gated other phase change memory unit; the gated other phase change memory cell outputs a read stimulus response to the read circuit, which reads the state value of the gated other phase change memory cell, i.e., the second state value.
Preferably, the writing method includes the steps of:
x1. reading the first state value of one phase change memory cell in the basic unit by gating;
x2. reading the second state value of another phase-change memory cell in the basic unit by gating;
x3. inputting the first state value, the second state value, the data to be written, and the external write enable to the write operation judgment circuit at the same time;
x4. the write operation judging circuit judges the type of the phase change memory cell and write operation that need to be written, and outputs control signal;
controlling a gating circuit to gate the phase change memory cell needing write operation by the control signal, and controlling a write driving circuit to apply write excitation of a corresponding write operation type to the phase change memory cell;
and X6. the phase change memory cell responds to the write excitation to carry out write operation and write data.
Further preferably, step X1 is specifically:
the gating circuit receives the address signal and gates one phase change storage unit in the read-write basic unit; the read driving circuit receives external read enable, generates pulse current and applies read excitation to the gated phase change memory unit; the gated phase change memory cell outputs a read excitation response to the read circuit, and the read circuit reads a state value, namely a first state value, of the gated phase change memory cell;
step X2 specifically includes:
the gating circuit gates another phase change storage unit in the reading and writing basic unit; the read driving circuit receives external read enable, generates pulse current and applies read excitation to the gated other phase change memory unit; the gated other phase change memory cell outputs a read stimulus response to the read circuit, which reads the state value of the gated other phase change memory cell, i.e., the second state value.
The state value expresses the stable resistance state and the stable resistance value of the phase change memory cell; the relative resistance value refers to the difference value of resistance values of stable resistance states expressed by the state values of the two phase change memory cells.
According to another aspect of the present invention, there is provided a read/write system based on a multilevel storage type phase change memory, comprising a gate circuit, a read drive circuit, a read/write basic unit, a read circuit, a data output circuit, a write operation judgment circuit, and a write drive circuit, wherein,
the gating circuit is used for receiving an external address signal or a first control signal sent by the write operation judging circuit and gating a corresponding phase change storage unit in the read-write basic unit according to the external address signal or the first control signal;
the reading drive circuit is used for receiving reading enable and providing reading excitation required by reading operation to the reading and writing basic unit;
the reading and writing basic unit comprises two phase change memory cells, namely a first phase change memory cell and a second phase change memory cell, wherein the phase change memory cells have multi-level memory capacity and are used for realizing a memory function, receiving a read excitation to provide a read excitation response signal or receiving a write excitation to execute write operation; the phase change memory cell has three or more stable resistance states corresponding to three or more state values;
the reading circuit is used for receiving a reading excitation response signal, amplifying the signal, comparing the signal with a reference value to obtain a first state value of the first phase change memory cell and a second state value of the second phase change memory cell, and outputting the first state value and the second state value; the reference value is a reference voltage value obtained according to the steady-state resistance value of the phase change memory unit; the first state value expresses the stable resistance state and the stable resistance value of the first phase change memory unit, and the second state value expresses the stable resistance state and the stable resistance value of the second phase change memory unit;
the data output circuit defines the relation between data and state combination according to the relative resistance value between the state values of the phase change memory unit, wherein the relative resistance value between the state values refers to the resistance difference value between the state values; the data output circuit is used for inputting the first state value and the second state value, obtaining a state combination according to the two state values, and outputting corresponding data according to the state combination and a defined relation between the data and the state combination;
the write operation judging circuit judges the phase change memory cell needing write operation according to the input data to be written, the first state value, the second state value and the external write enable, and outputs a first control signal to the gating circuit; further judging the type of the write operation required by the phase change memory unit, and outputting a second control signal to the write driving circuit;
the first control signal is used for controlling the gating circuit to gate the phase change memory unit needing write operation, and the second control signal is used for controlling the write driving circuit to generate write excitation;
and the writing driving circuit inputs the second control signal and outputs writing excitation to the phase change storage unit controlled and gated by the first control signal.
Preferably, the phase change memory material adopted by the phase change memory unit is a material with three or more stable resistance states.
Preferably, the write driver circuit generates a write stimulus that causes the phase change memory cell to switch between states.
Preferably, the read circuit includes a sense amplifier and a comparison circuit, the sense amplifier is configured to amplify the read stimulus response signal, and the comparison circuit is configured to compare the amplified signal with a reference value to obtain a state value of the phase change memory cell.
The reading and writing method and the system use a reading and writing basic unit formed by two phase change memory units with multi-level memory capacity as a minimum unit for implementing the reading and writing method, and realize the memory function based on the 2-bit data expressed by the relative resistance values of the two phase change memory units in the reading and writing basic unit.
In general, compared with the prior art, the above technical solution contemplated by the present invention can achieve the following beneficial effects:
1. based on the multilevel storage capacity of the phase change memory unit, two phase change memory units with the multilevel storage capacity are adopted to form a read-write basic unit, and the relative resistance value of the phase change unit in the read-write basic unit is used for expressing stored 2-bit data, so that the execution times of write operation are obviously reduced, the read-write efficiency is improved, and the low-power-consumption read-write of the phase change memory PCRAM is realized under the condition that the data storage density is unchanged;
2. the power consumption generated by frequent writing operation of the PCRAM is reduced, and the negative effect on the memory cell caused by the power consumption is weakened.
Drawings
FIG. 1 is a block diagram of a read/write system according to a preferred embodiment of the present invention;
FIG. 2 is a diagram illustrating the steps of a read method in the read/write method according to the preferred embodiment of the present invention;
FIG. 3 is a block diagram illustrating the connection of the reading method according to the preferred embodiment of the present invention;
FIG. 4 is a schematic diagram of a read circuit according to a preferred embodiment of the present invention;
FIG. 5 is a diagram illustrating the steps of a write method in the read/write method according to the preferred embodiment of the present invention;
FIG. 6 is a block diagram illustrating the connection of the write method according to the preferred embodiment of the present invention;
FIG. 7 is a diagram illustrating the steps performed by the write operation determination circuit in accordance with the preferred embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. In addition, the technical features involved in the embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
The invention discloses a low-power-consumption reading and writing method and a low-power-consumption reading and writing system of a phase change memory based on multi-level storage, and aims to reduce the power consumption of the phase change memory and weaken the negative influence caused by overhigh power consumption of writing operation of the phase change memory.
The following describes details of the present invention in detail, taking a phase change memory cell with three-level storage capability as an example, and taking two phase change memory cells with multi-level storage capability as a basic unit for reading and writing implemented by the method. The three stable resistance values of the phase change memory cell with three-level storage capability are respectively referred to as a state a, a state b and a state c, wherein the resistance value of the state a is the lowest, and the resistance value of the state c is the highest after the state b, which will not be described in detail hereinafter.
The invention provides an embodiment of a read-write system based on a multilevel storage type phase change memory.
Fig. 1 is a schematic structural diagram of a read/write system. Comprises a gate circuit 101, a read drive circuit 102, a read-write basic unit 103, a read circuit 108, a data output circuit 109, a write operation judgment circuit 110, and a write drive circuit 111, wherein,
the gating circuit 101 is configured to receive an external address signal or receive the control signal 1 sent by the write operation determining circuit 110, and gate the corresponding phase change memory cell a (104) or B (105) in the read/write basic unit 103 according to the external address signal or the control signal 1.
The read drive circuit 102 is configured to receive an external read enable and provide a read stimulus required to perform a read operation to the read/write basic unit 103.
The read-write basic unit 103 comprises two phase change memory cells, namely a phase change memory cell A (104) and a phase change memory cell B (105), wherein the phase change memory cells have multi-level memory capacity and are used for realizing a memory function, receiving a read stimulus to provide a read stimulus response signal or receiving a write stimulus to execute a write operation; the phase change memory cell has three or more steady state resistance values corresponding to three or more state values.
The read circuit 108 is configured to receive the read stimulus response signal, amplify the signal, obtain a state value 1 of the phase change memory cell a (104) and a state value 2 of the phase change memory cell B (105) by comparing the amplified signals with a reference value, and output the two state values; the reference value is a reference resistance value obtained according to the state value of the phase change memory cell; the state value 1 expresses the stable resistance state and the stable resistance value of the phase change memory cell a (104), and the state value 2 expresses the stable resistance state and the stable resistance value of the phase change memory cell B (105).
The read circuit 108 includes a sense amplifier 106 and a comparison circuit 107, the sense amplifier 106 is used for amplifying the read stimulus response signal, and the comparison circuit 107 is used for comparing the amplified signal with a reference value to obtain a state value of the phase change memory cell.
The write operation judging circuit 110 judges a phase change memory cell to be written according to input data to be written, the state value 1, the state value 2 and external write enable, and outputs a control signal 1 to the gating circuit 101; and further determines the type of write operation to be performed on the phase change memory cell, and outputs a control signal 2 to the write driving circuit 111.
The control signal 1 is used for controlling the gating circuit 101 to gate the phase change memory cell to be written, and the control signal 2 is used for controlling the write driving circuit 111 to generate write excitation.
The write driving circuit 111 inputs the control signal 2 and outputs write stimuli to the phase change memory cell whose gate is controlled by the control signal 1.
The invention also provides an embodiment of a read-write method based on the multilevel storage type phase change memory, and further elaborates the implementation mode of the read-write system by combining the read-write method.
Referring to fig. 2 to fig. 3, schematic diagrams of steps of a reading method of a phase change memory and a module connection diagram implemented by the reading method provided by the present invention are shown, where the reading method includes the following steps:
201: after receiving an external address signal, the gating circuit gates the phase change memory cell A303 in the read-write basic unit 302, the read driving circuit 301 receives external read enable, generates pulse current, applies read excitation to the pulse current, and reads the state value of the cell A through the read circuit 305;
202: after receiving the address signal, the gating circuit gates the phase change memory cell B304 in the read-write basic unit 302, the read driving circuit 301 receives external read enable, generates a pulse current, applies read excitation to the pulse current, and reads the state value of the cell B through the read circuit 305;
203: the state values of the cells a and B are input to the data output circuit 308;
204: the data output circuit 308 obtains a state combination according to the state values of the cells a and B, and outputs corresponding data according to the state combination. Wherein the data output circuit defines a relationship between data and combinations of states based on a relative resistance between state values of the phase change memory cell.
Wherein the reading circuit 305 includes two parts, a sense amplifier 306 and a comparison circuit 307.
Fig. 4 is a schematic diagram of a read circuit. And after the read excitation is applied to the phase change memory unit, generating a read excitation response, inputting the read excitation response into a read circuit, and comparing and outputting the state value of the phase change memory unit through a sensitive amplifier and a comparison circuit. The key of the reading circuit is that two reference values are used for comparing and outputting the states: vref1, Vref 2. In this embodiment, a current read stimulus is used, and the read stimulus response is a voltage value. Different voltage values are generated when the phase change memory cell passes through the phase change memory cells with different resistance values, and the phase change memory cell with the higher resistance value generates the higher voltage value, so that the read stimulus response voltage value of the state a is the lowest, and the read stimulus response voltage value of the state c is the highest after the state b. Vref1 is taken in the middle of the interval of the read stimulus response voltage values of state a and state b, and Vref2 is taken in the middle of the interval of the read stimulus response voltage values of state b and state c.
When the phase change memory cell is in a state a, a read stimulus response is amplified through SA (401-1) and compared with Vref1 to output a low level, a read stimulus response is amplified through SA (401-2) and compared with Vref2 to output a low level, and after combinational logic, a signal (402) outputs a high level to indicate that the state value of the read phase change memory cell is in the state a; when the phase change memory cell is in the state b, the read excitation response is amplified through SA (401-1) and compared with Vref1 to output high level, amplified through SA (401-2) and compared with Vref2 to output low level, and after the combination logic, a signal (403) outputs high level to indicate that the state value of the read phase change memory cell is in the state b; when the phase change memory cell is in the state c, the read stimulus response is amplified by SA (401-1) and compared with Vref1 to output high level, amplified by SA (401-2) and compared with Vref2 to output high level, and after combinational logic, the signal (404) outputs high level to indicate that the state value of the read phase change memory cell is in the state c.
The key in the module connection diagram realized by the reading method is a data output circuit. The data output circuit defines a relationship between the data and the state combinations according to a relative resistance value between state values of the phase change memory cell, wherein the relative resistance value between the state values refers to a resistance difference between the state values.
The low-power-consumption reading and writing method of the phase change memory is characterized in that the relative resistance value of the phase change unit in the reading and writing basic unit is used for expressing data. When the same data is expressed, the number of times of execution of the write operation can be reduced, and the power consumption can be reduced.
In the embodiment, the resistance of the phase change memory cell material in the state a is two orders of magnitude different from that in the state B, and the resistance of the state B is four orders of magnitude different from that in the state c, and the 'approximate resistance of the phase change memory cell A and the phase change memory cell B' is defined as data '00'; the resistance value of the phase change memory cell A is two to four orders of magnitude higher than that of the phase change memory cell B, and the resistance value is data '01'; the ' data ' 10 ' represents that the resistance value of the phase change memory cell B is two to four orders of magnitude higher than that of the phase change memory cell A; the difference between the resistance values of the phase change memory cell a and the phase change memory cell B is about six orders of magnitude, which is data '11'.
The relationship between the data and the state combinations in the data output circuit in this embodiment is as follows:
the state combinations aa, bb, cc corresponding to data '00';
the state combination cb and ba corresponding to the data '01';
the state combination bc, ab corresponding to the data '10';
the state combinations ca, ac corresponding to the data '11'.
And inputting the state values of the two phase change storage units in the read-write basic unit into a data output circuit, obtaining state combination by the data output circuit according to the state values of the two phase change storage units, and outputting corresponding data according to the state combination. For example, inputting the state value a of the phase change memory cell a and the state value B of the phase change memory cell B, the data output circuit obtains the state combination ab and outputs the data '10'.
Referring to fig. 5 to 6, schematic diagrams of steps of a writing method of a phase change memory and a module connection diagram implemented by the writing method provided by the present invention are shown, where the writing method includes the following steps:
501: after receiving the address signal, the gating circuit gates and reads the phase change memory cell A (603) in the basic unit 602, the read driving circuit 601 receives external read enable, generates pulse current, applies read excitation to the pulse current, and reads the state value of the cell A through the read circuit 605;
502: the gating circuit gates the phase change memory cell B (604) in the read-write basic unit 602, the read driving circuit 601 receives external read enable, generates pulse current, applies read excitation to the pulse current, and reads the state value of the cell B through the read circuit 605;
503: the state values of the phase change memory cell a and the phase change memory cell B, the data to be written, and the external write enable are simultaneously input to the write operation determination circuit 608;
504: the write operation determining circuit 608 compares the state values of the phase change memory cell a and the phase change memory cell B with the data to be written, determines the type of the phase change memory cell and the write operation that need to be performed, and outputs a control signal;
505: the control signal controls the gating of the phase change memory cell needing write operation and controls the write driving circuit 609 to apply write excitation of a corresponding write operation type to the phase change memory cell;
506: and responding to the write excitation by the phase change memory unit, performing write operation, and writing data.
The read driving circuit 601, the read/write basic unit 602, and the read circuit 605 in fig. 6 have the same structures as the read driving circuit 301, the read/write basic unit 302, and the read circuit 305 in fig. 3, as can be seen from fig. 1.
The key in the module connection diagram realized by the writing method is a writing operation judgment circuit. After the state values of the phase change memory cell A and the phase change memory cell B in the read-write basic unit and the data to be written are input into the write operation judgment circuit, the write operation judgment circuit starts to judge the write operation.
Referring to fig. 7, a step diagram of the write operation determining circuit is shown. The execution step of the write operation judgment circuit includes:
701: inputting state values, data to be written and write enable of two phase change memory cells in a read-write basic unit;
702: comparing the possible state combination condition of the data to be written, and judging the phase change storage unit needing to be written according to the state values of the two phase change storage units in the basic reading and writing unit;
703: comparing the state value with the state value to be written, and further judging the type of the write operation required by the corresponding unit according to the state value of the phase change memory unit required to be written;
704: and outputting a control signal 1 and a control signal 2, wherein the control signal 1 is input into a gating circuit, the gating circuit gates the phase change storage unit which is judged in the step 702 and needs to be subjected to the write operation, the control signal 2 is input into a write driving circuit, and the write driving circuit outputs corresponding write excitation to the gated phase change storage unit.
Tables 1 to 4 show the specific judgment of the write operation judgment circuit in the present embodiment for four cases of writing data '00' ', 01' ', 10' ', 11'.
TABLE 1 determination of write operations when writing 00 data
TABLE 2 write operation determination when 01 data is written
TABLE 3 write operation determination when writing 10 data
TABLE 4 write operation determination when writing 11 data
The types of write operations are classified into 6 types: 1 represents the transition of the memory cell from state a to state b; 2 denotes the transition of the memory cell from state a to state c; 3 denotes the transition of the memory cell from state b to state a; 4 denotes the transition of the memory cell from state b to state c; 5 represents the transition of the memory cell from state c to state a; and 6 denotes the transition of the memory cell from state c to state b.
For some cell state combinations, there may be multiple operation methods when performing operation determination according to the write method, and in this case, one operation method may be selected as a fixed operation in order to balance the wear of each phase change memory cell. Example (c): when 01 data is written, for the case that the combination of cell states is ca, there can be two operation methods, one is to operate a, the other is to operate B, in this embodiment, it is fixed that a is operated in this case; for the case where the cell state combination is bb, there may also be two operation methods, and for the sake of balance, the operation of B is fixed in this case in the present embodiment.
Corresponding write operation is performed according to the control signal output by the write operation judging circuit, and as can be seen from tables 1 to 4, the probability that both the two phase change memory cells need to be operated is obviously reduced, and in most cases, two bits of storage data can be successfully written into the two phase change memory cells without performing operation or only performing write operation on one of the two phase change memory cells, so that the average number of write operations is reduced, and the power consumption is reduced.
The invention aims to reduce power consumption generated by frequent write operation based on the multilevel storage capacity of a phase change memory unit and realize a low-power-consumption read-write method of a phase change memory PCRAM. The invention uses the read-write basic unit formed by two phase change memory cells with multi-level memory capacity as the minimum unit for implementing the method. The stored 2-bit data is expressed based on the relative resistance values of the two phase change memory cells in the read-write basic unit, so that the memory function is realized. Compared with the scheme that the conventional memory expresses 2-bit data by the absolute resistance value of the two-bit memory cell, the invention reduces write operation based on the multilevel storage capacity of the phase change memory cell under the condition of unchanged data storage density, improves read-write efficiency and effectively solves the problem of larger power consumption of the PCRAM.
It will be understood by those skilled in the art that the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the invention, and that any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (7)
1. A read-write method based on a multilevel storage type phase change memory is characterized by comprising a read method and a write method, wherein the read-write method adopts two phase change memory units with multilevel storage capacity to form a read-write basic unit; the read-write basic unit expresses stored 2-bit data based on the relative resistance values of the two phase change storage units to realize a storage function; the relative resistance values of the two phase change memory cells are the difference value of the steady-state resistance values of the two phase change memory cells; the number of the steady-state resistance values of one phase change memory cell is three or more;
the reading method is used for reading data from the reading and writing basic unit, and the writing method is used for writing data into the reading and writing basic unit;
the reading method comprises the following steps:
D1. gating one phase change storage unit in the read-write basic unit, and reading a state value, namely a first state value;
D2. gating another phase change memory cell in the read-write basic unit, and reading a state value, namely a second state value;
D3. inputting the first state value and the second state value into a data output circuit;
D4. the data output circuit obtains a state combination according to the first state value and the second state value, and outputs corresponding data according to the state combination, wherein the data output circuit defines the relationship between the state combination and the data according to the relative resistance value;
the writing method comprises the following steps:
x1. reading the first state value of one phase change memory cell in the basic unit by gating;
x2. reading the second state value of another phase-change memory cell in the basic unit by gating;
x3. inputting the first state value, the second state value, the data to be written, and the external write enable to the write operation judgment circuit at the same time;
x4. the write operation judging circuit judges the type of the phase change memory cell and write operation that need to be written, and outputs control signal;
controlling a gating circuit to gate the phase change memory cell needing write operation by the control signal, and controlling a write driving circuit to apply write excitation of a corresponding write operation type to the phase change memory cell;
and X6. the phase change memory cell responds to the write excitation to carry out write operation and write data.
2. The method according to claim 1, wherein step D1 is specifically:
the gating circuit receives an external address signal and gates one phase change storage unit in the read-write basic unit; the read driving circuit receives external read enable, generates pulse current and applies read excitation to the gated phase change memory unit; the gated phase change memory cell outputs a read excitation response to the read circuit, and the read circuit reads a state value, namely a first state value, of the gated phase change memory cell;
the step D2 specifically includes:
the gating circuit gates another phase change storage unit in the reading and writing basic unit; the read driving circuit receives external read enable, generates pulse current and applies read excitation to the gated other phase change memory unit; the gated other phase change memory cell outputs a read stimulus response to the read circuit, which reads the state value of the gated other phase change memory cell, i.e., the second state value.
3. The method according to claim 1, wherein step X1 is specifically:
the gating circuit receives the address signal and gates one phase change storage unit in the read-write basic unit; the read driving circuit receives external read enable, generates pulse current and applies read excitation to the gated phase change memory unit; the gated phase change memory cell outputs a read excitation response to the read circuit, and the read circuit reads a state value, namely a first state value, of the gated phase change memory cell;
step X2 specifically includes:
the gating circuit gates another phase change storage unit in the reading and writing basic unit; the read driving circuit receives external read enable, generates pulse current and applies read excitation to the gated other phase change memory unit; the gated other phase change memory cell outputs a read stimulus response to the read circuit, which reads the state value of the gated other phase change memory cell, i.e., the second state value.
4. A read-write system based on a multi-level storage type phase change memory is characterized by comprising a gating circuit, a read driving circuit, a read-write basic unit, a read circuit, a data output circuit, a write operation judging circuit and a write driving circuit, wherein,
the gating circuit is used for receiving an external address signal or a first control signal sent by the write operation judging circuit and gating a corresponding phase change storage unit in the read-write basic unit according to the external address signal or the first control signal;
the reading drive circuit is used for receiving reading enable and providing reading excitation required by reading operation to the reading and writing basic unit;
the reading and writing basic unit comprises two phase change memory cells, namely a first phase change memory cell and a second phase change memory cell, wherein the phase change memory cells have multi-level memory capacity and are used for realizing a memory function, receiving a read excitation to provide a read excitation response signal or receiving a write excitation to execute write operation; the phase change memory cell has three or more stable resistance states corresponding to three or more state values;
the reading circuit is used for receiving a reading excitation response signal, amplifying the signal, comparing the signal with a reference value to obtain a first state value of the first phase change memory cell and a second state value of the second phase change memory cell, and outputting the first state value and the second state value; the reference value is a reference voltage value obtained according to the steady-state resistance value of the phase change memory unit; the first state value expresses the stable resistance state and the stable resistance value of the first phase change memory unit, and the second state value expresses the stable resistance state and the stable resistance value of the second phase change memory unit;
the data output circuit defines the relation between data and state combination according to the relative resistance value between the state values of the phase change memory unit, wherein the relative resistance value between the state values refers to the resistance difference value between the state values; the data output circuit is used for inputting the first state value and the second state value, obtaining a state combination according to the two state values, and outputting corresponding data according to the state combination and a defined relation between the data and the state combination;
the write operation judging circuit judges the phase change memory cell needing write operation according to the input data to be written, the first state value, the second state value and the external write enable, and outputs a first control signal to the gating circuit; further judging the type of the write operation required by the phase change memory unit, and outputting a second control signal to the write driving circuit;
the first control signal is used for controlling the gating circuit to gate the phase change memory unit needing write operation, and the second control signal is used for controlling the write driving circuit to generate write excitation;
and the writing driving circuit inputs the second control signal and outputs writing excitation to the phase change storage unit controlled and gated by the first control signal.
5. The multi-level phase change memory-based read-write system of claim 4, wherein the phase change memory cell is made of a phase change memory material having three or more stable resistance states.
6. A multi-level storage type phase change memory based read-write system according to claim 4 or 5, wherein the write drive circuit generates a write stimulus to cause the phase change memory cell to switch between states.
7. The multi-level storage type phase change memory-based read-write system of claim 4, wherein the read circuit comprises a sense amplifier and a comparison circuit, the sense amplifier is used for amplifying the read stimulus response signal, and the comparison circuit is used for comparing the amplified signal with a reference value to obtain the state value of the phase change memory cell.
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