CN102890962B - System and method for multilevel storage of phase change memory - Google Patents
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Abstract
The invention relates to a system and a method for multilevel storage of a phase change memory. The system comprises a phase change memory array (510) composed of multiple phase change memory cells (511, 512), a row decoder (520) connected to the phase change memory array (510), a column decoder (530), a writing drive circuit (750) and a reading functional circuit (720). The row decoder (520) and the column decoder (530) are used for selecting the phase change memory cell. A control signal (770) controls the writing drive circuit (750) to write corresponding data in the corresponding phase change memory cell. The reading functional circuit (720) transmits a read result into an I/O interface (760) by the control signal (770) after discrimination. The system and the method solve the problem that multilevel storage of a phase change memory has unstability, and satisfy high density and reliability requirements of a phase change memory.
Description
Technical field
The present invention relates to micro-nano art of electronics, particularly a kind of phase transition storage multilevel memory system and method.
Background technology
Phase transition storage (Phase Change Memory) is as the nonvolatile memory of a new generation, at late 1960s (Phys.Rev.Lett. based on Ovshinsky, 21,1450 ~ 1453,1968) beginning of the seventies (Appl.Phys.Lett., 18,254 ~ 257,1971) phase-change thin film proposed can be applied to that the conception of phase change memory medium sets up.Existing storer in facing memory market, the advantage of phase transition storage is that its read or write speed is fast, and height can write wiping number of times, non-volatile, low in energy consumption, and storage density is high, and component size is little, radioresistance, and cost is low and get well with CMOS technology compatibility.Be acknowledged as the main product most possibly becoming future memory.
Phase transition storage depends on the phase-change material of such as chalcogenide compound etc., and the material of this class stably reversibly can change between crystalline phase and amorphous phase, and Typical Representative material is wherein Ge
2sb
2te
5(GST).Two kinds of crystalline phases present different resistances, and namely crystalline state (Set state) shows as low resistance state, the logical value of corresponding stored unit ' 0 ', and amorphous state (Reset state) shows as high-impedance state, the logical value of corresponding stored unit ' 1 '.
Fig. 1 shows the temperature of Set process and Reset process operation process phase-change material over time.When carrying out Set operation, applying the less voltage of a wider width amplitude or current impulse, making the temperature of phase-change material between Tc and temperature of fusion, in order to ensure the generation of crystalline polamer, the width (t of pulse signal
2) the crystallization sensitive time (induction timefor crystallization) must be greater than.When carrying out Reset operation, in order to ensure the formation of non crystalline structure, the fall time of pulse must be less than the crystallization sensitive time.As mentioned above, the Set operation of phase-change material and Reset operate pulse signals different requirements, finally obtains the larger resistance difference between amorphous state and crystalline state.
The storage unit typical structure of phase transition storage is a phase change material unit and a transistor composition, also substitutes transistor by employing diode or triode and forms phase-change memory cell.As shown above, a storage unit can store 2 bits information i.e. ' 0 ' and ' 1 ', but in recent years, a main development direction of phase transition storage is exactly dynamic data attemper.Dynamic data attemper is not reducing on the basis storing area, cellar area stores as far as possible many quantity of information, the information of a phase-change memory cell storage can be 4 bits, 8 bits or more, 4 can be programmed to exactly accordingly, 8 or more states between complete crystalline state and amorphous state to the requirement of phase-change memory cell.When phase-change memory cell is in complete crystalline state, the representative value of its resistance is ~ 1-10K Ω, and during complete amorphous state, the representative value of its resistance is more than 1M Ω.With 4bits dynamic data attemper for row, storage unit can operate ~ 1-10K Ω, ~ 10-100K Ω, ~ 100-1M Ω by respectively, the resistance different with ~ more than 1M 4.When carrying out read operation again, can obtain 4 different readouts, like this, we just achieve the dynamic data attemper of 4 bits of single phase-change memory cell.
Although dynamic data attemper improves the high-density city of phase transition storage greatly, but dynamic data attemper is also faced with a series of challenge, one of them challenge is exactly change along with the time, and the phase-change memory cell resistance that can change drifts about (ResistanceDrift).According to " the Low-Field Amorphous State Resistance and Threshold Voltage Driftin Chalcogenide Materials of the people such as Pirovano, " IEEE Transaction on Electron Devices, Vol.51, No.5, May 2004, description in literary composition in pp714-719, namely resistance drift situation thereupon the resistance of phase-change material become large and become serious, the resistance drift situation being in the unit of Set state is negligible, therefore when phase transition storage only adopts 2 bits storage modes, the resistance drift of Set state is negligible, the resistance drift of Reset state makes Reset resistance become larger and larger, the resistance difference between Reset state and Set state is made to become large like this, add the readability of resistance.But when phase transition storage adopts dynamic data attemper, resistance drift situation can make the resistance of intermediate state overlapping with the discriminant value originally set, and causes read error.For such problem, we can from phase-change material, and the aspect such as device architecture and programmed method is eliminated resistance and to be drifted about the negative influence brought to dynamic data attemper.
Summary of the invention
The technical problem to be solved in the present invention is to provide
In order to solve the problems of the technologies described above, the present invention adopts following technical method: a kind of phase transition storage multilevel memory system, and this system comprises the phase change memory array (510) be made up of several phase-change memory cells (511,512), the line decoder (520) be connected with described phase change memory array, column decoder (530), writes driving circuit (730) and read out function circuit (720); Described ranks code translator (520,530) is for choosing described phase-change memory cell; Then control to write driving circuit (750) by control signal (770) and on affiliated phase-change memory cell, write corresponding data by control signal (770); Reading result is being passed in I/O mouth (760) after discriminating step by control signal (770) by described read out function circuit (720).
Preferably, described read out function circuit (720) comprises the sense amplifier (610) gathering the signal that described phase-change memory cell transmits, the discriminant value generation module (620) be connected with described sense amplifier output terminal and another sense amplifier (630) be connected with discriminant value generation module output terminal.
Preferably, the phase-change storage material in described phase-change memory cell is chalcogenide compound alloy; The non-metal-oxide-semiconductor of its gate tube, bipolar transistor or diode.
The present invention also comprises a kind of phase transition storage dynamic data attemper method, and the read-write operation forming two phase-change memory cells (511,512) of a unit carries out simultaneously.
Preferably, the method comprises the following steps:
Write: choose phase-change memory cell by ranks code translator, then control to write driving circuit by control signal on phase-change memory cell, write corresponding data, choose another phase-change memory cell of same unit again with column decoder, same control to write driving circuit by control signal write corresponding data on another phase-change memory cell described; Described control signal is the signal exported after carrying out rational combinations of states to two phase-change memory cells;
Read: choose two phase-change memory cells by ranks code translator simultaneously, then read out function circuit is controlled by control signal, output in read out function circuit generating condition discrimination value after discriminant value generation module, finally output results in I/O mouth by read out function circuit;
Preferably, in described read operation, the generation method formula of condition discrimination value is as follows:
Vref2′＝V2+ΔV1
Vref3′＝Vref3+α*(V2+ΔV1)
Wherein, Δ V1 is a constant, and α is a constant, and is less than 1.
The present invention is writing in driving circuit, write the many-valued state of driving circuit reasonable combination phase-change memory cell, utilize read out function circuit to complete the algorithm circuit of the discriminant value being generated the many-valued state of phase change cells by the resistance of phase change cells, more accurately read the many-valued state of phase change cells in conjunction with sense amplifier (SA).
The phase transition storage dynamic data attemper method that the present invention proposes, its read out function circuit is one step completed is the read operation of two phase-change memory cells of a formation unit.
The phase transition storage dynamic data attemper method that the present invention proposes, the many-valued state that may write of its phase-change memory cell presets, and the value of setting is combined with follow-up discriminant value generating algorithm circuit.
The phase transition storage dynamic data attemper method that the present invention proposes, first its follow-up read out function circuit directly differentiates some many-valued states of reading according to complete crystalline state resistance drift is negligible, as for other many-valued state again by algorithm circuit evolving discriminant value, the correct decision finally realizing all many-valued states reads
The phase transition storage dynamic data attemper method that the present invention proposes, the key of its discriminant value generating algorithm circuit is the some particular states reading wherein phase-change memory cell from the many-valued state that cannot directly differentiate, using this state as with reference to state, then carry out a series of computing by this reference state and obtain discriminant value.
Accompanying drawing explanation
Fig. 1 is the time dependent curve of temperature of existing phase-change material;
Fig. 2 is phase-change storage material 4 state distribution of resistance curve;
Fig. 3 is the resistance drift situation of phase-change storage material 4 state distribution of resistance curve;
Fig. 4 is a solution of the resistance drift situation of phase-change storage material 4 state distribution of resistance curve;
Fig. 5 is the ranks code translator that the memory array structure that adopts in the present invention and array are corresponding;
Fig. 6 is the read out function circuit adopted in the present invention;
Fig. 7 is the concrete structure of a memory of the present invention.
Embodiment
Be described in further detail below in conjunction with the enforcement of accompanying drawing to technical method:
The present invention relates to a kind of New-type phase change memory multi-stage storage means.Object is that eliminating resistance drifts about the negative influence brought to dynamic data attemper, improves the reliability of dynamic data attemper.
Below with 4 state storage modes for row, elaborate detailed content of the present invention.As shown in Figure 2: the complete crystalline state of the corresponding phase-change material of distribution of resistance curve 20, the partiallycrystalline states of the corresponding phase-change material of distribution of resistance curve 21, the part amorphous state of the corresponding phase-change material of distribution of resistance curve 22, the complete amorphous state of the corresponding phase-change material of distribution of resistance curve 23, use 1 respectively, 2,3 and 4 mark above-mentioned 4 states.30,31 and 32 is the resistance separatrix of state 1,2,3 and 4 respectively.Namely, when the resistance of storage unit is less than 30, its state is just 1, when the resistance of storage unit is greater than 30 and is less than 31, its state is just 2, and when the resistance of storage unit is greater than 31 and is less than 32, its state is just 3, when the resistance of storage unit is greater than 32, its state is just 4.According to the introduction of background knowledge, intermediateness 2 can be learnt, 3 and be in the impact that complete amorphous state 4 is easier to be subject to resistance drift phenomenon.
As shown in Figure 3, the resistance drift phenomenon of 4 states can be seen.Over time, the distribution of resistance curve of each state changes, and distribution curve 20,21,22 and 23 is at first respectively by 20 ', and 21 ', 22 ' and 23 ' substitutes.Resistance is drifted about along with the change of the resistance of each state becomes large greatly.State 1 does not almost have resistance to drift about, and situation about misreading can not appear in resistance separatrix 30 and state 1 because resistance is drifted about.The resistance of state 4 is drifted about and the distance of itself and resistance separatrix 32 is widened, and so also can not cause situation about misreading.But the resistance of the state that mediates 2 and 3 and resistance separatrix 31,32 overlap.Simultaneously along with the time is elongated, state 2, state 3 and resistance separatrix 31,32 lap all can become many.If do not take any measure to this phenomenon, the read operation that will certainly make the mistake.As shown in Figure 4, one of the method for solution is exactly make resistance separatrix 31 and 32 occur to float to 31 ' and 32 ' respectively along with the resistance drift of phase change cells.Such 31 ' and 32 ' can accurate differentiation state 2 and state 3.
When carrying out read operation to phase change cells, directly cannot judge with regard to the resistance value of phase change cells, need the resistance value of phase-change memory cell to be converted into current value or magnitude of voltage carries out differentiating (principle of work depending on sensor amplifier and SA).The read signal supposing to give phase-change memory cell is certain read current signal, and so resistance separatrix 30,31 and 32 just corresponds to voltage separatrix Vref1, Vref2 and Vref3.Namely when the magnitude of voltage on unit B L is less than Vref1, be determined as state 1, when value is greater than Vref1 and is less than Vref2, be determined as state 2, value is greater than Vref2 when being less than Vref3, is determined as state 3, when value is greater than Vref3, is determined as state 4.Unit be in just complete crystalline state time (state 1) almost do not have resistance to drift about, therefore the discriminant value Vref1 of state 1 does not change and can not cause misreading of device cell yet.The key of problem provides the Vref2 ' of the discriminant value after drift, Vref3 ' for SA when being converted into and being carried out read operation by the resistance separatrix 31 ' after original drift and 32 ' to phase-change memory cell.
After clear and definite the present invention solves the key issue of resistance drift, specifically set forth method of the present invention below in conjunction with figure.
The array constituted mode that two phase-change memory cells (1T1R is example) are unit.As shown in Figure 5: the array 510 being unit for two phase-change memory cells (1T1R), line decoder 520 and column decoder 530.511 comprise 2 1T1R phase-change memory cells 512 and 513, and these two phase-change memory cells share same bit line WL_0, and wordline is respectively BL_0, BL_1.Sketch in the selected process of the unit of two phase-change memory cells compositions for 511: first action row decoding and column decoder are chosen 512, carry out write operation or read operation to it, then by column decoder, choose 513, carry out identical operation to it.Must be continuous print to the operation of two unit, only have after the operation of these two unit completed, just can operate other unit.Because the time of being separated by between two continuous read operations or write operation is all shorter, in such time range, the resistance drift of phase-change memory cell is negligible.Therefore from resistance drift, two phase change cells of a composition unit carry out read operation and write operation simultaneously.
Can know from above-mentioned introduction, need to generate condition discrimination value in read operation process from the resistance of two phase-change memory cells of a formation unit, therefore just must carry out rational combinations of states to two storage unit when carrying out write operation to unit.Adopt 8 states to store to the unit that two phase-change memory cells are formed, namely 2 1T1R store 3 scale-of-two.These 8 states can be taken as: 11,14,24,34,41,42,43,44.The write of these 8 states is no problem, and key is the process read.
The block diagram of read out function circuit is as shown in Figure 6: first the resistance of two phase-change memory cells is input in 610, in 610, first the state of two storage unit is differentiated with Vref1, can be known by the state set, the result differentiated has 4 classes, first kind result is that the voltage on two phase-change memory cell BL is all less than Vref1, and the state of two unit is exactly 11, so time just can directly obtain result 11.Equations of The Second Kind result is exactly that voltage on unit 1BL is less than Vref1, and the voltage on unit 2BL is greater than Vref1, and according to 8 states that may write in advance, the state of two unit is followed successively by 14, so time also can directly obtain result 14.3rd class result is exactly that voltage on unit 1BL is greater than Vref1, and the voltage on unit 2BL is less than Vref1, and same can directly obtaining reads result 41.Last class result is exactly that voltage on two phase-change memory cell BL is all greater than Vref1, according to 8 states preset, the state of two unit have 5 may, cannot directly obtain reading result.Therefore be above-mentioned front 3 class situations, can directly obtain reading result, no longer carry out other operation.Last class result then needs further judgement.Voltage on two phase-change memory cells is input in 620,620 sizes first comparing two voltages, the resistance that larger magnitude of voltage is corresponding larger.According to 8 states of setting, larger magnitude of voltage correspond to the magnitude of voltage of state 4, so time state 4 just as with reference to state, the magnitude of voltage V4 on its BL marks.Certain conversion is carried out to this magnitude of voltage and can obtain Vref2 ', Vref3 '.Such as, as shown in Figure 7: can adopt and V4 is deducted Δ V1 obtain Vref3 ', wherein Δ V1 can be taken as a constant.Calculate the difference DELTA V2 between Vref3 ' and Vref3 again, the value of Vref2 is added α * Δ V2 and is just obtained Vref2 ', and wherein α is a constant, and is less than 1, and reason is that the situation of resistance drift increases the weight of owing to becoming large along with resistance.Above-mentioned algorithm is summarized as follows:
Vref2′＝V2+ΔV1
Vref3′＝Vref3+α*(V2+ΔV1)
By Vref2 ', Vref3 ' be input in 630, so just can differentiate the state that cannot differentiate in 610.So far, read operation process completes.
It needs to be noted and wherein adopt 8 states with different selections, such as these 8 states can be taken as 11,12,21,22,23,24,42,32.But the operation done of the various piece of corresponding read out function circuit now also will difference to some extent.For 610, do not need to make to change, directly can determine 11,12,21 these 3 states.Same is input to the state of failing directly to judge in 620.For 620, need to obtain magnitude of voltage less on BL in two phase-change memory cells, this magnitude of voltage correspond to state 2, represents this magnitude of voltage with V2.The algorithm then now generating discriminant value employing is as follows:
Vref2′＝V2+ΔV1
Vref3′＝Vref3+α*(V2+ΔV1)
The value that wherein Δ V1 can be taken as a constant α is greater than 1, and reason is also that the situation of resistance drift increases the weight of owing to becoming large along with resistance.Be input in 630 as the Vref2 ' obtained, Vref3 ', the state that cannot differentiate in 610 can be differentiated.Can find out, the algorithm generating Vref2 ' and Vref3 ' is closely related with the state write in advance.
Some other for structural integrity in Fig. 5 and Fig. 6 circuit structure is obtained the complete structure of phase transition storage as shown in Figure 7.710 correspondences are exactly structure as shown in Figure 5, are made up of ranks code translator and phase-changing memory cell array.720 correspondences be the read out function circuit shown in Fig. 6,730,740 be two phase-change memory cell input.For 511 storage cells, specific works pattern can be described below: first choose phase-change memory cell 512 by ranks code translator, then control to write driving circuit 750 by control signal 770 on 512, write corresponding data, choosing the phase-change memory cell 513 of same unit with column decoder 530, same controlling to write driving circuit 750 by control signal 770 write corresponding data on phase-change memory cell 2.Write operation terminates.Read operation process can be described as: chosen two phase-change memory cells in 511 by ranks code translator simultaneously, then control to read functional circuit 720 by control signal 770, after reading through a series of differentiation, reading result is passed in I/O, so far, storage and the reading of phase transition storage data is achieved.
The present invention is directed to the resistance drift of the unit in phase transition storage, carry out write operation and read operation in units of two phase change cells simultaneously, in write operation process, in conjunction with the data that will write, write the many-valued state of driving circuit reasonable combination phase-change memory cell, in read operation process, utilize read out function circuit to complete the algorithm circuit of the discriminant value being generated the many-valued state of phase change cells by the resistance of phase change cells, more accurately read the many-valued state of phase change cells in conjunction with sense amplifier (SA).
The present invention is that the drift of one of the key issue existed in dynamic data attemper resistance provides solution.The present invention has taken into account the requirement of phase transition storage to high density and reliability.Wherein, the read out function circuit algorithm circuit as key component is simply effective, and completes two phase change cells read operations, on the few of impact of the speed of phase transition storage simultaneously.
The above-mentioned description to embodiment can understand and apply the invention for ease of those skilled in the art.Person skilled in the art obviously easily can make various amendment to these embodiments, and General Principle described herein is applied in other embodiments and need not through performing creative labour.Therefore, the invention is not restricted to embodiment here, those skilled in the art are according to announcement of the present invention, and the improvement made for the present invention and amendment all should within protection scope of the present invention.
Claims (4)
1. a phase transition storage multilevel memory system, is characterized in that: this system comprises the phase change memory array (510) be made up of several phase-change memory cells, the line decoder (520) be connected with described phase change memory array, column decoder (530), writes driving circuit (750) and read out function circuit (720); Described read out function circuit (720) comprises the sense amplifier (610) gathering the signal that described phase-change memory cell transmits, the discriminant value generation module (620) be connected with described sense amplifier output terminal and another sense amplifier (630) be connected with discriminant value generation module output terminal; Described line decoder (520), column decoder (530) are for choosing described phase-change memory cell; Then control to write driving circuit (750) by control signal (770) and on described phase-change memory cell, write corresponding data by control signal (770); Reading result is being passed in I/O mouth (760) after discriminating step by control signal (770) by described read out function circuit (720), wherein, described discriminating step is that described control signal (770) outputs in another sense amplifier (630) in generation condition discrimination value after discriminant value generation module (620), and described another sense amplifier (630) obtains described reading result according to described condition discrimination value.
2. a kind of phase transition storage multilevel memory system as claimed in claim 1, is characterized in that: the phase-change storage material in described phase-change memory cell is chalcogenide compound alloy; Gate tube in described phase-change memory cell is metal-oxide-semiconductor, bipolar transistor or diode.
3. based on a phase transition storage dynamic data attemper method for phase transition storage multilevel memory system according to claim 1, it is characterized in that: the read-write operation forming two phase-change memory cells (512,513) of a unit carries out simultaneously; The method comprises the following steps:
Write operation: the phase-change memory cell being chosen a unit by line decoder and column decoder, then control to write driving circuit by control signal on phase-change memory cell, write corresponding data, choose another phase-change memory cell of same unit again with column decoder, same control to write driving circuit by control signal write corresponding data on another phase-change memory cell described; Described control signal is the signal exported after carrying out rational combinations of states to two phase-change memory cells;
Read operation: two phase-change memory cells simultaneously being chosen a unit by line decoder and column decoder, then read out function circuit is controlled by control signal, output in another sense amplifier generating condition discrimination value after discriminant value generation module, finally outputted results in I/O mouth by read out function circuit.
4. method as claimed in claim 3, it is characterized in that: in described read operation, the generation method formula of condition discrimination value is as follows:
Vref2'＝V2+ΔV1
Vref3'＝Vref3+α*(V2+ΔV1)
Wherein, Δ V1 is a constant, α is a constant, and be less than 1, V2 is magnitude of voltage less on wordline BL in two phase-change memory cells, this magnitude of voltage correspond to the partiallycrystalline states of phase-change material, Vref2' is the condition discrimination value between the partiallycrystalline states of phase-change material after resistance drift and part amorphous state, Vref3 is the part amorphous state of phase-change material and the condition discrimination value completely between amorphous state before resistance drift, and Vref3' is the part amorphous state of phase-change material and the condition discrimination value completely between amorphous state after resistance drift.
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| CN106024054A (en) * | 2016-05-24 | 2016-10-12 | 中国科学院上海微系统与信息技术研究所 | Phase change memory with retention test function |
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