CN101335046A - Phase-change memory - Google Patents
Phase-change memory Download PDFInfo
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- CN101335046A CN101335046A CNA2008100414143A CN200810041414A CN101335046A CN 101335046 A CN101335046 A CN 101335046A CN A2008100414143 A CNA2008100414143 A CN A2008100414143A CN 200810041414 A CN200810041414 A CN 200810041414A CN 101335046 A CN101335046 A CN 101335046A
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Abstract
The invention discloses a phase-change memory which comprises a plurality of memory units, a column gating circuit, a decoder, a comparative readout resistor, a sensitive amplifier, a read-write drive circuit and a row decoder; bit lines of all the memory units are connected to the column gating circuit and the decoder; the word lines of all the memory units are connected to the row decoder; the column gating circuit and the decoder are connected with the read-write drive circuit and the sensitive amplifier; the read-write drive circuit is connected with the sensitive amplifier by the comparative readout resistance; the memory unit comprises a gating diode and at least two phase-change memory units; after being parallel, the phase-change memory units are connected with the gating diode. The phase-change memory of the invention adopts a 1DnR memory unit structure, thus reducing the chip area occupied by the gating diode.
Description
Technical field
The invention belongs to technical field of semiconductor memory, relate to a kind of storer, relate in particular to a kind of storer of can accelerating and read speed, increase and read the phase transition storage of allowance.
Background technology
The phase transition storage technology is based on Ovshinsky at late 1960s (Phys.Rev.Lett., 21,1450～1453,1968) beginning of the seventies (Appl.Phys.Lett., 18,254～257,1971) phase-change thin film of Ti Chuing can be applied to that the conception of phase change memory medium sets up, and is the memory device of a kind of low price, stable performance.Phase transition storage can be made on the silicon wafer substrate, its critical material is that the research focus of recordable phase-change thin film, heating electrode material, thermal insulation material and extraction electrode material also just launches around its device technology: the physical mechanism research of device comprises how reducing device material etc.The ultimate principle of phase transition storage is to utilize electric impulse signal to act on the device cell, make phase-change material between amorphous state and polycrystalline attitude, reversible transition take place, low-resistance when high resistant during by the resolution amorphous state and polycrystalline attitude can realize writing, wipe and read operation of information.
Phase transition storage owing to have reads at a high speed, high erasable number of times, non-volatile, advantages such as component size is little, strong motion low in energy consumption, anti-and radioresistance, is thought flash memories that most possible replacement is present by international semiconductor TIA and becomes following storer main product and become the device of commercial product at first.
The reading and writing of phase transition storage, wiping operation apply the voltage or the current pulse signal of different in width and height exactly on device cell: wipe operation (RESET), after phase-change material temperature in adding a weak point and strong pulse enable signal device cell is elevated to more than the temperature of fusion, through thereby cooling realization phase-change material polycrystalline attitude is to amorphous conversion fast, promptly one state is to the conversion of " 0 " attitude again; Write operation (SET), when apply one long and pulse enable signal phase-change material temperature medium tenacity is raised under the temperature of fusion, on the Tc after, and keep a period of time to impel nucleus growth, thus realize the conversion of amorphous state to the polycrystalline attitude, promptly " 0 " attitude is to the conversion of one state; Read operation behind the pulse signal that adds a little less than in the of, is read its state by the resistance value of measuring element unit.
The tradition phase transition storage structure as shown in Figure 3, traditional phase transition storage comprises some storage unit 301, DUMMY resistance 303, sense amplifier 304, read-write drive circuit 305, column selection circuit passband and code translator 306, line decoder 307; The bit line of described some storage unit 301 inserts described column selection circuit passband and code translator 306, and the word line of each storage unit 301 inserts described line decoder 307; Described column selection circuit passband is connected described read-write drive circuit 305, reaches sense amplifier 304 with code translator 306, described read-write drive circuit 305 connects described sense amplifier 304 by DUMMY resistance 303.Described each storage unit is made up of a phase-change memory cell 302 and a diode.Wherein, DUMMY resistance 303 is used to finish under read operation, and 302 resistance values of the phase-change memory cell in self-resistance and the array are compared; When the resistance of phase-change memory cell 302 is higher than DUMMY resistance 303, then difference sense amplifier 304 judges that phase change cells resistance 302 is " RESET " state, otherwise, when the resistance of phase-change memory cell 302 is lower than DUMMY resistance 303, sense amplifier 304 judges that phase change cells resistance 302 are " SET " state.
There are problems in the 1D1R storer of this kind traditional structure: first, because process deviation, and the distance of storage unit and driving circuit is unequal during chip layout, " RESET " of phase change cells, resistance value distribution under " SET " state is all wider, even the phenomenon that the resistance under the two states overlaps mutually can appear, cause the storage errors of data.Second, because read operation needs a pulse signal, phase transformation meeting after read operation repeatedly among the 1R1D is along with the accumulation of read pulse signal, resistance value constantly reduces, after the resistance value under " RESET " is less than DUMMY resistance, will free data read errors, if use higher read operation voltage, perhaps higher read operation electric current, this phenomenon will be more serious.The 3rd, because after RESET repeatedly and the SET operation, it is very complicated that the resistance value of phase-change memory cell can become, and corresponding change can not take place in DUMMY resistance usually, so difficult more with relatively can becoming of DUMMY resistance.
As known from the above, traditional phase transition storage exists following problem to be needed to solve: the first, and under the structure of traditional 1T1R or 1D1R, most of area of storage array all is used as the metal-oxide-semiconductor of gate tube, or diode consumed, and do not reach the maximum set Cheng Du of phase change cells.Second, find according to experiment, phase-change memory cell on same phase change memory chip, outstanding inadequately and phase change cells and the equal reason of driving circuit distance owing to process consistency, RESET operation back high value distribute with SET after low resistance distribution all very extensive (high resistant 20k-500kOhm, low-resistance 1k-10kOhm), even the situation that the high resistant low resistance overlaps appears, the data that correctly read on the phase change cells are made a big impact, and a little less than the antijamming capability of circuit, reading speed is slow; The 3rd, phase transition storage depends on Joule heat and changes its resistance states, find according to experiment, after phase-changing memory unit is carried out repeatedly read operation, the RESET state of unit and the resistance of SET state all can increase along with the number of times of read operation and reduce, under traditional 1T1R and 1D1R structure, when low the arriving to a certain degree of phase change cells resistance value of " RESET " state, read error may take place, and the gap of high low resistance diminishes and also can have influence on the chip read margin.Four, after phase change cells was by RESET repeatedly or SET operation, the resistance situation of device own also can be very complicated.
Summary of the invention
Technical matters to be solved by this invention is: a kind of phase-change memory for high speed complementation unit is provided, can accelerates storer and read speed, increase and to read allowance, and reduce the influence to phase transition storage of the cumulative effect, technology, laying out pattern of read current.
For solving the problems of the technologies described above, the present invention adopts following technical scheme:
A kind of phase transition storage comprises some storage unit, column selection circuit passband and code translator, reads comparison resistance, sense amplifier, read-write drive circuit, line decoder; The bit line of described each storage unit inserts described column selection circuit passband and code translator, and the word line of each storage unit inserts described line decoder; Described column selection circuit passband is connected described read-write drive circuit, reaches sense amplifier with code translator, described read-write drive circuit connects described sense amplifier by reading comparison resistance; Described each storage unit comprises a gating diode and at least two phase-change memory cells; Be connected with described gating diode after described each phase-change memory cell parallel connection.
As a preferred embodiment of the present invention, be connected with the positive pole of described gating diode after described each phase-change memory cell parallel connection.Perhaps, be connected with the negative pole of described gating diode after described each phase-change memory cell parallel connection.
As a preferred embodiment of the present invention, described column selection circuit passband is controlled the resistance state of gating and each word line of each bit line; The same time, in a plurality of bit lines that a plurality of phase-change memory cells on the same diode are connected, have only a bit line to be strobe state, all the other bit lines all are in high-impedance state, and to have only a word line be low level, and remaining word line is a high level; Be on the bit line of gating, the phase-change memory cell that is in simultaneously on the low level word line is the unit that code translator is chosen, and by read-write drive circuit it is operated.
As a preferred embodiment of the present invention, described phase-change memory cell is a phase change memory resistance.
As a preferred embodiment of the present invention, the described comparison resistance of reading is a DUMMY resistance, under read operation, the phase-change memory cell resistance value in self-resistance and the array is compared.When the resistance of phase-change memory cell is higher than DUMMY resistance, then sense amplifier judges that phase change cells resistance is the RESET state; Otherwise when the resistance of phase-change memory cell is lower than DUMMY resistance, sense amplifier judges that phase change cells resistance is the SET state.
As a preferred embodiment of the present invention, the phase-change memory cell number of described each storage unit is identical or different or incomplete same.
As a preferred embodiment of the present invention, in the described storage unit, n the shared gating diode of phase change resistor, storage n bit data.
Another embodiment of the present invention is: a kind of phase transition storage comprises some storage unit, column selection circuit passband and code translator, sense amplifier, read-write drive circuit, line decoder; The bit line of described some storage unit inserts described column selection circuit passband and code translator, and the word line of each storage unit inserts described line decoder; Described column selection circuit passband is connected described read-write drive circuit, reaches sense amplifier with code translator, described read-write drive circuit connects described sense amplifier; Described each storage unit comprises a gating diode and two complementary state phase change cells; Be connected with described gating diode after described each complementary state phase change cells parallel connection; Described two complementary state phase change cells are stored the data of two state complementations respectively.
As a preferred embodiment of the present invention, in the described storage unit, 2 shared gating diodes of complementary state phase change cells are stored 1 bit data.
Beneficial effect of the present invention is:
Phase transition storage of the present invention adopts the 1DnR memory cell structure, thereby has reduced the chip area that gate tube takies.Another embodiment of the present invention adopts the 1D2R memory cell structure to increase and reads allowance, reduces read operation voltage or electric current; Higher reading speed is arranged simultaneously, can effectively reduce, the far and near different influences that cause of storage unit and driving circuit storer owing to process deviation; In addition, the accumulation of adopting this mode can also effectively reduce the read operation pulse changes the influence that causes to the storage unit resistance, can reduce repeatedly the influence that device aging produces behind the write operation simultaneously.
Description of drawings
Fig. 1 is 1D2R memory cell structure figure among the embodiment one;
Fig. 2 is another structural drawing of 1D2R storage unit among the embodiment one;
Fig. 3 is traditional 1D1R phase change memory structure figure;
Fig. 4 is 1D2R phase change memory structure figure;
Fig. 5 is typical differential amplifier structural drawing;
Fig. 6 is the traditional 1D1R and the playback mode and the bit-line voltage comparison diagram of 1D2R structure;
Fig. 7 is the phase change memory structure figure of 1DnR among the embodiment two.
Embodiment
Describe the preferred embodiments of the present invention in detail below in conjunction with accompanying drawing.
Phase transition storage of the present invention uses the shared gating diode of a plurality of phase change cells to go to replace the unitized construction storage data of a traditional gating diode and a phase change cells, thereby improves the storage density of phase transition storage.Of the present invention another implemented by using complementary storage phase change resistor unit, being that (wherein " D " refers to diode diode to 1D2R, " R " refers to resistance resistance) structure, improve under the situation of chip area in little amplitude, improve reading speed, reliability, the stability of chip.Below describe in detail with embodiment.
Embodiment one
See also Fig. 1, Fig. 2 and Fig. 4, present embodiment is introduced the phase transition storage 400 that storage unit is the 1D2R structure.
At first introduce the structure of storage unit in the present embodiment.As shown in Figure 1, storage unit 100 comprises phase-change memory cell 101a and 101b, gating diode 102, phase-change material top electrode 103a and 103b, word line WL, bit line BL and BLn.Wherein phase-change memory cell 101a and phase-change memory cell 101b store the data (so " phase-change memory cell " also can be described as " complementary state phase change cells " in the present embodiment) of two complementations, for example when 101a is " RESET " state, 101b is " SET " state, promptly stores the data of 1bit with two phase change cells.In the present embodiment, insert the positive pole of gating diode 102 after phase-change memory cell 101a, the 101b parallel connection.Storage unit can also be the structure among Fig. 2, i.e. phase-change memory cell 202a and the negative pole that inserts gating diode 201 after 202b is in parallel.Storage unit 100 is not limited only to 1D2R with the structure of storage unit 200, can be 1DnR, and n is the integer more than or equal to 2.
Introduce the structure of phase transition storage in the present embodiment below in conjunction with Fig. 4.As shown in Figure 4, the present invention has disclosed a kind of phase transition storage, comprises some storage unit 407, sense amplifier 403, read-write drive circuit 404, column selection circuit passband and code translator 405, line decoder 406; The bit line of described some storage unit 407 inserts described column selection circuit passband and code translator 405, and the word line of each storage unit 407 inserts described line decoder 406; Described column selection circuit passband is connected described read-write drive circuit 404, reaches sense amplifier 403 with code translator 405, described read-write drive circuit 404 connects described sense amplifier 403.Described each storage unit 407 comprises a gating diode 402 and two complementary state phase change cells 401 (being phase-change memory cell 101a, the 101b among Fig. 1); Described each complementary state phase change cells 401 back in parallel are connected with described gating diode 402.
Described two complementary state phase change cells 401 are stored two opposite resistance states respectively.For example in two complementary phase change cells, first is " RESET " state, and then another is " SET " state, and what thought memory stores this moment is " RESET " state; When first was " SET " state, second what then think this a pair of phase change cells storage for " RESET " was " SET " state.
The storage unit of phase transition storage of the present invention has overcome the shortcoming of the traditional phase transition storage among Fig. 3 (storage unit is by adopting the 1D1R structure) by the structure that adopts 1D2R.First, because the structure of 1D2R is the data of storage 1bit in two phase change cells of facing mutually, the phase change cells of two complementations compares mutually when data are read, then can eliminate because process deviation, and the distance of storage unit and driving circuit is unequal during chip layout, the phase change cells resistance deviation that causes.The second, in normal operating process, the phase change cells of two complementations has necessarily experienced the read operation of same number, and both resistance can reduce simultaneously, can effectively reduce the influence of the cumulative effect of read operation to phase change resistor.The 3rd, because write operation carries out a pair of complementation unit, and be that both compare mutually when reading, storage unit increases and problem aging, that DUMMY does not change thereupon along with writing number of times in the 1D1R structure so can reduce, and has improved the global reliability of device.
Fig. 5 is a typical differential amplifier structural drawing, and upward voltage is greater than the voltage on the BLkn as BLk, and Data_out exports high level, on the contrary output low level.
See also Fig. 6 on the theoretical foundation of Fig. 5, Fig. 6 is the traditional 1D1R and the playback mode and the bit-line voltage comparison synoptic diagram of 1D2R structure.Wherein Vmin is the minimum voltage difference that amplifier 403 is correctly read BLk and the last data of BLkn among Fig. 4.Δ V is the allowance of reading of this circuit, and VBLk_read is the high operation voltage on the word line in the read operation, Td be the 1D2R structure with respect to the 1D1R structure, the delay that reduces when reading.
Because in the structure of 1D2R, voltage difference is the twice of voltage difference between BLk and the VREF in the 1D1R structure between BLk and the BLkn, thus can reach the Vmin that amplifier needs earlier, thus fast speeds is arranged, and read the twice that allowance also is 1D1R.Simultaneously, 1D2R realizes that reading among the 1D1R postpones and read allowance, only needs to use half read operation voltage or the operating current of 1D1R, can effectively reduce since read pulse to the change of phase change cells resistance.
Embodiment two
See also Fig. 7, present embodiment is introduced the phase transition storage 700 that storage unit is the 1DnR structure, and wherein, n is the integer more than or equal to 2.In the storage unit of 1DnR structure, n the shared gating diode of phase change resistor, the data of storage n bit.
As shown in Figure 7, the present invention has disclosed a kind of phase transition storage 700, comprises some storage unit 701, column selection circuit passband and code translator 702, reads comparison resistance 703, sense amplifier 704, read-write drive circuit 705, line decoder 706.The bit line of described each storage unit 701 inserts described column selection circuit passband and code translator 702, and the word line of each storage unit 701 inserts described line decoder 706; Described column selection circuit passband is connected described read-write drive circuit 705, reaches sense amplifier 704 with code translator 702, described read-write drive circuit 705 connects described sense amplifier 704 by reading comparison resistance 703.Described column selection circuit passband is controlled the resistance state of gating and each word line of each bit line; The same time, in a plurality of phase-change memory cells 701 are connected on the same diode a plurality of bit lines, have only a bit line to be strobe state, all the other bit lines all are in high-impedance state, and to have only a word line be low level, and remaining word line is a high level; The phase-change memory cell that be on the bit line of gating, is on the low level word line simultaneously is the unit that code translator is chosen, by read-write drive circuit 705 to its operation.The described comparison resistance of reading is a DUMMY resistance, under read operation, the phase-change memory cell resistance value in self-resistance and the array is compared.When the resistance of phase-change memory cell is higher than DUMMY resistance, then sense amplifier judges that phase change cells resistance is the RESET state; Otherwise when the resistance of phase-change memory cell is lower than DUMMY resistance, sense amplifier judges that phase change cells resistance is the SET state.
Described each storage comprises a gating diode and at least two phase-change memory cells for single 701 yuan, is connected with the positive pole or the negative pole of described gating diode after described each phase-change memory cell parallel connection.Wherein, phase-change memory cell is a phase change memory resistance.
In the present embodiment, phase transition storage substitutes traditional 1D1R structure by the structure of using 1DnR, thereby reduces the chip area that gate tube takies.
Embodiment three
The difference of present embodiment and embodiment two is, in the present embodiment, and the phase-change memory cell number difference of described each storage unit or incomplete same.It implements principle with embodiment two, does not do at this and gives unnecessary details.
Above embodiment is the unrestricted technical scheme of the present invention in order to explanation only.Any modification or partial replacement that does not break away from spirit and scope of the invention all should be encompassed in the middle of the claim scope of the present invention.
Claims (11)
1, a kind of phase transition storage comprises some storage unit, column selection circuit passband and code translator, reads comparison resistance, sense amplifier, read-write drive circuit, line decoder;
The bit line of described each storage unit inserts described column selection circuit passband and code translator, and the word line of each storage unit inserts described line decoder;
Described column selection circuit passband is connected described read-write drive circuit, reaches sense amplifier with code translator, described read-write drive circuit connects described sense amplifier by reading comparison resistance; It is characterized in that:
Described each storage unit comprises a gating diode and at least two phase-change memory cells; Be connected with described gating diode after described each phase-change memory cell parallel connection.
2, phase transition storage according to claim 1 is characterized in that: be connected with the positive pole of described gating diode after described each phase-change memory cell parallel connection.
3, phase transition storage according to claim 1 is characterized in that: be connected with the negative pole of described gating diode after described each phase-change memory cell parallel connection.
4, phase transition storage according to claim 1 is characterized in that: described column selection circuit passband is controlled the resistance state of gating and each word line of each bit line; The same time, in a plurality of bit lines that a plurality of phase-change memory cells on the same diode are connected, have only a bit line to be strobe state, all the other bit lines all are in high-impedance state, and to have only a word line be low level, and remaining word line is a high level; Be on the bit line of gating, the phase-change memory cell that is in simultaneously on the low level word line is the unit that code translator is chosen, and by read-write drive circuit it is operated.
5, phase transition storage according to claim 1 is characterized in that: described phase-change memory cell is a phase change memory resistance.
6, phase transition storage according to claim 1 is characterized in that: the described comparison resistance of reading is a DUMMY resistance, under read operation, the phase-change memory cell resistance value in self-resistance and the array is compared.
7, phase transition storage according to claim 7 is characterized in that: when the resistance of phase-change memory cell is higher than DUMMY resistance, then sense amplifier judges that phase change cells resistance is the RESET state; Otherwise when the resistance of phase-change memory cell is lower than DUMMY resistance, sense amplifier judges that phase change cells resistance is the SET state.
8, phase transition storage according to claim 1 is characterized in that: the phase-change memory cell number of described each storage unit is identical or different or incomplete same.
9, phase transition storage according to claim 1 is characterized in that: in the described storage unit, and n the shared gating diode of phase-change memory cell, storage n bit data.
10, a kind of phase transition storage comprises some storage unit, column selection circuit passband and code translator, sense amplifier, read-write drive circuit, line decoder;
The bit line of described some storage unit inserts described column selection circuit passband and code translator, and the word line of each storage unit inserts described line decoder;
Described column selection circuit passband is connected described read-write drive circuit, reaches sense amplifier with code translator, described read-write drive circuit connects described sense amplifier; It is characterized in that:
Described each storage unit comprises a gating diode and two complementary state phase change cells; Be connected with described gating diode after described each complementary state phase change cells parallel connection;
Described two complementary state phase change cells are stored the data of two state complementations respectively.
11, phase transition storage according to claim 10 is characterized in that: in the described storage unit, 2 shared gating diodes of complementary state phase change cells are stored 1 bit data.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101694779B (en) * | 2009-10-21 | 2012-07-25 | 中国科学院上海微系统与信息技术研究所 | Gating method of memory and circuit structure implementing same |
| CN102890962A (en) * | 2011-07-20 | 2013-01-23 | 中国科学院上海微系统与信息技术研究所 | System and method for multilevel storage of phase change memory |
| CN103943144A (en) * | 2014-04-30 | 2014-07-23 | 中国科学院上海微系统与信息技术研究所 | Reference resistance-optimized phase change memory reading circuit and reference resistance optical selection method |
| CN110390990A (en) * | 2018-04-18 | 2019-10-29 | 力旺电子股份有限公司 | Memory circuit and the method for operating memory circuit |
| CN110428861A (en) * | 2019-09-12 | 2019-11-08 | 上海明矽微电子有限公司 | A method of reducing eeprom memory area |
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| CN1725369B (en) * | 2005-06-02 | 2010-05-05 | 复旦大学 | Storage mode and circuit using ratio as station guide |
| KR100674997B1 (en) * | 2005-10-15 | 2007-01-29 | 삼성전자주식회사 | Phase-change random access memory device and method of controlling read operation using the same |
| JP2007201081A (en) * | 2006-01-25 | 2007-08-09 | Elpida Memory Inc | Semiconductor memory device |
| CN101232038B (en) * | 2008-02-26 | 2010-12-08 | 中国科学院上海微系统与信息技术研究所 | Structure of high-density phase transition memory and process of preparation thereof |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101694779B (en) * | 2009-10-21 | 2012-07-25 | 中国科学院上海微系统与信息技术研究所 | Gating method of memory and circuit structure implementing same |
| CN102890962A (en) * | 2011-07-20 | 2013-01-23 | 中国科学院上海微系统与信息技术研究所 | System and method for multilevel storage of phase change memory |
| CN102890962B (en) * | 2011-07-20 | 2015-05-13 | 中国科学院上海微系统与信息技术研究所 | System and method for multilevel storage of phase change memory |
| CN103943144A (en) * | 2014-04-30 | 2014-07-23 | 中国科学院上海微系统与信息技术研究所 | Reference resistance-optimized phase change memory reading circuit and reference resistance optical selection method |
| CN103943144B (en) * | 2014-04-30 | 2017-07-11 | 中国科学院上海微系统与信息技术研究所 | The phase transition storage reading circuit and reference resistance method for optimizing of reference resistance optimization |
| CN110390990A (en) * | 2018-04-18 | 2019-10-29 | 力旺电子股份有限公司 | Memory circuit and the method for operating memory circuit |
| CN110428861A (en) * | 2019-09-12 | 2019-11-08 | 上海明矽微电子有限公司 | A method of reducing eeprom memory area |
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| CN100570747C (en) | 2009-12-16 |
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