CN102890962A - System and method for multilevel storage of phase change memory - Google Patents
System and method for multilevel storage of phase change memory Download PDFInfo
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Abstract
The invention relates to a system and a method for multilevel storage of a phase change memory. The system comprises a phase change memory array (510) composed of multiple phase change memory cells (511, 512), a row decoder (520) connected to the phase change memory array (510), a column decoder (530), a writing drive circuit (750) and a reading functional circuit (720). The row decoder (520) and the column decoder (530) are used for selecting the phase change memory cell. A control signal (770) controls the writing drive circuit (750) to write corresponding data in the corresponding phase change memory cell. The reading functional circuit (720) transmits a read result into an I/O interface (760) by the control signal (770) after discrimination. The system and the method solve the problem that multilevel storage of a phase change memory has unstability, and satisfy high density and reliability requirements of a phase change memory.
Description
Technical field
The present invention relates to the micro-nano art of electronics, particularly a kind of phase transition storage multilevel memory system and method.
Background technology
Phase transition storage (Phase Change Memory) is as the nonvolatile memory of a new generation, be based on Ovshinsky at late 1960s (Phys.Rev.Lett., 21,1450～1453,1968) beginning of the seventies (Appl.Phys.Lett., 18,254～257,1971) phase-change thin film that proposes can be applied to that the conception of phase change memory medium sets up.Relative existing storer in the storage market, the advantage of phase transition storage is that its read or write speed is fast, and height can be write the wiping number of times, and is non-volatile, low in energy consumption, and storage density is high, and component size is little, radioresistance, cost is low and good etc. with the CMOS processing compatibility.Be acknowledged as the main product that most possibly becomes following storer.
Phase transition storage depends on the phase-change material such as chalcogenide compound etc., and the material of this class can stably reversibly change between crystalline phase and amorphous phase, and Typical Representative material wherein is Ge
2Sb
2Te
5(GST).Two kinds of crystalline phases present different resistances, and namely crystalline state (Set attitude) shows as low resistance state, the logical value of corresponding stored unit ' 0 ', and amorphous state (Reset attitude) shows as high-impedance state, the logical value of corresponding stored unit ' 1 '.
The temperature that Fig. 1 has shown Set process and Reset process operation process phase-change material over time.When carrying out the Set operation, apply a wider width amplitude less voltage or current impulse, make the temperature of phase-change material between Tc and temperature of fusion, in order to ensure the generation of crystalline polamer, the width (t of pulse signal
2) must be greater than crystallization sensitive time (induction time for crystallization).When carrying out the Reset operation, in order to guarantee the formation of non crystalline structure, the fall time of pulse must be less than the crystallization sensitive time.As mentioned above, the Set of phase-change material operation has different requirements with Reset operation pulse signals, finally obtains the larger resistance difference between amorphous state and the crystalline state.
The storage unit typical structure of phase transition storage is that a phase change material unit and a transistor form, also by adopting diode or triode place of transistor to form phase-change memory cell.As shown above, a storage unit can be stored 2 bits information i.e. ' 0 ' and ' 1 ', but in recent years, a main development direction of phase transition storage is exactly multistage storage.Multistage being stored on the basis of not reducing the storage area, in cellar area storage quantity of information as much as possible, a phase-change memory cell canned data can be 4 bits, 8 bits or more, can be programmed to exactly 4,8 or more states between complete crystalline state and amorphous state to the requirement of phase-change memory cell accordingly.The representative value of its resistance was～1-10K Ω when phase-change memory cell was in complete crystalline state, and the representative value of its resistance is more than the 1M Ω during complete amorphous state.With the multistage row that are stored as of 4bits, we can operate storage unit respectively～1-10K Ω ,～10-100K Ω, and～100-1M Ω, with～above 4 the different resistances of 1M.When carrying out read operation again, can obtain 4 different readouts, like this, we have just realized the multistage storage of 4 bits of single phase-change memory cell.
Although multistage storage has improved the high density storage of phase transition storage greatly, but multistage storage also is faced with a series of challenge, one of them challenge is exactly variation along with the time, the phase-change memory cell resistance drift about (Resistance Drift) that can change.According to the people such as Pirovano " Low-Field Amorphous State Resistance and Threshold Voltage Drift in Chalcogenide Materials; " IEEE Transaction on Electron Devices, Vol.51, No.5, May 2004, description in the literary composition among the pp714-719, be thereupon large the change seriously of resistance change of phase-change material of resistance drift situation, the resistance drift situation that is in the unit of Set attitude can be ignored, therefore when phase transition storage only adopts 2 bits storage modes, the resistance drift of Set attitude can be ignored, the resistance drift of Reset attitude makes Reset resistance become larger and larger, make like this resistance difference between Reset attitude and the Set attitude become large, increased the readability of resistance.But when phase transition storage adopted multistage storage, resistance drift situation can make the resistance of intermediate state overlapping with original discriminant value of setting, and causes read error.For such problem, we can be from phase-change material, and the negative influence that resistance is drifted about and brought to multistage storage is eliminated in the aspects such as device architecture and programmed method.
Summary of the invention
The technical problem to be solved in the present invention is to provide
In order to solve the problems of the technologies described above, the present invention adopts following technical method: a kind of phase transition storage multilevel memory system, this system comprise by phase change memory array (510), the line decoder (520) that links to each other with described phase change memory array, the column decoder (530) of several phase-change memory cells (511,512) formation, write driving circuit (730) and read out function circuit (720); Described ranks code translator (520,530) is used for choosing described phase-change memory cell; Then write driving circuit (750) by control signal (770) control and write corresponding data by control signal (770) at affiliated phase-change memory cell; Described read out function circuit (720) is being passed in the I/O mouth (760) through reading the result after the discriminating step by control signal (770).
Preferably, described read out function circuit (720) comprises sense amplifier (610), the discriminant value generation module (620) that is connected with described sense amplifier output terminal that gathers the signal that transmits on the described phase-change memory cell and another sense amplifier (630) that is connected with discriminant value generation module output terminal.
Preferably, the phase-change storage material in the described phase-change memory cell is the chalcogenide compound alloy; Its gate tube is metal-oxide-semiconductor, bipolar transistor or diode not.
The present invention also comprises the multistage storage means of a kind of phase transition storage, and the read-write operation that consists of two phase-change memory cells (511,512) of a unit carries out simultaneously.
Preferably, the method may further comprise the steps:
Write: choose phase-change memory cell by the ranks code translator, then write driving circuit by control signal control and write corresponding data at phase-change memory cell, choose again another phase-change memory cell of same unit with column decoder, same pass through control signal control and write driving circuit and write corresponding data at described another phase-change memory cell; Described control signal is that two phase-change memory cells are carried out the signal exported after the rational combinations of states;
Read: choose simultaneously two phase-change memory cells by the ranks code translator, then by control signal control read out function circuit, after through the discriminant value generation module, generate the condition discrimination value and output in the read out function circuit, outputted results in the I/O mouth by the read out function circuit at last;
Preferably, in the described read operation, the generation method formula of condition discrimination value is as follows:
Vref2′＝V2+ΔV1
Vref3′＝Vref3+α*(V2+ΔV1)
Wherein, Δ V1 is a constant, and α is a constant, and less than 1.
The present invention is in writing driving circuit, write the many-valued state of driving circuit reasonable combination phase-change memory cell, utilize the read out function circuit to finish the algorithm circuit that is generated the discriminant value of the many-valued state of phase change cells by the resistance of phase change cells, accurately read again the many-valued state of phase change cells in conjunction with sense amplifier (SA).
The multistage storage means of phase transition storage that the present invention proposes, its read out function circuit is one step completed to be the read operation that consists of two phase-change memory cells of a unit.
The multistage storage means of phase transition storage that the present invention proposes, the many-valued state that may write of its phase-change memory cell is predefined, the value of setting is combined with follow-up discriminant value generating algorithm circuit.
The multistage storage means of phase transition storage that the present invention proposes, its follow-up read out function circuit at first can be ignored according to complete crystalline state resistance drift and directly be differentiated some many-valued states of reading, as for other many-valued state again by algorithm circuit evolving discriminant value, realize that at last the correct decision of all many-valued states reads
The multistage storage means of phase transition storage that the present invention proposes, the key of its discriminant value generating algorithm circuit is to read wherein some particular states of phase-change memory cell from the many-valued state that can't directly differentiate, this state as the reference state, is carried out a series of computing by this reference state again and obtains discriminant value.
Description of drawings
Fig. 1 is the time dependent curve of the temperature of existing phase-change material;
Fig. 2 is phase-change storage material 4 attitude distribution of resistance curves;
Fig. 3 is the resistance drift situation of phase-change storage material 4 attitude distribution of resistance curves;
Fig. 4 is a solution of the resistance drift situation of phase-change storage material 4 attitude distribution of resistance curves;
Fig. 5 is memory array structure and ranks code translator corresponding to array that adopts among the present invention;
Fig. 6 is the read out function circuit that adopts among the present invention;
Fig. 7 is the concrete structure of a memory of the present invention.
Embodiment
Be described in further detail below in conjunction with the enforcement of accompanying drawing to technical method:
The present invention relates to a kind of New-type phase change memory multi-stage storage means.Purpose is to eliminate the negative influence that resistance is drifted about and brought to multistage storage, improves the reliability of multistage storage.
The below elaborates detailed content of the present invention take 4 attitude storage modes as row.As shown in Figure 2: the complete crystalline state of distribution of resistance curve 20 corresponding phase-change materials, the part crystalline state of distribution of resistance curve 21 corresponding phase-change materials, the part amorphous state of distribution of resistance curve 22 corresponding phase-change materials, the complete amorphous state of distribution of resistance curve 23 corresponding phase-change materials, use respectively 1,2,3 and 4 come above-mentioned 4 states of mark.30,31 and 32 is respectively state 1,2,3 and 4 resistance separatrix.Namely when the resistance of storage unit less than 30 the time, its state just is 1, when the resistance of storage unit greater than 30 and less than 31 the time, its state just is 2, when the resistance of storage unit greater than 31 and less than 32 the time, its state just is 3, when the resistance of storage unit greater than 32 the time, its state just is 4.According to the introduction of background knowledge, can learn intermediateness 2,3 and be in the impact that complete amorphous state 4 is easier to be subject to the resistance drift phenomenon.
As shown in Figure 3, can see the resistance drift phenomenon of 4 attitudes.Over time, the distribution of resistance curve of each attitude changes, and distribution curve 20,21,22 and 23 at first is respectively by 20 ', and 21 ', 22 ' and 23 ' substitutes.The resistance drift is along with the change of the resistance of each attitude becomes large greatly.State 1 does not almost have the resistance drift, the situation that resistance separatrix 30 and state 1 can not occur misreading because the resistance drift.The drift of the resistance of state 4 so can not cause situation about misreading so that the distance of itself and resistance separatrix 32 widens yet.But the resistance of the attitude that mediates 2 and 3 and resistance separatrix 31,32 overlap.Simultaneously along with the time is elongated, state 2, state 3 and resistance separatrix 31,32 laps all can become many.If this phenomenon is not taked any measure, the read operation that will certainly make the mistake.As shown in Figure 4, one of solution is exactly to make resistance separatrix 31 and the 32 resistance drifts along with phase change cells occur to float to respectively 31 ' and 32 '.Such 31 ' and 32 ' can accurate differentiation state 2 and state 3.
When phase change cells is carried out read operation, can't directly judge with regard to the resistance value of phase change cells, the resistance value of phase-change memory cell need to be converted into current value or magnitude of voltage and differentiate (depending on that sensor amplifier is the principle of work of SA).The read signal of supposing to give phase-change memory cell is certain read current signal, and resistance separatrix 30,31 and 32 just corresponds to voltage separatrix Vref1, Vref2 and Vref3 so.Be magnitude of voltage on the unit B L during less than Vref1, differentiate and be state 1, value is during greater than Vref1 and less than Vref2, differentiates to be state 2, and value is greater than Vref2 during less than Vref3, differentiates to be state 3, and value is during greater than Vref3, differentiates to be state 4.(state 1) almost do not have the resistance drift when unit was in just complete crystalline state, can not cause misreading of device cell therefore the discriminant value Vref1 of state 1 does not change yet.When being converted into phase-change memory cell carried out read operation, the resistance separatrix 31 ' and 32 ' of the key of problem after by original drift provide discriminant value Vref2 ' after the drift, Vref3 ' for SA.
After clear and definite the present invention solves the key issue of resistance drift, below in conjunction with the concrete elaboration of figure method of the present invention.
Two phase-change memory cells (1T1R is example) are the array constituted mode of unit.As shown in Figure 5: array 510, line decoder 520 and column decoder 530 take two phase-change memory cells (1T1R is as example) as unit.511 comprise 2 1T1R phase- change memory cells 512 and 513, and these two phase-change memory cells are shared same bit line WL_0, and the word line is respectively BL_0, BL_1.Take 511 as the unit selected process of example summary at two phase-change memory cells compositions: at first action row decoding and column decoder are chosen 512, and it is carried out write operation or read operation, by column decoder, choose 513 again, and it is carried out identical operation.Operation to two unit must be continuous, only have the operation of these two unit finished after, just can operate other unit.Owing to the time of being separated by between two continuous read operations or the write operation is all shorter, the drift of the resistance of phase-change memory cell can be ignored in such time range.Therefore upper from the resistance drift, two phase change cells that form a unit are to carry out simultaneously read operation and write operation.
Can know from above-mentioned introduction, in the read operation process, need from the resistance of two phase-change memory cells consisting of a unit, to generate the condition discrimination value, therefore when the unit is carried out write operation, just must carry out rational combinations of states to two storage unit.The unit that two phase-change memory cells are consisted of adopts the storage of 8 attitudes, i.e. 3 scale-of-two of 2 1T1R storages.These 8 states can be taken as: 11,14,24,34,41,42,43,44.Writing of these 8 attitudes is no problem, and key is the process of reading.
The block diagram of read out function circuit is as shown in Figure 6: the resistance of two phase-change memory cells at first is input in 610, in 610, at first differentiate the state of two storage unit with Vref1, can be known by the state of setting, the result who differentiates has 4 classes, first kind result be two voltages on the phase-change memory cell BL all less than Vref1, the state of two unit is exactly 11, so the time just can directly obtain result 11.The Equations of The Second Kind result be exactly voltage on the unit 1BL less than Vref1, the voltage on the unit 2BL is greater than Vref1, according to 8 states that may write in advance, the state of two unit is followed successively by 14, so the time also can directly obtain result 14.The 3rd class result be exactly voltage on the unit 1BL greater than Vref1, the voltage on the unit 2BL is less than Vref1, same can directly obtain reading result 41.Last class result be exactly two voltages on the phase-change memory cell BL all greater than Vref1, according to predefined 8 states, the state of two unit have 5 may, can't directly obtain reading the result.Therefore be above-mentioned front 3 class situations, can directly obtain reading the result, no longer carry out other operation.Last class result then needs further judgement.Voltage on two phase-change memory cells is input in 620, and 620 at first compare the size of two voltages, the larger larger resistance of magnitude of voltage correspondence.According to 8 states setting, larger magnitude of voltage correspondence the magnitude of voltage of state 4, so the time state 4 just as with reference to attitude, the V4 mark of the magnitude of voltage on its BL.This magnitude of voltage is carried out certain conversion can obtain Vref2 ', Vref3 '.Such as, as shown in Figure 7: can adopt V4 is deducted Δ V1 to obtain Vref3 ', wherein Δ V1 can be taken as a constant.Calculate the difference DELTA V2 between Vref3 ' and the Vref3, the value of Vref2 is added α * Δ V2 and is just obtained Vref2 ' again, and wherein α is a constant, and less than 1, reason is because along with resistance becomes large, the situation of resistance drift increases the weight of.Above-mentioned algorithm is summarized as follows:
Vref2′＝V2+ΔV1
Vref3′＝Vref3+α*(V2+ΔV1)
With Vref2 ', Vref3 ' is input in 630, so just can differentiate the state that can't differentiate in 610.So far, read operation process is finished.
It needs to be noted and wherein adopt 8 states can be with different selections, such as these 8 attitudes being taken as 11,12,21,22,23,24,42,32.But the operation that the various piece of the read out function circuit of corresponding this moment is done is difference to some extent also.For 610, do not need to make change, can directly determine 11,12,21 these 3 states.The same state that will fail directly to judge is input in 620.For 620, need to obtain in two phase-change memory cells less magnitude of voltage on the BL, this magnitude of voltage correspondence state 2, represents this magnitude of voltage with V2.The algorithm that then generates the discriminant value employing this moment is as follows:
Vref2′＝V2+ΔV1
Vref3′＝Vref3+α*(V2+ΔV1)
Wherein Δ V1 can be taken as a constant α value greater than 1, reason also is because along with resistance becomes large, the situation of resistance drift increases the weight of.As for the Vref2 ' that obtains, Vref3 ' is input in 630, can differentiate the state that can't differentiate in 610.Can find out, the algorithm that generates Vref2 ' and Vref3 ' is closely related with the state that writes in advance.
Structure among Fig. 5 and Fig. 6 is integrated the complete structure that some other circuit structure obtains phase transition storage as shown in Figure 7.710 correspondences are exactly structure as shown in Figure 5, are comprised of ranks code translator and phase-changing memory cell array.720 correspondences be read out function circuit shown in Figure 6,730,740 are two phase-change memory cell input.Take 511 storage cells as example, the specific works pattern can be described below: at first choose phase-change memory cell 512 by the ranks code translator, then write driving circuit 750 by control signal 770 controls and write corresponding data 512, at the phase-change memory cell 513 of choosing same unit with column decoder 530, same pass through control signal 770 controls and write driving circuit 750 and write corresponding data at phase-change memory cell 2.Write operation finishes.The read operation process can be described as: choose simultaneously two phase-change memory cells in 511 by the ranks code translator, then read functional circuit 720 by control signal 770 controls, after reading through a series of differentiation, to read the result is passed among the I/O, so far, realized the phase transition storage data storage and read.
The present invention is directed to the resistance drift of the unit in the phase transition storage, carry out simultaneously write operation and read operation take two phase change cells as unit, in the write operation process, in conjunction with the data that will write, write the many-valued state of driving circuit reasonable combination phase-change memory cell, in the read operation process, utilize the read out function circuit to finish the algorithm circuit that is generated the discriminant value of the many-valued state of phase change cells by the resistance of phase change cells, accurately read again the many-valued state of phase change cells in conjunction with sense amplifier (SA).
The present invention provides solution for the drift of one of the key issue that exists in multistage storage resistance.The present invention has taken into account the requirement of phase transition storage to high density and reliability.Wherein, simply effective as the read out function circuit algorithm circuit of key component, and finish simultaneously two phase change cells read operations, on the few of impact of the speed of phase transition storage.
Above-mentioned description to embodiment is can understand and apply the invention for ease of those skilled in the art.The person skilled in the art obviously can easily make various modifications to these embodiment, and needn't pass through performing creative labour being applied in the General Principle of this explanation among other embodiment.Therefore, the invention is not restricted to the embodiment here, those skilled in the art should be within protection scope of the present invention for improvement and modification that the present invention makes according to announcement of the present invention.
Claims (6)
1. phase transition storage multilevel memory system is characterized in that: this system comprises the phase change memory array (510), the line decoder (520) that links to each other with described phase change memory array, the column decoder (530) that are made of several phase-change memory cells (511,512), writes driving circuit (730) and read out function circuit (720); Described ranks code translator (520,530) is used for choosing described phase-change memory cell; Then write driving circuit (750) by control signal (770) control and write corresponding data by control signal (770) at affiliated phase-change memory cell; Described read out function circuit (720) is being passed in the I/O mouth (760) through reading the result after the discriminating step by control signal (770).
2. a kind of phase transition storage multilevel memory system as claimed in claim 1 is characterized in that: described read out function circuit (720) comprises sense amplifier (610), the discriminant value generation module (620) that is connected with described sense amplifier output terminal that gathers the signal that transmits on the described phase-change memory cell and another sense amplifier (630) that is connected with discriminant value generation module output terminal.
3. a kind of phase transition storage multilevel memory system as claimed in claim 1 or 2, it is characterized in that: the phase-change storage material in the affiliated phase-change memory cell is the chalcogenide compound alloy; Its gate tube is metal-oxide-semiconductor, bipolar transistor or diode.
4. multistage storage means of phase transition storage is characterized in that: the read-write operation that consists of two phase-change memory cells (511,512) of a unit carries out simultaneously.
5. the multistage storage means of a kind of phase transition storage as claimed in claim 4, it is characterized in that: the method may further comprise the steps:
Write: choose phase-change memory cell by the ranks code translator, then write driving circuit by control signal control and write corresponding data at phase-change memory cell, choose again another phase-change memory cell of same unit with column decoder, same pass through control signal control and write driving circuit and write corresponding data at described another phase-change memory cell; Described control signal is that two phase-change memory cells are carried out the signal exported after the rational combinations of states;
Read: choose simultaneously two phase-change memory cells by the ranks code translator, then by control signal control read out function circuit, after through the discriminant value generation module, generate the condition discrimination value and output in the read out function circuit, outputted results in the I/O mouth by the read out function circuit at last;
6. the multistage storage means of a kind of phase transition storage as claimed in claim 5, it is characterized in that: in the described read operation, the generation method formula of condition discrimination value is as follows:
Vref2′＝V2+ΔV1
Vref3′＝Vref3+α*(V2+ΔV1)
Wherein, Δ V1 is a constant, and α is a constant, and less than 1.
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| CN106328204A (en) * | 2015-07-01 | 2017-01-11 | 中芯国际集成电路制造(上海)有限公司 | Selection gate driving circuit of memory, and control apparatus and control method of selection gate driving circuit |
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| CN108665925B (en) * | 2018-04-25 | 2020-08-04 | 华中科技大学 | Read-write method and system based on multi-level storage type phase change memory |
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