CN101329908A - Phase-change memory for high speed complementation unit - Google Patents

Phase-change memory for high speed complementation unit Download PDF

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Publication number
CN101329908A
CN101329908A CNA2008100409516A CN200810040951A CN101329908A CN 101329908 A CN101329908 A CN 101329908A CN A2008100409516 A CNA2008100409516 A CN A2008100409516A CN 200810040951 A CN200810040951 A CN 200810040951A CN 101329908 A CN101329908 A CN 101329908A
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China
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phase
resistance
memory
high speed
phase change
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CNA2008100409516A
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宋志棠
富聪
陈邦明
封松林
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Shanghai Institute of Microsystem and Information Technology of CAS
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Shanghai Institute of Microsystem and Information Technology of CAS
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Priority to CNA2008100409516A priority Critical patent/CN101329908A/en
Publication of CN101329908A publication Critical patent/CN101329908A/en
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Abstract

The invention discloses a high speed complementary unit phase-change memory. Every memory unit in the memory is provided with two components used for storing information and the components can be written; the resistance of the two components is compared and taken as a basis for dividing different memory statues. The high speed complementary unit phase-change memory of the invention can speed up memory reading speed, increase reading surplus capacity, reduce the cumulative effect of reading current or voltage and the effect of technique and layout planning over the phase-change memory. Meanwhile, the memory of the invention can reduce the effect of the change of resistance on the phase-change unit on rightly reading memory data after multiple times of reading operation or writing operation.

Description

Phase-change memory for high speed complementation unit
Technical field
The invention belongs to technical field of semiconductor memory, relate to a kind of storer, relate in particular to a kind of phase-change memory for high speed complementation unit.
Background technology
The phase transition storage technology is based on Ovshinsky at late 1960s (Phys.Rev.Lett., 21,1450~1453,1968) beginning of the seventies (Appl.Phys.Lett., 18,254~257,1971) phase-change thin film of Ti Chuing can be applied to that the conception of phase change memory medium sets up, and is the memory device of a kind of low price, stable performance.Phase transition storage can be made on the silicon wafer substrate, its critical material is that the research focus of recordable phase-change thin film, heating electrode material, thermal insulation material and extraction electrode material also just launches around its device technology: the physical mechanism research of device comprises how reducing device material etc.The ultimate principle of phase transition storage is to utilize electric impulse signal to act on the device cell, make phase-change material between amorphous state and polycrystalline attitude, reversible transition take place, low-resistance when high resistant during by the resolution amorphous state and polycrystalline attitude can realize writing, wipe and read operation of information.
Phase transition storage owing to have reads at a high speed, high erasable number of times, non-volatile, advantages such as component size is little, strong motion low in energy consumption, anti-and radioresistance, is thought flash memories that most possible replacement is present by international semiconductor TIA and becomes following storer main product and become the device of commercial product at first.
The reading and writing of phase transition storage, wiping operation apply the voltage or the current pulse signal of different in width and height exactly on device cell: wipe operation (RESET), after phase-change material temperature in adding a weak point and strong pulse enable signal device cell is elevated to more than the temperature of fusion, through thereby cooling realization phase-change material polycrystalline attitude is to amorphous conversion fast, promptly one state is to the conversion of " 0 " attitude again; Write operation (SET), when apply one long and pulse enable signal phase-change material temperature medium tenacity is raised under the temperature of fusion, on the Tc after, and keep a period of time to impel nucleus growth, thus realize the conversion of amorphous state to the polycrystalline attitude, promptly " 0 " attitude is to the conversion of one state; Read operation behind the pulse signal that adds a little less than in the of, is read its state by the resistance value of measuring element unit.
The problem that phase transition storage also exists self needs to solve.First, find according to experiment, phase-change memory cell on same phase change memory chip, good inadequately and phase change cells and the equal reason of driving circuit distance owing to process consistency, RESET operation back high value distribute and SET after low resistance distribution all very extensive (high resistant 20k-500kOhm, low-resistance 1k-10kOhm), even the situation that the high resistant low resistance overlaps appears, the data that correctly read on the phase change cells are made a big impact, and a little less than the antijamming capability of circuit, reading speed is slow; Second, phase transition storage depends on Joule heat and changes its resistance states, find according to experiment, after phase-changing memory unit is carried out repeatedly read operation, " RESET " state of unit and the resistance of " SET " state all can increase along with the number of times of read operation and reduce, under traditional 1T1R and 1D1R structure, when low the arriving to a certain degree of phase change cells resistance value of " RESET " state, read error may take place, and the gap of high low resistance diminishes and also can have influence on the chip read margin.Three, after phase change cells is by RESET repeatedly or SET operation, the resistance situation of device own also can very complicated.
The 300 traditional phase transition storage circuit structure diagrams that are to use 1D1R among Fig. 3,301 is storage unit of a 1D1R, the 302nd, phase-change memory cell, the 303rd, DUMMY resistance, can realize that for example N trap resistance or polysilicon are realized by fixing resistance, also can go to realize by phase-change material.Under read operation, in DUMMY resistance and the array the phase-change memory cell resistance value compare, when the resistance of phase change cells is higher than DUMMY resistance, then difference sense amplifier 304 judges that phase change cells resistance is " RESET " state, otherwise, when the resistance of phase change cells is lower than DUMMY resistance, sense amplifier judges that phase change cells resistance is " SET " state.305 is read-write drive circuit, and 306 are column selection circuit passband and column decoder, and 307 is line decoder.
There are problems in the 1D1R storer of this kind traditional structure, first, because process deviation, and the distance of storage unit and driving circuit is unequal during chip layout, " RESET " of phase change cells, resistance value distribution under " SET " state is all wider, even the phenomenon that the resistance under the two states overlaps mutually can occur, and causes the storage errors of data.Second, because read operation needs a pulse signal, phase transformation meeting after read operation repeatedly among the 1R1D is along with the accumulation of read pulse signal, resistance value constantly reduces, after the resistance value under " RESET " is less than DUMMY resistance, will free data read errors, if use higher read operation voltage, perhaps higher read operation electric current, this phenomenon will be more serious.The 3rd, because after RESET repeatedly and the SET operation, it is very complicated that the resistance value of phase-change memory cell can become, and corresponding change can not take place in DUMMY resistance usually, so difficult more with relatively can becoming of DUMMY resistance.The problems referred to above are present in the 1T1R structure equally.
Summary of the invention
Technical matters to be solved by this invention is: provide a kind of storer of can accelerating to read speed, increase and read the phase-change memory for high speed complementation unit of allowance.
For solving the problems of the technologies described above, the present invention adopts following technical scheme:
A kind of phase-change memory for high speed complementation unit, each storage unit has two components and parts that are used for canned data in the described storer, and these components and parts have by the ability of writing; Resistance sizes by these two components and parts compares mutually, as the foundation of dividing different storage states.
As a preferred embodiment of the present invention, described components and parts are made of two diodes and two phase change resistor storage unit.In the described components and parts, resistance states of device stores that first diode and the first phase change resistor storage unit are formed, the opposite resistance states of device stores that second diode and the second phase change resistor storage unit are formed, and two phase change resistor storage unit can independently be write resistance.
As a preferred embodiment of the present invention, described two phase change cells storage is respectively two opposite resistance states, the data of storage 1bit.
As a preferred embodiment of the present invention, when described storer carries out read operation, reduce operating voltage or electric current that the phase transition storage read operation needs.
Beneficial effect of the present invention is: the present invention can accelerate storer and read speed, increases to read allowance, and reduces the cumulative effect and the technology of read current or voltage, and laying out pattern is to the influence of phase transition storage.Simultaneously, can also reduce repeatedly read operation and write operation after, resistance changes correctly reading the influence of resistance on the phase change cells.
Description of drawings
Fig. 1 is 2R2D memory cell structure figure.
Fig. 2 a, Fig. 2 b, Fig. 2 c are the implementation synoptic diagram of 2D2R storage unit.
Fig. 3 is traditional 1D1R phase change memory structure figure.
Fig. 4 is 2D2R phase change memory structure figure.
Fig. 5 is typical differential amplifier structural drawing.
Fig. 6 is the traditional 1R1T and the playback mode and the bit-line voltage comparison diagram of 2D2R structure.
Embodiment
Describe the preferred embodiments of the present invention in detail below in conjunction with accompanying drawing.
The present invention has disclosed a kind of phase-change memory for high speed complementation unit, comprises that the phase change cells of two gating diodes of use and two complementary states goes to replace a traditional gating diode and the data of a phase change cells storage 1bit, i.e. 2D2R structure.
Each storage unit has two components and parts that are used for canned data in the described storer, and these components and parts have by the ability of writing; Resistance sizes by these two components and parts compares mutually, as the foundation of dividing different storage states.
In the present embodiment, described components and parts are made of two diodes and two phase change resistor storage unit.Resistance states of device stores that first diode and the first phase change resistor storage unit are formed, the opposite resistance states of device stores that second diode and the second phase change resistor storage unit are formed, and two phase change resistor storage unit can independently be write resistance.Wherein, diode is the gating diode, and the phase change resistor storage unit is the phase change cells of complementary state.Described two phase change cells storage is respectively two opposite resistance states, the data of storage 1bit.
See also Fig. 1, Fig. 1 has disclosed 2D2R storage unit 100 of the present invention, comprises phase- change memory cell 101a and 101b, gating diode 102a and 102b, phase-change material top electrode 103a and 103b, word line WL, bit line BL and BLn.WL is the word line of normal memory, and BL and BLn are the bit lines of normal memory.The data of two phase change cells 101a and two complementations of 101b storage, for example when 101a is " RESET " state when, 101b is " SET " state, promptly stores the data of 1bit with two phase change cells, so be called the 2D2R structure.Fig. 2 a, Fig. 2 b, Fig. 2 c are other implementations of 2D2R.
400 are to use 2D2R to store the phase change memory structure of 1bit data among Fig. 4,401 is storage unit of a 1D1R, the 402nd, phase-change memory cell, the 403rd, with the difference sense amplifier of comparison resistance size, the 404th, read-write drive circuit, 405 are column selection circuit passband and column decoder, and 406 is line decoder.407 is a pair of 2D2R storage unit, store the state of a pair of opposed complementary, for example in two complementary phase change cells, first is " RESET " state, then another is " SET " state, this moment, what think memory stores was " RESET " state, and when first be " SET " state, second what think then that this a pair of phase change cells stores for " RESET " was " SET " state.2D2R has overcome the shortcoming of the traditional 1D1R among Fig. 3.First, because the structure of 2D2R is the data of storage 1bit in two phase change cells of facing mutually, the phase change cells of two complementations compares mutually when data are read, then can eliminate because process deviation, and the distance of storage unit and driving circuit is unequal during chip layout, the phase change cells resistance deviation that causes.The second, in normal operating process, the phase change cells of two complementations has necessarily experienced the read operation of same number, and both resistance can reduce simultaneously, can effectively reduce the influence of the cumulative effect of read operation to phase change resistor.The 3rd, because write operation carries out a pair of complementation unit, and be that both compare mutually when reading, increase and wear out along with writing number of times so can reduce in the 1D1R structure storage unit, the problem that DUMMY does not but change has thereupon improved the global reliability of device.
Fig. 5 is a typical differential amplifier structural drawing, and upward voltage is greater than the voltage on the BLkn as BLk, and Data_out exports high level, on the contrary output low level.
Fig. 6 is the traditional 1R1T and the playback mode and the bit-line voltage comparison synoptic diagram of 2D2R structure.Wherein Vmin is the minimum voltage difference that amplifier 403 is correctly read BLk and the last data of BLkn among Fig. 4.Δ V is the allowance of reading of this circuit, and VBLk_read is the high operation voltage on the word line in the read operation, Td be the 2D2R structure with respect to the 1D1R structure, the delay that reduces when reading.
Because in the structure of 2D2R, voltage difference is the twice of voltage difference between BLk and the VREF in the 1D1R structure between BLk and the BLkn, thus can reach the Vmin that amplifier needs earlier, thus fast speeds is arranged, and read the twice that allowance also is 1D1R.Simultaneously, 2D2R realizes that reading among the 1D1R postpones and read allowance, only needs to use half read operation voltage or the operating current of 1D1R, can effectively reduce since read pulse to the change of phase change cells resistance.
In addition, for reducing of the influence of read operation cumulative effect, when described storer carries out read operation, reduce operating voltage or electric current that the phase transition storage read operation needs to phase-change material resistance.
The present invention is with respect to traditional 1D1R structure, reading speed is faster arranged, the bigger allowance of reading, and reduced since process consistency and laying out pattern to the influence of phase change cells stability, after also can reducing repeatedly read operation and write operation, resistance changes correctly reading the influence of resistance on the phase change cells.
Above embodiment is the unrestricted technical scheme of the present invention in order to explanation only.Any modification or partial replacement that does not break away from spirit and scope of the invention all should be encompassed in the middle of the claim scope of the present invention.

Claims (5)

1, a kind of phase-change memory for high speed complementation unit is characterized in that: each storage unit has two components and parts that are used for canned data in the described storer, and these components and parts have by the ability of writing; Resistance sizes by these two components and parts compares mutually, as the foundation of dividing different storage states.
2, phase-change memory for high speed complementation unit according to claim 1 is characterized in that: described components and parts are made of two diodes and two phase change resistor storage unit.
3, phase-change memory for high speed complementation unit according to claim 2, it is characterized in that: in the described components and parts, resistance states of device stores that first diode and the first phase change resistor storage unit are formed, the opposite resistance states of device stores that second diode and the second phase change resistor storage unit are formed, and two phase change resistor storage unit can independently be write resistance.
4, phase-change memory for high speed complementation unit according to claim 1 is characterized in that: described two phase change cells storage is respectively two opposite resistance states, the data of storage 1bit.
5, according to claim 1 or 2 or 3 or 4 described phase-change memory for high speed complementation unit, it is characterized in that: when described storer carries out read operation, reduce needed minimum operation voltage of single phase change resistor read operation or electric current.
CNA2008100409516A 2008-07-24 2008-07-24 Phase-change memory for high speed complementation unit Pending CN101329908A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110428861A (en) * 2019-09-12 2019-11-08 上海明矽微电子有限公司 A method of reducing eeprom memory area

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110428861A (en) * 2019-09-12 2019-11-08 上海明矽微电子有限公司 A method of reducing eeprom memory area

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Open date: 20081224