JPWO2008035392A1 - Semiconductor integrated circuit device - Google Patents

Abstract

For example, when the phase change element in the memory cell provided at the intersection of the word line WL0 and the bit line BL0 is brought into an amorphous state by a reset operation, the rise time trb / fall of the bit line BL0 The time tfb is configured to be longer than the rise time trw / fall time tfw of the word line WL0. At this time, the rapid cooling of the phase change element necessary for the reset operation is performed using the fall time tfw of the word line WL0. By using such a configuration and operation, disturb current IBL01 for the phase change element in the non-selected memory cell provided at the intersection of bit line BL0 and word line WL1 is reduced, and the reliability of the phase change memory is improved. .

Description

  The present invention relates to a semiconductor integrated circuit device, and more particularly to a memory cell that discriminates stored information using a difference in resistance value, for example, a high-density integrated memory circuit including a memory cell using a phase change material, or a memory circuit and The present invention relates to a technology effective when applied to a logic-embedded memory in which a circuit is provided on the same semiconductor substrate or a semiconductor integrated circuit device having an analog circuit.

  The non-volatile memory market has grown significantly, driven by demand for mobile devices such as mobile phones. A typical example is a FLASH memory, which is used as a programmable ROM because of its inherently low speed. On the other hand, a high-speed RAM is required as a working memory, and both FLASH and DRAM memories are mounted on portable devices. If an element having the characteristics of these two memories can be realized, not only will it be possible to integrate FLASH and DRAM on one chip, but the impact will be extremely large in that all semiconductor memories will be replaced. .

One candidate for realizing the element is a nonvolatile memory using a phase change film. The phase change memory is sometimes called PRAM (Phase change RAM) or OUM (Ovonic Unified Memory). As already known, phase change memory cells use materials that can be reversibly switched from one phase to another. These phase states can be read out depending on the difference in electrical characteristics. For example, these materials can change between a disordered phase in the amorphous state and an ordered phase in the crystalline state. The amorphous state has a higher electrical resistance than the crystalline state, and information can be stored using the difference in electrical resistance. A suitable material for the phase change memory cell is an alloy containing at least one element of sulfur, selenium, and tellurium called chalcogenide. At present, the most promising chalcogenide is an alloy (Ge ₂ Sb ₂ Te ₅ ) made of germanium, antimony and tellurium, and is already widely used for information storage units in rewritable optical disks.

  As described above, information is stored by using a difference in phase state of chalcogenide. The phase change is obtained by locally raising the temperature of the chalcogenide. At 70 ° C. or lower or 130 ° C. or lower, both phases are stable and information is retained. The 10-year data retention temperature for chalcogenides is generally 70-130 ° C., depending on the composition. Holding for 10 years above this temperature causes a phase change from an amorphous state to a thermodynamically stable crystalline state. When the chalcogenide is held at a crystallization temperature of 200 ° C. or higher for a sufficient time, the phase changes and becomes a crystalline state. The crystallization time varies depending on the composition of chalcogenide and the temperature to be held. In the case of Ge2Sb2Te5, it is 150 nanoseconds, for example. In order to return the chalcogenide to an amorphous state, the temperature is raised to the melting point (about 600 ° C.) or more and then rapidly cooled.

  As a method of raising the temperature, there is a method in which an electric current is passed through the chalcogenide and heated by Joule heat generated from the chalcogenide inside or from an adjacent electrode. Hereinafter, crystallizing the chalcogenide of the phase change memory cell is referred to as a set operation, and making it amorphous is referred to as a reset operation. The state in which the phase change portion is crystallized is referred to as a set state or a crystalline state, and the state in which it is amorphized is referred to as a reset state or an amorphous state. The set time is, for example, 150 nanoseconds, and the reset time is, for example, 50 nanoseconds.

  A read operation (hereinafter referred to as a read operation) is as follows. By applying a voltage to the chalcogenide and measuring the current passing through it, the resistance of the chalcogenide is read to identify the information. At this time, if the chalcogenide is in the set state, even if the temperature is raised to the crystallization temperature, the chalcogenide has been crystallized from the beginning, so that the set state is maintained. However, in the reset state, information is destroyed. Therefore, the read voltage must be a very small voltage such as 0.3 V so as not to cause crystallization. The feature of the phase change memory is that the resistance value of the phase change part varies by 2 to 3 digits depending on whether it is crystalline or non-crystalline, and this resistance value corresponds to binary information '0' and '1' Therefore, the sensing operation is easy and the reading is fast because the resistance difference is large. Furthermore, multivalue storage can be performed by corresponding to information of ternary or higher.

  In addition, the structure of the phase change memory cell is usually composed of an information storage unit and a selection transistor, but a cross-point type memory cell having no selection transistor is also conceivable. The information storage unit includes a chalcogenide, an upper electrode and a lower electrode sandwiching the chalcogenide. Generally, the lower electrode has a plug structure having a smaller contact area with the chalcogenide than the upper electrode.

Non-Patent Document 1 describes a general operation of the phase change memory cell as described above. The reset operation is performed by starting the word line and applying a current pulse having a pulse width of 20 to 50 nanoseconds to the bit line. The set operation is performed by starting the word line and applying a current pulse having a pulse width of 60 to 200 nanoseconds to the bit line. The read operation is performed by starting the word line and applying a current pulse having a pulse width of 20 to 100 nanoseconds to the bit line. In such an operation, a method of controlling the reset current using a word line has been proposed as described in FIG. Non-Patent Document 2 describes that the characteristics of an irregular solid such as an amorphous semiconductor can be expressed by an equivalent circuit based on a CTRW (continuous-time random-walk) approximation.
JP 2005-260014 A “2004 IEEE International Solid-State Circuits Conference, Digest of Technical Papers”, p. 40-41 “Universality of dynamic electric conduction in disordered systems”, Applied Physics, 1996, Vol. 65, No. 3, p. 256-260

  The memory cell of the phase change memory as described above has a configuration as shown in FIG. 16, for example. FIG. 16 is a circuit diagram showing a configuration example around the memory cell in the semiconductor integrated circuit device studied as a premise of the present invention. Memory cell MC includes a selection element SW and a phase change element R. As the selection element SW, it is preferable to use an NMOS transistor having a good process compatibility as a microcomputer mixed memory and a large driving capability. The NMOS transistor has a larger drive current than the PMOS transistor. At this time, the current flowing through the phase change element R flows from the bit line BL toward the source line SL.

  In FIG. 16, the phase change element R is placed between the selection element SW and the bit line BL. When the selection element SW is placed between the phase change element R and the bit line BL, the source potential of the SW rises compared to the source line SL, so that the current drive capability of the SW is lower than the arrangement of FIG. . In that case, in order to secure the same reset current, the gate width of the selection element SW has to be increased, which causes a problem that the memory cell area increases. Therefore, the phase change element R is preferably placed between the selection element SW and the bit line BL.

  FIG. 17 is a waveform diagram showing an example of the operation of the semiconductor integrated circuit device of FIG. In FIG. 17, for example, the memory cell MC00 is selected and the reset operation, the set operation, and the read operation are performed, and the memory cell MC01 is not selected. However, when a pulse having a rectangular waveform is applied to the bit line BL0 during the operation of MC00, the memory cell MC01 connected to the same bit line BL0 is affected.

  That is, the voltage of the word line WL1 connected to MC01 is 0V and is not selected. Therefore, the selection element SW01 is turned off and the drain current ID01 does not flow. However, if the phase change element R01 of MC01 is in the reset state, the equivalent circuit of R01 uses a CTRW approximation described in Non-Patent Document 2, and a pair of a capacitor and a resistor as shown in FIG. It becomes a connected circuit. Therefore, R01 accumulates electric charges, and as a result, as shown in FIG. 17, a current IBL01 is generated with respect to R01 when the bit line BL0 rises / falls. In a practical process, a capacitive interface layer may be formed between the phase change element R and the selection element SW. In this case, the current IBL01 is generated similarly.

  When such a current IBL01 is generated, the data retention characteristic of the memory cell MC01 is degraded. A semiconductor memory is generally required to retain data for 10 years at a temperature of 70 to 120 ° C. On the other hand, the 10-year data retention temperature of amorphous chalcogenide is generally 70 to 130 ° C., depending on the composition, but has a margin of 10 ° C. on the high temperature side. Therefore, in order to ensure the data retention characteristic, it is necessary to minimize the current flowing through the non-selected memory cell in the reset state.

  19 and 20 are diagrams for explaining the contents of experiments conducted by the present inventors in order to investigate the influence of disturbance on unselected memory cells. The operation as shown in FIG. 20 was performed on a TEG (Test Element Group) having a circuit as shown in FIG. The memory cell MC shown in FIG. 19 includes a selection element SW and a phase change element R, and the source line SL is set to 0V and the word line WL is set to 0.1V. The selection element SW is an NMOS transistor, and its threshold voltage is 0.2 to 0.4 V, and is off. Normally, the current that flows when 3 V is applied to the drain of the selection element SW is 100 nanoamperes or less, and even if such a current is applied, the resistance of the phase change element R does not change.

  Therefore, as shown in FIG. 20, a pulse having an amplitude of 3 V, a pulse width of 30 nanoseconds, a rising width of 2 nanoseconds, and a falling width of 2 nanoseconds was applied to the bit line BL. There are a plurality of types of definitions of the rise time and the fall time. Here, the time until the pulse amplitude transitions from 10% (0.3 V) to 90% (2.7 V) and the pulse amplitude is 90%. % (2.7V) to 10% (0.3V) transition time. And such a pulse was applied 100,000 times continuously.

  FIG. 21 is a diagram illustrating an example of the experimental results of FIGS. 19 and 20. FIG. 21 shows the resistance value of the TEG immediately after resetting and the resistance value of the TEG after performing a disturb test in which 100,000 pulses are applied. By conducting the disturb test, the resistance value increased by an order of magnitude or more. The voltage required for the set operation increases after the resistance rises, and it is difficult to shift to the set state in the normal set operation. In addition, when the current flows through the phase change element R, the data retention characteristics of the phase change memory at a high temperature deteriorate, the reset state is easily destroyed, and information may be lost by changing to the set state. As described above, when the bit line BL is driven by the rectangular wave-shaped pulse, there is a concern that the reliability of the phase change memory may be lowered due to the current flowing through the non-selected memory cells MC connected to the bit line. .

  The present invention has been made in view of such problems. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  A semiconductor integrated circuit device according to the present invention includes a word line and a bit line, a phase change element (storage element) having one end connected to the bit line, and a first transistor connected to the other end of the storage element and controlled by the word line When the memory element is written in a high resistance state, the rise / fall time of the bit line is longer than that of the word line. As a result, disturbance to non-selected storage elements connected to the same bit line is reduced, and the reliability of the phase change memory can be improved. Similarly, when the memory element is written in a low resistance state, the reliability of the phase change memory can be improved by lengthening the rise / fall time of the bit line.

  Note that when the memory element is written in a high resistance state, the memory element needs to be rapidly cooled. This rapid cooling can be realized by using the falling edge of the word line. Further, as a specific means for extending the rise / fall time of the bit line, for example, a capacitive element is provided in the write circuit connected from the bit line via the bit line selection switch (second transistor), There is a system in which CR delay is generated by connecting this capacitive element when writing. Another example is a method of designing the writing circuit with a low driving capability. When the latter is used, the circuit area can be reduced compared to the former.

  In the latter case, more specifically, for example, the driving capability (for example, gate width) of a write switch (third transistor) that is provided in the write circuit and outputs a voltage or a current at the time of writing is set to a bit line selection switch (first It is preferable to make it smaller than the driving capability (for example, gate width) of two transistors. This maintains high speed during the read operation and reduces the disturbance to the non-selected storage elements connected to the same bit line, thereby improving the reliability during the write operation. The disturbance to the non-selected memory element becomes more obvious when a capacitive interface layer for increasing thermal efficiency is formed at the connection portion on the first transistor side of the memory element. If the configuration as described above is applied to a simple configuration, it becomes more effective.

  Further, as described above, in the method of increasing the rise / fall time of the bit line by adjusting the driving capability of the writing circuit, the same writing is performed when the storage element is set to the high resistance state and to the low resistance state. A circuit can be used to output the same voltage value toward the bit line. In this case, currents with different magnitudes may be supplied to the memory element by using different word line voltage values for the high resistance state and the low resistance state. Thus, by realizing writing in a high resistance state and writing in a low resistance state with a common writing circuit, the circuit area can be further reduced.

  If the effect obtained by the representative one of the inventions disclosed in the present application is briefly described, the reliability of the phase change memory can be improved.

1 is a circuit diagram showing a configuration example of a part around a memory cell in a semiconductor integrated circuit device according to a first embodiment of the present invention; FIG. 2 is a waveform diagram showing an example of operation of the semiconductor integrated circuit device of FIG. 1. FIG. 2 is a main part layout diagram illustrating a configuration example of a memory cell array including the memory cell of FIG. 1. FIG. 4 is a cross-sectional view of a main part illustrating a manufacturing process of the memory cell array of FIG. 3 in stages and illustrating a configuration example between X and X ′ in FIG. 3 in each stage. FIG. 4 is a cross-sectional view of a main part illustrating a manufacturing process of the memory cell array of FIG. 3 in stages and illustrating a configuration example between X and X ′ in FIG. 3 in each stage. FIG. 4 is a cross-sectional view of a main part illustrating a manufacturing process of the memory cell array of FIG. 3 in stages and illustrating a configuration example between X and X ′ in FIG. 3 in each stage. FIG. 4 is a cross-sectional view of a main part illustrating a manufacturing process of the memory cell array of FIG. 3 in stages and illustrating a configuration example between X and X ′ in FIG. 3 in each stage. FIG. 6 is a circuit diagram showing an example of the configuration of a semiconductor integrated circuit device according to a second embodiment of the present invention. FIG. 9 is a waveform diagram showing an example of operation of the semiconductor integrated circuit device of FIG. 8. FIG. 10 is a circuit diagram showing an example of the configuration of a semiconductor integrated circuit device according to a third embodiment of the present invention. FIG. 11 is a waveform diagram showing an example of the operation of the semiconductor integrated circuit device of FIG. 10. FIG. 10 is a circuit diagram showing an example of the configuration of a semiconductor integrated circuit device according to a fourth embodiment of the present invention. FIG. 13 is a waveform diagram showing an example of operation of the semiconductor integrated circuit device of FIG. 12. FIG. 10 is a circuit diagram showing a configuration example of a memory cell included in a semiconductor integrated circuit device according to a fifth embodiment of the present invention. FIG. 16 is a circuit diagram showing a configuration example of a memory cell included in a semiconductor integrated circuit device according to a sixth embodiment of the present invention. 1 is a circuit diagram showing a configuration example around a memory cell in a semiconductor integrated circuit device studied as a premise of the present invention. FIG. 17 is a waveform diagram showing an example of operation of the semiconductor integrated circuit device of FIG. 16. It is an equivalent circuit diagram showing a memory element in an amorphous state. It is a figure explaining the content of the experiment which the present inventors etc. conducted in order to investigate the influence of disturbance of a non-selected memory cell. It is a figure explaining the content of the experiment which the present inventors etc. conducted in order to investigate the influence of disturbance of a non-selected memory cell. It is a figure which shows an example of the experimental result of FIG. 19 and FIG.

  Several preferred examples of the semiconductor device according to the present invention will be described below with reference to the drawings. In the drawing, the PMOS transistor is distinguished from the NMOS transistor by adding an arrow symbol to the gate. In the drawing, the connection of the substrate potential of the MOS transistor is not specified, but the connection method is not particularly limited as long as the MOS transistor can operate normally. In this specification, the reset state is low level 'L' (or '0') and the set state is high level 'H' (or '1'). Of course, the reset state is 'H' and set state. Can be set to 'L'.

(Embodiment 1)
As described above, the cause of disturbance of unselected memory cells is that when the voltage of the bit line changes, the current is connected to the same bit line and the word line flows to different memory cells. As a solution to this, in the first embodiment, the charge / discharge time of the capacitive component included in the phase change element is lengthened by reducing the speed of the voltage change of the bit line. As a result, the peak current can be reduced, so that the heat generated by the non-selected memory cells is reduced by thermal diffusion, and the influence of disturbance can be reduced.

  FIG. 1 is a circuit diagram showing a configuration example of a part around a memory cell in the semiconductor integrated circuit device according to the first embodiment of the present invention. In FIG. 1, the semiconductor integrated circuit device includes a bit line BL0, a plurality of word lines WL0 and WL1 corresponding to the BL0, and memory cells MC00 and MC01 arranged at intersections of these word lines and bit lines, respectively. It is out. Memory cell MC00 includes selection element SW00 and phase change element R00. The phase change element R00 is connected between the selection element SW00 and the bit line BL0. When the SW00 is controlled to be turned on by the word line WL0, a current flows from BL0 to the source line SL0 serving as one end of SW00 via R00. A path is formed. Similarly, the memory cell MC01 includes a selection element SW01 and a phase change element R01, which is connected between the selection element SW01 and the bit line BL0, and the selection element SW01 is controlled by the word line WL1.

  FIG. 2 is a waveform diagram showing an example of the operation of the semiconductor integrated circuit device of FIG. Here, a case where the memory cell MC00 is operated is taken as an example. At this time, the bit line BL0 and the word line WL0 are driven, and the other bit lines and the word line remain fallen. When performing the reset operation, the bit line BL0 is first raised. The rise time trb at this time is made longer than the rise time trw of a word line WL0 described later. Next, the word line WL0 is raised, and a current is passed through the phase change element R00 to melt it. Thereafter, the word line WL0 is lowered to rapidly cool R00 and make it amorphous. At this time, the fall time tfw of the word line WL0 needs to be shortened for convenience of rapid cooling. Thereafter, the bit line BL0 is lowered. The fall time tfw at this time is made longer than the fall time tfw of the word line WL0. Since the phase change element is not rapidly cooled by lowering the bit line, the fall time of the bit line need not be short.

  Thus, by increasing the rise time and fall time of the bit line BL0, the charge / discharge current IBL01 flowing through the phase change element R01 of the non-selected memory cell MC01 can be reduced. In addition, since the rapid cooling necessary for the reset operation is performed by using the fall of the word line WL0, the reset operation can be performed without any problem even if the fall time of the bit line BL0 is lengthened. Therefore, it is possible to reduce the influence of disturbance while ensuring a reliable memory operation, and to improve the reliability of the phase change memory.

  Normally, the current flowing through the bit line BL0 is the largest during the reset operation, and therefore, it is most effective to reduce the charge / discharge current IBL01, especially by increasing the rise / fall time of BL0 during the reset operation. Of course, it is of course also beneficial to increase the rise / fall time during the set operation. In FIG. 2, similarly to the reset operation, the rise / fall time of the bit line BL0 is longer than the rise / fall time of the word line WL0 during the set operation. In this case, the timing at which a voltage is applied to the phase change element R00 with the set operation may be defined by the word line WL0 or the bit line BL0. In addition, the voltage value applied to the phase change element R00 is determined here by the voltage value of the bit line BL0.

  FIG. 3 is a main part layout diagram showing a configuration example of a memory cell array including the memory cell of FIG. In the memory array shown in FIG. 3, a plurality of word lines WL are arranged in parallel, and a plurality of bit lines BL are arranged in parallel in a direction perpendicular thereto. A plug electrode PLG is provided on one side across a word line WL, and a source line SL is provided on the other side. The plug electrode PLG is located below the bit line BL in a cross-sectional structure, and a phase change element (not shown) is connected to the plug electrode PLG. As the interval between the source line SL and the bit line BL, an optimum distance is selected according to the drive current of the memory cell.

  Next, an example of a method for manufacturing the memory cell array in FIG. 3 will be described. 4 to 7 show the manufacturing process of the memory cell array of FIG. 3 step by step, and are principal part cross-sectional views showing a configuration example between X and X ′ of FIG. 3 in each step. First, the structure shown in the cross-sectional view of the main part of FIG. In the structure shown in FIG. 4, the diffusion layer DF is separated by the field oxide film ISL1. The gate electrode GT is in contact with the gate insulating film ISL2, the sidewall SDW, and the metal silicide SS. An adhesion layer (barrier layer) BR1 is formed in order to improve adhesion between the contact CNT1 and the interlayer insulating film ISL3 and prevent peeling. A metal wiring layer M1 is formed on the contact CNT1.

  Next, a contact hole toward the metal wiring layer M1 is formed in the interlayer insulating film ISL3, and an adhesion layer BR2 and a plug electrode PLG are formed by chemical vapor deposition (CVD). The plug electrode PLG selects a material that forms a non-ohmic contact with the chalcogenide. In addition, by using a plug material having a high thermal resistance, the diffusion of Joule heat from the plug can be prevented, and the power required for rewriting can be reduced. TiN (titanium nitride) can be used as the composition of the adhesion layer BR2, and W (tungsten) can be used as the composition of the plug electrode PLG.

Subsequently, as shown in FIG. 5, an interface layer L may be formed between the plug electrode PLG and the adhesion layer BR2 and the chalcogenide CN. The interface layer L has an electric resistance higher than that of the plug electrode PLG, and efficiently converts current to Joule heat as a heater during the rewriting operation. The interface layer L can also be used as an adhesive layer. The interface layer L has a good adhesive force with the interlayer insulating film ISL3, the plug electrode PLG, and the chalcogenide CN, peeling of the chalcogenide in the manufacturing process, generation of a depletion portion in the chalcogenide, and formation of a depletion portion in the chalcogenide during the memory cell operation. Generation can be prevented. As a result, the manufacturing yield and the reliability associated with rewriting are improved. Examples of the interface layer L include capacitive materials such as Ta ₂ O ₅ (tantalum oxide).

  Further, a chalcogenide CN serving as a phase change element and the upper electrode U are formed by sputtering or vacuum deposition to form an interlayer insulating film ISL4. As the composition of the chalcogenide CN, for example, a Ge—Sb—Te alloy having a wide track record in a recordable optical disk, or an alloy obtained by adding an additive to the alloy is suitable.

  Thereafter, as shown in FIG. 6, a contact hole is formed, and an adhesion layer BR3 and a contact CNT2 with the bit line are formed by chemical vapor deposition (CVD). Further, as shown in FIG. 7, the adhesion layer BR4 is formed, and the bit line BL is formed by sputtering. Subsequently, by forming an interlayer insulating film ISL5 and further forming an upper wiring, a desired memory can be manufactured.

  Such a manufacturing method can be manufactured according to a normal CMOS logic mixed design rule, and is also suitable for manufacturing a logic embedded memory. Further, as described with reference to FIG. 5, when the interface layer L is formed, the charge / discharge current flowing through the phase change element of the non-selected memory cell described above may be increased. Therefore, a more beneficial effect can be obtained by applying the operation of increasing the rise / fall time as described in FIG. 2 to the configuration including such an interface layer.

  As described above, by using the semiconductor integrated circuit device according to the first embodiment, the reliability of the phase change memory can be improved. In particular, when the phase change memory includes an interface layer between the chalcogenide and the plug electrode, the reliability of the phase change memory can be improved.

(Embodiment 2)
In the second embodiment, an example of a circuit configuration that realizes the function of extending the rise / fall time described in the first embodiment will be described. FIG. 8 is a circuit diagram showing an example of the configuration of the semiconductor integrated circuit device according to the second embodiment of the present invention. The semiconductor integrated circuit device shown in FIG. 8 includes a memory array unit ARY, an X-system address decoder X-DEC, a Y-system address decoder Y-DEC, and a read / write circuit RWC. The memory array unit ARY includes a plurality of word lines WL0 to WLn, a plurality of bit lines BL0 to BLm, and a plurality of memory cells MC00 to MCnm provided at the intersections of the word lines and the bit lines. Actually, in addition to this, for example, a plurality of source lines SL0 to SLm may be included in pairs with a plurality of bit lines BL0 to BLm, but here, the source line SL is omitted and the ground GND is omitted. It is said.

  Each of the memory cells MC00 to MCnm has the same configuration except that the corresponding word line and bit line are different from each other, and therefore the configuration will be described by taking the memory cell MC00 as an example. The memory cell MC00 includes a selection element MN00 and a storage element R00. The memory element R00 is a phase change element, and has a low resistance of, for example, 1 kΩ to 10 kΩ in the crystalline state, and has a high resistance of, for example, 100 kΩ to 100 MΩ in the amorphous state. The selection element MN00 is an NMOS transistor. The gate electrode of the selection element MN00 is connected to the word line WL0, the drain electrode is connected to one end of the storage element R00, and the source electrode is connected to the source line (ground GND). The other end of the storage element R00 is connected to the bit line BL0. Here, a MOS transistor is used as the selection element MN00, but a bipolar transistor may be used instead. In this case, since the selection element of the phase change memory cell cannot be formed at the same time as the logic circuit of the microcomputer, there is a problem that the manufacturing cost rises as a microcomputer-embedded memory, but since the driving capability per area of the selection element is large, the memory cell There is an advantage that the area can be reduced.

  Each word line WL0 to WLn is connected to an X-system address decoder X-DEC, and one word line WL is selected by an X-system address signal generated by the X-DEC. A Y-system address decoder Y-DEC is connected to one end of the bit line BL, and one of the bit line selection switches YS0 to YSm is selected by a Y-system address signal generated by the Y-DEC, and the bit line BL The line BL is connected to an RWC described later via the node N1. Here, one read / write circuit RWC is provided for each memory array unit ARY, but a plurality of RWCs may of course be provided. In this case, since writing / reading operations can be performed simultaneously on a plurality of bits, there is an effect that high-speed operation is possible.

  The read / write circuit RWC includes a read current source Ird and a read switch RSW, a set current source Iset and a set switch SS-SW, a reset current source Irst and a reset switch RS-SW, and a sense amplifier SA. It is out. Further, the RWC includes a capacitor Cwt and a capacitor addition switch WC-SW, and a ground switch GSW. RSW, SS-SW, and RS-SW are switches that connect Ird, Iset, and Irst to the node N1, respectively. The node N1 is connected to the corresponding bit line when the bit line selection switch YS is selected. Connected. Note that voltages Vrd, Vset, and Vrst are respectively supplied to one ends of the Ird, Iset, and Irst that are different from the switch side. When the sense amplifier enable signal SE is activated, the sense amplifier SA amplifies the read signal of the selected bit line in comparison with the reference voltage REF, and outputs it to the data output line D.

  The capacity addition switch WC-SW is a switch that connects the capacity Cwt to the node N1. Cwt is formed using, for example, a MOS transistor. The ground switch GSW is a switch that connects the node N1 to the ground GND. WC-SW, Cwt, and GSW are means for extending the rise / fall time of the bit line BL as will be described later.

  Next, the effect of MCn0 connected to the same bit line BL0 as MC00 will be described by taking the case where memory cell MC00 is operated as an example. FIG. 9 is a waveform diagram showing an example of the operation of the semiconductor integrated circuit device of FIG. As shown in FIG. 9, the reset operation (RESET) is performed as follows. The read switch RSW, the set switch SS-SW, and the ground switch GSW are turned off. First, the capacitor addition switch WC-SW is turned on, BL0 is selected by Y-DEC and YS0, and then the reset switch RS-SW is turned on. Then, since charges are accumulated in the capacitor Cwt in addition to the wiring capacitance such as BL0, the voltage of BL0 does not rise instantaneously, and the rise time can be made longer than the word line WL0 described later.

  Thereafter, by selecting WL0 by X-DEC, a current larger than a set current described later is caused to flow through the memory cell MC00. After supplying a current for a certain time, the word line WL0 is lowered. As a result, the memory element R00 is rapidly cooled from the melted state to be in an amorphous state. Thereafter, the reset switch RS-SW is turned off and the ground switch GSW is turned on. Thereby, charges are discharged from the capacitance Cwt in addition to the wiring capacitance such as BL0. Therefore, the voltage of BL0 does not decrease instantaneously, and the fall time can be made longer than that of the word line WL0 described above. After BL0 falls, YS0, GSW and WC-SW are turned off. When such a reset operation is performed, the memory element Rn0 of the memory cell MCn0 is hardly affected by the voltage change because the voltage change speed of the bit line BL0 to which the memory cell MCn0 is connected is slow. As a result, the current Iceln0 flowing through Rn0 can be reduced.

  The set operation (SET) is performed as follows. The read switch RSW and the reset switch RS-SW are turned off. First, the capacitor addition switch WC-SW is turned on, and BL0 is selected by Y-DEC and YS0. Next, the set switch SS-SW is turned on. Then, charges are accumulated in the capacitance Cwt in addition to the wiring capacitance such as BL0, so the voltage of BL0 does not rise instantaneously, and the rise time can be made longer than the word line WL0 described later.

  Subsequently, by selecting WL0 by X-DEC, a current smaller than that in the reset operation described above is caused to flow through the memory cell MC00. After passing a current for a longer time than the above-described reset operation, the set switch SS-SW is turned off and the ground switch GSW is turned on. Then, charges are discharged from the capacitance Cwt in addition to the wiring capacitance such as BL0, so that the voltage of BL0 does not drop instantaneously and the fall time can be made longer than that of the word line WL0 described above. As a result, the memory element R00 is crystallized. When such a set operation is performed, the memory element Rn0 of the memory cell MCn0 is hardly affected by the voltage change because the voltage change speed of the bit line BL0 to which the memory cell MCn0 is connected is slow. As a result, the current Iceln0 flowing through Rn0 can be reduced.

  The read operation (READ) is performed as follows. The reset switch RS-SW, the ground switch GSW, the set switch SS-SW, and the capacitance addition switch WC-SW are turned off. The memory cell MC00 is selected by X-DEC and Y-DEC, and the read switch RSW is turned on. After a certain time, the read switch RSW is turned off. At this time, a current corresponding to the resistance value flows in the memory element R00. That is, if the memory element R00 is in a high resistance state (amorphous state), the bit line BL0 is charged with a higher voltage than in the low resistance state (crystalline state). By turning on the sense amplifier enable signal SE, this potential difference is amplified by the sense amplifier SA, and data can be obtained from the data output line D.

  In the read operation, since the capacitance addition switch WC-SW is off, the bit line capacitance is small, and high-speed and power-saving reading is possible. That is, in the read operation, the voltage used is low unlike the set operation or the reset operation. Therefore, even if the capacitor addition switch WC-SW is turned off, the storage element of the non-selected memory cell is not easily affected, and the information is destroyed. Hateful.

  As described above, by using the semiconductor integrated circuit device according to the second embodiment, it is possible to improve the reliability of the phase change memory as described in the first embodiment while maintaining the reading speed. Become. In practice, even if the capacitor Cwt or the like is provided in the read / write circuit RWC, the influence of the area overhead is small. That is, as shown in FIG. 8, it is sufficient to provide one capacitor Cwt for a plurality of bit lines BL0 to BLm, and the capacitance value can be covered to some extent by the wiring capacitance.

  Further, providing the capacitor Cwt in the read / write circuit RWC has an effect of stabilizing the bit line capacitance at the time of writing. That is, the capacity of the memory cell viewed from the bit line is larger in the memory cell in the reset state than in the set state. Therefore, comparing the case where a large number of memory cells in the reset state are connected to the bit line and the case where a large number of memory cells in the set state are connected, the former has a larger bit line capacity. The change in the bit capacity depending on the storage state of each memory cell affects the transition timing of the bit line at the time of writing, so that stable writing becomes difficult. Therefore, by using the capacitance Cwt, the bit line capacitance at the time of writing can be maintained at a certain value or more, and the change in relative bit line capacitance can be reduced. As a result, stable writing is possible regardless of the storage state of the memory cell.

(Embodiment 3)
In the third embodiment, an example of a circuit configuration different from the second embodiment that realizes the function of extending the rise / fall time described in the first embodiment will be described. FIG. 10 is a circuit diagram showing an example of the configuration of the semiconductor integrated circuit device according to the third embodiment of the present invention. The semiconductor integrated circuit device shown in FIG. 10 includes a memory array unit ARYa, an X-system address decoder X-DECa, a Y-system address decoder Y-DECa, and a read / write circuit RWCa.

  The memory array unit ARYa has the same configuration as that of FIG. 8 described above, and a plurality of sub word lines SWL0 to SWLn, a plurality of bit lines BL0 to BLm, and a plurality of sub word lines provided at intersections of the bit lines. Memory cells MC00 to MCnm. Here again, as in FIG. 8, the source line is omitted and the ground GND is used. Each of the memory cells MC00 to MCnm has the same configuration as that in FIG. 8. For example, MC00 includes a selection element MN00 and a storage element R00, and the selection element MN00 is an NMOS transistor, for example. The gate electrode of the selection element MN00 is connected to the sub word line SWL0, the drain electrode is connected to one end of the storage element R00, and the source electrode is connected to the source line (ground GND). The other end of the storage element R00 is connected to the bit line BL0.

  Each sub word line SWL0 to SWLn is connected to an X-system address decoder X-DECa. X-DECa is when sub word line drivers XDR0 to XDRn for driving sub word lines SWL0 to SWLn, main word lines MWL1 to MWLp for controlling on / off of XDR0 to XDRn, and when XDR0 to XDRn are turned on. FX drivers FXDR1 to FXDR8 for setting drive voltages of SWL0 to SWLn. For example, when XDR0 is turned on, the output voltage FXO of FXDR1 is output to SWL0 via the word line drive transistor XTR in XDR0. Further, the output voltage FXO of FXDR1 becomes the power supply voltage VDD corresponding to the control signal FXXI, and becomes the ground GND corresponding to the control signal FXB.

  Each bit line BL0 to BLm is connected to a Y-system address decoder Y-DECa. Y-DECa includes bit line selection switches YS0 to YSm that select any of the plurality of bit lines BL0 to BLm and connect to the node N1. For example, YS0 includes a bit line connection transistor YTR0. This YTR0 connects BL0 and N1 when the bit line selection signal BLSW0 is activated. Here, YTR0 is formed of, for example, a MOS transistor. Similarly, a bit line connection transistor (not shown) in YSm connects BLm and N1 when the bit line selection signal BLSWm is activated.

  A read / write circuit RWCa is connected to the node N1. The RWCa includes a reset current source Irst and a reset switch RS-SW, a set current source Iset and a set switch SS-SW, and a readout circuit. The read circuit includes a voltage source Vpre for bit line precharge, a precharge switch PRE and a read switch TG for connecting Vpre to the node N1, and a sense amplifier SA connected to a node between TG and PRE. Contains. Note that the voltage Vrst and the voltage Vset are respectively supplied to one ends of the Irst and Iset different from the switch side. The RS-SW and SS-SW are composed of, for example, MOS transistors.

  In such a configuration, in the third embodiment, the rise / fall time of the bit line during the write operation is lengthened by lowering the drive capability of the reset switch RS-SW and the set switch SS-SW. Specifically, for example, the gate width of the reset switch RS-SW and the set switch SS-SW is made smaller than the gate width of the word line driving transistor XTR in the sub word line driver XDR. For example, the gate width of the reset switch RS-SW and the set switch SS-SW is made smaller than the gate width of the bit line connection transistor YTR in the bit line selection switch YS.

  FIG. 11 is a waveform diagram showing an example of the operation of the semiconductor integrated circuit device of FIG. Here, a case where an operation is performed on the memory cell MC00 will be described as an example. As shown in FIG. 11, when the reset operation (RESET) is performed, the bit line BL0 is selected and activated by turning on the reset switch RS-SW and the bit line connection transistor YTR0 in the bit line selection switch YS0. . At this time, since the drive capability of the RS-SW is low, the rise time of BL0 becomes long. Therefore, for example, the current Icel10 flowing through the storage element R10 of the memory cell MC10 connected to the same bit line BL0 can be reduced.

  Thereafter, the control signal FXI and the main word line MWL1 for the FX driver FXDR1 are selected, and the control signal FXB is deselected to start up the sub word line SWL0. After a sufficient time has elapsed for the memory element R00 to be heated to the melting point, FXI and MWL1 are deselected and the control signal FXB is selected to cause SWL0 to fall. At this time, each transistor in the sub word line driver XDR0 including the word line drive transistor XTR is designed to have high driving capability, and SWL0 can be rapidly lowered. As a result, the memory element R00 is rapidly cooled to be in an amorphous state. Subsequently, BL0 is lowered by turning off RS-SW and YTR0. Also at this time, since the drive capability of the RW-SW is designed to be low, the fall time of BL0 becomes long. Therefore, for example, the current Icel10 flowing through the memory element R10 can be reduced.

  When performing the set operation (SET), the bit line BL0 is selected and turned on by turning on the set switch SS-SW and the bit line connection transistor YTR0 in the bit line selection switch YS0. At this time, since the drive capability of SS-SW is low, the rise time of BL0 becomes long, and for example, the current Icel10 flowing through the memory element R10 can be reduced. Thereafter, the sub-word line SWL0 is raised in the same manner as in the reset operation, and a current smaller than that in the reset operation is passed through the storage element R00 for a longer time than in the reset operation, and then SWL0 is lowered. In addition, by turning off SS-SW and YTR0 along with the fall of SWL0, BL0 is lowered. At this time, since the SS-SW drive capability is designed to be low, the fall time of BL0 becomes long. As a result, the memory element R00 enters a crystalline state, and further, for example, the current Icel10 flowing through the memory element R10 can be reduced.

  Further, when the read operation (READ) is performed, the read switch TG, the precharge switch PRE, and the bit line connection transistor YTR0 are turned on to select the bit line BL0 and precharge the voltage of the voltage source Vpre to BL0. Charge. At this time, since the precharge voltage is low, for example, the current Icel10 flowing as a disturb in the storage element R10 is small, and the influence of the disturb on the unselected memory cells is small. Thereafter, PRE is turned off, and the sub word line SWL0 is raised in the same manner as in the reset operation. Then, the voltage of BL0 is maintained at a precharge voltage when the storage element R00 is in an amorphous state, and is discharged toward the ground GND when the storage element R00 is in a crystalline state. Therefore, reading is possible by sensing the difference in voltage of BL0 with the sense amplifier SA. After the read data is determined, TG and YTR0 are turned off.

  By the way, generally, in order to supply / stop the current or voltage to / from the bit line BL at high speed, the drive capability (gate width) of the reset switch RS-SW or the set switch SS-SW is designed to be somewhat large. In particular, in the method of realizing the rapid cooling in the reset operation by stopping the current for the bit line BL, the gate width of the RS-SW must be sufficiently increased. In general, the bit line connection transistor YTR needs to be provided for each bit line, unlike the RS-SW or SS-SW, and the number of transistors increases. Therefore, the bit line connection transistor YTR is usually more than the RS-SW or SS-SW. The gate width is designed to be small.

  On the other hand, in the circuit of the third embodiment, the magnitude relationship is opposite to this, and a bit line connection transistor YTR having a gate width as large as possible within the allowable circuit area is designed, and the gate width is larger than this YTR. RS-SW or SS-SW is designed so as to be small. Then, at the time of the read operation, the gate width of the bit line connection transistor YTR is designed to be somewhat large, so that a high-speed read operation can be performed. Furthermore, since the gate width of the RS-SW or SS-SW is designed to be small at the time of the reset operation or the set operation, the bit line transition time at the time of the write operation can be lengthened, and the influence of disturb on the unselected memory cells can be reduced. It becomes possible to reduce. Even when the gate width of the RS-SW is designed to be small, no problem arises because the rapid cooling during the reset operation is performed by the fall of the word line WL.

  In general, in a phase change memory that requires a large current to flow at reset, the gate width of the word line drive transistor XTR in the sub word line driver XDR is the same as that of the reset switch RS-SW or the set switch SS-SW. Designed to be smaller than the gate width. This is because the number of RS-SWs or SS-SWs that exist only one in the plurality of bit lines BL is smaller than the XTRs that exist for each sub-word line SWL. On the other hand, in the circuit of the third embodiment, an RS− with a gate width smaller than this XTR is secured after securing a gate width of XTR sufficient for rapid reset operation by the fall of the word line WL. By providing SW or SS-SW, the influence of disturb on unselected memory cells is reduced. That is, the magnitude relationship can be opposite to that of the general configuration described above.

  As described above, by using the semiconductor integrated circuit device according to the third embodiment, it is possible to improve the reliability of the phase change memory as described in the first embodiment while maintaining the reading speed. Become. Further, since the transistor size of the reset switch RS-SW or the set switch SS-SW can be reduced, the reliability of the phase change memory can be improved with a small circuit area.

(Embodiment 4)
In the fourth embodiment, an example of a circuit configuration different from the second and third embodiments that realizes the function of extending the rise / fall time described in the first embodiment will be described. FIG. 12 is a circuit diagram showing an example of the configuration of the semiconductor integrated circuit device according to the fourth embodiment of the present invention. The semiconductor integrated circuit device shown in FIG. 12 includes a memory array unit ARYb, an X-system address decoder X-DECb, a Y-system address decoder Y-DECb, and a read / write circuit RWCb. The configuration example of FIG. 12 is a modification of the configuration example of FIG. 10 described in the third embodiment, and the following description will be made by paying attention to different points from the configuration example of FIG.

  ARYb and Y-DECb shown in FIG. 12 have the same configuration as ARYa and Y-DECa of FIG. 10 described above. The X-DECb in FIG. 12 is the same as the X-DECa in FIG. 10 except for the configuration of the FX driver. That is, the FX driver FXDR in FIG. 10 is a driver that outputs a binary value of the power supply voltage VDD or the ground GND, whereas the FX driver FXbDR in FIG. 12 has the set power supply voltage VWset or the reset power supply voltage VWrst or the ground. It is a driver that outputs three values of GND. The output voltage FXO of FXbDR becomes VWset corresponding to the control signal FXSET, becomes VWrst corresponding to the control signal FXRST, and becomes ground GND corresponding to the control signal FXB. This output voltage FXO is supplied to the sub word line driver XDR as in FIG. 10, and when the main word line MWL is selected, the drive voltage of the sub word line SWL is passed through the word line drive transistor XTR in the XDR. It becomes.

  Further, the read / write circuit RWCb shown in FIG. 12 is different from the read / write circuit RWCa of FIG. 10 in that the write transistor WTR controlled by the write control signal WT and the read transistor RTR controlled by the read control signal RD. And a sense amplifier SA. The RWCb of FIG. 12 is different from the RWCa of FIG. 10 in that it includes a reset operation switch and current source, and a set operation switch and current source, whereas the reset operation and the set operation have a common transistor WTR and voltage source. It is characterized by having Vwt. The WTR is composed of, for example, a MOS transistor.

  In such a configuration, in the fourth embodiment, as in the third embodiment, the rise / fall time of the bit line during the write operation is lengthened by lowering the drive capability of the WTR. Specifically, for example, the gate width of the WTR is made smaller than the gate width of the bit line connection transistor YTR in the bit line selection switch YS.

  FIG. 13 is a waveform diagram showing an example of the operation of the semiconductor integrated circuit device of FIG. The operation of FIG. 13 is different from the operation of FIG. 11 in that the drive voltage of the sub word line is changed by the set operation and the reset operation. Hereinafter, an example of operation will be described by taking as an example the case of performing an operation on the memory cell MC00. As shown in FIG. 13, when performing a reset operation (RESET), the bit line BL0 is selected by turning on the WTR by the write control signal WT and turning on the bit line connection transistor YTR0 in the bit line selection switch YS0. Then, the voltage Vwt is supplied to BL0. At this time, since the drive capability of the WTR is low, the rise time of BL0 becomes long. Therefore, for example, the current Iceln0 that is connected to the same bit line BL0 and flows through the memory element Rn0 of the memory cell MCn0 can be reduced.

  Thereafter, the control signal FXRST and the main word line MWL1 for the FX driver FXbDR1 are selected, and the control signal FXB is deselected, thereby starting up the sub word line SWL0. At this time, the reset power supply voltage VWrst is output by FXbDR1, and this voltage becomes the drive voltage of the sub word line SWL0 via the word line drive transistor XTR. After a sufficient time has elapsed for the memory element R00 to be heated to the melting point, FXRST and MWL1 are deselected and the control signal FXB is selected to cause SWL0 to fall. At this time, each transistor in the sub word line driver XDR0 including the word line drive transistor XTR is designed to have high driving capability, and SWL0 can be rapidly lowered. As a result, the memory element R00 is rapidly cooled to be in an amorphous state. Subsequently, BL0 is lowered by turning off WTR and YTR0. Also at this time, since the drive capability of the WTR is designed to be low, the fall time of BL0 becomes long. Therefore, for example, the current Iceln0 flowing through the memory element Rn0 can be reduced.

  When performing the set operation (SET), WTR is turned on by the write control signal WT and the bit line connection transistor YTR0 is turned on to select the bit line BL0, and BL0 has the same voltage Vwt as in the reset operation. Supply. At this time, since the drive capability of the WTR is low, the rise time of BL0 becomes long, and for example, the current Iceln0 flowing through the storage element Rn0 can be reduced. Thereafter, the control signal FXSET and the main word line MWL1 for the FX driver FXbDR1 are selected, and the control signal FXB is deselected to start up the sub word line SWL0. At this time, FXbDR1 outputs a set power supply voltage VWset having a voltage value smaller than VWrst, and this voltage becomes the drive voltage of SWL0 via XTR.

  By using the difference in the drive voltage of SWL0, a current smaller than that in the reset operation is passed through the storage element R00 for a longer time than in the reset operation, and then SWL0 is lowered. In addition, BL0 is lowered by turning off WTR and YTR0 simultaneously with the fall of SWL0. At this time, since the drive capability of the WTR is designed to be low, the fall time of BL0 becomes long. As a result, the memory element R00 enters a crystalline state, and for example, the current Iceln0 flowing through the memory element Rn0 can be reduced.

  When the read operation (READ) is performed, the read transistor RTR is turned on by the read control signal RD and the bit line connection transistor YTR0 is turned on to select the bit line BL0, and the read voltage Vrd with respect to BL0. Is applied. At this time, since the voltage or current for reading is small, for example, the current Iceln0 flowing through the memory element Rn0 is also small. Thereafter, the sub word line SWL0 is raised using the control signal FXRST, for example, as in the reset operation. Thereby, in the memory element R00, a discharge corresponding to the state is generated, and the difference in the discharge state is sensed and amplified by the sense amplifier SA. After the read data is determined, the sub word line SWL0 is lowered and the read transistors RTR and YTR0 are turned off.

  In the configuration example of FIG. 12, similarly to the configuration example of FIG. 10, the read operation can be speeded up by designing the gate width of the write transistor WTR to be smaller than the bit line connection transistor YTR0, and the reset operation. Disturbances to unselected memory cells during the time or set operation can be reduced. Furthermore, since the writing circuit is shared between the set operation and the reset operation by changing the drive voltage of the sub word line SWL, the circuit area can be further reduced as compared with the configuration example of FIG. It becomes possible.

  As described above, by using the semiconductor integrated circuit device according to the fourth embodiment, it is possible to improve the reliability of the phase change memory as described in the first embodiment while maintaining the reading speed. Become. Further, the circuit area can be further reduced as compared with the semiconductor integrated circuit device according to the third embodiment.

(Embodiment 5)
In the semiconductor integrated circuit device according to the fifth embodiment, disturbance to unselected memory cells is prevented by the configuration of the memory cells. FIG. 14 is a circuit diagram showing a configuration example of the memory cell included in the semiconductor integrated circuit device according to the fifth embodiment of the present invention. The memory cell MC of FIG. 14 includes a diode D in addition to the selection element SW and the storage element (phase change element) R. Selection element SW is an NMOS transistor, for example, and has a gate connected to word line WL, a source connected to source line SL, and a drain connected to one end of phase change element R. The other end of phase change element R is connected to the cathode of diode D, and the anode of diode D is connected to bit line BL.

  When such a configuration is used, the current flowing in the reverse direction due to the diode D can be prevented, so that the influence of the disturb of the unselected memory cell can be halved. The diode D can be formed using a diffusion layer, for example.

(Embodiment 6)
In the semiconductor integrated circuit device according to the sixth embodiment, similarly to the fifth embodiment, the disturbance to the non-selected memory cells is prevented by the configuration of the memory cells. FIG. 15 is a circuit diagram showing a configuration example of the memory cell included in the semiconductor integrated circuit device according to the sixth embodiment of the present invention. The memory cell MC of FIG. 15 includes two selection elements SWa and SWb, and a storage element (phase change element) R connected therebetween. The selection elements SWa and SWb are, for example, NMOS transistors. SWa has a gate connected to word line WL, a drain connected to bit line BL, and a source connected to one end of phase change element R. SWb has a gate connected to word line WL, a drain connected to the other end of phase change element R, and a source connected to source line SL.

  When such a configuration is used, when the memory cell MC is not selected, the bit line BL and the phase change element R are cut off by the selection element SWa, so that the influence of disturbance hardly occurs. Note that the selection element SWa is designed to have a threshold voltage lower than that of the selection element SWb, and the leakage current increases, but it has a sufficient driving force. Therefore, the amount of current at the time of writing is substantially adjusted by the design of SWb.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The semiconductor integrated circuit device of the present invention can be widely applied to a high-density integrated memory circuit including memory cells using a phase change material, or a logic-embedded memory in which a memory circuit and a logic circuit are provided on the same semiconductor substrate. Yes, it is even more beneficial when such products are used under high temperature conditions.

Claims (17)

Multiple word lines,
A plurality of bit lines extending in a direction intersecting the plurality of word lines;
A plurality of memory cells respectively disposed at intersections of the plurality of word lines and the plurality of bit lines;
Each of the plurality of memory cells includes
One end is connected to one of the plurality of bit lines, and a storage element that stores information by being written in a high resistance state or a low resistance state;
A first transistor having one end connected to the other end of the memory element and controlled on / off by any of the plurality of word lines;
When writing the storage element to a high resistance state, the rise time of the plurality of bit lines is longer than the rise time of the plurality of word lines, or the fall time of the plurality of bit lines is the plurality of words. A semiconductor integrated circuit device characterized by being longer than the fall time of the line. The semiconductor integrated circuit device according to claim 1, further comprising:
When writing the memory element to a low resistance state, the rise time of the plurality of bit lines is longer than the rise time of the plurality of word lines, or the fall time of the plurality of bit lines is the plurality of words. A semiconductor integrated circuit device characterized by being longer than the fall time of the line. The semiconductor integrated circuit device according to claim 1.
The plurality of bit lines are connected to a write circuit through a second transistor whose on / off is controlled by a selection signal from an address decoder,
The write circuit uses the capacitor provided in the write circuit to increase the rise time / fall time of the plurality of bit lines when the memory element is written in a high resistance state. Semiconductor integrated circuit device. The semiconductor integrated circuit device according to claim 1.
The plurality of bit lines are connected to a write circuit through a second transistor whose on / off is controlled by a selection signal from an address decoder,
The write circuit is designed to increase the rise time / fall time of the plurality of bit lines by designing the write circuit to have a low driving capability when writing the memory element in a high resistance state. . The semiconductor integrated circuit device according to claim 1.
A semiconductor integrated circuit device characterized in that when the memory element is written in a high resistance state, the memory element is rapidly cooled using a fall of a word line corresponding to the memory element. The semiconductor integrated circuit device according to claim 1.
2. A semiconductor integrated circuit device according to claim 1, wherein a capacitive interface layer for efficiently transferring heat to the storage element is formed at a connection portion on the first transistor side of the storage element. The semiconductor integrated circuit device according to claim 4.
The write circuit outputs a voltage signal or a current signal through a third transistor toward a bit line corresponding to the storage element when writing the storage element to a high resistance state,
The semiconductor integrated circuit device, wherein the third transistor has a driving capability smaller than that of the second transistor. Multiple word lines,
A plurality of bit lines extending in a direction intersecting the plurality of word lines;
A plurality of memory cells respectively disposed at intersections of the plurality of word lines and the plurality of bit lines;
Each of the plurality of memory cells includes
One end is connected to one of the plurality of bit lines, and a storage element that stores information by being written in a high resistance state or a low resistance state;
A first transistor having one end connected to the other end of the memory element and controlled on / off by any of the plurality of word lines;
The plurality of bit lines are connected to a write circuit through a second transistor whose on / off is controlled by a selection signal from an address decoder,
The writing circuit outputs a voltage value of the same level using the same circuit when writing the storage element in a high resistance state and when writing in a low resistance state,
The plurality of word lines output a first level voltage value when the memory element is written in a high resistance state, and output a second level voltage value when the memory element is written in a low resistance state. A semiconductor integrated circuit device driven by a drive circuit. The semiconductor integrated circuit device according to claim 8.
When writing to the storage element, rise times of the plurality of bit lines are longer than rise times of the plurality of word lines, or fall times of the plurality of bit lines are equal to the plurality of words. A semiconductor integrated circuit device characterized by being longer than the fall time of the line. The semiconductor integrated circuit device according to claim 8.
The write circuit outputs a voltage value of the same level via the fourth transistor when writing the storage element in a high resistance state and when writing to the low resistance state,
The semiconductor integrated circuit device, wherein the fourth transistor has a driving capability smaller than that of the second transistor. The semiconductor integrated circuit device according to claim 8.
A semiconductor integrated circuit device characterized in that when the memory element is written in a high resistance state, the memory element is rapidly cooled using a fall of a word line corresponding to the memory element. The semiconductor integrated circuit device according to claim 8.
2. A semiconductor integrated circuit device according to claim 1, wherein a capacitive interface layer for efficiently transferring heat to the storage element is formed at a connection portion on the first transistor side of the storage element. Multiple word lines,
A plurality of bit lines extending in a direction intersecting the plurality of word lines;
A plurality of memory cells respectively disposed at intersections of the plurality of word lines and the plurality of bit lines;
Each of the plurality of memory cells includes
One end is connected to one of the plurality of bit lines, and a storage element that stores information by being written in a high resistance state or a low resistance state;
A first transistor having one end connected to the other end of the memory element and controlled on / off by any of the plurality of word lines;
The plurality of bit lines are connected to a write circuit through a second transistor whose on / off is controlled by a selection signal from an address decoder,
The write circuit outputs a voltage signal or a current signal through a third transistor toward a bit line corresponding to the storage element when writing the storage element to a high resistance state,
The semiconductor integrated circuit device according to claim 1, wherein the driving capability of the third transistor is smaller than the driving capability of the second transistor. 14. The semiconductor integrated circuit device according to claim 13, further comprising:
The write circuit outputs a voltage signal or a current signal through a fifth transistor toward the bit line corresponding to the storage element when writing the storage element in a low resistance state.
The semiconductor integrated circuit device according to claim 5, wherein the drive capability of the fifth transistor is smaller than the drive capability of the second transistor. The semiconductor integrated circuit device according to claim 13.
A semiconductor integrated circuit device characterized in that when the memory element is written in a high resistance state, the memory element is rapidly cooled using a fall of a word line corresponding to the memory element. The semiconductor integrated circuit device according to claim 13.
2. A semiconductor integrated circuit device according to claim 1, wherein a capacitive interface layer for efficiently transferring heat to the storage element is formed at a connection portion on the first transistor side of the storage element. The semiconductor integrated circuit device according to claim 14.
When writing the storage element to a high resistance state or a low resistance state, the rise time of the plurality of bit lines is longer than the rise time of the plurality of word lines, or the fall time of the plurality of bit lines is 2. A semiconductor integrated circuit device, wherein the plurality of word lines have a fall time longer than the fall time.