JP2020155166A - Resistance change type memory and drive method thereof - Google Patents

Abstract

To provide a resistance change type memory capable of improving a reset operation.SOLUTION: The resistance change type memory in an embodiment comprises a resistance change film capable of reversibly changing between a low resistance state and a high resistance state, a selection transistor and a drive part for driving them. The gate, drain and sauce of the selection transistor are connected to one end of the resistance change film, a word line and a bit line, respectively, and a plate line is connected to the other end of the resistance change film. The drive part applies a voltage VL equal to or more than the threshold voltage of the selection transistor to the word line when the resistance change film is in the low resistance state, applies a voltage V2 at which the resistance change film changes to the high resistance state from the low resistance state between the bit line and the plate line while applying the voltage VL, and applies a voltage V1 less than the threshold voltage of the selection transistor to the word line while applying the voltage V2.SELECTED DRAWING: Figure 5

Description

An embodiment of the present invention relates to a resistance change type memory and a method for driving the same.

A phase change memory is known as one of the resistance change type memories. In the phase change memory, a memory cell including a resistance change film is used. The resistance change film can reversibly change between a high resistance state and a low resistance state. The operation of changing the resistance change film from the low resistance state to the high resistance state is called a reset operation.

K.-J. Lee et al., A 90 nm 1.8 V 512 Mb Diode-Switch PRAM With 266 MB / s Read Throughput, IEEE Journal of Solid-State Circuits, vol. 43, no. 1, pp. 150-162 , 2008.

An object of the present invention is to provide a resistance change type memory capable of improving the reset operation and a method for driving the same.

The resistance-changing memory of the embodiment has a first resistance-changing film capable of reversibly changing between a first resistance state and a second resistance state having a resistance higher than that of the first resistance state. A selection transistor having a gate, a drain, and a source, the source of which is connected to one end of the first resistance change film, a first conductive wire connected to the gate, and a first conductive wire connected to the drain. The second conductive wire, a third conductive wire connected to the other end of the first resistance change film, and a drive unit for driving the first resistance change film and the selection transistor are included. When the first resistance change film is in the first resistance state, the drive unit applies a first voltage equal to or higher than the threshold voltage of the selection transistor to the first conductive wire, and the drive unit applies the first voltage to the first conductive wire. While the first voltage is applied to the first conductive wire, the first resistance changing film is formed between the second conductive wire and the third conductive wire to form the first resistance. While applying a second voltage that changes from the state to the second resistance state and applying the second voltage between the second conductive wire and the third conductive wire, the above-mentioned A third voltage less than the threshold voltage is applied to the first conductive wire.

FIG. 1 is a diagram showing a configuration of a resistance change type memory according to the first embodiment. FIG. 2 is a diagram showing a configuration of a memory cell array. FIG. 3 is a diagram showing a configuration of memory cells. FIG. 4 is a block showing the configuration of the drive unit. FIG. 5 is a waveform diagram for explaining the reset operation of the first embodiment. FIG. 6 is a waveform diagram for explaining the set operation of the comparative example. 7 (a) and 7 (b) are diagrams showing the resistance-pulse voltage characteristics of the resistance change storage elements of the embodiment and the comparative example, respectively. FIG. 8 is a diagram showing a memory cell array of the second embodiment. FIG. 9 is a waveform diagram for explaining the reset operation of the second embodiment. FIG. 10 is a diagram showing the current-voltage characteristics observed when a current is applied to the chalcogenide.

Hereinafter, embodiments will be described with reference to the drawings. The drawings are schematic or conceptual and may not always be the same as the real ones. Further, in the drawings, the same reference numerals are given the same or corresponding parts, and duplicate explanations will be given as necessary. Further, for simplification, even if there are the same or equivalent parts, they may not be labeled.

(First Embodiment)
FIG. 1 is a diagram showing a configuration of a resistance change type memory 1 according to the first embodiment. The resistance change type memory 1 includes a memory cell array 2 and a drive unit 3.
As shown in FIG. 2, the memory cell array 2 has a plurality of word lines WL (WL1, WL2, WL3, WL4, ...) Extending in the first direction and a second line intersecting the first direction. A plurality of bit lines BL (BL1, BL2, BL3, BL4, ...) Extending in the direction and a plurality of memory cells MC are included. Each of the plurality of memory cells MC is arranged so as to correspond to each intersection of the plurality of word lines WL and the plurality of bit lines BL.

The memory cell MC can reversibly change between a first resistance state (low resistance state) and a second resistance state (high resistance state) having a higher resistance than the first resistance state. Hereinafter, the state of the memory cell MC to which no voltage is applied is referred to as a low resistance state, and the state of the memory cell MC to which no voltage is applied is also referred to as a reset state.

In the present embodiment, as shown in FIG. 3, the memory cell MC is a resistance change storage element including a selection transistor (selection element) 11 and a resistance change film 12. FIG. 3 shows four memory cells MC1 to MC4. In the memory cell MC1, the gate of the selection transistor 11 is connected to the word line WL (WL0), the drain of the selection transistor 11 is connected to the bit line BL (BL0), and the source of the selection transistor 11 is connected to one end of the resistance change film 12. It is connected and the other end of the resistance change film 12 is connected to the plate wire PL. The memory cell MC2 is the same as the memory cell MC1, except that the drain of the selection transistor 11 is connected to the bit line BL (BL1). The memory cell MC3 is the same as the memory cell MC1, except that the gate of the selection transistor 11 is connected to the word line WL (WL1). The memory cell MC4 is the same as the memory cell MC1, except that the drain of the selection transistor 11 is connected to the bit line BL (BL1) and the gate of the selection transistor 11 is connected to the word line WL (WL1).

The resistance change film 12 includes, for example, GeSbTe or a superlattice in which GeTe and SbTe are laminated. When the resistance change film 12 includes GeSbTe, the resistance change type memory 1 is a PCM (Phase Change Memory). When the resistance change film 12 includes a superlattice in which GeTe and SbTe are laminated, the resistance change type memory 1 is an iPCM (interfacial Phase Change Memory).

The drive unit 3 drives a memory cell (resistance change film, selection transistor) by controlling a voltage on a word line, a bit line, and a plate line. In the present embodiment, the drive unit 3 includes a selection circuit 21 and a voltage generation application circuit 22 as shown in FIG.
The selection circuit 21 selects a word line, a bit line, and a plate line necessary for selecting a memory cell MC to be read or written. The voltage generation application circuit 22 generates voltages to be applied to the word line, the bit line, and the plate line necessary for the read operation or the write operation, and the generated voltage is selected by the selection circuit 21 for the word line, the bit line, and the plate line. Apply to plate wire.

FIG. 5 is a waveform diagram (timing chart) for explaining the setting operation of the resistance change type memory of the present embodiment. More specifically, the waveforms of the voltages applied to the word lines, bit lines, plate lines and memory cells are shown. The horizontal axis is time and the vertical axis is voltage.
The reset operation is a write operation that changes the memory cell MC to be selected (hereinafter referred to as a selected cell) from a low resistance state to a high resistance state. In the case of PCM, it is an operation of changing the resistance changing film from a crystalline state (low resistance state) to an amorphous state (high resistance state). The set operation is a write operation that changes the selected cell from the high resistance state to the low resistance state. In this embodiment, the reset operation of the memory cell MC1 (hereinafter referred to as a selected cell) of FIG. 3 will be described.

The drive unit 3 (FIG. 1) applies a first voltage VH (for example, the power supply voltage VDD of the resistance change type memory 1) equal to or higher than the threshold voltage of the selection transistor to the word line WL0 (hereinafter referred to as the selection word line). (Step S1). As a result, the selected transistor of the memory cell changes from the off state to the on state. During the reset operation, 0 V is applied to the plate line, VL is applied to the word line WL1 (non-selected word line), and 0 V is applied to the bit line BL1 (non-selected bit line).

Next, the drive unit 3 applies the second voltage V2 to the bit line BL0 (hereinafter referred to as the selected bit line) while applying the first voltage VH to the selected word line (step S2). Since the voltage V2 is applied between the selection bit line and the plate line, a second voltage is applied to the selection cell. Here, since the voltage of the plate wire is 0 V, the voltage V2 of the selected bit wire is applied to the selected cell.

Here, PCM utilizes the difference in physical properties between the crystalline state and the amorphous state of the same substance as storage information, and a Te alloy called chalcogenide is used for storing the information. FIG. 18 shows typical current-voltage characteristics observed when a current is applied to chalcogenide. When the current applied to the chalcogenide in the amorphous state is increased and the voltage reaches a certain value, impact ionization occurs inside the chalcogenide, the carriers are multiplied, and the resistance drops sharply. If a voltage higher than the "threshold voltage" that causes this phenomenon is applied, a large current flows, Joule heat is generated, and the temperature of chalcogenide rises. If the applied voltage is controlled to keep the temperature of chalcogenide in the crystallization temperature region, the state transitions to the polycrystalline state and the resistance is lowered. Therefore, in order to crystallize by the set operation, it is necessary to apply a voltage higher than the set operation threshold voltage of FIG.

The voltage V2 is a voltage required for a current to flow through the selected cell due to the reset operation to generate heat, and for a current to reach the reset current region to flow through the resistance change film in the selected cell.
Next, the drive unit 3 applies a third voltage (here, 0V) less than the threshold voltage to the selection word line while applying the voltage V2 to the selection bit line (step S3). In addition, in this specification, the expression of applying a voltage includes the case where the voltage is set to 0V. As a result of step S3, the selection transistor of the selection cell changes from the on state to the off state, and the current flowing through the selection cell is immediately cut off. As a result, the selected cell is rapidly cooled, and the resistance change film is amorphized to change from a low resistance state to a high resistance state. After that, the drive unit 3 sets the voltage of the bit line to 0V.

FIG. 6 is a waveform diagram (timing chart) for explaining the reset operation of the comparative example.
In the comparative example, the voltage VH is applied to the selected word line, and then the voltage V2 is applied to the selected bit line. Up to this point, it is the same as the embodiment. However, in the case of the comparative example, the voltage applied to the selection bit line changes from V2 to 0V before the voltage of the selection word line changes from VH to VL. In the comparative example (FIG. 6), unlike the present embodiment (FIG. 5), the voltage of the selected cell becomes 0 V after a certain period of time has passed after the voltage V2 applied to the selected bit line is changed to 0 V. This is due to the wiring resistance and capacitance of the bit wire.

FIG. 7A is a diagram showing the characteristics of the resistance-pulse voltage of the resistance change storage element of the comparative example. More specifically, the relationship between the pulse voltage applied to the bit line during the reset operation of the comparative example and the resistance of the resistance change storage element read after the reset operation of the comparative example is shown. In FIG. 7A, U1 shows a voltage at which the reset state starts to change to the set state. U2 indicates the voltage at which the set state starts to change to the reset state. U3 indicates the voltage at which the resistance change storage element increases the resistance.

FIG. 7B is a diagram showing the characteristics of the resistance-pulse voltage of the resistance change storage element of the embodiment. More specifically, the relationship between the pulse voltage applied to the bit line during the reset operation of the embodiment and the resistance of the resistance change storage element read after the reset operation of the embodiment is shown. In FIG. 7B, U0 shows the voltage at which the set state starts to change to the reset state.

From FIGS. 7 (a) and 7 (b), in the present embodiment, the set state starts to break from the voltage U0 lower than the voltage U2, and at the voltage U2 (<voltage U3), the resistance change storage element has already become high resistance. You can see that. Therefore, according to the present embodiment, it is possible to reduce the voltage of the reset operation (improve the reset operation).

(Second Embodiment)
In the present embodiment, a case where a resistance change type memory using a crosspoint type (three-dimensional type) memory cell array is used will be described.
FIG. 8 is a diagram showing a memory cell array of the present embodiment.
The memory cell array includes the global bit lines GBL0 and GBL1. In FIG. 8, for simplification, two global bit lines, bit lines GBL0 and GBL1, are shown.

The memory cell array further includes a selection transistor 11 connected to the global bit line GBL0. The drain of the selection transistor 11 is connected to the global bit line GBL0. In FIG. 8, the number of selection transistors 11 is set to 2 for simplification.
In FIG. 8, the global word line GWL0 and the local bit line LBL are connected to the gate and source of the left selection transistor 11 connected to the global bit line GBL0, respectively. One end of a memory cell (hereinafter referred to as a cell) C000 to C003 is connected to this local bit line LBL. Local word lines LWL0 to LWL3 are connected to the other ends of cells C000 to C003, respectively. Each cell C000 to C003 includes a resistance change film 12. One end and the other end of each cell C000 to C003 are one end and the other end of the resistance change film 12, respectively.

On the other hand, the global word line GWL1 and the local bit line LBL are connected to the gate and source of the selection transistor 11 on the right side connected to the global bit line GBL0, respectively. One end of cells C010 to C013 is connected to this local bit line LBL. Local word lines LWL0 to LWL3 are connected to the other ends of cells C010 to C013, respectively. Each cell C010 to C013 includes a resistance change film 12. One end and the other end of each cell C010 to C013 are one end and the other end of the resistance change film 12, respectively.

In FIG. 8, the global word line GWL0 and the local bit line LBL are connected to the gate and source of the left selection transistor 11 connected to the global bit line GBL1, respectively. One end of cells C100 to C103 is connected to this local bit line LBL. Local word lines LWL0 to LWL3 are connected to the other ends of cells C100 to C103, respectively.

On the other hand, the global word line GWL1 and the local bit line LBL are connected to the gate and source of the selection transistor 11 on the right side connected to the global bit line GBL1, respectively. One end of cells C110 to C113 is connected to the local bit line LBL. Local word lines LWL0 to LWL3 are connected to the other ends of cells C110 to C113, respectively.

FIG. 9 is a waveform diagram (timing chart) for explaining the setting operation of the resistance change type memory of the present embodiment. In this embodiment, a reset operation for changing the cell C000 (hereinafter referred to as the selected cell C000) from the low resistance state to the high resistance state will be described.
The drive unit 3 (FIG. 1) applies a voltage VH equal to or higher than the threshold voltage of the selection transistor 11 to the global word line GWL0 (hereinafter referred to as selection GWL0) used for the reset operation of the selection cell C000 (step S1). As a result, the selection transistor 11 changes from the off state to the on state. Before applying the voltage VH to the selected GWL0, the voltage VL of the selected GWL0. During the reset operation, the voltage V1 is applied to the local word lines LWL1 to LWL3, the global bit line GBL1 (hereinafter referred to as non-selected GBL1), and the global word line GWL1 (hereinafter referred to as non-selected GWL1).

Next, the drive unit 3 applies the voltage V2 to the local word line LWL0 (hereinafter, referred to as the selection LWL0) connected to the other end of the selection cell C000 while applying the voltage VH to the selection GWL0, and at the same time, simultaneously. The voltage of the global bit line GBL0 (hereinafter referred to as selective GBL0) is changed from V1 to 0V (step S2). As a result, the voltage V2 is applied to the selected cell C000.

Next, while the voltage of the selected GBL 0 is 0 V, a voltage VL lower than the threshold voltage is applied to the selected GWL 0 (step S3). As a result, the selection transistor 11 connected to the selection GWL0 changes from the on state to the off state, and the current flowing through the selection cell C000 is immediately cut off. As a result, the selection cell C000 is rapidly cooled, and the resistance change film is amorphized to change from a low resistance state to a high resistance state. As a result, the same effect as that of the first embodiment can be obtained in this embodiment. After that, the drive unit 3 applies a voltage V1 to the selected LWL0 and the selected GBL0.

In addition to the selected cell COO, FIGS. 9 show cells C001 to C003 and cells C010 to C.
Waveform diagrams of 013, cells C110 to C113, cells C100, and cells C101 to C103 are also shown.
Some or all of the superordinate concepts, intermediate and subordinate concepts of the above-described embodiments, and other embodiments not described above, are, for example, any of the following Appendix 1-11 and Appendix 1-11. It can be expressed as a combination (excluding combinations that are clearly inconsistent).
[Appendix 1]
A first resistance change film capable of reversibly changing between a first resistance state and a second resistance state having a resistance higher than that of the first resistance state.
A selection transistor having a gate, a drain, and a source, the source of which is connected to one end of the first resistance change film.
The first conductive wire connected to the gate and
The second conductive wire connected to the drain and
A third conductive wire connected to the other end of the first resistance change film,
It includes the first resistance change film and a drive unit for driving the selection transistor.
The drive unit
When the first resistance change film is in the first resistance state, a first voltage equal to or higher than the threshold voltage of the selection transistor is applied to the first conductive wire.
While the first voltage is applied to the first conductive wire, the first resistance changing film is formed between the second conductive wire and the third conductive wire. A second voltage that changes from the resistance state to the second resistance state is applied,
While the second voltage is applied between the second conductive wire and the third conductive wire, a third voltage lower than the threshold voltage is applied to the first conductive wire. Resistive random access memory.
[Appendix 2]
The first conductive wire is a ward wire and is
The second conductive wire is a bit wire and is
The resistance change type memory according to Appendix 1, wherein the third conductive wire is a plate wire.
[Appendix 3]
The first conductive wire is a global word wire and is
The second conductive wire is a global bit wire and is
The resistance change type memory according to Appendix 1, wherein the third conductive wire is a first local word wire.
[Appendix 4]
A second resistance changing film capable of reversibly changing between the first resistance state and the second resistance state, one end of which is connected to the source,
Further provided with a second local word line connected to the other end of the second resistance changing film.
The drive unit is the resistance change type memory according to Appendix 3 that drives the second resistance change film.
[Appendix 5]
While applying the first voltage to the global word line, the drive unit applies a fourth voltage between the global bit line and the second local word line.
The resistance change memory according to Appendix 4, wherein the fourth voltage is lower than the voltage at which the second resistance change film changes from the first resistance state to the second resistance state.
[Appendix 6]
Further equipped with local bit lines,
The resistance change type memory according to Appendix 5, wherein the first resistance change film and the second resistance change film are connected to the source of the selection transistor via the local bit line.
[Appendix 7]
A first resistance change film capable of reversibly changing between a first resistance state and a second resistance state having a resistance higher than that of the first resistance state.
A selection transistor having a gate, a drain, and a source, the source of which is connected to one end of the first resistance change film.
The first conductive wire connected to the gate and
The second conductive wire connected to the drain and
A method for driving a resistance change type memory including a third conductive wire connected to the other end of the first resistance change film.
When the first resistance change film is in the first resistance state, a first voltage equal to or higher than the threshold voltage of the selection transistor is applied to the first conductive wire.
While the first voltage is applied to the first conductive wire, the first resistance changing film is formed between the second conductive wire and the third conductive wire. While applying a second voltage that changes from the resistance state to the second resistance state and applying the second voltage between the second conductive wire and the third conductive wire, the second voltage is applied. A method for driving a resistance change type memory, comprising applying a third voltage lower than the threshold voltage to the conductive wire of 1.
[Appendix 8]
The first conductive wire is a ward wire and is
The second conductive wire is a bit wire and is
The third conductive wire is a plate wire, which is the method for driving a resistance-changing memory according to Appendix 7.
[Appendix 9]
The first conductive wire is a global word wire and is
The second conductive wire is a global bit wire and is
The method for driving a resistance-changing memory according to Appendix 8, wherein the third conductive wire is a first local word wire.
[Appendix 10]
The resistance change type memory is
A second resistance change film capable of reversibly changing between the first resistance state and the second resistance state, one end of which is connected to the source.
The method for driving a resistance-changing memory according to Appendix 8, further comprising a second local word line connected to the other end of the second resistance-changing film.
[Appendix 11]
Further comprising applying a fourth voltage between the global bit line and the second local word line while applying the first voltage to the global word line.
The driving method according to Appendix 10, wherein the fourth voltage is lower than the voltage at which the second resistance change film changes from the first resistance state to the second resistance state.

Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other embodiments, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are also included in the scope of the invention described in the claims and the equivalent scope thereof.

BL ... Bit line, GWL ... Global word line, LBL ... Local bit line, LWL ... Local word line, MC, C000 ... Memory cell, WL ... Word line, 1 ... Resistance change type memory, 2 ... Memory cell array, 3 ... Drive Part, 11 ... selection transistor (selection element), 12 ... resistance change film, 21 ... selection circuit, 22 ... voltage generation application circuit.

Claims (11)

A first resistance change film capable of reversibly changing between a first resistance state and a second resistance state having a resistance higher than that of the first resistance state.
A selection transistor having a gate, a drain, and a source, the source of which is connected to one end of the first resistance change film.
The first conductive wire connected to the gate and
The second conductive wire connected to the drain and
A third conductive wire connected to the other end of the first resistance change film,
It includes the first resistance change film and a drive unit for driving the selection transistor.
The drive unit
When the first resistance change film is in the first resistance state, a first voltage equal to or higher than the threshold voltage of the selection transistor is applied to the first conductive wire.
While the first voltage is applied to the first conductive wire, the first resistance changing film is formed between the second conductive wire and the third conductive wire. A second voltage that changes from the resistance state to the second resistance state is applied,
While the second voltage is applied between the second conductive wire and the third conductive wire, a third voltage lower than the threshold voltage is applied to the first conductive wire. Resistive random access memory. The first conductive wire is a ward wire and is
The second conductive wire is a bit wire and is
The resistance change type memory according to claim 1, wherein the third conductive wire is a plate wire. The first conductive wire is a global word wire and is
The second conductive wire is a global bit wire and is
The resistance change type memory according to claim 1, wherein the third conductive wire is a first local word wire. A second resistance changing film capable of reversibly changing between the first resistance state and the second resistance state, one end of which is connected to the source,
Further provided with a second local word line connected to the other end of the second resistance changing film.
The resistance change type memory according to claim 3, wherein the drive unit drives the second resistance change film. While applying the first voltage to the global word line, the drive unit applies a fourth voltage between the global bit line and the second local word line.
The resistance change type memory according to claim 4, wherein the fourth voltage is lower than the voltage at which the second resistance change film changes from the first resistance state to the second resistance state. Further equipped with local bit lines,
The resistance change type memory according to claim 5, wherein the first resistance change film and the second resistance change film are connected to the source of the selection transistor via the local bit line. A first resistance change film capable of reversibly changing between a first resistance state and a second resistance state having a resistance higher than that of the first resistance state.
A selection transistor having a gate, a drain, and a source, the source of which is connected to one end of the first resistance change film.
The first conductive wire connected to the gate and
The second conductive wire connected to the drain and
A method for driving a resistance change type memory including a third conductive wire connected to the other end of the first resistance change film.
When the first resistance change film is in the first resistance state, a first voltage equal to or higher than the threshold voltage of the selection transistor is applied to the first conductive wire.
While the first voltage is applied to the first conductive wire, the first resistance changing film is formed between the second conductive wire and the third conductive wire. While applying a second voltage that changes from the resistance state to the second resistance state and applying the second voltage between the second conductive wire and the third conductive wire, the second voltage is applied. A method for driving a resistance change type memory, comprising applying a third voltage lower than the threshold voltage to the conductive wire of 1. The first conductive wire is a ward wire and is
The second conductive wire is a bit wire and is
The method for driving a resistance-changing memory according to claim 7, wherein the third conductive wire is a plate wire. The first conductive wire is a global word wire and is
The second conductive wire is a global bit wire and is
The method for driving a resistance-changing memory according to claim 8, wherein the third conductive wire is a first local word wire. The resistance change type memory is
A second resistance changing film capable of reversibly changing between the first resistance state and the second resistance state, one end of which is connected to the source,
The method for driving a resistance-changing memory according to claim 9, further comprising a second local word line connected to the other end of the second resistance-changing film. Further comprising applying a fourth voltage between the global bit line and the second local word line while applying the first voltage to the global word line.
The driving method according to claim 10, wherein the fourth voltage is lower than the voltage at which the second resistance change film changes from the first resistance state to the second resistance state.

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