JP6972059B2 - Resistive random access memory - Google Patents

Description

Embodiments of the present invention relate to resistance random access memory.

A resistance change type memory using a memory cell capable of reversibly changing between a high resistance state and a low resistance state is known. When changing from a high resistance state to a low resistance state, a pulse voltage (set voltage) is applied to the memory cell. After that, it is determined whether or not the memory cell is in the low resistance state, and if it is not in the low resistance state, the set voltage is applied to the memory cell again. The application of the set voltage is repeated a certain number of times until the memory cell is confirmed to be in a low resistance state.

K.-J. Lee et al., A 90 nm 1.8 V 512 Mb Diode-Switch PRAM With 266 MB / s Read Throughput, IEEE Journal of Solid-State Circuits, vol. 43, no. 1, pp. 150-162 , 2008.

An object of the present invention is to provide a resistance change type memory capable of reducing the number of times a voltage is applied to a memory cell when the memory cell is changed from a high resistance state to a low resistance state.

The resistance change type memory of the embodiment is a memory cell capable of reversibly changing between a first resistance state and a second resistance state having a resistance higher than that of the first resistance state, and the memory cell. Includes a drive unit that drives the. The drive unit applies a first pulsed voltage to bring the memory cell into the low resistance state. After applying the first pulsed voltage to the memory cell, the driving unit determines whether or not the memory cell is in the first resistance state, and determines that the memory cell is not in the first resistance state. If so, a second pulsed voltage having a maximum voltage lower than that of the first pulsed voltage is applied to the memory cell.

FIG. 1 is a diagram showing a configuration of a resistance change type memory according to the first embodiment. FIG. 2 is a diagram showing a configuration of a memory cell array. FIG. 3 is a diagram showing a configuration of memory cells. FIG. 4 is a block showing the configuration of the drive unit. FIG. 5 is a diagram showing a voltage used for the set operation of the first embodiment. FIG. 6 is a flowchart showing the set operation of the first embodiment. FIG. 7 is a diagram showing resistance-pulse voltage characteristics of the resistance change storage element. FIG. 8 is a diagram showing an implementation example of the resistance change type memory of the embodiment. FIG. 9 is a diagram showing a voltage used for the set operation of the second embodiment. FIG. 10 is a flowchart showing the set operation of the second embodiment. FIG. 11 is a diagram showing a voltage used for the set operation of the third embodiment. FIG. 12 is a diagram showing an example of another set pulse of the embodiment.

Hereinafter, embodiments will be described with reference to the drawings. The drawings are schematic or conceptual and may not always be the same as the real ones. Further, in the drawings, the same reference numerals are given the same or corresponding parts, and duplicate explanations will be given as necessary. Further, for simplification, even if there are the same or equivalent parts, they may not be labeled.

(First Embodiment)
FIG. 1 is a schematic diagram showing the configuration of the resistance change type memory 1 according to the first embodiment.
The resistance change type memory 1 includes a memory cell array 2 and a drive unit 3.
As shown in FIG. 2, the memory cell array 2 has a plurality of word lines WL (WL1, WL2, WL3, WL4, ...) Extending in the first direction and a second direction intersecting with the first direction. Includes a plurality of bit lines BL (BL1, BL2, BL3, BL4, ...) Extending to, and a memory cell MC provided at each intersection of the plurality of word lines WL and the plurality of bit lines BL.

The memory cell MC can reversibly change between a first resistance state (low resistance state) and a second resistance state (high resistance state) having a higher resistance than the first resistance state. As shown in FIG. 3, the memory cell MC is, for example, a resistance change storage element including a resistance change film 11 and a selection element 12. One end of the resistance change film 11 is connected to the bit line BL, the other end of the resistance change film 11 is connected to one end of the selection element 12, and the other end of the selection element 12 is connected to the word line WL.

The resistance change type memory 1 includes PCM (Phase Change Memory), and the resistance change film 11 includes, for example, GeSbTe or GeTe. When the resistance change type memory 1 is a PCM (Phase Change Memory), the resistance change film 11 includes, for example, a superlattice in which GeTe and SbTe are laminated.

The selection element 12 is, for example, a diode or a bidirectional diode. The selection element 12 may be the following two-terminal switch element. That is, when the voltage applied between the two terminals of the switch element between the two terminals is equal to or less than the threshold value, the switch element is in a high resistance state, for example, an electrically non-conducting state. When the voltage applied between the two terminals is equal to or greater than the threshold value, the switch element changes to a low resistance state, for example, an electrically conductive state. The two-terminal switch element may have this function regardless of the polarity of the voltage. The two-terminal switch element may contain at least one chalcogen element selected from the group consisting of Te, Se and S, or chalcogenide which is a compound containing the chalcogen element. The switch element may also contain at least one element selected from the group consisting of B, Al, Ga, In, C, Si, Ge, Sn, As, P, and Sb.

The drive unit 3 controls the drive voltage applied to the memory cell MC, reads and writes data, and controls the data. As shown in FIG. 4, for example, the address selection circuit 21, the voltage generation circuit 22, and the voltage. The application circuit 23, the current detection circuit 24, and the controller 25 are included.

The address selection circuit 21 selects the address of the memory cell MC when reading information (reading operation) and writing information (writing operation). The voltage generation circuit 22 generates a voltage applied to the memory cell MC required for the read operation and the write operation. The voltage application circuit 23 applies the voltage generated by the voltage generation circuit 22 to the memory cell MC selected by the address selection circuit 21. The current detection circuit 24 detects the current flowing through the selected memory cell MC during the read operation and the verify read operation. The controller 25 is configured to be able to integrally control the address selection circuit 21, the voltage generation circuit 22, the voltage application circuit 23, and the current detection circuit 24. The above configuration is an example, and different configurations may be used. For example, instead of detecting the current flowing through the memory cell MC selected during the read operation, the voltage when a constant current is passed may be detected.

Next, the set operation of the resistance change type memory 1 of the present embodiment will be described. FIG. 5 is a diagram showing a voltage used for the set operation of the present embodiment. FIG. 6 is a flowchart showing the set operation of the present embodiment.
The set operation is a write operation that changes the selected memory cell MC from a high resistance state to a low resistance state. In the case of PCM, it is an operation of changing the resistance change film 11 of the memory cell MC from an amorphous state (high resistance state) to a crystalline state (low resistance state). The reset operation is a write operation that changes the selected memory cell MC from a low resistance state to a high resistance state.

_{First, a pulsed voltage (hereinafter referred to as pulse voltage) PN} (initial value N = 1), which is a write voltage, is applied to the selected memory cell MC (step S1). In this embodiment, the write voltage is the potential difference between the selected word line and the selected bit line.
Pulse voltage P1, as shown in FIG. 5, shorter with a rise time reaches the voltage V ₀ to the maximum voltages V _1, the maximum voltage V ₁ was continues for a predetermined period of time, then the pulse voltage P1 is toward voltage V ₀ It goes down slowly. A pulse having such a shape is called a set pulse. The pulse voltage P1 is applied to the selected memory cell MC by applying an appropriate voltage to each of the word line WL and the bit line BL, for example.

Next, verify is performed. That is, it is determined whether or not the memory cell MC to which the pulse voltage P1 is applied is in the low resistance state (step S2).
More specifically, for example, the current flowing through the memory cell MC is read, and if the value of the read current (read current) is equal to or less than the reference value, it is determined that the memory cell MC is in a low resistance state, and the read current is high. If it exceeds the reference value, it is determined that the memory cell MC is in a low resistance state. This determination is made, for example, by the controller 25. The read current value is detected by using, for example, the current detection circuit 24.

If it is determined in step S2 that the memory cell MC is in the low resistance state (Yes), the set operation ends. On the other hand, if it is determined that the memory cell MC is in a high resistance state (No), the process proceeds to step S3.
In step S3, the number of N is incremented by one, and then a pulse voltage _PN (N ≧ 2) is applied to the memory cell MC (step S4). Period during which a pulse voltage is applied P _N to the memory cell MC is shorter than the period in which a pulse voltage is applied P ₁ to the memory cell MC.

As shown in FIG. 5, the pulse voltage P2 reaches the maximum voltage V ₂ (<V _{1 ) from the voltage V 0} with a short rise time, the maximum voltage V ₂ continues for a certain period, and then a short fall time. Therefore, the voltage drops to _{V 0.} A pulse having such a shape is called a reset pulse. Comparing the reset pulse and the set pulse, if the time other than the falling time is the same, the set pulse has a longer pulse application time than the reset pulse.

After step 4, it is determined whether or not N has reached a certain value (Nmax) (step S5). When it is determined in step S5 that N has reached a certain value (Nmax) (Yes), the set operation ends.
On the other hand, when it is determined in step S5 that N is less than a certain value (Nmax) (No), steps S2 to S5 until the determination in step S2 becomes Yes or until the determination in step S5 becomes Yes. Loop is repeated.

In the present embodiment, the voltage used in step S4 in N = 3 (write voltage) is almost the same as the pulse voltage P2 as shown in FIG. 5 (or the same) pulsed voltage P3 having the maximum voltage V ₂ (the reset pulse) Is. The same applies to N ≧ 4.
In this embodiment, as described above, the set pulse is used in step S4 (reapplying the write voltage). The reason is as follows.

FIG. 7 is a diagram showing an example of the characteristics of the resistance-pulse voltage of the resistance change storage element.
In FIG. 7, the solid line shows the characteristics when the set pulse is applied to the resistance change storage element in the high resistance state, and the broken line shows the characteristics when the reset pulse is applied to the resistance change storage element in the low resistance state.

As can be seen from FIG. 7, when a set pulse having a constant voltage value or more is applied to the resistance change storage element in the high resistance state, the resistance value of the resistance change storage element is lowered to some extent, and then the above-mentioned set is applied to the resistance change storage element. When a reset pulse having a voltage lower than the pulse and a constant current value or less is applied, the resistance value of the resistance change storage element is further lowered.

Further, when a set pulse having a constant voltage value or more was applied to the resistance change storage element in the high resistance state, the resistance change storage element was able to transition to the lower resistance state, but the above-mentioned low voltage reset pulse. It was found that the resistance value varied more than after the application.
From the above, in the case of the above characteristics, in order to reduce the resistance from the high resistance state, it is effective to first apply a set pulse with a high maximum voltage, but the resistance value of the resistance change storage element is to some extent. It can be seen that it is more effective to apply a reset pulse having a maximum voltage that is somewhat lower than the above-mentioned maximum voltage in order to further reduce the resistance value after the decrease. Therefore, in the present embodiment, the reset pulse shown in FIG. 5 is used in step S4 (reapplying the write voltage).

By using the reset pulse as the pulse voltage for the second and subsequent times, the number of loops can be reduced by lowering the resistance and reducing the variation as described above, and if the reset pulse is used, the writing voltage application time can be shortened compared to the set pulse. Since it can be shortened, the speed of the iterative process including step S2 (verify) and step S4 (reapplying the write voltage) can be increased.

In step S2 (verify), a different determination criterion may be used for each loop repetition rate (N).
Further, after applying the pulse voltage P2, the verification may be completed without performing the verify (step S2). Such a change is adopted, for example, when it is known that the memory cell is likely to be in a low resistance state when a pulse voltage P2 is applied. Similarly, even after the pulse voltage P3, it may be terminated without performing the verify (step S2).

FIG. 8 is a diagram showing an implementation example of the resistance change type memory 1.
The resistance change type memory 1 includes, for example, a memory cell array 2, a column switch 31, a sense amplifier circuit 32, a bit line (BL) driver circuit 33, a low decoder circuit 34, a word line (WL) driver circuit 35, and a voltage generation circuit 36a. 36b and peripheral circuit 37 are included.

Each bit line BL is connected to the sense amplifier circuit 32 and the bit line driver circuit 33 via the column switch 31. Each word line WL is connected to the word line driver circuit 35 via the row decoder circuit 14.
The address selection circuit 21 of FIG. 4 is implemented by using the column switch 31 and the row decoder circuit 34. The voltage generation circuit 22 of FIG. 4 is mounted by using the voltage generation circuit 36a provided in the BL driver 33 and the voltage generation circuit 36b provided in the WL driver circuit 35. The voltage generation circuits 36a and 36b may be provided outside the BL driver 33 and the WL driver circuit 35. The voltage application circuit 23 of FIG. 4 is mounted by using the BL driver circuit 33 and the WL driver circuit 35. The current detection circuit 24 of FIG. 4 is mounted using the sense amplifier circuit 32. The controller 25 of FIG. 4 is mounted using the peripheral circuit 37. The peripheral circuit 37 includes a column switch 31, a sense amplifier circuit 32, a bit line driver circuit 33, a low decoder circuit 34, a word line driver circuit 35, and a voltage generation circuit so that data can be written, read out, and verified. It is configured so that 36a and 36b can be controlled in an integrated manner.

(Second embodiment)
FIG. 9 is a diagram showing a voltage used for the set operation of the resistance change type memory of the present embodiment. FIG. 10 is a flowchart for explaining the setting operation of the resistance change type memory of the present embodiment.
The difference between this embodiment and the first embodiment is that when N ≧ 2, the maximum pulse voltage (reset pulse) P2, P3, ... Is increased each time the loop repetition rate (N) is increased by one. The voltage (V ₂ <V ₃ <...) becomes high (step S4).

As shown in FIG. 7, if the voltage is a certain value or less, the higher the voltage is, the lower the resistance is even if it is a reset pulse. Therefore, according to the present embodiment, it is possible to further reduce the resistance in one loop, and thereby it is possible to reduce the number of loops (N).

The increase width of the maximum voltage of the reset pulse does not have to be constant in each loop.
(Third embodiment)
FIG. 11 is a diagram showing a voltage used for the set operation of the resistance change type memory of the present embodiment. The flowchart of the set operation of the resistance change type memory of the present embodiment is the same as that of the second embodiment except that the write voltage when N ≧ 2 is a set pulse.

The difference between this embodiment and the second embodiment is that a set pulse is used as the pulse voltages P2, P3, ... In step S4. This makes it possible to reduce the possibility that the memory cell MC will be in a high resistance state when the maximum voltage of the pulse voltages P2, P3, ... Is increased in step S4.

Further, in the present embodiment, since the pulse voltages P1, P2, P3, ... Have the same type of waveform, it is possible to simplify the configuration of the circuit that generates the pulse voltage.
The increase width of the maximum voltage of the pulse voltage (set pulse) P2, P3, ... Does not have to be constant in each loop. Further, when N ≧ 3, a set pulse having a maximum voltage higher than the pulse voltage P1 may be applied.

In the first to third embodiments described above, those which are set pulse of the pulse voltage P _N, as shown in FIG. 12, also include a gradually drops waveform stepwise the maximum voltage V _N I do not care.
Further, in the above-described embodiment, the configuration of the memory cell MC has been described by using an example including one resistance change storage element and one selection element, but different configurations may be used. For example, the configuration may be adopted from only the resistance change storage element. Further, a component other than the selection element such as a resistance element may be used. Further, a configuration in which a plurality of resistance change storage elements and selection elements are connected in series or in parallel may be adopted.

Some or all of the superordinate concepts, intermediate concepts and subordinate concepts of the above-described embodiments, and other embodiments not described above are, for example, any of the following appendices 1-15 and 1-15. It can be expressed as a combination (excluding combinations that are clearly inconsistent).
[Appendix 1]
A memory cell that can reversibly change between a first resistance state and a second resistance state having a higher resistance than the first resistance state.
A drive unit for driving the memory cell is provided.
The drive unit applies a first pulsed voltage to bring the memory cell into the first resistance state.
After applying the first pulsed voltage to the memory cell, the drive unit determines whether or not the memory cell is in the first resistance state, and determines that the memory cell is not in the first resistance state. If so, a resistance change type memory that applies a second pulsed voltage having a maximum voltage lower than that of the first pulsed voltage to the memory cell.
[Appendix 2]
The fall time of the first pulsed voltage is longer than the rise time of the first pulsed voltage.
The resistance change type memory according to Appendix 1, wherein the fall time of the second pulse-shaped voltage is shorter than the fall time of the first pulse-shaped voltage.
[Appendix 3]
The fall time of the first pulsed voltage is longer than the rise time of the first pulsed voltage.
The resistance change type memory according to Appendix 1, wherein the fall time of the second pulse voltage is longer than the rise time of the second pulse voltage.
[Appendix 4]
The period during which the second pulse-shaped voltage is applied to the memory cell is described in any one of Supplementary notes 1 to 3 shorter than the period during which the first pulse-shaped voltage is applied to the memory cell. Resistive random access memory.
[Appendix 5]
When the drive unit determines that the memory cell is not in the second resistance state after applying the second pulse-shaped voltage to the memory cell, the second pulse-shaped voltage is applied to the memory cell. The resistance change type memory according to any one of Supplementary note 1 to 4, wherein a third pulsed voltage having a maximum voltage substantially the same as or higher than the maximum voltage is applied.
[Appendix 6]
The resistance change type memory according to Appendix 5, wherein the falling time of the third pulsed voltage is shorter than the falling time of the first pulsed voltage.
[Appendix 7]
The resistance change type memory according to Appendix 5, wherein the rising time of the third pulsed voltage is longer than the rising time of the third pulsed voltage.
[Appendix 8]
The resistance change type memory according to any one of Supplementary note 5 to 7, wherein the second pulse-shaped voltage and the third pulse-shaped voltage have substantially the same maximum voltage.
[Appendix 9]
The resistance change type memory according to any one of Supplementary note 5 to 7, wherein the third pulse-shaped voltage has a maximum voltage higher than that of the second pulse-shaped voltage.
[Appendix 10]
The period during which the third pulse-shaped voltage is applied to the memory cell is described in any one of Supplementary note 5 to 9, which is shorter than the period during which the first pulse-shaped voltage is applied to the memory cell. Resistive random access memory.
[Appendix 11]
13. Resistive random access memory.
[Appendix 12]
The resistance change type memory according to any one of Supplementary note 1 to 11, wherein the memory cell includes a resistance change film.
[Appendix 13]
The resistance-changing memory according to Appendix 12, wherein the resistance-changing film includes GeSbTe or a superlattice in which GeTe and SbTe are laminated.
[Appendix 14]
The resistance change type memory according to any one of Supplementary note 1 to 13, wherein the memory cell includes a selection element.
[Appendix 15]
The resistance change memory according to Appendix 14, wherein the selection element includes a diode or a bidirectional diode.

Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other embodiments, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are also included in the scope of the invention described in the claims and the equivalent scope thereof.

MC ... Memory cell, 1 ... Resistance change type memory, 2 ... Memory cell array, 3 ... Drive unit, 11 ... Resistance change film, 12 ... Selection element, 21 ... Address selection circuit, 22 ... Voltage generation circuit, 23 ... Voltage application circuit , 24 ... Current detection circuit, 25 ... Controller, 31 ... Column switch, 32 ... Sense amplifier circuit, 33 ... BL driver circuit, 34 ... Low decoder circuit, 35 ... WL driver circuit, 36a, 36b ... Voltage generation circuit, 37 ... Peripheral circuit.

Claims (10)

A memory cell that can reversibly change between a first resistance state and a second resistance state having a higher resistance than the first resistance state.
A drive unit for driving the memory cell is provided.
The drive unit applies a first pulsed voltage to bring the memory cell into the first resistance state.
After applying the first pulsed voltage to the memory cell, the driving unit determines whether or not the memory cell is in the first resistance state, and determines that the memory cell is not in the first resistance state. If so, a second pulsed voltage having a maximum voltage lower than that of the first pulsed voltage is applied to the memory cell.
The fall time of the first pulsed voltage is longer than the rise time of the first pulsed voltage.
The resistance change type memory in which the falling time of the second pulsed voltage is shorter than the falling time of the first pulsed voltage. The resistance change type according to claim 1, wherein the period in which the second pulse-shaped voltage is applied to the memory cell is shorter than the period in which the first pulse-shaped voltage is applied to the memory cell. memory. When the drive unit determines that the memory cell is not in the second resistance state after applying the second pulse-shaped voltage to the memory cell, the second pulse-shaped voltage is applied to the memory cell. The resistance change type memory according to claim 1 or 2 , wherein a third pulsed voltage having a maximum voltage substantially the same as or higher than the maximum voltage is applied. The resistance change type memory according to claim 3 , wherein the falling time of the third pulsed voltage is shorter than the falling time of the first pulsed voltage. The resistance change type memory according to claim 3 , wherein the rising time of the third pulsed voltage is longer than the rising time of the third pulsed voltage. The resistance change type memory according to any one of claims 3 to 5 , wherein the second pulse-shaped voltage and the third pulse-shaped voltage have substantially the same maximum voltage. The resistance change type memory according to any one of claims 3 to 5 , wherein the third pulse-shaped voltage has a maximum voltage higher than that of the second pulse-shaped voltage. The period in which the third pulse-shaped voltage is applied to the memory cell is shorter than the period in which the first pulse-shaped voltage is applied to the memory cell according to any one of claims 3 to 7. The described resistance variable memory. The driving unit is according to any one of claims 1 to 8 , wherein the driving unit includes a voltage generating unit that generates a pulsed voltage and a determining unit that determines whether or not the memory cell is in the first resistance state. Resistive random access memory. The resistance change type memory according to any one of claims 1 to 9 , wherein the memory cell includes a resistance change film.

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