JP5223005B2 - Semiconductor memory device and manufacturing method thereof - Google Patents

Semiconductor memory device and manufacturing method thereof Download PDF

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JP5223005B2
JP5223005B2 JP2011521720A JP2011521720A JP5223005B2 JP 5223005 B2 JP5223005 B2 JP 5223005B2 JP 2011521720 A JP2011521720 A JP 2011521720A JP 2011521720 A JP2011521720 A JP 2011521720A JP 5223005 B2 JP5223005 B2 JP 5223005B2
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resistance
memory cell
voltage
memory device
semiconductor memory
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JPWO2011004448A1 (en
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佳孝 笹子
勝治 木下
則克 高浦
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株式会社日立製作所
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    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C13/00Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00 - G11C25/00
    • G11C13/0002Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00 - G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0004Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00 - G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C13/00Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00 - G11C25/00
    • G11C13/0002Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00 - G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021Auxiliary circuits
    • G11C13/0023Address circuits or decoders
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/24Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying or switching without a potential-jump barrier or surface barrier, e.g. resistance switching non-volatile memory structures
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2213/00Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70Resistive array aspects
    • G11C2213/71Three dimensional array
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2213/00Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70Resistive array aspects
    • G11C2213/72Array wherein the access device being a diode
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2213/00Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70Resistive array aspects
    • G11C2213/79Array wherein the access device being a transistor

Description

  The present invention relates to a semiconductor memory device and a method for manufacturing the same, and more particularly to a technique for realizing high reliability of a rewritable nonvolatile semiconductor memory device.

  In recent years, a phase change memory (Patent Document 1) using a chalcogenide material as a recording material has been actively studied. The memory structure of the phase change memory has a recording material sandwiched between metal electrodes. The phase change memory is a resistance change type memory that stores information using the fact that recording materials between electrodes have different resistance states.

The phase change memory stores information using the fact that the resistance value of a phase change material such as Ge 2 Sb 2 Te 5 is different between an amorphous state and a crystalline state. The resistance is high in the amorphous state and low in the crystalline state. Therefore, reading is performed by applying a potential difference to both ends of the element, measuring the current flowing through the element, and determining the high resistance state / low resistance state of the element.

  In the phase change memory, data is rewritten by changing the electric resistance of the phase change film to a different state by Joule heat generated by current. The reset operation, that is, the operation of changing to a high resistance amorphous state is performed by flowing a large current for a short time to dissolve the phase change material, and then rapidly decreasing and rapidly cooling the current. On the other hand, the set operation, that is, the operation of changing to a low-resistance crystal state is performed by flowing a current sufficient for maintaining the crystallization temperature of the phase change material for a long time.

  These variable resistance elements are used in a structure in which selection elements such as diodes and transistors are added to individual variable resistance elements when integrated. For example, it is possible to form a high-density memory cell array by arranging memory cells in which diodes and resistance variable elements are connected in series and combined in a cross-point type. The diode and the transistor are used for selecting and rewriting or reading out individual memories from the memory cell array. By increasing the number of memory cells as in Patent Document 1, it is possible to further increase the capacity.

JP 2005-260014 A

  If a selection element used in combination with a resistance variable element includes a defective element having a leakage current exceeding an allowable value, a short circuit problem occurs in the circuit of the memory cell array when the resistance variable element is in a low resistance state. That is, a large current can flow through a memory cell including a defective element during rewriting and reading even when it is not selected. At the time of writing, if the resistance variable element of the memory cell including the defective element is in a low resistance state, the memory cell array circuit is short-circuited, so that a desired voltage cannot be applied to the memory cell array and the device malfunctions. To do. At the time of reading, the leakage current value varies greatly depending on whether the resistance variable element connected to the defective element is in a low resistance state or a high resistance state, and the result of the reading current of the memory cell to be originally selected varies greatly. Giving the device a malfunction.

  An object of the present invention is to provide a technique for preventing a semiconductor memory device including a phase change memory cell array from malfunctioning due to a leakage current of a defective selection element and promoting high reliability of the semiconductor memory device.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  According to the present invention, in a semiconductor memory device having a phase change memory cell array, Joule heat required for rewriting is generated even if rewriting operation is performed on the resistance value of a resistance change element of a memory cell having a defective selection element. Use a high resistance that is not too high. As a result, the resistance value of the variable resistance element connected to the defective selection element is kept high, and malfunction of the semiconductor memory device is prevented.

  According to the present invention, a large-capacity, high-performance, and high-reliability nonvolatile semiconductor memory device can be provided at a high yield, that is, at low cost.

1 is a schematic diagram of a semiconductor memory device of the present invention. It is a three-dimensional schematic diagram of the memory cell array of the present invention. It is a figure explaining high resistance and low resistance operation | movement of the phase change memory of this invention. FIG. 5 is a circuit diagram illustrating a read operation of the memory cell array according to the present invention. FIG. 6 is a circuit diagram illustrating a set operation and a reset operation of the memory cell array according to the present invention. It is a figure explaining high resistance and low resistance operation | movement of the phase change memory of this invention. It is the circuit diagram which showed the high resistance operation | movement of the defective cell used in an example of Example 1 of this invention. It is the circuit diagram which showed the high resistance operation | movement of the defective cell used in an example of Example 1 of this invention. It is the operation | movement sequence diagram which showed an example of Example 1 of this invention. It is the circuit diagram which showed the high resistance operation | movement of the defective cell used in an example of Example 1 of this invention. It is the operation | movement sequence diagram which showed an example of Example 1 of this invention. It is the figure which showed the effect of Example 1 of this invention. FIG. 3 is a three-dimensional view of a memory cell array to which the first embodiment can be applied. FIG. 3 is a three-dimensional view of a memory cell array to which the first embodiment can be applied. It is sectional drawing of the memory cell array by which the memory cell provided with the serial structure of a transistor and a resistance change element was arrange | positioned at an intersection type. FIG. 16 is a circuit diagram illustrating a read operation, a set operation, and a reset operation of the memory cell array in FIG. 15. It is the circuit diagram which showed the high resistance operation | movement of the defective cell used in an example of Example 2 of this invention. It is the operation | movement sequence diagram which showed an example of Example 2 of this invention. It is the circuit diagram which showed the high resistance operation | movement of the defective cell used in an example of Example 2 of this invention. It is the operation | movement sequence diagram which showed an example of Example 2 of this invention. FIG. 6 is a three-dimensional view of a memory cell array to which the second embodiment can be applied. It is the memory hierarchy figure which showed an example of the semiconductor memory device which is Example 3 of this invention. It is the operation | movement sequence diagram which showed an example of Example 3 of this invention. It is the operation | movement sequence diagram which showed an example of Example 3 of this invention. It is the operation | movement sequence diagram which showed an example of Example 3 of this invention. It is the operation | movement sequence diagram which showed an example of Example 3 of this invention. It is the operation | movement sequence diagram which showed an example of Example 5 of this invention.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted.

  FIG. 1 is an overall view showing a semiconductor memory device using a phase change memory according to a first embodiment of the present invention. FIG. 2 is a partial three-dimensional view of the memory cell array, and shows a diagram in which memory cells in which a resistance change element of a phase change memory and a diode are connected in series are arranged in an intersection type. FIG. 4 is a circuit diagram showing a read operation of the memory cell array, and FIG. 5 is a circuit diagram showing a write operation. The diode as the selection element can have a reverse voltage withstand voltage of, for example, 4 V by device design such as profile design of N-type impurities and P-type impurities. In this embodiment, an example in which the reverse voltage withstand voltage of the diode is 4V is shown.

  As shown in FIG. 1, the semiconductor memory device according to the first embodiment of the present invention includes a plurality of different I / O interfaces 1001 including an input / output buffer for exchanging data with the outside, and a memory cell array 1002. A plurality of power supplies 1003 to 1007 for supplying a voltage, a voltage selector 1008 for selecting a voltage from the power supplies 1003 to 1007, and a connection destination of an output from the voltage selector 1008 such as a bit line and a word line of the memory cell array 1002 A wiring selector 1009 for selecting from among the wirings and a control unit 1010 for controlling the entire apparatus are provided. A reading unit 1011 having a sense amplifier or the like is connected to the wiring selector 1009. In the memory cell array 1002, a management area 1012 for recording various information of the device is provided.

  When data is input from the external device to the I / O interface 1001, the control unit 1010 selects a voltage for writing data with the voltage selector 1008, generates a voltage pulse with one of the power supplies 1003 to 1007, and performs wiring. A voltage pulse is supplied to a predetermined wiring of the memory cell array 1002 using the selector 1009. Thereby, the input data is written to the phase change memory cell of the memory cell array.

  When a data read signal is input to the I / O interface 1001 from an external device, the control unit 1010 selects a voltage for reading data with the voltage selector 1008 and generates a voltage with one of the power supplies 1003 to 1007. Then, a voltage is supplied to a predetermined wiring of the memory cell array 1002 by the wiring selector 1009. As a result of supplying the voltage, the read current is read by the reading unit 1011 and the stored data is reproduced, and the data is supplied to the external device via the control unit 1010 and the I / O interface 1001.

  FIG. 2 is a three-dimensional view in which a part of the memory cell array 1002 is enlarged. As shown in FIG. 2, the semiconductor memory device according to the first embodiment of the present invention includes a plurality of word lines 2 formed above a silicon substrate and a plurality of bit lines provided in a direction intersecting the word lines 2. 3 is provided. On the word line 2, a p-type semiconductor layer 4 such as p-type polysilicon or p-type semiconductor oxide, an n-type semiconductor layer 5 such as n-type polysilicon or n-type semiconductor oxide, and a resistance change element A lower electrode 8, a resistance change element recording layer 6, a resistance change element upper electrode 7, and a bit line 3 are formed in this order. The layer 10 between the lower electrode 8 and the n-type semiconductor layer 5 is a barrier metal layer such as TiN or a metal silicide layer such as TiSi. The layer 10 may have a laminated structure having a metal silicide layer on the side in contact with the n-type semiconductor layer 5 and a barrier metal layer on the side in contact with the lower electrode 8.

  The p-type semiconductor layer 4 and the n-type semiconductor layer 5 form a diode serving as a selection element. For example, a phase change material can be used as the material of the recording layer 6 to be a resistance variable element. As the phase change material, for example, a material containing germanium, antimony, or tellurium can be used.

For the recording layer 6 of the resistance variable element, for example, a laminated film of a layer containing a metal oxide and a layer containing a phase change material formed on the lower electrode 8 can be used. Here, the laminated film has a layer structure in which a layer containing a metal oxide is formed on the lower electrode 8 and a layer containing a phase change material is formed on the layer containing the metal oxide, or A layer structure including a metal oxide layer in contact with the upper electrode 7 and a layer including a phase change material under the metal oxide layer is provided. For example, Ta 2 O 5 can be used as the metal oxide. By making the recording film 6 a laminated film of a layer containing a metal oxide and a layer containing a phase change material, the resistance change described later is made in comparison with the case where the recording layer 6 is not provided with a layer containing a metal oxide. The high resistance state of the mold element becomes more thermodynamically stable.

  A set of resistance variable elements and selection elements connected in series are hereinafter referred to as memory cells. In the memory cell array shown in FIG. 2, memory cells are arranged at intersections of a plurality of word lines 2 and a plurality of bit lines 3. A diode as a selection element is connected to the word line 2, and the recording layer 6 of the resistance variable element is connected to the bit line 3 via the upper electrode 7.

The semiconductor memory device of the present invention stores information by utilizing the fact that the phase change material such as Ge 2 Sb 2 Te 5 contained in the recording layer 6 has different resistance values between an amorphous state and a crystalline state. The resistance is high in the amorphous state and low in the crystalline state. Therefore, reading can be performed by determining a high resistance state and a low resistance state of the element by applying a potential difference to both ends of the resistance variable element and measuring a current flowing through the element.

FIG. 3 is a diagram showing the temperature change of the recording layer during the rewrite operation of the phase change memory according to the first embodiment of the present invention. The operation to change the phase change material from the high-resistance amorphous state to the low-resistance crystalline state, and conversely the low-resistance crystalline state to the high-resistance amorphous state 3 is performed by giving the temperature change as shown in FIG. 3 to the phase change material. Specifically, the phase change material in an amorphous state can be brought into a crystalline state by heating to a temperature higher than the crystallization temperature and holding it for about 10 −6 seconds or longer. Further, the phase change material in a crystalline state can be brought into an amorphous state by heating it to a temperature equal to or higher than the melting point to make it liquid and then rapidly cooling it.

  In Embodiment 1 of the present invention, data writing is performed by heating the phase change material of the recording layer 6 to a temperature equal to or higher than the melting point by Joule heat generated by current and changing the electric resistance to different states. The reset operation, that is, the operation of changing to the high resistance amorphous state is performed by flowing a large current for a short time and dissolving it, and then rapidly decreasing and rapidly cooling the current. On the other hand, the set operation, that is, the operation of changing to a low-resistance crystal state is performed by flowing a current sufficient for maintaining the crystallization temperature for a long time. Hereinafter, the state of the memory cell in which the recording layer is in the crystalline state by the set operation is referred to as a first state or a set state. The resistance state of the resistance variable element when the memory cell is in the first state is referred to as a first resistance state. The state of the memory cell in which the recording layer 6 is brought into an amorphous state by the reset operation is referred to as a second state or a reset state. The resistance state of the resistance variable element when the memory cell is in the second state is referred to as a second resistance state.

  Here, in the second state, not all of the phase change material of the recording layer 6 is amorphized, and a part of the phase change material is amorphized to be in a high resistance state. Accordingly, if the ratio of the amorphous state of the recording layer 6 is larger than that in the second state, the recording layer 6 is in a higher resistance state than in the second state. The higher resistance can be realized, for example, by applying a higher voltage to the memory cell and setting the phase change material of the recording layer 6 to a higher temperature.

  As shown in FIG. 4, in order to perform reading by selecting one cell from the memory cell array, the word line to which the selected cell is connected (SWL: selected word line) and the word line to which the selected cell is not connected (USWL) : Unselected word line), bit line to which the selected cell is connected (SBL: selected bit line), bit line to which the selected cell is not connected (USBL: unselected bit line) For example, voltages of 1V, 0V, 0V, and 1V are applied, respectively. That is, Vread is set to 1V. Here, 0V means a reference voltage. In the following description, 0V means a reference voltage. Thanks to the fact that the diode as the selection element hardly causes a leak current of reverse voltage to flow, the current flows only in the selected cell SMC, and the resistance state can be determined by measuring with a sense amplifier.

In order to select one cell from the memory cell array and perform the set operation, as shown in FIG. 5, SWL, USWL, SBL, and USBL are respectively connected to, for example, 2. Apply 5V, 0V, 0V, 2.5V voltage. That is, Vset is set to 2.5V. At this time, no current flows in CellD connected to USWL and USBL because the voltage applied to the diode as the selection element is a reverse voltage. In addition, no current flows through CellB connected to USWL and SBL and CellC connected to SWL and USBL because the bit line and the word line are equipotential. A current flows only through the selected cell SMC and the recording layer 6 is heated by Joule heat. The voltage Vset applied between SBL and SWL may be a voltage sufficient to heat the phase change material of the selected memory cell to the crystallization temperature. When a phase change memory cell array is manufactured by a 30 nm process, the power Wth necessary for crystallization is about 1 mW. The voltage for crystallization is determined by the electric power Wth necessary for crystallization and the resistance value of the resistance variable element in the second resistance state. When a voltage is applied for a time sufficient for crystallization (about 10 −6 seconds or more), the phase change material of the recording layer 6 of the selected cell is in a low resistance crystalline state, and the resistance variable element of the selected cell is in the set state, The first resistance state is entered. Other cells do not change state.

  To perform a reset operation by selecting one cell from the memory cell array, for example, 3V, 0V, 0V, respectively, in SWL, USWL, SBL, USBL in FIG. 5 using one of the power supplies 1003 to 1007. Apply 3V voltage. That is, Vreset is set to 3V. At this time, no current flows in CellD connected to USWL and USBL because the voltage applied to the diode as the selection element is a reverse voltage. In addition, no current flows through CellB connected to USWL and SBL and CellC connected to SWL and USBL because the bit line and the word line are equipotential. A current flows only through the selected cell SMC, and the phase change material of the recording layer 6 is heated by Joule heat. The voltage applied to the selected bit line and the selected word line may be a voltage sufficient to heat the phase change material of the recording layer 6 of the selected memory cell to a temperature higher than the melting point. When the applied voltage is rapidly set to 0 V and the recording layer 6 is rapidly cooled, the phase change material of the recording layer 6 of the selected cell is in a high resistance amorphous state, and the resistance variable element of the selected cell is in the second resistance state. Other cells do not change state.

  As described above, since the read operation of FIG. 4 and the set / reset operation of FIG. 5 can be correctly performed in the selected voltage within the withstand voltage of the diode as the selection element, the leakage current, That is, the current during reverse bias application is sufficiently small. If the current at the time of reverse bias application of the selection element of CellB is not sufficiently small, the SBL potential V of CellB becomes positive because of the voltage drop at RBL during the read operation of CellA in FIG. Leakage current is generated. Since the magnitude of the leakage current differs depending on the resistance state of the CellB variable resistance element, that is, the state of the recorded information, the current Iread determined by the sense amplifier varies depending on the state of CellB even if Icell flowing through CellA is the same. Readout malfunctions. In order to prevent at least malfunction, the leakage current needs to be smaller than the read current. When the semiconductor memory device of this embodiment is manufactured by the 50 nm generation manufacturing process, the read current is about 1 microampere. Therefore, in this case, it is necessary to suppress the leakage current to less than 1 microampere.

  Similarly, in the case of the set / reset operation of CellA in FIG. 5, if the reverse bias current of the selection element of CellD is large, a large current flows through CellD, so that the USBL potential of CellD and CellC is 2 due to the voltage drop due to RBL. .5V (when set), 3V (at reset). As a result, a forward bias voltage is applied to the unselected CellC diode, and there is a possibility that the unselected CellC will be rewritten by the flowing current.

  As described above, if a defective memory cell (FC) having a selection element having a large current when reverse bias is applied is present in the memory cell array, not only the FC but also other normal cells read and set / reset operation malfunctions. As a result, the defect rate of the entire array including the FC and further the entire semiconductor memory device including the FC is remarkably increased.

  The malfunction occurs because the variable resistance element included in the FC can take a low resistance state, that is, a set state here. The combination of a diode with a large leakage current and a low resistance set state causes a short circuit in the memory array circuit. This short circuit causes a fluctuation that greatly affects the read current value between the high resistance state and causes malfunction. Further, at the time of writing, application of a desired voltage to the memory cell array is prevented.

  Therefore, in the present invention, the resistance variable element included in the FC is increased in resistance. At this time, the variable resistance element included in the FC is set to a third resistance state having a higher resistance value than the second resistance state, that is, the reset state. Here, the resistance value in the third resistance state is equal to the maximum voltage used for data recording, that is, even if a reset voltage, which is a voltage for a reset operation in this embodiment, is applied to the memory cell, the recording layer 6 The phase change material has a high resistance that does not give Joule heat, that is, power, to crystallize. Under this condition, even if a set voltage, which is a voltage lower than the reset voltage and is used for the set operation, is applied to the memory cell having the resistance change element in the third resistance state, It does not give Joule heat, that is, electric power for the phase change material to crystallize. Therefore, in the third resistance state, the phase change material of the recording layer 6 does not reach the crystallization temperature depending on the set operation and the reset operation, so that the resistance variable element maintains the high resistance third resistance state. become.

  By setting the resistance variable element of FC to the above-described resistance state, the resistance variable element in the memory cell array transitions from the first resistance state to the second resistance state by applying a reset voltage pulse, A memory cell that stores data by transitioning from a resistance state of 2 to a first resistance state by a pulse of a voltage for a set operation, and a third resistance state by application of a pulse of a set voltage and a pulse of a reset voltage Memory cell exists. Hereinafter, the reset voltage pulse is referred to as a reset pulse, and the set voltage pulse is referred to as a set pulse.

  In the semiconductor memory device of the present invention, since the variable resistance element of the FC is held in the high resistance third resistance state, the above-described problem that a malfunction occurs when reading data due to the leakage current of the FC selection element is solved. Is done. Furthermore, even in the problem at the time of setting and resetting described above, in the third resistance state, the resistance variable element is in a state of higher resistance than the reset state, and thus the reverse bias current is prevented from increasing. And malfunction can be prevented.

  FIG. 6 shows the relationship between the voltage applied to the memory cell and the obtained resistance value in the semiconductor memory device of Example 1 of the present invention. The horizontal axis shows the voltage of the voltage pulse applied to the memory cell. The vertical axis represents the resistance of the resistance variable element.

  As shown in FIG. 6, the first resistance state, that is, the set state, is in a low resistance state. When a reset pulse is applied to the memory cell, the phase change material of the recording layer 6 is heated to the melting point or more by Joule heat, and as shown by the dashed arrow, the resistance increases due to the increase in the proportion of the amorphous phase. By the reset pulse, the second resistance state indicated by point A, that is, the resistance value in the reset state is obtained. Conversely, from the second state, by applying a voltage exceeding the voltage V2 in FIG. 6, the phase change material of the recording layer 6 is heated above the crystallization temperature by Joule heat, and the phase change of the recording layer 6 occurs. The proportion of the crystalline phase of the material increases and returns to the set state of the first resistance state as indicated by the dotted arrow. As described above, data can be stored by reversibly transitioning between the first resistance state and the second resistance state by applying a voltage to the memory cell.

  The resistance value of the resistance variable element connected to the defective selection element is set to be equal to or higher than the threshold value of the third resistance state in FIG. The threshold value of the third resistance state is the maximum voltage used when data is stored, here the Joule heat necessary for crystallization of the phase change material even when a reset voltage is applied to the memory cell, that is, the crystal of the phase change material This shows the lower limit of the resistance value in the third resistance state, which does not lead to the power necessary for the conversion. If the resistance value is lower than the lower limit, the crystallization gradually proceeds by applying the reset pulse, and the resistance variable element may have a low resistance. Accordingly, the resistance value of the variable resistance element of the FC memory cell is set to the third resistance state equal to or greater than this threshold value, thereby preventing the FC memory cell from being lowered in resistance and preventing malfunction of the device. As a result, a highly reliable nonvolatile semiconductor memory device can be provided at a high yield, that is, at low cost. In order to further improve the reliability, by applying a higher voltage to the memory cell, the phase change material of the recording layer 6 is vaporized to form a void in the recording layer 6, and the resistance value in the third resistance state is further increased. By using a high resistance value, it is possible to further increase the resistance of the resistance variable element more reliably. Further, as described above, the recording layer 6 is a laminated film of a layer containing a metal oxide and a layer containing a phase change material, so that the recording layer 6 without a layer containing a metal oxide is used. As a result, the third resistance state becomes more thermodynamically stable, and the resistance variable element can be reliably increased in resistance.

  When reading is performed on a memory cell having a resistance variable element in the third resistance state, the resistance value in the third resistance state is higher than that in the second resistance state, so that the read is performed as a high resistance state. It is. For example, after a set operation is performed on a memory cell having a resistance variable element in the third resistance state, if it is expected to be read out in the first resistance state, the erroneous result of the high resistance state is read out. It is. However, an error when a write operation is performed on a memory cell in the third resistance state can be sufficiently corrected by applying an error correction code technique at the time of recording / reproducing information, and does not cause a problem. In addition, the address of the memory cell having the resistance variable element in the third resistance state is stored in the management area 1012 of the memory cell array, and the control unit 1010 stores the address at the time of data writing based on the stored address information. It is also possible to perform control while avoiding the memory cells in the state 3.

  The third resistance state described above is realized by applying a voltage pulse having a voltage value higher than the reset voltage to the memory cell.

  FIG. 7 shows a pattern of voltage applied to each bit line and word line in the device operation mode in which the resistance variable element included in FC is increased in resistance to the third resistance state. As shown in FIG. 7, by applying 3.5V, 0V, 0V, and 3.5V to SWL, USWL, SBL, and USBL, respectively, the voltage VFC (in this case, 3.5V) is changed to the FC diode order. This can be done by applying in the direction. The voltage application is performed with a pulse similar to the reset pulse in FIG. 3, and the fall is rapidly performed to rapidly cool the phase change material of the melted recording layer. Because the applied voltage to the FC is 3.5 V, which is larger than 3.0 V in the normal reset operation, it is possible to set the resistance of the FC variable resistance element to a third resistance state higher than the reset state. It is.

  Further, for example, by applying 7V, 0V, 0V, and 3.5V to SWL, USWL, SBL, and USBL, for example, a voltage VFC (in this case, 7V) is applied in the forward direction of the FC diode. It can also be done. In the case of this voltage condition, the potential difference between both ends is 0V in the memory cell other than FC in FIG. 8, or the normal diode reverse breakdown voltage of 3.5V in the reverse direction of the diode is smaller than 4V in this case. Since voltage is applied, no current flows. That is, the applied voltage of 7V is larger than the withstand voltage of the diode and is selected within twice the withstand voltage of the diode, and the applied voltage of 3.5V is itself within the withstand voltage of the diode, and 7V The difference from the applied voltage is also within the breakdown voltage of the diode.

  The operation will be described with reference to FIG. Two of the power supplies 1003 to 1007 are 7V and 3.5V power supplies, respectively. The reference voltage is set to 0 V, and the voltage selector 1008 and the wiring selector 1009 are operated based on the control of the control unit 1010 so that the pattern shown in FIG. 7 is obtained, and the power source, the word line, and the bid line are connected. The control unit 1010 generates a voltage pulse from the power source and increases the resistance of the FC variable resistance element. In FC, since a large current flows due to a potential difference of 7 V applied to both ends, the phase change material of the FC recording layer melts. By rapidly lowering the applied voltage to rapidly cool the phase change material of the FC recording layer, the resistance change element is increased in resistance to the third resistance state. In this embodiment, since a voltage higher than the withstand voltage of the diode of the selection element can be applied, the resistance value in the third resistance state of the resistance variable element can be made higher. As a result, the range that can be taken by the resistance in the reset state can be expanded, which is advantageous for, for example, multilevel recording using three or more different resistance states. Also, application of a high voltage is advantageous for vaporizing the phase change material of the recording layer 6 to form voids in the recording layer 6 and to make the third resistance state have a higher resistance value.

  FIG. 9 shows an operation sequence for increasing the resistance of the variable resistance element to the third resistance state. First, the forward voltage of the diode is applied to the memory cell to reduce the resistance of the resistance variable elements of all the memory cells (S901). Next, a reverse voltage of the diode is applied to select a memory cell having a leak current larger than a certain threshold (S902), and the memory cell (FC) having a large leak current is shown in FIG. 7 or FIG. A voltage is applied in the mode to increase the resistance of the FC resistance variable element to the third resistance state (S903). By reducing the resistance of the variable resistance element of the memory cell in S901, the influence of the resistance of the variable resistance element is reduced, and the leakage current of the selected diode can be correctly determined.

  In order to increase the resistance of the variable resistance element paired with the diode having a large off-state current to the third resistance state, there is still another configuration. FIG. 10 shows a pattern of voltage applied to each bit line and word line for setting to the third resistance state. In FIG. 10, 0V, 0V, 4V, and 4V are applied to SWL, USWL, SBL, and USBL, respectively, that is, by setting VFC to 4V, not only FC diodes but also memory cells having normal diodes. In addition, a voltage of 4 V is applied in the reverse direction of the diode. In a memory cell having a normal diode, a voltage equal to or lower than the breakdown voltage is applied in the reverse direction of the diode, so that almost no current flows through the memory cell, so that the resistance value of the resistance variable element does not change even after voltage application. In FC, since the reverse breakdown voltage of the diode is low, a large current flows due to a potential difference of 4 V applied to both ends, and the phase change material of the recording layer 6 is melted. When the phase change material is rapidly cooled by rapidly lowering the applied voltage, the operation of increasing the resistance of the FC resistance change element to the third resistance state can be performed. When such a voltage condition is used, it is possible to increase the resistance of the resistance variable element to the third resistance state by automatically supplying a current only to the FC without selecting a cell having a large leakage current of the selection element.

  As shown in FIG. 11, the operation sequence is merely to apply a voltage in the mode of FIG. 10 to increase the resistance of the FC variable resistance element (S1101). Therefore, in a short time, the semiconductor resistance device can be obtained in which the FC variable resistance element is brought into the third resistance state to operate normally.

  The above-described operation of increasing the resistance of a defective cell can be performed by causing the control unit 1010 to operate the semiconductor memory device in each of the above modes. Further, at the manufacturing stage of the semiconductor memory device, it is possible to increase the resistance of the FC to the third state by applying the above voltage from the outside with the pattern shown in FIGS.

  FIG. 12 shows the effect of the first embodiment. In the nonvolatile semiconductor memory device in which the resistance change type element of the FC is increased in resistance, the failure of the nonvolatile semiconductor memory device due to the leakage current of the diode can be greatly reduced as compared with the case where this process is not performed.

  Even when a single-crystal silicon diode or a transistor formed on a single-crystal silicon substrate with a low frequency of off-current failure due to crystal defects, metal contamination, etc. is used as the selection element, the effect can be seen, but as shown in FIGS. The effect is greater when a polysilicon diode or an oxide diode that can be multi-layered is used as the selection element.

  In the second embodiment, a case where a transistor is used as the selection element is shown. FIG. 15 shows a memory cell in which a transistor and a phase change memory used in the second embodiment are connected. As shown in FIG. 15, the word line 2 is connected to the gate of the transistor, and the recording layer 6 of the resistance variable element is formed on the lower electrode 8 of the resistance variable element electrically connected to the source or drain of the transistor. The upper electrode 7 of the resistance variable element and the bit line 3 are formed in this order. The variable resistance element of the semiconductor memory device according to the first embodiment corresponds to a device in which a diode is replaced with a transistor, and high density can be achieved by forming an intersection type array as shown in FIG.

  As shown in FIG. 16, in order to select and read one cell from the memory cell array, a word line to which the selected cell is connected (SWL: selected word line), a word line to which the selected cell is not connected (USWL) : Unselected word line), bit line to which the selected cell is connected (SBL: selected bit line), bit line to which the selected cell is not connected (USBL: unselected bit line), for example, 2V, 0V, Apply 1V and 0V voltage. An N channel transistor is used as the selection transistor. Since the selection transistor has almost no leakage current when the gate potential is 0 V, the current flows only in the selection cell SMC, and the resistance state can be determined by measuring with the sense amplifier.

To select one cell from the memory cell array and perform the set operation, for example, voltages of 3V, 0V, 1.5V, and 0V are applied to SWL, USWL, SBL, and USBL, respectively. At this time, no current flows through CellD connected to USWL and USBL because both USBL and ground potential are 0V. In addition, no current flows through CellB connected to USWL and SBL because the selection transistor is in the OFF state. In CellC connected to SWL and USBL, no current flows because the bit line potential and the ground potential are equal. A current flows only in the selected cell SMC, and the phase change material is heated by Joule heat. The voltage applied to the selected bit line and the selected word line may be a voltage sufficient to heat the phase change material of the selected memory cell to the crystallization temperature. When a voltage is applied for a time sufficient for crystallization (about 10 −6 seconds or more), the resistance variable element of the selected cell undergoes crystallization of the phase change material in its recording layer 6 and the first resistance state with low resistance become. Other cells do not change state.

  To select one cell from the memory cell array and perform the reset operation, for example, voltages of 3V, 0V, 2V, and 0V are applied to SWL, USWL, SBL, and USBL, respectively. At this time, no current flows through CellD connected to USWL and USBL because both USBL and ground potential are 0V. In addition, no current flows through CellB connected to USWL and SBL because the selection transistor is in the OFF state. In CellC connected to SWL and USBL, no current flows because the bit line potential and the ground potential are equal. A current flows only in the selected cell SMC, and the phase change material is heated by Joule heat. The voltage applied to the selected bit line and the selected word line may be a voltage sufficient to heat the phase change material of the selected memory cell to a temperature higher than the melting point. When the applied voltage is rapidly set to 0 V and the phase change material is rapidly cooled, the phase change material of the recording layer 6 of the selected cell is in a high resistance amorphous state, and the resistance variable element is in the second resistance state. Other cells do not change state.

  The reason why the read operation and the set / reset operation shown in FIG. 16 can be correctly performed in the selected cell is that the operation is performed within the breakdown voltage of the transistor as the selection element, and the leakage current, that is, the current in the off state is sufficiently small. For example, in the read operation of CellA in FIG. 16, the SBL potential V of CellB becomes positive due to the voltage drop at RBL, so if the current in the off state of the select transistor of CellB is large, a large leakage current will occur. Arise. Since the magnitude of the leakage current differs depending on the resistance state of the CellB variable resistance element, that is, the state of the recorded information, the current Iread determined by the sense amplifier varies depending on the state of CellB even if Icell flowing through CellA is the same. Readout malfunctions. As in the first embodiment, at least the leakage current needs to be smaller than the read current so as not to malfunction.

  Similarly, in the case of the set / reset operation of CellA in FIG. 16, if the current in the off state of the selection element of CellB is large, a large current flows through CellB, so that the SBL potential of CellA is 1 due to the voltage drop due to RBL. .5V (when set), 2V (at reset). As a result, there is a possibility that the set / reset operation to CellA is not normally performed. When a memory cell (FC) having a selection element with a large off-state current is present in the memory cell array, not only FC but also other normal cells connected to the same bit line as FC are read, set / reset A malfunction occurs in the operation, and the defect rate of the entire semiconductor memory device is remarkably increased.

  Therefore, in order to prevent the failure of memory cells other than FC, the resistance variable element included in FC is increased in resistance. At this time, as in the first embodiment, the resistance variable element included in the FC is set to the third resistance state. As a result, similarly to the first embodiment, the problem that the read operation malfunctions due to the leakage current of the FC selection element described above is solved. Similarly to the first embodiment, an error caused by the memory cell in the third resistance state can be sufficiently corrected by applying an error correction code technique at the time of recording / reproducing information, and does not cause a problem. In addition, the address of the memory cell having the resistance variable element in the third resistance state is stored in the management area 1012 of the memory cell array, and the control unit 1010 stores the address at the time of data writing based on the stored address information. It is also possible to perform control while avoiding the memory cells in the state 3.

  In order to increase the resistance of the resistance variable element included in FC, as shown in FIG. 17, for example, voltages of 3V, 0V, 2.5V, and 0V are applied to SWL, USWL, SBL, and USBL, respectively, and VFC (in this case) Can be achieved by applying 2.5V) to FC. The voltage application is performed with a pulse similar to the reset pulse in FIG. 1, and the fall is rapidly performed to rapidly cool the melted phase change material. Since the applied voltage to FC is larger than 2.0 V in the normal reset operation, the current is also larger than in the normal reset operation. For this reason, it is possible to set the resistance of the FC phase change element to the third resistance state higher than the reset state.

  The entire operation sequence is shown in FIG. First, the gate voltage of the selection transistor is set so that the transistor is turned on, and a voltage is applied to both ends of the memory cell to lower the resistance change type elements of all the memory cells (S1801). Next, the gate voltage of the selection transistor is set so that the transistor is turned off, the voltage is applied to both ends of the memory cell, and a memory cell having a leakage current larger than a certain threshold is selected (S1802). The gate voltage of the selection transistor of the memory cell FC having a large current is set so that the transistor is turned on, and a voltage is applied to both ends of the memory cell to change the resistance variable element of the memory cell to the third resistance state. (S1803).

  In order to increase the resistance of the variable resistance element paired with the transistor having a large off-state current to the third state, the voltage condition shown in FIG. 19 can be used. In FIG. 19, by applying 0 V, 0 V, 2.5 V, and 2.5 V to SWL, USWL, SBL, and USBL, respectively, not only FC but also a memory cell having a normal selection transistor is connected to both ends of the memory cell. Is applied with a voltage of 2.5V. In a memory cell having a normal selection transistor, since the gate voltage is 0 V, almost no current flows through the memory cell, so that the resistance value of the resistance variable element does not change even after voltage application. In FC, since the off current of the selection transistor is large, a large current flows due to a potential difference of 2.5 V applied to both ends, and the phase change material of the recording layer is melted. When the phase change material is rapidly cooled by rapidly lowering the applied voltage, the resistance change element can be increased in resistance to the third resistance state. When such a voltage condition is used, it is possible to increase the resistance of the variable resistance element to the third resistance state by automatically flowing a current only to FC without selecting a cell having a large off-state current of the selection transistor.

  As shown in FIG. 20, the operation sequence is merely to apply a voltage in the mode of FIG. 19 to increase the resistance of the FC variable resistance element (S2001).

  The above-described operation of increasing the resistance of a defective cell can be performed by causing the control unit 1010 to operate the semiconductor memory device in each of the above modes, as in the first embodiment. It is also possible to increase the resistance of the FC to the third state by applying the above voltage from the outside.

  The method of this embodiment can also be used in a stacked phase change memory array using vertical polysilicon transistors and oxide transistors as shown in FIG.

  In the third embodiment, an embodiment in which the address of the memory cell in the third resistance state is stored in the management area 1012 by the control unit 1010 is shown. When the control unit 1010 divides the memory cell into one or a plurality of groups as shown in FIG. 22 and assigns a memory management area to each group, and increases the resistance of the memory cells included in the group to the third state. The information is recorded in the management area 1012. The sequence by the control part of Example 3 is shown in FIGS.

  When a diode is used as the selection element, the sequence of FIG. 23 can be used corresponding to the operation sequence of FIG. After increasing the resistance of the variable resistance element of FC to the third resistance state in the same sequence as in FIG. 9 (S2301, S2302, S2303), the FC address is recorded in the memory management area of the group including FC (S2304). .

  Further, the sequence of FIG. 24 can be used corresponding to the operation sequence of FIG. 11 of the first embodiment. After the resistance variable elements of all the memory cells are reduced in resistance by a method such as applying a forward voltage of the diode to the memory cells (S2401), the FC variable resistance elements are connected in the same sequence as in FIG. After the resistance state is increased (S2402), a normal read operation is performed on the memory cell, the memory cell whose resistance is increased is determined to be FC (S2403), and FC is included in the memory management area of the group including FC. Is recorded (S2404). The reason why the resistance variable elements of all the memory cells are reduced in resistance in S2401 is to determine the cell in the high resistance state in S2404 as a defective memory cell FC.

  When a transistor is used as the selection element, the sequence shown in FIG. 25 can be used corresponding to the operation sequence shown in FIG. Similarly to FIG. 18, after the resistance change type elements of all the memory cells are lowered in resistance (S2501), the defective cell FC is selected (S2502), and the resistance change type elements of FC are set to the third resistance state to have a high resistance. (S2503), the FC address is recorded in the memory management area of the group including the FC (S2504).

  Further, the sequence of FIG. 26 can be used in correspondence with the operation sequence of FIG. 20 of the second embodiment. After the resistance variable elements of all the memory cells are reduced in resistance (S2601), the resistance variable elements of FC are increased to the third resistance state (S2602) in the same sequence as in FIG. On the other hand, a normal read operation is performed, and the memory cell whose resistance has been increased is determined to be FC (S2603), and the FC address is recorded in the memory management area of the group including FC (S2604). The reason why the resistance change type elements of all the memory cells are lowered in S2601 is to determine that the cell in the high resistance state in S2604 is a defective memory cell FC.

  After the FC address information is recorded in these sequences, the data can be stored correctly by not using the FC during normal information rewriting or reading. Note that it is important to use a memory cell having no defect as a memory cell in the memory management area.

  The same memory cell group in FIG. 22 may include memory cells that are physically close to each other, for example, memory cells in the same array. These memory cells can be selected and assigned to the same memory cell group.

  In the third embodiment, the memory cells for recording normal data and the memory cells in the management area are not distinguished from each other. However, as in the fourth embodiment, they are physically different from each other or physically different from each other. It can also be a memory cell made in place. For example, a memory cell for recording normal data that requires a large capacity is manufactured with the structure shown in FIGS. 13, 14, and 21. A transistor formed on a silicon substrate as shown in FIG. 15 can be manufactured as a selection element.

  Alternatively, a memory cell for recording normal data that requires a large capacity is manufactured in the lower layer than the second layer from the top of FIGS. 14 and 21, and a memory in a management area that needs a small capacity but is free from defects. The cell can also be fabricated with the top layer of FIGS. Also in this embodiment, data can be stored correctly.

  In the fifth embodiment, a semiconductor memory device manufacturing method in which the resistance change type element of the FC of the semiconductor memory device shown in the first embodiment is increased by voltage application from the outside of the semiconductor memory device will be described.

  FIG. 27 shows a process flow. An electrode is connected to the bit line and the word line from the outside to the semiconductor memory device shown in the first embodiment, and a first inspection voltage is applied to the memory cell in the reverse direction of the diode, and the leakage current value of the diode is determined. Measure (S2701). As in the first embodiment, the leakage current value can be correctly determined by applying the forward voltage of the diode to the memory cell and reducing the resistance of the resistance variable element. When the leakage current value of the diode is greater than or equal to the first predetermined current value (S2702), that is, when it is FC, the memory cell including this diode has a third voltage value higher than the set pulse and the reset pulse. A voltage pulse is applied to increase the resistance of the resistance variable element (S2703). The first predetermined current value may be, for example, a normal diode leakage current value. Alternatively, as described above, when the semiconductor memory device of Example 1 is manufactured by a 50 nm generation manufacturing process, the read current is about 1 microampere. Therefore, in this case, the first predetermined current value may be 1 microampere.

  In order to make the process more reliable, the current value of the current that flows when the second test voltage is applied in the forward direction of the diode to the memory cell to which the third voltage pulse is applied is measured (S2704). . When the current value of the current that flows when the second test voltage is applied is equal to or greater than the second predetermined current value (S2705), the third voltage pulse is applied to the memory cell to which the third voltage pulse is applied. A fourth voltage pulse having a higher voltage value is applied to further increase the resistance of the resistance variable element (S2706). At this time, the value of the ratio between the voltage value of the second inspection voltage and the second predetermined current value is the voltage value of the maximum voltage among the voltages used for recording in the semiconductor memory device, that is, reset here. The relationship of being larger than the value of the ratio between the voltage value of the voltage and the first predetermined current value is satisfied. If the relationship is not satisfied even by application of the fourth voltage pulse, a voltage pulse having a higher voltage is applied to the memory cell to further increase the resistance of the resistance variable element.

  According to the manufacturing method of the present embodiment, even when a maximum voltage among the voltages used for recording of the semiconductor memory device, that is, here, a reset voltage is applied, the current flowing through the FC is higher than the first predetermined current value. Get smaller. That is, by satisfying the above relationship, the resistance variable element of FC can be in a high resistance state in which only a current smaller than the first predetermined current value flows even when a reset voltage is applied to FC.

  For example, by setting the first predetermined current value as a normal diode leakage current value, only a smaller current than the normal diode leakage current can flow through the FC by the set operation and the reset operation. . As a result, the phase change material of the recording layer 6 of the FC variable resistance element does not reach the crystallization temperature due to the set operation and the reset operation, and the variable resistance element is prevented from entering the low resistance state. That is, the semiconductor memory device can be manufactured so as to satisfy the condition that the resistance value of the FC variable resistance element is equal to or greater than the threshold value of the third resistance state shown in the first embodiment.

  In addition, for example, even when the first predetermined current value is set as the read current, only a current less than the read current can flow through the FC by the set operation and the reset operation. Accordingly, the phase change material of the recording layer 6 of the FC variable resistance element does not reach the crystallization temperature by the set operation and the reset operation, and the variable resistance element is prevented from being in a low resistance state. That is, the semiconductor memory device can be manufactured so as to satisfy the condition that the resistance value of the FC variable resistance element is equal to or greater than the threshold value of the third resistance state shown in the first embodiment.

  As described above, the manufacturing method shown in this embodiment can prevent the malfunction of the device due to the low resistance state of the variable resistance element of the FC. Therefore, a highly reliable semiconductor memory device with high yield can be obtained. It can be manufactured.

  The nonvolatile semiconductor memory device of the present invention is suitable for use in a memory device for small portable information devices such as a portable personal computer and a digital still camera.

1 Semiconductor substrate (silicon substrate)
2 Word line 3 Bit line 4 p-type semiconductor layer such as p-type polysilicon or p-type semiconductor oxide 5 n-type semiconductor layer such as n-type polysilicon or n-type semiconductor oxide 6 Recording layer of resistance variable element 7 Upper electrode of resistance variable element 8 Lower electrode of resistance variable element 9 Barrier metal or silicide 10 of p-type semiconductor interface Barrier metal or silicide 21 or 22 of n-type semiconductor interface Gate insulating film 100 Plate electrode 101 Well 111 Source line 112 Electrode 1001 I / O interface 1002 Memory cell array 1003 Power source 1004 Power source 1005 Power source 1006 Power source 1007 Power source 1008 Voltage selector 1009 Wiring selector 1010 Control unit 1011 Reading unit 1012 Management region Dif Diffusion layer RBL Resistance RWL per bit line cell pitch Lead wires of the resistance per cell pitch SWL selected word line USWL unselected word lines SBL selected bit line USBL unselected bit lines SMC selected memory cell CellA selected word line, selected bit line memory cells (selected memory cell)
CellB Unselected word line, selected bit line memory cell CellC Selected word line, unselected bit line memory cell CellD Unselected word line, unselected bit line memory cell FC Memory cell Sense Amp. Sense amplifier Vread Memory cell applied voltage Vset at the time of reading Memory cell applied voltage Vset at the time of setting Memory cell applied voltage Icell at the time of resetting Selected cell current Iread at the time of reading Sense amplifier current Iset at the time of reading Selected cell current at the time of setting Selected cell current at the time of resetting Gate voltage VOFF that turns on the channel of the VON selection element transistor VOFF Resistance change type of the memory cell applied voltage VFUSWL FC when the resistance change type element of the gate voltage VFC FC that turns off the channel of the selection element transistor is increased USWL applied voltage VFCUSBL FC for increasing resistance of element USBL applied voltage for increasing resistance of resistance variable element

Claims (13)

  1. A plurality of first wires;
    A plurality of second wirings intersecting with the plurality of first wirings;
    A plurality of memory cells arranged at intersections of the plurality of first wirings and the plurality of second wirings;
    Each of the plurality of memory cells is configured by connecting a resistance variable element and a diode in series,
    The variable resistance element has a recording layer containing a phase change material, and the variable resistance element has a first resistance state and a second resistance value higher than the resistance value of the first resistance state. A resistance state and a third resistance state having a resistance value higher than the resistance value of the second resistance state;
    By applying a first voltage pulse to the memory cell, the phase change material of the resistance change element in the first resistance state is heated to the melting point or more by Joule heat, and the ratio of the amorphous phase of the phase change material Of the resistance variable element in the second resistance state by applying a second voltage pulse lower than the first voltage pulse to the memory cell. The phase change material is heated above the crystallization temperature by Joule heat, and the data is stored by transitioning to the first resistance state by increasing the proportion of the crystal phase of the phase change material,
    The resistance value of the third resistance state is such that the phase change material is brought to a crystallization temperature even when the first voltage pulse is applied to the memory cell having the resistance variable element in the third resistance state. Resistance value that does not generate Joule heat,
    2. The semiconductor memory device according to claim 1, wherein the resistance variable element of the memory cell having the diode having a leakage current value equal to or larger than a predetermined value among the plurality of memory cells is in the third resistance state.
  2. The semiconductor memory device according to claim 1,
    The semiconductor memory device, wherein the phase change material includes germanium, antimony, and tellurium.
  3. The semiconductor memory device according to claim 1,
    The resistance variable element has a stacked structure of a layer containing a metal oxide and a layer containing a phase change material.
  4. The semiconductor memory device according to claim 1,
    The semiconductor memory device according to claim 1, wherein the predetermined leakage current value is 1 microampere.
  5. Having a memory cell array,
    Each of the memory cells of the memory cell array is configured by connecting a resistance variable element and a selection element,
    The variable resistance element has a recording layer containing a phase change material,
    The resistance variable element includes a first resistance state, a second resistance state having a resistance value higher than the resistance value of the first resistance state, and a resistance value higher than the resistance value of the second resistance state. And at least a third resistance state having a resistance value exists,
    Among the memory cells,
    The resistance variable element transitions from the first resistance state to the second resistance state by applying a reset pulse, and the resistance variable element from the second resistance state by applying a set pulse. A first memory cell that stores data by transitioning to the first resistance state;
    The resistance variable element of the memory cell to which the reset pulse is applied is in the third resistance state, and the resistance variable element of the memory cell to which the set pulse is applied is in the third resistance state. A semiconductor memory device characterized in that a certain second memory cell exists.
  6. The semiconductor memory device according to claim 5.
    A management area in the memory cell array;
    The semiconductor memory device, wherein an address of the second memory cell is stored in the management area.
  7. The semiconductor memory device according to claim 6.
    Having a control unit,
    The semiconductor memory device, wherein the control unit determines the memory cell used for storing data based on address information of the second memory cell stored in the management area.
  8. The semiconductor memory device according to claim 5.
    The semiconductor memory device, wherein the phase change material includes germanium, antimony, and tellurium.
  9. The semiconductor memory device according to claim 5.
    The semiconductor memory device, wherein the selection element is a diode.
  10. The semiconductor memory device according to claim 5.
    The semiconductor memory device, wherein the selection element is a transistor.
  11. Having a memory cell array,
    Each of the memory cells of the memory cell array is configured by connecting a resistance variable element and a diode in series,
    The variable resistance element has a recording layer containing a phase change material,
    Preparing a semiconductor memory device for storing data by applying a set pulse and a reset pulse to the memory cell;
    Applying a first test voltage to the memory cell in the reverse direction of the diode to measure a leakage current value of the diode;
    Applying a third voltage pulse having a voltage value higher than the reset pulse to the memory cell including the diode having a leakage current value equal to or higher than a first predetermined current value. Device manufacturing method.
  12. The method of manufacturing a semiconductor memory device according to claim 11.
    Measuring a current value of a flowing current by applying a second inspection voltage in a forward direction of the diode to the memory cell to which the third voltage pulse is applied;
    When the current value of the current flowing by applying the second test voltage is equal to or greater than a second predetermined current value, the fourth voltage pulse having a voltage value higher than the third voltage pulse is set to the third voltage pulse. Applying to the memory cell to which the voltage pulse is applied,
    The value of the ratio between the voltage value of the second inspection voltage and the second predetermined current value is greater than the value of the ratio between the voltage value of the reset pulse and the first predetermined current value. A method for manufacturing a semiconductor memory device.
  13. The method of manufacturing a semiconductor memory device according to claim 11.
    The method of manufacturing a semiconductor memory device, wherein the first predetermined current value is 1 microampere.
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