JP5308497B2 - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technology applied to a semiconductor device having memory cells using a phase-change material, which can speed up a setting operation limiting a writing speed in the semiconductor device. <P>SOLUTION: A set pulse voltage applied to a phase-change material has two pulse levels. In the first pulse level of the voltage, a temperature of the phase-change material is set to a temperature at which seed formation reaches its fastest speed, and in the second pulse level of the voltage, the temperature is set to a temperature at which crystal growth reaches its fastest speed. Accordingly, the phase-change material is crystallized by solid-phase growth without being melted. The voltage having two pulse levels applied to the phase-change material is controlled by a voltage having two levels applied to a word line so that variation in drain current can be reduced. <P>COPYRIGHT: (C)2012,JPO&amp;INPIT

Description

  The present invention relates to a semiconductor device, and in particular, a high-density integrated memory circuit including a memory cell that discriminates stored information using a difference in resistance, for example, a memory cell using a phase change material, a memory circuit, and a logic circuit are the same The present invention relates to a technology effective when applied to a logic-embedded memory provided on a semiconductor substrate, a semiconductor integrated circuit device having an analog circuit, a random access memory having a nonvolatile property, and the like.

  As a technique studied by the present inventor, for example, in a memory using a phase change material, the following technique can be considered.

  Phase change memory, which is a memory using resistance elements made of phase change material, crystallizes phase change material by set operation or amorphizes by reset operation, and the difference in resistance value due to phase state of phase change material This is a non-volatile memory that stores information. Incidentally, the low resistance state set and the high resistance state reset do not necessarily need to be in a completely crystalline state and an amorphous state, but are in a completely crystalline state, a low resistance state and a completely amorphous state. It is possible to take any value in the middle of the high resistance state.

  For resetting, a high voltage is applied to raise the temperature of the phase change material above the melting point. Further, after the phase change material is melted, in order to prevent crystallization, a short-time pulse that sharply attenuates is used. The set holds the phase change material for a certain period of time at a temperature above the crystallization temperature and below the melting point. Therefore, the set pulse is a pulse having a lower voltage and longer time than the reset pulse.

  As an application destination of the phase change memory, first, replacement of the FALSH memory, which is the mainstream of the nonvolatile memory, can be mentioned. The phase change memory can be said to be a higher performance nonvolatile memory because it can operate at a lower voltage and can be rewritten at a higher speed than the FLASH memory. If the speed is further increased, a high-speed nonvolatile RAM can be realized. Currently, many portable devices are equipped with both a nonvolatile FLASH memory and a DRAM, which is a high-speed volatile RAM, and if a nonvolatile RAM having the characteristics of these two memories can be realized, the FLASH memory And the DRAM can be integrated into one chip, and all semiconductor memories can be replaced.

  In addition, there exist patent document 1, nonpatent literature 1, etc. as technical literature relevant to this invention, for example.

JP 2003-100085 A

“Japanese Journal of Applied Physics”, January 1991, vol. 30, p. 97-100

  By the way, as a result of examination of the phase change memory technology as described above by the present inventors, the following has been clarified.

For example, in a reset operation of a conventional phase change memory, a rectangular voltage pulse is applied, the temperature of the phase change material is raised to the melting point or higher, the phase change material is once melted, and then rapidly cooled. For example, when the phase change material is Ge ₂ Sb ₂ Te ₅ and when a rectangular reset pulse is applied, the time constant of the temperature change of the phase change material Ge ₂ Sb ₂ Te ₅ is about 2 ns (nanoseconds), so the reset is performed. Even if the pulse width is 30 ns, the phase change material exceeds the melting point, and can be reset after rapid cooling.

  On the other hand, the set operation of the conventional method applies a rectangular voltage pulse, raises the temperature of the phase change material to below the melting point and the crystallization temperature and holds it at that temperature for about 1 μs, not only the phase change material, Warm up to the surroundings. After the voltage pulse is set to 0 V, the phase change material is gradually cooled and crystallized in the temperature range below the melting point where the crystallization of the phase change material proceeds and above the crystallization temperature by ambient heat. In this conventional method, since it takes about 1 μs to sufficiently warm the ambient temperature of the phase change material, it takes about 1 μs to set.

  Thus, in the conventional method, it is the set operation that determines the write time of the phase change memory.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  That is, in the semiconductor device according to the present invention, in the set operation, as the voltage pulse to be applied to the phase change material, a voltage pulse in which the reached temperature of the phase change material is higher than the melting point is applied, and the temperature of the phase change material is rapidly increased. And has a function of stopping application of the voltage pulse before reaching the melting point.

  In addition, the semiconductor device according to the present invention has a function of applying a second voltage lower than the first voltage after applying the first voltage to the set voltage applied to the phase change material in two stages.

  Of the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  The rewrite speed of the memory cell element using the phase change material that requires a high-speed set operation can be improved.

(A), (b) is a figure which shows a pulse voltage waveform in Embodiment 1 and 2 of this invention. (A), (b) is a figure which shows the temperature change of phase change material in Embodiment 1 and 2 of this invention. In Embodiment 1 of this invention, it is a block diagram which shows the structure of a phase change memory. In Embodiment 1 of this invention, it is a circuit diagram which shows the structure of a memory cell array. In Embodiment 1 of this invention, it is a layout figure which shows the structure of a memory cell array. In Embodiment 1 of this invention, it is sectional drawing which shows the structure of a memory cell. In Embodiment 1 of this invention, it is a circuit diagram which shows the structure of a column selector. In Embodiment 1 of this invention, it is a circuit diagram which shows the structure of a write buffer block. In Embodiment 1 of this invention, it is a wave form diagram which shows the timing of write-in operation. In Embodiment 1 of this invention, it is a wave form diagram which shows the timing of a read operation. In Embodiment 2 of this invention, it is a block diagram which shows the structure of a phase change memory. In Embodiment 2 of this invention, it is a circuit diagram which shows the structure of a word line control circuit. In Embodiment 2 of this invention, it is a circuit diagram which shows the structure of a short pulse generation circuit. In Embodiment 2 of this invention, it is a wave form diagram which shows the timing of a two-stage pulse control signal. In Embodiment 2 of this invention, it is a circuit diagram which shows the structure of the word line driver which can generate | occur | produce two-stage pulses. In Embodiment 2 of this invention, it is a figure which shows the temperature dependence of the crystallization rate of a phase change material. In Embodiment 2 of this invention, it is a figure which shows the 2 step | paragraph pulse waveform used for experiment. In Embodiment 2 of this invention, it is a figure which shows the experimental result of the set / reset resistance ratio by a two-stage pulse. (A)-(h) is a figure which shows the relationship between a pulse waveform and the temperature change of phase change material in Embodiment 2 of this invention. In Embodiment 3 of this invention, it is a figure which shows the transistor characteristic curve when a 2 step | paragraph pulse is applied to a bit line. In Embodiment 3 of this invention, it is a figure which shows the transistor characteristic curve when a two-step pulse is applied to the word line. In Embodiment 4 of this invention, it is sectional drawing which shows the structure of the phase change material vicinity at the time of interface layer insertion. In Embodiment 4 of this invention, it is sectional drawing which shows the structure of phase change material vicinity when an interface layer is inserted only on a plug. (A), (b) is a circuit diagram which shows the structure of the memory cell when the interface layer is inserted in Embodiment 4 of this invention.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

(Embodiment 1)
FIG. 3 is a principal block diagram of a configuration example of the asynchronous phase change memory according to the first embodiment of the present invention.

  First, an example of the configuration of the asynchronous phase change memory according to the first embodiment will be described with reference to FIG. Although not particularly limited, the asynchronous phase change memory operates in accordance with the state of the control signal and also by detecting address transition. The asynchronous phase change memory according to the first embodiment includes a command buffer CB, a control signal generation circuit CPG, an address buffer AB, an address transition detection circuit ATD, a row predecoder RPD, a column predecoder CPD, an input buffer DIB, and an output buffer. A DOB, a sense amplifier block SA, a write buffer block WB, and the like are provided, and a row decoder RDEC, a word line driver WD, a column decoder CDEC, a column selector CSEL, and the like are provided corresponding to the memory cell array MCA. Although only one memory cell array MCA is shown here, a plurality of memory cell arrays MCA may be provided according to the memory cell capacity.

  Each circuit block plays the following role. The control signal generation circuit CPG generates a control signal CTL for controlling the input buffer DIB, the output buffer DOB, the sense amplifier block SA, the write buffer block WB, and the like in accordance with an external control signal CMD taken in by the command buffer CB. The address buffer AB takes in the address ADR from the outside and sends the internal address AI to the address transition detection circuit ATD, the row predecoder RPD, and the column predecoder CPD. The address transition detection circuit ATD detects a transition of the internal address AI and outputs an address transition signal AT to the control signal generation circuit CPG. Specifically, the logic for detecting the change is taken for each bit of the address, and the logical sum of these is taken as the address transition signal AT.

  The row predecoder RPD predecodes the row address and outputs the row predecode address RPA to the row decoder RDEC. Row decoder RDEC further decodes row predecode address RPA, and word line driver WD selectively drives word lines in memory cell array MCA accordingly. The column predecoder CPD predecodes the column address and outputs the column predecode address CPA to the column decoder CDEC. Column decoder CDEC further decodes column predecode address CPA, and column selector CSEL selectively connects bit lines in memory cell array MCA to input / output line IO accordingly.

  The input buffer DIB takes in the input / output data DQ with the outside at a desired timing and sends the input data DI to the write buffer block WB. Write buffer block WB drives input / output line IO according to input data DI for a write operation. The sense amplifier block SA includes a number of sense amplifiers corresponding to the number of bits operating at the same time, and amplifies and discriminates the signal of the input / output line IO for a read operation, and outputs read data DO. The output buffer DOB outputs the read data DO to the input / output data DQ at a desired timing.

  FIG. 4 shows a configuration example of the memory cell array MCA. Memory cells MC are provided at the intersections of the word lines WL0, WL1, WL2, WL3,... Connected to the word line driver WD and the bit lines BL0, BL1, BL2, BL3,. Further, source lines SL01, SL23,... Are provided and connected to the ground voltage VSS. Each memory cell MC includes a phase change resistor PCR and a memory cell transistor MT. One end of the phase change resistor PCR is connected to the bit line, and the other end is connected to one of the source and drain of the memory cell transistor MT. The phase change resistance is made of a chalcogenide material containing Te or the like, for example. The other of the source and drain of the memory cell transistor is connected to the source line, and the gate is connected to the word line. In FIG. 4, a MIS (Metal Insulator Semiconductor) type transistor is used as the memory cell transistor MT, but a bipolar type transistor may be used.

  Although not shown here for simplicity, a dummy cell for generating a reference signal for reading is also provided if necessary. Further, although an NMOS transistor is shown here as a memory cell transistor, a PMOS transistor or a bipolar transistor can also be used. However, a MOS transistor is desirable from the viewpoint of high integration, and an NMOS transistor having a smaller channel resistance in the on state than the PMOS transistor is preferable. Hereinafter, the operation and the like will be described in terms of voltage when an NMOS transistor is used as the memory cell transistor.

  FIG. 5 shows a layout corresponding to the memory cell array configuration of FIG. The circuit elements shown in FIG. 4 are given the same reference numerals. In FIG. 5, the areas separated by thick black lines are areas corresponding to the memory array MCA illustrated in FIG. 4. In FIG. 5, M1 is a first metal layer, M2 is a second metal layer, FG is a layer used as a gate electrode of a transistor formed on a silicon substrate, and FCT is a contact connecting the FL upper surface and the M1 lower surface. A hole, R is a laminated film of the memory element PCR and its upper electrode layer UE, SCT is a contact hole connecting the upper surface of M1 and the lower surface of R, and TCT is a contact hole connecting the upper surface of M1 and the lower surface of M2. The memory element R is pulled up to the second metal layer M2 through the contact hole TCT between memory cells connected to the same bit line. This second metal layer M2 is used as each bit line. The word lines WL0 to WL3 are formed of FG. For FG, a laminate of polysilicon and silicide (an alloy of silicon and a refractory metal) is used. One MOS transistor constituting the memory cell MC11 is QM1. The transistor QM2 constituting the memory cell MC21 shares the source region with the transistor QM1. As shown in the figure, the MOS transistors constituting other cells follow this.

  FIG. 6 is a cross-sectional view of the main part of the memory cell array. This example is a specific configuration example for realizing the array configuration shown in FIG. FIG. 6 is a cross-sectional view of the memory cell area of the logic embedded memory, the logic logic circuit area, and the phase change memory cell. Desired transistors QM1, QM2, etc. are formed in the well PW formed in the semiconductor substrate SUB. The first layer wiring M1, the source line wiring, and the like are arranged at the position of the interlayer insulating film ILIc.

  Then, in this memory cell region, the phase change material PCR is formed via the lower electrode plug PLUG in the memory cell region, and the main part constituting the memory cell is formed. The memory cell portion is connected to the bit line BL via a plug-like metal contact We disposed on the memory cell portion.

  For example, n-channel type memory cell selection MOS transistors QM1 and QM2 are formed in the memory cell region. The n-channel memory cell selection MOS transistors QM1 and QM2 are formed on the p well PW so as to be separated from each other. These transistors have semiconductor regions DN and DNC having an LDD (Lightly Doped Drain) structure, a gate insulating film formed on a semiconductor substrate, and a gate electrode formed thereon. The semiconductor region DNC is shared by adjacent n-channel type memory cell selection MOS transistors formed in the same element active region.

  Such n-channel MOS transistors QM1 and QM2 for memory cell selection are covered with interlayer insulating films ILIa and ILIb deposited on the semiconductor substrate SUB.

  The interlayer insulating films ILIa and ILIb are made of, for example, a silicon oxide film, and are formed by, for example, a usual plasma CVD method. The upper surface of the interlayer insulating film ILIb is formed flat so that the heights of the memory region and the logic circuit region are substantially the same.

  Connection holes are formed in the interlayer insulating films ILIa and ILIb in the memory cell region so that the upper surfaces of the semiconductor regions DN and DNC of the memory cell selection MOS transistors QM1 and QM2 are exposed.

  In this connection hole, conductive materials Wa and Wb made of, for example, tungsten are embedded, and a contact electrode is formed. When tungsten is used as the conductive material, for example, about 10 nm of TiN exists as a barrier metal layer between the correlation insulating films ILIa and ILIb.

  This contact electrode is electrically connected to the semiconductor regions DN and DNC of the memory cell selection MOS transistors QM1 and QM2.

  A connection hole is formed in the interlayer insulating film ILIc in the memory cell region so as to expose a contact electrode made of conductive materials Wc and Wd made of tungsten, for example. When tungsten is used as the conductive material, for example, about 10 nm of TiN exists as a barrier metal layer between the correlation insulating film ILIc. This contact electrode is electrically connected to the semiconductor region DNC shared by the memory selection n-channel MOS transistors QM1 and QM2.

  An interlayer insulating film ILid is deposited on the upper surface of the interlayer insulating film ILIc. The interlayer insulating film ILId is made of, for example, silicon oxide.

  A connection hole is formed in the interlayer insulating film ILId in the memory cell region so that the source line wiring SL is exposed. In this connection hole, a conductive material PLUG made of, for example, tungsten is buried, and a contact electrode is formed. When tungsten is used as the conductive material, for example, about 10 nm of TiN exists as a barrier metal layer between the correlation insulating film ILId. This contact electrode is electrically connected to the source line wiring SL.

  A resistance element R to be a memory element is formed in the interlayer insulating film ILIe in the memory cell region. The resistance element R is formed in a stripe shape, and is composed of a phase change material PCR and an upper electrode UE made of tungsten, for example, coated on the surface thereof. The phase change material PCR constituting the resistance element R is, for example, a Ge—Sb—Te phase change material, a Zn—Te phase change material, or X-Ge—Sb—Te to which an additive element X of these materials is added. There is a system phase change material or a Y—Zn—Te system phase change material to which an additive Y is added. Examples of the additive element X include In, Cr, O, N, Zn, Bi, Ag, Au, and Se. Examples of the additive element Y include Sb, In, Cr, O, N, Ge, Bi, Ag, Au, and Se.

  Examples of the material used for the lower electrode plug PLUG of the phase change memory include W, TiN, TiW, TiAlN, and polysilicon.

  The lower portion of the resistance element R is electrically connected to the memory cell lower contact electrode, and is electrically connected to the semiconductor region DN of the n-channel MOS transistors QM1 and QM2 for memory cell selection through this.

  A hard mask insulating film HM is deposited on the upper surface of the resistance element R. The hard mask insulating film HM is made of, for example, silicon oxide. The hard mask insulating film HM is deposited for patterning the resistance element R, and is formed in a stripe shape.

  A connection hole is formed in the interlayer insulating film ILIe and the hard mask insulating film HM in the memory cell region so that the upper surface of the upper electrode UE is exposed. In this connection hole, a metal film We made of, for example, tungsten is buried to form a memory cell upper electrode contact. When tungsten is used as the conductive material, for example, about 10 nm of TiN exists as a barrier metal layer between the correlation insulating film ILIe.

  This memory cell upper electrode contact is electrically connected to the upper surface of resistance element R, and is electrically connected to semiconductor region DN of n channel type MOS transistors QM1 and QM2 for memory cell selection through this.

  A bit line BL is formed on the upper surface of the interlayer insulating film ILIe. This bit line is formed by depositing a metal layer ML made of aluminum. The bit line BL is electrically connected to a bit line contact made of, for example, a barrier metal BM and tungsten We, and is further electrically connected to the resistance element R through the bit line contact.

  FIG. 7 shows a configuration example of the column selector CSEL in FIG. This is an example in which a memory cell is selected from the memory cell array by 2 bits and operated. Even if the number of memory cells to be selected at the same time is different, the same configuration is possible. A column switch CSL2 is provided for every two bit lines and is controlled by a column selection signal output from the column decoder CDEC to connect two bit lines to the input / output lines IO0 and IO1. The column selection signal is a complementary signal to C01b and C01t, C23b and C23t,. The column switch CSL2 includes four NMOS transistors MNP0, MNP1, MNS0, and MNS1 and two PMOS transistors MPS0 and MPS1. The NMOS transistors MNP0 and MNP1 hold the unselected bit lines at the ground voltage VSS. The NMOS transistors MNS0 and MNS1 and the PMOS transistors MPS0 and MPS1 constitute two CMOS pass gates and connect the selected bit line to the input / output lines IO0 and IO1. Thus, by using the CMOS pass gate, the bit line and the input / output line can be connected with a low resistance in a wide voltage range. As a result, the range of the applied voltage of the bit line is widened, and a margin can be ensured when the resistance reduction and the resistance increase in the read operation and the write operation are divided by the value of the current flowing through the phase change resistor.

  FIG. 8 shows a configuration example of the write buffer block WB in FIG. The write buffer block WB includes a write pulse generation circuit WPG and two write buffers WB1. This is also an example in the case where data is simultaneously written in two memory cells in the memory cell array. If the write buffer WB1 is provided in accordance with the number of memory cells to be simultaneously written, other memory cell numbers can be handled. The write pulse generation circuit WPG generates pulses for lowering resistance and increasing resistance and outputs them to the write pulse lines WP0 and WP1, respectively. The write buffer WB1 is composed of two CMOS pass gates including three inverters, two two-input NAND gates, two NMOS transistors MNC0 and MNC1, and two PMOS transistors MPC0 and MPC1. The write buffer WB1 is activated by the write control signal WRIT, and connects the input / output lines IO0 and IO1 to the write pulse lines WP0 and WP1 according to the write data DI0 and DI1. Here, by using the CMOS pass gate, the write pulse generation circuit WPG can be driven to the ground voltage at the fall of the input / output lines IO0 and IO1. This prevents the charge charged in the parasitic capacitance of the input / output lines from being discharged through the bit lines and memory cells, making the pulse waveform of the bit line current fall sharply and realizing a stable write operation. it can.

  Next, the operation of the asynchronous phase change memory described above will be described. FIG. 9 shows an example of the timing of the write operation. In response to the transition of the external address ADR, the address transition detection circuit ATD generates a pulse in the address transition signal AT, and the word lines WL (WL0, WL1, WL2, WL3,... In FIG. 4) are switched. When the chip select bar signal CSb and the write enable bar signal WEb, which are part of the control signal CMD, become low level, the write control signal WRIT becomes “1”, and the write operation is performed. The selected bit line BL (BL0, BL1, BL2, BL3,... In FIG. 4) is driven according to the input Din to the input / output data DQ. Here, if the input Din is “0”, the bit line BL is driven to the set voltage VSET, but if it is “1”, the bit line BL is kept at the ground voltage VSS. If the input Din is “1”, the bit line BL is driven to the reset voltage VRST. The write control signal WRIT becomes “0” so that the high-resistance pulse has a desired pulse width, the bit line BL is returned to the ground voltage VSS, and the write operation is completed. Although Din is described as being 1 bit here, in the case of a plurality of bits, an operation corresponding to data is performed for each bit. In the following, other operation timings will be similarly simplified and described.

  In general asynchronous SRAM specifications, it is determined that the input Din is valid when the write operation period ends. In the operation of FIG. 7, if the input Din is “0”, the bit line is driven as it is to ensure a low resistance period. On the other hand, if the input Din is “1”, the bit line is driven after it is determined that it is valid, the pulse width for driving the bit line is shortened, and the surroundings of the phase change resistance of the selected memory cell are necessary. This prevents the temperature from rising and the cooling time from extending. As a result, a stable write operation can be realized for both ‘0’ and ‘1’. In addition, by limiting the pulse width for increasing the resistance as described above, an unnecessary write current is not flowed, so that a low-power write operation can be realized.

  FIG. 10 shows an example of the timing of the read operation. Similarly to the write operation shown in FIG. 9, the word line WL is switched according to the transition of the external address ADR. When the chip select bar signal CSb and the output enable bar signal OEb, which are part of the control signal CMD, become low level, the output buffer is activated, and the output Dout corresponding to the read / output data DQ is output from the input / output data DQ. To drive. When either the chip select bar signal CSb or the output enable bar signal OEb becomes high level and the read operation period ends, the output buffer DOB enters a high impedance state.

  The voltage pulse applied at the time of rewriting the phase change memory is applied as the voltage of the upper electrode UE with respect to the lower electrode plug PLUG or the voltage of the lower electrode plug PLUG with respect to the upper electrode UE. When a potential difference is generated between the upper electrode UE and the lower electrode plug PLUG, a current flows through the phase change material PCR, and Joule heat is generated in the lower electrode plug PLUG and the phase change material PCR having high resistance. This Joule heat induces a phase change of the phase change material PCR and rewrites the phase change memory.

  FIG. 1 is a diagram showing a waveform of a pulse voltage applied to the phase change material PCR, where (a) shows a reset operation and (b) shows a set operation. 2A and 2B are diagrams showing a temperature change of the phase change material PCR, where FIG. 2A shows a reset operation and FIG. 2B shows a set operation. In FIG. 1B and FIG. 2B, “present invention 1” is the waveform of the first embodiment, and “present invention 2” is the waveform of the second embodiment described later. It is a waveform. In addition, in order to make the characteristics of the present invention easier to understand, the waveforms of the conventional method studied as a premise of the present invention are also shown.

The phase change memory is reset by applying a rectangular pulse as shown in FIG. By applying the pulse, the temperature is raised to the melting point or higher, and the phase change material PCR is once melted and then rapidly cooled. For example, a temperature change when Ge ₂ Sb ₂ Te ₅ is used for the phase change material PCR will be described. Since the time constant of temperature change of Ge ₂ Sb ₂ Te ₅ is about 2 ns, if a sufficiently high voltage pulse is applied, the temperature of the phase change material PCR exceeds the melting point in 30 ns or less as shown in FIG. . Next, when the voltage pulse is returned to 0 V, it cools rapidly. As a result, the reset operation can be sufficiently performed in a time of 30 ns or less.

A set of phase change memories applies a rectangular voltage pulse of “present invention 1” as shown in FIG. When this voltage is applied, as shown in FIG. 2B, the temperature of the phase change material PCR rapidly rises due to the voltage application of “Invention 1” and reaches a temperature equal to or higher than the melting point when applied for a sufficiently long time. Before reaching the melting point, the pulse voltage is set to 0 V to cool. When this method is used, for example, when the phase change material PCR is Ge ₂ Sb ₂ Te ₅ , the crystal of the phase change material PCR is crystallized from the time when it exceeds 160 ° C., which is the temperature at which crystallization starts, to 160 ° C. by cooling Crystallization proceeds during this time because it is present in a temperature range where crystallization is promoted, ie, a crystallization temperature of 160 ° C. or higher and a melting point of less than 600 ° C. If the phase change material PCR exceeds the melting point due to the application of a voltage pulse, the phase change material PCR becomes amorphous, so that crystallization starts at a point below the melting point, which is disadvantageous from the viewpoint of speeding up. By using this method, the phase change material PCR can be crystallized at high speed.

(Embodiment 2)
FIG. 11 is a principal block diagram of a configuration example of the asynchronous phase change memory according to the second embodiment of the present invention. The memory array circuit, the memory array structure, the memory cell cross-sectional structure, the configuration of the column selector CSEL, the write buffer block WB, the write timing, and the read timing described in FIGS. 4 to 10 of the first embodiment are the same. Is omitted. Most of them are the same as the block diagram of FIG. 3 explained in the first embodiment, but in addition, a circuit for applying a two-stage voltage to the word line is incorporated. A signal from the external clock buffer CLKB to which a signal is input from the external clock CLK is input to the control signal generation circuit CPG, and a low set pulse RSP is generated, which is input to the word line control circuit WDCTL.

12 shows a part of the word line control circuit WDCTL shown in FIG. 11, FIG. 13 shows a configuration example of the short pulse generation circuit SPG shown in FIG. 12, and FIG. 14 shows the configuration shown in FIG. FIG. 15 is a diagram showing a configuration example of a word line driver WD capable of generating a two-stage pulse, and FIG. 15 is a diagram showing waveforms of two-stage pulse control signals φ ₁ , φ ₂ , and φ ₃ .

The circuit shown in FIG. 12 is connected to each word line driver WD shown in FIG. 15, and is produced in the same number as the word line drivers. In the word line control circuit WDCTL, the input low set pulse RSP is received, and the pulse input to the input SPGin of the short pulse generation circuit shown in FIG. 13 is transferred to the short pulse generation circuit SPG including the delay circuit DLS. Then, the pulse waveforms of φ ₁ , φ ₂ , and φ ₃ as shown in FIG. 14 are output from the output SPGout of the short pulse generation circuit. These pulses are input to the word line driver WD shown in FIG. 15 to generate a two-stage pulse.

  In the circuit shown above, it is possible to apply a two-stage voltage to the word line. However, if the circuits of FIGS. 12, 13 and 15 are applied to a bit line driver, a two-stage voltage is applied to the bit line. Things are also possible.

  FIG. 1B shows a pulse waveform (present invention 2) used in the set of the second embodiment. Moreover, the temperature change (Invention 2) at that time is shown in FIG. The set pulse waveform of the second embodiment is a two-stage pulse using two levels of voltage. Compared to the first embodiment, the advantage of using this two-stage pulse can be explained as follows. In the method shown in the first embodiment, since the applied voltage is high, the temperature rise rate is very fast and the time margin for stopping the pulse application is small. That is, when the resistance of the phase change material PCR varies low, the time constant of the temperature change decreases, and the rate of temperature increase of the phase change material increases, and as a result, melting occurs at the set pulse time shown in the first embodiment. The temperature may be exceeded. On the other hand, the two-stage pulse, which can use a lower voltage set pulse, is a setting method with a low possibility of erroneous reset exceeding the melting temperature even if the time constant of the temperature change of the phase change material PCR changes. .

  FIG. 16 is a diagram showing the temperature dependence of the crystallization rate in the phase change material PCR.

According to Non-Patent Document 1, the crystallization process of the phase change material PCR can be divided into nucleation in the first half and crystal growth in the second half. And in each process, the temperature dependence of the crystallization speed as shown in FIG. 16 exists. Nucleation has a temperature T ₁ that maximizes the nucleation rate, and the nucleation rate decreases at temperatures above and below that. The reason why the nucleation rate decreases at a temperature T ₁ or higher is that the free energy in the crystalline state is lower than the free energy in the amorphous state in the nucleation of the phase change material. The reason why the nucleation rate decreases at a temperature T ₁ or less is that the diffusion coefficient of the atoms constituting the phase change material rapidly decreases with temperature.

Further, in the crystal growth, there exists a temperature T ₂ lower than the temperature T ₁ that maximizes the crystallization rate, and the crystallization rate decreases at a temperature higher or lower than that. The reason is the same mechanism as the temperature dependence of the nucleation rate. That is, in order to accelerate the crystallization most quickly, the temperature of the phase change material should be T _{1 in} the first half of crystallization and T _{2 in} the second half of crystallization, as shown in FIG.

In order to demonstrate that the speed can be increased by setting with a two-stage pulse, a set experiment of various shapes is applied to the phase change material PCR in the reset state, and a principle experiment for examining the set resistance is performed. It was. The applied set pulse is shown in FIG. As the first voltage, a voltage of 2.0 V at which the phase change material PCR has the fastest nucleation rate is applied for 30 ns. Subsequently, a voltage of V _2nd V was applied as the second voltage for t _2nd ns. In particular, V _2nd is selected to be 2.0 V, which is a rectangular wave pulse equal to the first voltage, and 1.8 V, which is the temperature at which the crystal growth rate is the fastest, as the temperature of the phase change material PCR, and t _{2nd is set} to 40 ns, respectively. From 10 ns to 10 ns at 5 ns intervals. With the application of these pulses, the temperature of the phase change material PCR does not exceed the melting point. The set resistance after applying these set pulses to the reset resistance was measured to determine the ratio of the reset resistance to the set resistance. The result is shown in FIG.

When V _2nd is 2.0 V, if t _2nd is shortened, crystallization of phase change material PCR becomes insufficient and set resistance increases. In order to read out the written information at a high speed, it is desirable that the ratio between the set resistance and the reset resistance is one digit or more. In order to satisfy the required value of the resistance ratio, t _2nd needs to be 30 ns or more from the result of FIG. That is, the set time by the rectangular pulse is 60 ns which is the sum of the application time 30 ns of the first voltage and the application time 30 ns of the second voltage.

On the other hand, when V _2nd is 1.8V, the resistance ratio takes a large value even when t _2nd is the same as when V _2nd is 2.0V. This is because when V _{2nd is set} to 1.8 V, the temperature of the phase change material PCR changes from the temperature at which the nucleation rate becomes the fastest to the temperature at which the crystal growth rate becomes the fastest, and V _2nd becomes 2. This is because crystallization proceeds in a shorter time than in the case of 0V. As a result, when V _2nd is 1.8 V, the shortest t _2nd that satisfies the required resistance ratio is 10 ns. That is, when a two-stage pulse is used, the set time is 40 ns, which is the sum of the first voltage application time 30 ns and the second voltage application time 10 ns.

  In other words, experiments have shown that using a two-stage pulse for a set can increase the speed compared to a one-stage pulse.

FIG. 19 shows the temperature change of the phase change material PCR depending on the pulse waveform. In FIG. 19, (a) to (d) are pulse waveforms, (e) to (h) are temperature changes, (a) and (e), (b) and (f), (c) and (g). ), (D), and (h) correspond to each other. T _m is a melting temperature (melting point), T _c is a crystallization temperature, and crystallization proceeds when the phase change material is at a temperature of T _c or more and less than T _m . (E), (f), (g), in (h), the temperature of the phase change material by applying each pulse _{T c} above, a is a time less _{T m, t 1, t 2} , t 3 , T ₄ . Note that a relational expression of t ₁ <t ₃ = t ₄ <t ₂ is established between the times t ₁ , t ₂ , t ₃ , and t ₄ .

FIG. 19A shows a reset pulse having a pulse width of 30 ns. Since the applied voltage is larger than the set pulse, the temperature rise rate is large as shown in (e), and the melting point _Tm is exceeded immediately after the reset pulse is applied. Although the temperature rapidly decreases after the reset pulse is applied, the crystallization hardly progresses because the time t _{1 at} a temperature not lower than T _{c and not} higher than T _m is very short. As a result, the resetting of the phase change material PCR is completed.

FIG. 19B shows a set pulse having a pulse width of 30 ns. This corresponds to the setting method described in the first embodiment. By applying a pulse voltage higher than the normal set voltage, the temperature of the phase change material rises as shown in FIG. 19 (f), and since the pulse voltage is high, the temperature reached when left alone is _Tm or more. Stops applying the pulse before _Tm is exceeded. Thereafter, the temperature of the phase change material decreases. As a result, the time t ₂ in which the phase change material is present in the temperature range of T _c or more and T _m or less does not exceed T _m as shown in (f), and therefore a longer time than in the case of (a). t ₂ is secured and crystallization proceeds.

FIG. 19C shows a set pulse corresponding to the one-stage pulse described in FIG. The voltage is a value at which the phase change material reaches a temperature at which nucleation is accelerated most quickly. Since the pulse voltage is lower than that in (b), the temperature change (g) indicates the temperature change compared to (f). The rise is slow. As a result, the time exceeding T _c is also delayed, and although the pulse width is 50 ns, which is longer than 30 ns in (b), the time t ₃ existing in the temperature range from T _c to T _m is t Shorter than ₂ . As a result, crystallization does not proceed sufficiently.

FIG. 19D shows a set pulse corresponding to the two-stage pulse described in FIG. This corresponds to the setting method described in the second embodiment. The rise in temperature due to the first stage pulse application shown in (h) is the same as in (g). As a result, the phase change material has a temperature at which the nucleation rate is fastest. Next, the voltage is switched to a second voltage that is lower than the first voltage and at which the phase change material is at a temperature that maximizes crystal growth. As a result, nucleation and crystal growth in the crystallization process are performed rapidly, and the time t ₄ when the phase change material is in the temperature range of T _c or more and T _m or less is t shown in (c) and (g). _This is almost the same as ₃ , but the crystallization is sufficient.

  20 is a diagram showing a transistor characteristic curve when a two-stage pulse is applied to the bit line, and FIG. 21 is a diagram showing a transistor characteristic curve when a two-stage pulse is applied to the word line.

The two-stage pulse applied to the phase change material in the second embodiment is created by applying the two-stage pulse to the bit line BL or the word line WL. When the phase change material PCR is, for example, Ge ₂ Sb ₂ Te ₅ , the current-voltage characteristics have non-ohmic properties as shown in the load curves of the transistors in FIGS. This non-ohmic feature is that the differential resistance decreases as the voltage applied to the phase change material PCR increases. Based on this mechanism, based on the change in the resistance of the phase change material and the change in the voltage applied to the phase change material when a two-stage pulse is applied to the bit line BL or the word line WL, the phase change material Consider Joule heat generated by PCR.

When a two-stage pulse is applied to the bit line BL, as shown in FIG. 20, when the voltage is _decreased from the first voltage V _BL1st applied to the bit line to the second voltage V _BL2nd applied to the bit line, it is applied to the selection transistor. The applied voltage _decreases from the first voltage V _BDS1st between the source and the drain when the bit line two-stage pulse is applied to the second voltage V _BDS2nd between the source and the drain when the bit line two-stage pulse is applied. The two load curves have a relationship shifted in the horizontal axis direction, and the resistance change of the phase change material PCR is R _PCR (V _BDS2nd ) −R _PCR (in consideration of the non-ohmic characteristics described above. It can be seen that V _BDS1st )> 0. Further, the voltage change applied to the phase change material PCR is (V _BL2nd −V _BDS2nd ) − (V _BL1st −V _BDS1st ) <0, which is a decrease. That is, Joule heat E generated in the phase change material PCR is expressed by E = V ² / R, but when the bit line BL voltage is changed from the first voltage to the second voltage, the resistance of the phase change material PCR increases. Since the voltage applied to the phase change material PCR decreases, the change amount ΔE _BL of the Joule heat E generated in the phase change material PCR when the bit line two-stage pulse is applied always satisfies ΔE _BL <0. This is suitable for generating a temperature change from the nucleation temperature to a lower crystal growth temperature.

Next, a case where a two-stage pulse is applied to the word line WL will be considered with reference to FIG. When the voltage applied to the word line is _decreased from the first voltage V _WL1st applied to the word line to the second voltage V _WL2nd applied to the word line, the voltage applied to the selection transistor is changed to the word line two-stage pulse. The first voltage V _WDS1st between the source and the drain at the time of application increases to the second voltage V _WDS2nd between the source and the drain at the time of applying the word line two-stage pulse. As a result, it can be seen that the resistance change of the phase change material increases as R _PCR (V _WDS2nd ) −R _PCR (V _WDS1st )> 0 due to the non-ohmic characteristics described above. The voltage change applied to the phase change material is (V _BL −V _WDS2nd ) − (V _BL −V _WDS1st ) = V _WDS1st −V _WDS2nd <0, which is a decrease. That is, when the word line WL voltage is changed from the first voltage to the second voltage, the resistance of the phase change material PCR increases, and the voltage applied to the phase change material PCR decreases. A change amount ΔE _WL of Joule heat E generated in the phase change material at that time is always ΔE _WL <0. This is suitable for generating a temperature change from the nucleation temperature to a lower crystal growth temperature.

That is, when a two-stage pulse is applied to the bit line BL or the word line WL, the Joule heat is reduced by changing both from the first voltage to the second voltage, which is lower than the temperature at which the nucleation rate is maximized. It is possible to change the temperature to accelerate crystal growth. However, the range of possible temperature changes varies depending on the applied voltage dependence of the resistance of the phase change material PCR. The width of this temperature change must be at least greater than the temperature difference between the temperature at which the nucleation rate is most accelerated and the temperature at which crystal growth is most accelerated. Therefore, there is a possibility that a predetermined temperature control can be performed by using a method having the largest Joule heat change among the bit line BL2 stage pulse and the word line WL2 stage pulse according to the applied voltage dependency of the resistance of the phase change material PCR. Is the highest. That is, when ΔE _BL > ΔE _WL , a method of applying a two-stage pulse to the bit line is desirable, and when ΔE _BL <ΔE _WL , a method of applying a two-stage pulse to the word line WL is desirable.

(Embodiment 3)
Since the memory cell circuit and the cross-sectional structure of the third embodiment are the same as those shown in FIGS. 4 to 15, description thereof is omitted.

The two-stage pulse applied to the phase change material according to the third embodiment is generated by applying a two-stage voltage pulse to the word line WL while applying a certain voltage to the bit line BL. The voltage applied to the word line WL includes a first voltage V _WL1st of the word line WL and a second voltage V _WL2nd of the word line WL lower than the first voltage V _{WL1st of the} word line WL. The first voltage V _WL1st of the word line WL is obtained from the relationship between the drain current, the drain voltage, and the word voltage of the selection transistor TR so that the first voltage V _PCR1st is appropriately applied to the phase change material PCR. The time of the first voltage V _WL1st of the word line WL is the same as the time of the first voltage V _{PCR1st to be} obtained. The second voltage V _WL2nd of the word line WL is obtained from the relationship between the drain voltage, the drain current, and the word voltage of the selection transistor TR so that the second voltage V _PCR2nd is appropriately applied to the phase change material PCR. The time of the second voltage _VWL2nd of the word line WL is the same as the time of the second voltage _VPCR2nd applied to the phase change material PCR.

  The reason why the two-stage pulse is directly applied to the word line WL instead of the bit line BL is to suppress variation in drain current of a selection transistor TR, for example, a MISFET (Metal Insulator Semiconductor Field Effect Transistor).

FIG. 20 shows a change in the load curve of the selection transistor TR when a two-stage voltage is applied to the bit line BL. The first voltage V _BL1st of the bit line BL is applied to the bit line BL, and then changed to the second voltage V _BL2nd of the bit line. At this time, the applied voltage between the source and drain of the MISFET _decreases from the first source-drain voltage V _BDS1st when the bit line voltage is applied to the second source-drain voltage V _BDS2nd when the bit line voltage is applied. In addition, the voltage applied to the phase change material PCR also decreases. As a result, the drain current moves to the linear region, and the variation in the drain current with respect to the variation in the bit line BL voltage becomes large. If the drain current varies in the direction of decreasing, the temperature of the phase change material PCR does not rise sufficiently, and the setting becomes insufficient.

On the other hand, FIG. 21 shows a change in the load curve of the selection transistor TR when a two-stage voltage is applied to the word line WL. The first voltage V _WL1st of the word line WL is applied to the word line WL, and then the word line WL is changed to the second voltage V _WL2nd of the word line WL. At this time, the voltage applied between the source and drain of the MISFET _increases from the first source-drain voltage V _WDS1st when the word line voltage is applied to the second source-drain voltage V _WDS2nd when the word line voltage is applied. . Also, the voltage applied to the phase change material PCR decreases. As a result, the drain current moves to the saturation region, and the drain current variation with respect to the bit line BL voltage variation becomes small. Also, it is desirable to apply a constant current pulse to the phase change material as compared to a constant voltage pulse. With constant voltage pulses, the resistance of the phase change material PCR decreases during set pulse application, and with constant voltage pulses, the current increases rapidly, resulting in a sudden increase in Joule heat, and the temperature of the phase change material PCR exceeds the melting point. . On the other hand, a rapid increase in Joule heat does not occur with a constant current pulse. The details of this phenomenon are as follows.

When a constant current is applied to the word line WL, a constant current I ₀ is applied between the upper electrode UE and the lower electrode PLUG. At that time, if the resistance between the upper electrode UE and the lower electrode PLUG at the start of set pulse application is R ₀ and the voltage between the upper electrode UE and the lower electrode PLUG in the reset state is V ₀ , V ₀ = R ₀ × I ₀ (1)
Holds. Next, assuming that the resistance between the upper electrode UE and the lower electrode PLUG at the end of the application of the set pulse is R ₁ , R ₁ <R ₀ holds. This is because the resistance value decreased due to the application of the set pulse. Also, assuming that the voltage between the upper electrode UE and the lower electrode PLUG in the reset state is V ₁ , V ₁ = R ₁ × I ₀ (2) according to Ohm's law immediately before the end of the set pulse application.
The relationship holds. From the relationship of R ₁ <R ₀ and the expressions (1) and (2), it can be seen that V ₁ <V ₀ holds. The set pulse is applied to the reset state of the phase change material PCR, but gradually changes to a low resistance state during the application of the set pulse. Therefore, the power consumed in the phase change material PCR changes from V ₀ I ₀ to V ₁ I ₀ . From the voltage relationship V ₁ <V ₀ , it can be seen that the magnitude relationship between these power consumptions is V ₀ I ₀ > V ₁ I ₀ . Since the electric power consumed by the phase change material is proportional to the generated Joule heat, the Joule heat generated by the application of the set pulse tends to gradually decrease, and there is no fear of liquid phase growth.

On the other hand, in the method for applying a constant voltage to the bit line BL, and between the upper electrode UE and the lower electrode PLUG constant voltage V ₂ is applied. The resistance R ₂ between the upper electrode UE and the lower electrode PLUG of the reset state of the set pulse is applied at the _start, when the voltage between the upper electrode UE and the lower electrode PLUG of the reset state and V _2, V ₂ Ohm's law = R ₂ × I ₂ (3)
Holds. Next, assuming that the resistance between the upper electrode UE and the lower electrode PLUG at the end of the set pulse application is R ₃ , R ₂ > R ₃ holds. Also, assuming that the current between the upper electrode UE and the lower electrode PLUG in the reset state is I ₃ , in the set state, V ₂ = R ₃ × I ₃ (4) according to Ohm's law
The relationship holds. From the relationship of R ₃ <R ₂ , it can be seen from formulas (3) and (4) that I ₃ > I ₂ holds. The power consumed by the phase change material changes from V ₂ I ₂ to V ₂ I ₃ , but it can be seen that the relationship of V ₂ I ₂ <V ₂ I ₃ holds from the relationship of I ₃ > I ₂ . That is, when a constant voltage is applied to the bit line, Joule heat increases during set pulse application. Since the Joule heat increase rate I ₃ / I ₂ is equal to R ₂ / R ₃ , it can be seen that the Joule heat increases 10 times or more because R ₂ is 10 times or more larger than R ₃ . As a result, the temperature of the phase change material PCR exceeds the crystallization temperature, and the possibility of liquid phase growth becomes very high. When the liquid phase is grown, high-speed setting is impossible due to the above reasons. That is, in order to perform high-speed setting, it is desirable to apply a current pulse to the phase change material PCR, and one means is to apply a voltage pulse to the word line WL.

Circuit diagrams capable of producing a two-stage pulse used in the present invention are shown in FIGS. FIG. 15 shows a word line driver WD for controlling the word voltage. From the first power supply voltages _{V 1} and the second power supply voltage _{V 2} applied to the word line WL, and controls the word line voltage VWL via respective PMOS transistors MP1 and MP2. The gate of the PMOS transistor are respectively connected to the write enable signal phi ₁ and phi _2. Further, it is drawn to the ground potential through the NMOS transistor MN from between the PMOS transistor and the word line voltage VWL. The gate of the NMOS transistor MN is connected to the write enable signal phi _0.

FIG. 14 shows changes in the write enable signals φ ₁ , φ ₂ , and φ ₃ when a two-stage voltage is applied to the word line from the standby time. When the first stage voltage is applied, the write enable signals φ ₀ and φ ₁ are changed from the high potential VDD to the ground potential VSS. Then, when a voltage of the second stage, is changed from a write enable signal phi ₁ from the ground potential VSS to the high potential VDD, also to alter the write enable signal phi ₂ from the high potential VDD to the ground potential VSS. Finally, when exiting the application of the second-stage voltage is changed to the high potential VDD than the ground potential VSS write enable signal phi _0, it changes the write enable signal phi ₂ from ground potential VSS to the high potential VDD.

(Embodiment 4)
22 and FIG. 23 are cross-sectional views showing the structure in the vicinity of the plug electrode of the phase change memory cell according to the fourth embodiment of the present invention. FIG. 22 shows that the interface layer IL is formed on the entire surface of the interlayer insulating film ILId. FIG. 23 shows a case where the interface layer IL is formed only on the lower electrode plug PLUG.

  The interface layer IL is a high resistance film formed on the interlayer insulating film ILId and the lower electrode plug PLUG and on the lower electrode plug PLUG shown in FIG.

  The purpose of interfacial layer IL insertion is to increase the heat generation efficiency and reduce the rewrite voltage by strengthening the adhesive force between the interlayer film INS and the lower electrode plug PLUG and the phase change material PCR or inserting a resistor. Examples of the material used for the interface layer IL include a Ti film, Al film, Ta film, Si film, TiN film, AlN film, TaN film, WN film, TiSi film, TaSi film, WSi film, TiW film, TiAlN film, Examples include a TaSiN film, a TiSiN film, and a WSiN film. Further, using the fact that Te contained in the phase change material PCR easily reacts with Ti or Al, a compound of Ti and Te or a compound of Al and Te may be used as the conductive interface layer. Examples of the insulating interface layer include a TiO film, AlO film, TaO film, NbO film, VO film, CrO film, WO film, ZrO film, HfO film, and SiO film.

A circuit diagram of the memory cell according to the fourth embodiment is expressed as shown in FIGS. For this reason, since the resistance of the interface layer depends on the voltage V _IL applied to the interface layer, it is expressed as R _IL (V _IL ). Assuming that the voltage applied to the phase change material is V _PCR , the resistance of the phase change material PCR is expressed as R _PCR (V _PCR ). Therefore, the voltage applied between the upper electrode UE and the lower electrode plug PLUG is expressed as V _{PCR. If TOTAL} , the phase change material PCR when the interface layer IL is inserted and the Joule heat E _TOTAL generated in the interface layer are expressed as E _TOTAL = V _TOTAL ² / (R _PCR (V _PCR ) + R _IL (V _IL )) Is done. _Between the V _TOTAL and _{V PCR} and _{V IL,} since the relation of _{V TOTAL = V} PCR _{+ V IL holds,} if _{V TOTAL} is _{determined, V TOTAL is} the _{V PCR} and _{V IL, R PCR} and _{R IL} The voltage is distributed at the ratio of. Defining the _{R TOTAL = R PCR + R IL} , since _{R TOTAL} is a function of _{V TOTAL,} it can be expressed as R _{TOTAL (V TOTAL).} In other words, it can be expressed as E _TOTAL = V _TOTAL ² / R _TOTAL (V _TOTAL ). Since R _PCR and R _IL are both non-ohmic, the sum R _TOTAL is also non-ohmic.

When R _TOTAL decreases with increasing V _TOTAL , it is appropriate to apply the two-stage pulse to the bit line BL or to the word line WL according to the same argument as described in the second embodiment. Can be determined. It is also true that the drain current variation can be reduced by applying a two-stage pulse to the word line WL described in the third embodiment.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention can be used in the manufacturing industry of semiconductor devices, electronic devices, and the like.

Claims (5)

Multiple word lines,
A plurality of bit lines intersecting the plurality of word lines;
A plurality of memory cells provided at intersections of the plurality of word lines and the plurality of bit lines;
A control circuit for controlling a write pulse to the plurality of memory cells,
The control circuit includes a first shot pulse generation circuit that outputs a first control signal, and a second shot pulse generation circuit that outputs a second control signal,
When writing to any of the plurality of memory cells, the first shot pulse generation circuit changes the potential of the first control signal to a selection level, thereby changing the potential of the write pulse to the first selection level. Thereafter, the second shot pulse generation circuit changes the potential of the second control signal from the first selection level to the second selection level by causing the potential of the second control signal to transition to the selection level .
A plurality of drivers for supplying the write pulses to the plurality of memory cells;
Each of the plurality of drivers corresponds to a first MOS transistor having a source and a drain between a first potential corresponding to the first selection level and an output node outputting the write pulse, and to the second selection level. A second MOS transistor having a source and a drain between a second potential and the output node;
The semiconductor device, wherein the first control signal is input to a gate of the first MOS transistor, and the second control signal is input to a gate of the second MOS transistor . The semiconductor device according to claim 1 ,
The semiconductor device, wherein the second potential is lower than the first potential. The semiconductor device according to claim 1 ,
The semiconductor device, wherein a transition period from the selection level of the first control signal to the non-selection level and a transition period of the second control signal from the non-selection level to the selection level overlap. The semiconductor device according to claim 1 ,
The control circuit outputs a third control signal for setting the write pulse to a non-selection level;
Each of the plurality of drivers further includes a third MOS transistor having a source / drain between a third potential corresponding to the non-selection level and the output node,
The semiconductor device according to claim 1, wherein the third control signal is input to a gate of the third MOS transistor. The semiconductor device according to claim 1 ,
The output node is connected to a corresponding one of the plurality of word lines.

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