JP4668668B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device and a semiconductor memory device, and more particularly to an on-chip memory mounted on a nonvolatile memory or a system LSI (microcomputer or the like).

Phase change memory is being developed with the aim of high-speed and highly integrated nonvolatile memory. The phase change memory is described in Non-Patent Document 1 and Patent Document 1. For example, as shown in Non-Patent Document 1, in a phase change memory, information is stored by utilizing the fact that a phase change material called a chalcogenide material has different resistance depending on the state. The rewriting of the phase change resistor is performed by changing the state by causing a current to flow to generate heat. High resistance (amorphization), also called reset (RESET) operation, is performed by keeping it at a relatively high temperature, and low resistance (crystallization), also called set operation (SET), is kept at a relatively low temperature for a sufficient period. To do. Further, Patent Document 1 states that the read current of the phase change material is made smaller than the rewrite current within a range in which the state of the phase change resistance is not changed.
IEE, International Solid-State Circuits Conference, Digest of Technical Papers, pages 202-203 (2002) (2002 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp. 202-203.) US Patent No. 6590807

  However, at the time of reading, it is necessary to flow a current within a range in which the state of the phase change resistance is not changed in order to prevent destruction of information, and a current smaller than the rewriting current is flowed. However, when the current is decreased, the reading speed is deteriorated. That is, from the viewpoint of preventing information destruction, it is necessary to reduce the reading current, and from the viewpoint of reading speed, it is necessary to increase the reading current, which is in a trade-off relationship.

  The following is a brief description of an outline of typical inventions among the inventions disclosed in this specification.

  The first is to have a memory cell and an input / output circuit for storing information by changing the crystal state depending on the applied temperature, and to rewrite the information read during the read operation.

  Second, it has a memory cell and an input / output circuit for storing information by changing the crystal state depending on the applied temperature, and at the time of write operation, the read information is replaced with external write information. To write to a memory cell.

  Third, there is a memory cell and an input / output circuit for storing information by changing the crystal state depending on the applied temperature, and the cell is current-driven by the same circuit for reading and writing.

  Fourth, between the reading and rewriting described in the first, or between the reading and writing described in the second, a rewriting pulse current or a pulse current having a polarity opposite to that is applied prior to the writing pulse current. It is in.

  Fifth, there is a memory cell and an input / output circuit for storing information by changing the crystal state depending on the applied temperature, and the word line voltage is made higher than the power supply voltage at the time of write operation.

  Sixth, there is a memory cell and an input / output circuit for storing information by changing the crystal state depending on the applied temperature, and the low level of the word line voltage is made lower than the ground potential.

  Seventh, there are memory cells and read / write circuits that store information by changing the crystal state depending on the applied temperature, and multiple memory cells on the same word line are connected to the corresponding multiple read / write circuits simultaneously There is something you can do.

  Eighth is to arbitrarily combine the first to seventh means.

  According to the present invention, the reading speed of the semiconductor device can be increased.

  Several preferred examples of the semiconductor memory device according to the present invention will be described below with reference to the drawings. The circuit elements constituting each functional block of the embodiment are not particularly limited, but are formed on a single semiconductor substrate such as single crystal silicon by a known integrated circuit technology such as a CMOS (complementary MOS transistor). . In the drawing, the connection of the substrate potential of the MOS transistor is not specified, but the connection method is not particularly limited as long as the MOS transistor can operate normally. Unless otherwise noted, the low level of the signal is ‘L’ and the high level is ‘H’.

Example 1
<Memory module configuration>
This will be described in detail using the memory module of FIG. The memory array ARRAY constituting the memory module is composed of a plurality of word lines WL and a plurality of bit lines BL, and a memory cell MC is connected to the intersection of the word line WL and the bit line BL. Each memory cell MC includes an N-channel MOS transistor MN00 and a storage element R00, as exemplified by the memory cell MC00. The memory element R00 is an element called a phase change resistor. For example, the memory element R00 is a low resistance of about 1 KΩ to 10 KΩ in a crystalline state and a high resistance of 100 KΩ or more in an amorphous state. A word line WL0 is connected to the gate electrode of the N-channel MOS transistor MN00, and the N-channel MOS transistor is controlled to be turned on in the selected state and turned off in the non-selected state. One terminal of R00 is connected to the bit line BL0, and the other terminal is connected to the drain electrode of MN00. The source electrode of MN00 is connected to the ground potential. In this embodiment, the phase change element R is connected between the bit line BL and the N-channel MOS transistor MN, but may be connected between the ground potential and the N-channel MOS transistor MN. It is also possible to use bipolar transistors instead of MOS transistors.

  An X-system address decoder block is connected to the word line WL, and one word line WL is selected by the X-system address signal.

  A bit line selection circuit BLS is connected to the bit line BL, and is selectively connected to the common line CL by the switch SW. The switch SW is controlled by a bit line selection signal BS from the Y-system address decoder block.

  The read / write circuit RWC includes a sense amplifier SA, a write amplifier WA, a write data selection circuit WDC, and a read control circuit RA. The sense amplifier SA amplifies the signal of the common line CL. The read control circuit RA includes a switch RSW and a current source (Iread). The write amplifier WA includes a P-channel MOS transistor (MP0, MP1), a current source (Iset, Ireset), and a write current selection circuit WIC, and forms a current mirror circuit. The source electrode of the P-channel MOS transistor MP0 has a power supply potential VDD, the gate electrode and the drain electrode have a node NG, the source electrode of the P-channel MOS transistor MP1 has a power supply potential VDD, the gate electrode has a node NG, A common line CL is connected to each drain electrode. A current source (set current source Iset or reset current source Ireset) is connected to the node NG by a write current selection circuit WIC. The potential of the node NG changes so that the current of the connected current source and the current IW0 flowing through MP0 are the same. Since MP1 and MP0 have the same gate-source voltage, the current IW1 is the same as IW0. As a result, the current flowing to the bit line BL becomes the same as the current of the current source connected to the node NG.

  The write data selection circuit WDC receives the write control signal WE, input data Di, and output data Do, and outputs signals (reset current selection signal RIS, set current selection signal SIS) to the write data selection circuit WIC.

<Operation method>
Next, a detailed operation will be described with reference to FIG. The power supply voltage VDD of the internal circuit is, for example, 1.5V. Initially, it is in the standby state STANDBY, the address ADD is switched, and the read operation READ starts when the write control signal WE becomes 'L'. Here, a case where “1” (reset (high resistance) state) is read from the memory cell MC00 will be mainly described. In FIG. 2, it is shown by a solid line. When reading “0” (set (low resistance) state), it is indicated by a broken line.

  At the same time that the word line WL0 is activated from ‘L’ to ‘H’, the switch RSW is turned on, and the drive current Iread is supplied to the bit line BL0. The phase change element is an element whose crystal state is changed by heat. In particular, the amorphous (reset) state is gradually crystallized (set) even by heat generated by a small current. Since this change is accumulated, in order to delay crystallization as much as possible, it has been necessary to flow a current smaller than the write current at the time of conventional reading. Fig. 3 shows the relationship between Iread and the number of reads. For example, if a current of 100 uA is applied, data is destroyed by reading once, but if the current is about 10 uA, reading can be performed almost infinitely. However, with a current of about 10 uA, it takes time until the potential of the bit line BL changes, and the reading speed becomes slow. Therefore, in the present invention, Iread is increased to, for example, 100 uA to increase the reading speed. However, since the data may be destroyed, the read data is rewritten.

  When the read current Iread is passed through the bit line BL0, the memory cell MC00 is written with a high resistance value of 100 kΩ (corresponding to data '1'), for example, so that the potential of the bit line BL0 rises to near the power supply, For example, it becomes 1.2V. If a value of a low resistance of 10 kΩ (corresponding to data “0”) is written in the memory cell MC00, the bit line BL0 does not rise so much and becomes about 1.0V. This voltage is compared with the reference voltage REF by the sense amplifier circuit SA by setting the sense amplifier activation signal SE to ‘H’, and this potential difference is amplified. The amplified data is output to Do and the reading ends. When a high resistance value is written, “1” is output to Do, and when a low resistance value is written, “0” is output to Do.

  In this embodiment, after reading, the read data is rewritten. This eliminates the problem of data destruction during reading.

  In this embodiment, “1” is read out, the read data is sent to the write data selection circuit WDC, and the reset current selection signal RIS changes from “L” to “H”. This drives the write current selection circuit WIC and connects the current source Ireset to NG. As a result, the current IW1 of the P-channel MOS transistor MP1 also becomes Ireset, and the current Ireset can flow toward the bit line BL0.

The reset current Ireset is, for example, 200 uA. When data is destroyed by reading and the element has a low resistance, a current of 200 uA continues to flow, and the bit line rises to near the power supply potential. Even if the resistance of the element is not reduced by reading, the element is reduced in resistance by the reset current Ireset, and a current of 200 uA continues to flow. By continuing this state from 5 nanoseconds to several tens of nanoseconds, the device enters a molten state. Thereafter, the current flowing in the element is rapidly lowered and rapidly cooled, whereby the memory element R00 becomes amorphous and becomes high resistance (corresponding to data '1').
The unselected bit line BL is connected to the ground potential.

  If “0” is read, the memory element R is in the set state, so that the resistance value does not change even when the read current Iread is passed during reading, and it is not necessary to write back the data. However, in this embodiment, in order to simplify the control, writing is performed even when “0” is read. In this case, a set current Iset is caused to flow toward the bit line BL0 by the write amplifier WA after reading. Since the element has a low resistance, a current of 100 uA continues to flow. This state is continued for about 100 nanoseconds and the writing operation is finished.

When the writing is completed, the word line WL0 changes from “H” to “L”, and the setting operation ends.
In the write operation WRITE, after the data is read, the write data selection circuit WDC selects the input data Di from the outside, and the reset current selection signal RIS and the set current selection signal SIS are controlled based on this data. Write.

  The waveform diagram indicated by the solid line in the present embodiment writes ‘0’ after reading ‘1’, and the waveform diagram indicated by the broken line writes ‘1’ after reading ‘0’. When “0” is written, the element is set by changing the SIS signal from “L” to “H” and passing a set current Iset to the bit line BL. When writing “1”, the RIS signal is changed from “L” to “H” to cause the reset current Ireset to flow to the bit line BL to reset the element.

  Reading in the write operation WRITE is not necessary, but the same control as the read operation READ is performed to simplify the control.

  In this embodiment, it is necessary to flow a current Ireset of 200 uA to the element at the time of reset. Accordingly, the N-channel MOS transistor MN of the memory cell MC also needs a driving force that allows an equivalent current to flow. In order to increase the current driving capability, the gate width of the transistor may be increased, but this increases the size of the memory cell. Therefore, instead of increasing the gate width, the voltage when the word line WL is ‘H’ is boosted to a value higher than the power supply voltage VDD to increase the current driving capability. In this embodiment, the word line voltage is set to 2.5 V, which is 1.0 V higher than the power supply voltage VDD. FIG. 4 shows the relationship between the memory cell size and the word voltage necessary for supplying a current of 200 uA. When the word voltage is increased, the flowing current increases, so that the gate width can be relatively reduced and the cell size can be reduced. When the word voltage is boosted to 2.5 V, compared with the case where the word voltage is 1.5 V and the gate width is increased, the cell area can be reduced to about 60% and the cell size can be 6F2. In consideration of reliability, the voltage to be boosted must be such that a voltage of 5 MV / cm or higher is not applied to the gate electrode.

  As another method for increasing the current driving capability of the N-channel MOS transistor MN of the memory cell MC, there is a method for lowering the threshold value. In this case, the voltage when the word line WL is “H” can be set to the power supply voltage VDD. However, since the leakage current when not selected increases, a negative voltage is applied when the word line WL is “L”. There is a need. For example, when the threshold value is lowered by 0.5 V, the same effect is obtained as when the word line WL is boosted to 2 V, but −0.5 V needs to be applied to the non-selected word line WL.

  FIG. 5 shows a plan view of the memory array. The word line WL is formed of a polysilicon layer (PS), the source line SL is formed of a first wiring layer M1, and the bit line BL is formed of a second wiring layer M2. The diffusion layer L and the wiring layer M1 are connected by a contact CNT, and the wiring layer M1 and the wiring layer M2 are connected by a via VIA.

<When controlling word lines>
A case where the word line is controlled using the memory module of FIG. 6 will be described. The memory array ARRAY constituting the memory module is composed of a plurality of word lines WL and a plurality of bit lines BL, and a memory cell MC is connected to the intersection of the word line WL and the bit line BL. Each memory cell MC includes an N-channel MOS transistor MN00 and a storage element R00, as exemplified by the memory cell MC00. The memory element R00 is an element called a phase change resistor. A word driver array WD_ARY is connected to the word line WL, and the X-system address decoder ADEC decodes the X-system address signal XADD to select one word line WL. The word driver array WD_ARY is composed of word drivers WD, and the word driver WD0 is an inverter circuit composed of, for example, an N-channel MOS transistor MN10 and a P-channel MOS transistor MP10, and the output is a word line WL. The source electrode of the P-channel MOS transistor MP10 is connected to the power supply line VWL.

  A bit line selection circuit BLS is connected to the bit line BL, and is selectively connected to the common line CL by the switch SW. The switch SW is controlled by a bit line selection signal BS from the Y-system address decoder block.

  The read / write circuit RWC includes a sense amplifier SA, a write amplifier WA, a write data selection circuit WDC, and a write control circuit WIC. The write data selection circuit WDC receives the write control signal WE, the input data Di, and the output data Do, and outputs the control signal CW to the write / write control circuit WIC. The write control circuit WIC controls the power supply line VWL and the signal BS based on the CE signal. The write amplifier WA is composed of a P-channel MOS transistor MP1, and a control signal BC is input to the gate electrode.

<Operation method>
Next, a detailed operation will be described with reference to FIG. The power supply voltage VDD of the internal circuit is, for example, 1.5V. Initially, it is in the standby state STANDBY, the address ADD is switched, and the read operation READ starts when the write control signal WE becomes 'L'. Here, a case where “1” (reset (high resistance) state) is read from the memory cell MC00 will be mainly described. In FIG. 2, it is shown by a solid line. When reading “0” (set (low resistance) state), it is indicated by a broken line.

  First, the bit line BL0 is precharged by setting the control signal BC to ‘L’. The word line WL0 is activated from 'L' to 'H', and current is drawn from the bit line BL0 by the memory cell MC00. Since the value of a high resistance of 100 kΩ (corresponding to data “1”) is written in the memory cell MC00, for example, the potential of the bit line BL0 hardly changes and becomes 1.5 V, for example. If a value of a low resistance of 10 kΩ (corresponding to data “0”) is written in the memory cell MC00, for example, the bit line BL0 is lowered to about 0.5V. This voltage is compared with the reference voltage REF by the sense amplifier circuit SA by setting the sense amplifier activation signal SE to ‘H’, and this potential difference is amplified. The amplified data is output to Do and the reading ends. When a high resistance value is written, “1” is output to Do, and when a low resistance value is written, “0” is output to Do.

  In this embodiment, after reading, the read data is rewritten. This eliminates the problem of data destruction during reading.

  In this embodiment, “1” is read, and the read data is sent to the write data selection circuit WDC to output a signal CW. As a result, the power supply line VWL and the signal BC are controlled by the write control circuit WIC. When ‘1’ is read, the bit line remains at the power supply voltage 1.5V and the word voltage remains at the power supply voltage 1.5V.

  The element has a high resistance before reading, but when data is destroyed by reading and the element has a low resistance, a reset current Ireset flows through 200 uA. Even if the resistance of the element is not reduced by reading, the element is reduced in resistance by the reset current Ireset, and a current of 200 uA continues to flow. By continuing this state from 5 nanoseconds to several tens of nanoseconds, the device enters a molten state. Thereafter, the current flowing in the element is rapidly lowered and rapidly cooled, whereby the memory element R00 becomes amorphous and becomes high resistance (corresponding to data “1”).

  The unselected bit line BL is connected to the ground potential.

  If “0” is read, the memory element R is in the set state, so that the resistance value does not change even when the read current Iread is passed during reading, and it is not necessary to write back the data. However, in this embodiment, in order to simplify the control, the set is written even when “0” is read. In this case, after reading, the bit line is set to the power supply voltage 1.5V, the word voltage is set to 1.0V, and the resistance of the element is reduced, so that a current of 100 uA continues to flow. This state is continued for about 100 nanoseconds and the writing operation is finished.

When the writing is completed, the word line WL0 changes from “H” to “L”, and the setting operation ends.
In the write operation WRITE, after reading data, the write data selection circuit WDC selects the input data Di from the outside, and writes the data by controlling the power supply voltage VWL based on this data.

The waveform diagram indicated by the solid line in this embodiment writes “0” after reading “1”, and the waveform diagram indicated by the broken line writes “1” after reading “0”.
Reading in the write operation WRITE is not necessary, but the same control as the read operation READ is performed to simplify the control.

Example 2
Here, a method of applying a current pulse before rewriting or writing will be described. With this method, rewriting can be performed infinitely. In this embodiment, the set current source Iset and the read current source Iread are shared, and the read control circuit RA is deleted to reduce the area.

<Memory module configuration>
Only differences from the first embodiment will be described with reference to FIG. The source line SL is not connected to the ground potential, is formed in parallel with the bit line BL, and is connected to the common source line CSL by the bit line selection circuit BLS. For example, the source line SL0 is connected to the common source line CSL by the source line switch SSW0. The bit line BL is also connected to the common bit line CBL by the bit line selection circuit BLS. For example, the bit line BL0 is connected to the common bit line CBL by the bit line switch BSW0.
The bit line switch BSW is controlled by a bit line selection signal BS, and the source line switch SSW is controlled by a source line selection signal SS.

  The common bit line CBL and the common source line CSL are input to the crossbar switch CBSW and connected to the common line CL or the ground potential.

<Operation method>
Only differences from the first embodiment will be described with reference to FIG. The process is the same as in the first embodiment until data is read by the read operation READ. After reading the data, first, a current pulse is input.

  For example, when “1” is read, the set current selection signal SIS is changed from “L” to “H”, thereby causing the set current Iset to flow through the bit line BL0. When ‘0’ is read, the reset current selection signal RIS is changed from ‘L’ to ‘H’, thereby causing the reset current Ireset to flow through the bit line BL <b> 0. Thereafter, the read value is rewritten in the reverse current direction. When '1' is read, the bit line BL0 is connected to the ground potential, the set current selection signal SIS is changed from 'H' to 'L', and the reset current selection signal RIS is changed from 'L' to 'H'. As a result, a reset current Ireset is caused to flow through the source line SL0, and “1” is written. When '0' is read, the bit line BL0 is connected to the ground potential, the reset current selection signal RIS is changed from 'H' to 'L', and the set current selection signal SIS is changed from 'L' to 'H'. As a result, a set current Iset is caused to flow through the source line SL0 and '0' is written.

  Similarly, in the write operation, after reading, a current pulse is input, and then write data (Di value) is written by flowing a current in the reverse direction.

  By applying a current pulse in the reverse direction before writing as described above, rewriting can be performed infinitely, and even if a method of rewriting at the time of reading is performed, there is no problem because there is no limit on the number of writing. This principle will be described by taking chalcogenide Ge2Sb2Te5 as an example of the material of the memory element.

  FIG. 10 shows a cross-sectional view of the chalcogenide when the writing operation has never been performed. An upper electrode 103 is formed on the chalcogenide film 102 having a uniform composition, and a plug electrode 154 is formed below. The upper electrode 103 is connected to the bit line BL, and the plug electrode 154 is connected to the source line SL via a transistor. FIG. 11 (a) is a cross-sectional view when “1” is written once. The chalcogenide film 102 is amorphized 111 in a semicircular shape only at the upper part of the plug electrode 154, and the other regions remain in the crystalline state 110.

  When writing is repeated, an electric field is applied in a state where the chalcogenide is at a high temperature. Therefore, ion conduction occurs due to the difference in electronegativity of the elements constituting the chalcogenide, resulting in a compositional bias. For example, in the case of Ge2Sb2Te5, Ge (Pauling electronegativity 1.8) and Sb (1.9) have lower electronegativity than Te (2.1) and move in the current direction because they are relatively positive elements. . On the other hand, Te moves in the opposite direction to the current because it is a relatively negative element.

  In the conventional method, since current always flows from the bit line BL to the source line SL and writing is performed, the chalcogenide on the bit line side of the phase change element R has a high Te composition ratio, and the chalcogenide on the transistor side has Ge, Sb The composition ratio becomes higher. FIG. 12 shows the composition of the chalcogenide after being rewritten many times. Near the upper electrode is Te1.8Sb1.8Te5.4 (132) with an increased Te composition ratio, and near the plug electrode is Ge2.2Sb2.2Te4.6 (133) with an increased composition ratio of Ge and Sb. .

  The crystallization rate depends on the chalcogenide composition. The portion 133 where the crystallization speed is increased due to the segregation of the material composition does not become amorphous even when a reset pulse is applied, and remains as a crystal (143 in FIG. 11 (b)), and normal writing is performed. Can not be. In other words, if writing is repeated by the conventional writing method, writing to the element becomes impossible.

  In this embodiment, the current direction is reversed during writing. For this reason, even if the composition is biased by writing, the composition bias is eliminated by applying a pulse with the current direction reversed, and the composition returns to the original state. As a result, segregation of the chalcogenide composition accompanying ion conduction can be prevented, the number of writable times can be increased, and infinite rewriting is possible.

  FIG. 13 shows a plan view of the memory array. The word line WL is formed of a polysilicon layer (PS), the source line SL is formed of a first wiring layer M1, and the bit line BL is formed of a second wiring layer M2. The bit line BL and the source line SL are formed in parallel.

Example 3
FIG. 14 shows an example in which a multi-port memory array is configured using this method. Each bit line is connected to two selection switches SW. For example, BL0 is connected to the read / write circuit RWC0 by the switch SW00, and is connected to RWC1 via SW10. With such a configuration, the read operation and the write operation can be processed in parallel. In addition, a test can be performed on the data read during the write operation using this method, and the data can be used effectively.

For example, when processing a read operation and a write operation in parallel, BL0 is connected to RWC0 by SW00 and a read operation is performed, and simultaneously, BL1 is connected to RWC1 by a switch SW11 and a write operation is performed.

2 is a circuit diagram of a memory module according to Embodiment 1. FIG. FIG. 2 is an operation waveform diagram of the memory module shown in FIG. It is a figure which shows the relationship between the frequency | count of reading, and read-out electric current. It is a figure which shows the effect of a word line boost. It is a top view of a memory array. 2 is a circuit diagram of a memory module according to Embodiment 1. FIG. FIG. 2 is an operation waveform diagram of the memory module shown in FIG. 3 is a circuit diagram of a memory module according to Embodiment 2. FIG. FIG. 6 is an operation waveform diagram of the memory module shown in FIG. It is a figure which shows the cross-sectional structure of an element. It is a figure which shows the phase state of Ge-Sb-Te. It is a figure which shows the composition of Ge-Sb-Te after many writing by the conventional system. It is a top view of a memory array. 6 is a circuit diagram of a memory module according to Embodiment 3. FIG.

Explanation of symbols

  102 ... chalcogenide film with uniform composition, 103 ... upper electrode, 110, 142, 143 ... crystalline state, 111, 141 ... amorphous state, 132 ... chalcogenide film (composition ratio: Ge1.8Sb1.8Te5.4), 133 ... chalcogenide Film (composition ratio: Ge2.2Sb2.2Te4.6), 154 ... plug electrode, ADD ... address, ARRAY ... memory array, BL ... bit line, BLS ... bit line selection circuit, BS ... bit line selection signal, BSW ... bit Line switch, CBL ... Common bit line, CBSW ... Crossbar switch, CL ... Common line, CNT ... Contact, CSL ... Common source line, Di ... Input data, Do ... Output data, Icell ... Memory cell current, Iread ... Read current (Source), Ireset ... reset current (source), Iset ... set current (source), IW ... write current, L ... diffusion layer, M1 ... second wiring layer, M2 ... first wiring layer, MC ... memory cell , MN ... N-channel MOS transistor, MP ... P-channel MOS transistor, NG ... Node, PS ... polysilicon layer, R ... memory element, RA ... read control circuit, READ ... read operation, REF ... reference voltage, RIS ... reset current selection signal, RSW ... switch, RWC ... read / write circuit, SA ... sense Amplifier, SE ... Sense amplifier activation signal, SIS ... Set current selection signal, SL ... Source line, SS ... Source line selection signal, SSW ... Source line switch, STANDBY ... Standby state, SW ... Switch, VDD ... Power supply potential, VIA ... via, WA ... write amplifier, WDC ... write data selection circuit, WE ... write control signal, WIC ... write current selection circuit, WL ... word line, WRITE ... write operation, WD_ARY ... word driver array, ADEC ... X system address decoder , VWL: Power line, WIC: Write control circuit.

Claims (7)

Multiple word lines,
A plurality of bit lines intersecting the plurality of word lines;
A plurality of memory cells arranged at intersections of the plurality of word lines and the plurality of bit lines;
It has a read / write circuit,
The plurality of memory cells include phase change elements;
Rewrite information read from the plurality of memory cells during a read operation ,
A semiconductor device , wherein a pulse current having a polarity opposite to that of the rewriting pulse current is applied between the reading and the rewriting .   2. The semiconductor device according to claim 1, wherein at the time of a write operation, the read information is replaced with external write information, and the replaced information is written into the memory cell.   3. The semiconductor device according to claim 1, wherein the memory cell is driven by the same circuit in the reading, the rewriting, and the writing.   3. The semiconductor device according to claim 2, wherein a pulse current having a polarity opposite to that of the write pulse current is applied between the read and the write. Multiple word lines,
A plurality of bit lines intersecting the plurality of word lines;
A plurality of memory cells arranged at intersections of the plurality of word lines and the plurality of bit lines;
Each of the plurality of memory cells includes a phase change element;
The high level of the word line is higher than the power supply voltage for driving the bit line, and is a voltage that is 5 MV / cm or less with respect to the gate oxide film ,
Rewrite information read from the plurality of memory cells during a read operation,
A semiconductor device , wherein a pulse current having a polarity opposite to that of the rewriting pulse current is applied between the reading and the rewriting . Multiple word lines,
A plurality of bit lines intersecting the plurality of word lines;
A plurality of memory cells arranged at intersections of the plurality of word lines and the plurality of bit lines;
Each of the plurality of memory cells includes a phase change element;
A low level potential of the word line is made lower than a ground potential ;
Rewrite information read from the plurality of memory cells during a read operation,
A semiconductor device , wherein a pulse current having a polarity opposite to that of the rewriting pulse current is applied between the reading and the rewriting . Multiple word lines,
A plurality of bit lines intersecting the plurality of word lines;
A plurality of memory cells arranged at intersections of the plurality of word lines and the plurality of bit lines, and a plurality of write / read circuits;
Each of the plurality of memory cells includes a phase change element;
The plurality of memory cells can be simultaneously connected to the corresponding plurality of write / read circuits ,
Rewrite information read from the plurality of memory cells during a read operation,
A semiconductor device , wherein a pulse current having a polarity opposite to that of the rewriting pulse current is applied between the reading and the rewriting .