TW200527656A - Semiconductor device - Google Patents

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Publication number
TW200527656A
TW200527656A TW93137644A TW93137644A TW200527656A TW 200527656 A TW200527656 A TW 200527656A TW 93137644 A TW93137644 A TW 93137644A TW 93137644 A TW93137644 A TW 93137644A TW 200527656 A TW200527656 A TW 200527656A
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Taiwan
Prior art keywords
phase change
sense amplifier
memory
semiconductor device
voltage
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TW93137644A
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Chinese (zh)
Inventor
Norikatsu Takaura
Riichiro Takemura
Motoyasu Terao
Hideyuki Matsuoka
Kenzo Kurotsuchi
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Renesas Tech Corp
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Publication of TW200527656A publication Critical patent/TW200527656A/en

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    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C13/00Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021Auxiliary circuits
    • G11C13/004Reading or sensing circuits or methods
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5678Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using amorphous/crystalline phase transition storage elements
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C13/00Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0004Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C13/00Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021Auxiliary circuits
    • G11C13/004Reading or sensing circuits or methods
    • G11C2013/0047Read destroying or disturbing the data

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  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

To improve recording/holding reliability in the case of operating a phase change memory at a low voltage and at a high temperature, or leaving it as it is. A high-speed operation is performed with a read voltage above set and reset voltages, and after a read operation, the status prior to the read operation is rewritten. That is, a so-called destructive read is performed. Alternatively, a so-called "OR-cell", in which a plurality of cells are used to record 1-bit information, is used to improve the reliability in the case of operating a phase change memory at a high temperature or leaving it as it is. There are used circuit arrangement and operation scheme required by the phase change memory using the destructive read and OR-cell.

Description

200527656 (1) 九、發明說明 【發明所屬之技術領域】 本發明係關於半導體裝置,特別是關於有效使用於使 用·相變化材料所形成之高密度集成記憶體電路,或者記憶 體電路與邏輯電路設置在同一半導體基板之邏輯混載型記 憶體,或者具有類比電路之半導體積體電路裝置有效之技 . 術。 【先前技術】 使用由相變化材料所成之阻抗元件之記憶體(相變化 記憶體)係使用電氣脈衝,使相變化材料在非晶質狀態與 結晶狀態間可逆地做相轉換,將非晶質狀態(重置)與結 晶狀態(設定)之阻抗値的不同當成資訊予以記錄之非揮 發性記憶體。即相變化材料之非晶質狀態的高阻抗値及結 晶狀態的低阻抗値分別不必要爲完全之非晶質狀態及完全 之結晶狀態故,可以取用完全之非晶質狀態的高阻抗狀態 Φ 與完全之結晶狀態的低阻抗狀態之中間的任意値。 以下’使用第1 4圖詳細說明相變化記憶體的動作機 _ 構。第1 4圖係實現相變化材料之記錄動作之相變化材料 · 的電流一電壓特性例。如將施加在爲非晶質狀態之相變化 材料的兩端之電壓由零陸續增加,則非晶質狀態之相變化 材料會相變化爲結晶狀態。引起由非晶質狀態往結晶狀態 之相變化的電壓係定義爲設定電壓(Vset )。由非晶質狀 態變化爲結晶狀態之相變化材料的阻抗値係由高阻抗狀態 -5- 200527656 (2) 變化爲低阻抗狀態。 另外,如將施加於爲結晶狀態之相變化材料的兩端之 電壓由零陸續增加,則結晶狀態之相變化材料會相變化爲 非晶質狀態。引起由結晶狀態變化爲非晶質狀態之電壓則 定義爲重置電壓(Vreset )。由結晶狀態變化爲非晶質狀 態之相變化材料的阻抗値係由低阻抗狀態變化爲高阻抗狀 難 〇 相變化記憶體係將結晶狀態之低阻抗値當成π 〇π狀態 ,另外,將非晶質狀態之高阻抗値當成” 1”狀態以記錄資 訊。資訊的讀出係藉由在相變化材料的兩端相加讀出電壓 (Vread )而進行。如第1 4圖所示般,藉由讀出電壓 Vread之施加,產生在具有低阻抗値之結晶狀態的電流係 比產生在具有高阻抗値之非晶質狀態的電流大。 記錄在相變化記憶體之資訊係藉由感測電性連接在相 變化材料之一端的位元線之電壓下降而被讀出。第1 5圖 係模型地顯示電性連接於相變化材料之位元線的電壓下降 圖。位元線在讀出時之起始狀態中,係被設定爲預先充電 位準Vp。在第1 5圖中,位元線之預先充電位準Vp係設 定爲0.3 V。如第1 5圖所示般,電性連接於具有高阻抗値 之非晶質狀態的相變化材料之位元線比起電性連接於具有 低阻抗値之結晶狀態的相變化材料之位元線’係以低速度 做電壓下降。其理由是,蓄積在位元線之電荷流入相變化 材料之速度,以具有高阻抗値之相變化材料比具有低阻抗 値之相變化材料慢的關係。 -6- 200527656 (3) 藉由使用讀出電壓以感測位元線之電壓下降的速度’ 相變化記憶體之狀態及”1"狀態被讀出來。即在本發明 中,雖然設結晶狀態之低阻抗値爲’’0 M狀態’另外’設非 晶質狀態之高阻抗値爲” 1π狀態’但是’也可以設非晶質 狀態之高阻抗値爲"狀態,設結晶狀態之低阻抗値爲” 1 ’’ 狀態。 [專利文獻1]日本專利特願2003 - 1 45 3 05號說明書 [專利文獻2]日本專利特願2003 -08 1 724號說明書 【發明內容】 [發明所欲解決之課題] 在相變化記憶體中,存在有非晶質狀態錯誤相轉換爲 '結晶狀態之所謂的錯誤設定的問題。錯誤設定係在低電壓 動作時之過剩的電能輸入或者高速動作時容易發生。使之 產生錯誤設定的原因是,例如物性値偏差或者電氣特性偏 差或者尺寸偏差。另外,例如相變化材料或者選擇電晶體 或者LSI配線等之特性偏差、動作電壓之偏差、或者電源 電壓之偏差等,也是使之產生錯誤設定的原因。 以下’詳細說明在讀出動作時產生錯誤設定之現象。 如第1 4圖所示般,在習知之方法中,讀出電壓係設定在 設定電壓以下。藉由將讀出電壓設定在設定電壓以下,可 以防止爲非晶質狀態之相變化材料基於讀出動作而被錯誤 口又足爲結晶狀態。 但是’在對相變化記憶體要求低電壓動作之情形,會 200527656 (4) 發生設定電壓與讀出電壓之餘裕變小之問題。例如,在行 動電話、或者移動攜帶資訊終端、或者IC卡等使用在低 消耗電力產品之情形,相變化記憶體被要求低電力動作。 另外,在當成低電壓動作之微電腦混載記憶體使用之情形 ,相變化記憶體也被要求低電壓動作。 在低電壓動作之相變化記憶體中’設定電壓與讀出電 壓的餘裕變小之理由是,相對於設定電壓變小’要使讀出 電壓變小有其困難之故。難於使讀出電壓變小之理由是, 讀出電流與讀出電壓一同地變小,相變化記憶體的動作速 度會降低之故。 利用第1 6圖說明相變化記億體之讀出電壓與讀出電 流之關係。如第16圖所示般,藉由讀出電壓Vreadl所獲 得之結晶狀態的讀出電流爲Iread 1。相對於此’藉由比讀 出電壓 Vread 1小之讀出電壓所獲得之結晶狀態的讀出電 流變成Iread2,比Ireadl小。讀出電流一變小,位元線之 放電速度降低,藉由感測放大器所感測之相變化材料的非 晶質狀態與結晶狀態之速度降低的結果,相變化記憶體的 1力作速度降低。 設定電壓與讀出電壓之餘裕變小之情形’相變化記憶 _的記錄保持可靠性會劣化。例如,相變化記憶體之特性 偏窆大之情形,設定電壓會偏差而變小,有可能比讀出電 職遼小。此結果爲,基於讀出動作,引起相變化材料由非 晶質狀態錯誤設定爲結晶狀態之現象。錯誤設定在如第]4 所示之重置電壓比設定電壓大之情形,及如第1 7圖所 200527656 (5) 示之重置電壓比設定電壓小之情形的兩種情形下’有產生 之可能性。 相變化記憶體爲低電壓動作之情形’讀出電壓與設定 電壓的餘裕變小故,基於少許之相變化材料或者選擇電晶 體之特性偏差,會產生錯誤設定。 另外,在相變化記憶體爲低電壓動作之情形,設定電 壓與重置電壓的餘裕變小故,基於少許之相變化材料或者 選擇電晶體之特性偏差,在重置動作時’會產生錯誤設定 〇 另外,基於累積讀出而使重置狀態的阻抗値改變之情 形,能量輸入隨之改變故,會產生錯誤設定。 另外,在使相變化記憶體大容量化之情形,基於配線 製程等之少許之產品率不良,會產生掉落位元之錯誤設定 〇 另外,爲了高速讀出相變化記憶體’在設讀出電壓大 之情形,讀出電壓與設定電壓的餘裕變小故,產生錯誤設 定。 另外,相變化記憶體會有結晶狀態誤爲非晶質狀態而 做相轉換之所謂的錯誤重置之問題。在相變化記憶體被要 求低電壓動作之情形,重置電壓與讀出電壓的餘裕也變小 。因此,在相變化記憶體之特性偏差大之情形,重置電壓 產生偏差而變小,會有比讀出電壓小之可能性。此結果爲 ,基於讀出動作,引起相變化材料由結晶狀態錯誤重置爲 非晶質狀態之現象。 冬 200527656 (6) 錯無重置在如桌1 4圖所不之重置電壓比設定電壓大 之情形,以及如第1 7圖所示之重置電壓比設定電壓小之 兩種情形下,存在有發生之可能性。 在相變化記憶體爲低電壓動作之情形,讀出電壓與重 置電壓的餘裕變小故,基於少許之相變化材料或選擇電晶 體之特性偏差,會產生錯誤重置。 另外,在相變化記憶體爲低電壓動作之情形,設定電 壓與重置電壓的餘裕變小故,基於少許之相變化材料或者 選擇電晶體之特性偏差,在設定動作時,會產生錯誤重置 〇 另外,爲了高速讀出相變化記憶體,在設讀出電壓大 之情形,讀出電壓與重置電壓的餘裕變小故,在讀出時, 會產生錯誤重置。 另外,相變化材料之非晶質狀態係準穩狀態故,相變 化記憶體之錯誤設定在高環境溫度或者高接合溫度動作或 被放置之情形也會產生。基於高溫度長時間放置所產生之 錯誤設定,在DRAM (動態隨機存取記憶體)等之大容量 記憶體可見到,以所謂之「掉落位元現象」而被觀測到,200527656 (1) IX. Description of the invention [Technical field to which the invention belongs] The present invention relates to semiconductor devices, and in particular, to high-density integrated memory circuits formed by use of phase change materials, or memory circuits and logic circuits. An effective technique for logic-mixed memory or semiconductor integrated circuit devices with analog circuits installed on the same semiconductor substrate. [Prior technology] The memory (phase change memory) using an impedance element made of a phase change material uses electrical pulses to make the phase change material reversibly phase-convert between the amorphous state and the crystalline state to change the amorphous state. The difference in impedance between the qualitative state (reset) and the crystalline state (set) is treated as information for nonvolatile memory. That is, the high impedance of the amorphous phase of the phase change material and the low impedance of the crystalline phase, respectively, do not need to be completely amorphous and completely crystalline. Therefore, a high impedance state of the completely amorphous state can be used. Arbitrary 値 between Φ and the low-impedance state of the perfect crystalline state. Hereinafter, the operation mechanism of the phase change memory will be described in detail using FIG. 14. Fig. 14 is an example of the current-voltage characteristics of a phase-change material that realizes the recording operation of the phase-change material. If the voltage applied across the phase change material in an amorphous state is gradually increased from zero, the phase change material in an amorphous state will phase change to a crystalline state. The voltage that causes a phase change from an amorphous state to a crystalline state is defined as a set voltage (Vset). (2) The impedance of a phase change material that changes from an amorphous state to a crystalline state changes from a high-impedance state to a low-impedance state. In addition, if the voltage applied to both ends of the phase change material in a crystalline state is gradually increased from zero, the phase change material in a crystalline state will phase change to an amorphous state. The voltage that causes the crystalline state to change to the amorphous state is defined as the reset voltage (Vreset). The phase resistance of a phase-change material that changes from a crystalline state to an amorphous state is difficult to change from a low-resistance state to a high-resistance state. The phase-change memory system treats the low-resistance state of the crystalline state as a π 〇π state. The high impedance of the qualitative state is regarded as a "1" state to record information. Information is read by adding a read voltage (Vread) across the phase change material. As shown in FIG. 14, by applying the read voltage Vread, a current generated in a crystalline state having a low resistance 値 is larger than a current generated in an amorphous state having a high resistance 値. The information recorded in the phase change memory is read by sensing the voltage drop of the bit line electrically connected to one end of the phase change material. Fig. 15 is a model diagram showing a voltage drop of a bit line electrically connected to a phase change material. In the initial state of the bit line at the time of reading, the bit line is set to the precharge level Vp. In Fig. 15, the precharge level Vp of the bit line is set to 0.3 V. As shown in FIG. 15, the bit lines electrically connected to the phase-change material in the amorphous state with high impedance 値 are more electrically connected to the bit lines of the phase-change material in the crystalline state with low resistance 値The line 'does voltage drop at low speed. The reason is that the speed at which the charge accumulated in the bit line flows into the phase-change material is that the phase-change material having a high resistance 値 is slower than the phase-change material having a low resistance 値. -6- 200527656 (3) The state of the phase change memory and the "1" state are read out by using the read voltage to sense the speed of the voltage drop of the bit line. That is, in the present invention, although the crystal state Low impedance: "0 M state" In addition, "high impedance in the amorphous state" is "1π state" but "You can also set high impedance in the amorphous state" to "state" and set low impedance in the crystalline state The state is "1". [Patent Document 1] Japanese Patent Application No. 2003-1 45 3 05 [Patent Literature 2] Japanese Patent Application No. 2003 -08 1 724 [Inventive Content] [Inventive Solution [Problem] In the phase change memory, there is a problem of a so-called erroneous setting in which an erroneous phase is changed from an amorphous state to a crystalline state. The erroneous setting is prone to occur when excessive power is input during low-voltage operation or during high-speed operation. .The reason for causing the wrong setting is, for example, physical property deviation or electrical characteristics deviation or dimensional deviation. In addition, for example, phase change materials or selection of transistor or LSI wiring, etc. Variations in operating voltage or power supply voltage can also cause erroneous settings. The following 'describes in detail the phenomenon of erroneous settings during read operation. As shown in Figure 14 in the conventional method The read voltage is set below the set voltage. By setting the read voltage below the set voltage, it is possible to prevent the phase change material in an amorphous state from being mistakenly changed to a crystalline state based on the read operation. But ' When a low-voltage operation is required for a phase-change memory, 200527656 (4) a problem occurs in which the margin between the set voltage and the readout voltage becomes small. For example, it is used in mobile phones, mobile information terminals, or IC cards. In the case of low power consumption products, phase change memory is required to operate at low power. In addition, in the case of microcomputer mixed memory used as low voltage operation, phase change memory is also required to operate at low voltage. The reason why the margin of the set voltage and the readout voltage in the change memory becomes smaller is to make the reading smaller than the set voltage. It is difficult to make the output voltage smaller. The reason why it is difficult to make the read voltage smaller is that the read current becomes smaller together with the read voltage, and the operating speed of the phase change memory decreases. Use Figure 16 The relationship between the readout voltage and the readout current of the phase change memory is shown. As shown in Figure 16, the readout current in the crystalline state obtained by the readout voltage Vreadl is Iread 1. In contrast, the ratio of The crystalline state read current obtained by a small read voltage Vread 1 becomes Iread2, which is smaller than Ireadl. As the read current decreases, the discharge speed of the bit line decreases, and the phase sensed by the sense amplifier As a result of the decrease in the speed of the amorphous state and the crystalline state of the material, the speed of the phase change memory decreases. In the case where the margin between the set voltage and the readout voltage becomes small, the recording retention reliability of the phase change memory _ is degraded. For example, if the characteristics of the phase change memory are too large, the set voltage will be smaller and smaller than the readout voltage. This result is a phenomenon in which the phase change material is erroneously set from the amorphous state to the crystalline state due to the read operation. Incorrect setting occurs in two cases: the reset voltage shown in Figure 4 is larger than the set voltage, and the reset voltage is smaller than the set voltage as shown in 200517656 (5) in Figure 17. Possibility. In the case where the phase change memory operates at a low voltage ', the margin between the read voltage and the set voltage becomes small. Therefore, a small amount of phase change material or a characteristic deviation in the selection of the transistor may cause incorrect setting. In addition, in the case where the phase change memory operates at low voltage, the margin between the set voltage and the reset voltage becomes smaller. Therefore, based on a small amount of phase change material or the characteristic deviation of the transistor, an incorrect setting will occur during the reset operation. 〇 In addition, if the impedance 重置 of the reset state is changed based on the accumulated readout, the energy input will be changed accordingly, and an incorrect setting may occur. In addition, in the case of increasing the capacity of the phase change memory, a small product failure due to the wiring process and the like may cause incorrect setting of dropped bits. In addition, in order to read out the phase change memory at high speed, When the voltage is large, the margin between the read voltage and the set voltage becomes small, and an incorrect setting occurs. In addition, the phase change memory has a problem of a so-called erroneous reset in which a crystalline state is erroneously changed to an amorphous state and a phase change is performed. In the case where the phase change memory is required to operate at a low voltage, the margin of the reset voltage and the read voltage also becomes smaller. Therefore, when the characteristic variation of the phase change memory is large, there is a possibility that the reset voltage becomes smaller and becomes smaller than the read voltage. This result is a phenomenon in which the phase change material is erroneously reset from the crystalline state to the amorphous state due to the read operation. Winter 200527656 (6) There are two cases where the reset voltage is greater than the set voltage as shown in Table 14 and the two cases where the reset voltage is lower than the set voltage as shown in Figure 17 There is a possibility of it happening. In the case where the phase change memory operates at a low voltage, the margin between the read voltage and the reset voltage becomes smaller. Therefore, a small amount of phase change material or the characteristic deviation of the selected transistor will cause an erroneous reset. In addition, when the phase change memory operates at a low voltage, the margin between the set voltage and the reset voltage becomes smaller. Therefore, based on a small amount of phase change material or the characteristic deviation of the transistor, an incorrect reset will occur during the set operation. 〇 In addition, in order to read the phase-change memory at high speed, when the read voltage is set to be large, the margin between the read voltage and the reset voltage becomes small. Therefore, an erroneous reset may occur during reading. In addition, since the amorphous state of the phase change material is a quasi-stable state, the erroneous setting of the phase change memory may be operated or placed at a high ambient temperature or a high junction temperature. Based on erroneous settings caused by high temperature and long-term storage, it can be seen in large-capacity memories such as DRAM (Dynamic Random Access Memory), and it is observed with the so-called "drop bit phenomenon",

Jt匕結果爲,高集成度記憶體電路及邏輯混載記憶體所使用 之相變化記憶體的長時間保持可靠性會有劣化之問題。相 變化記憶體而被要求高溫動作之產品例可舉汽車引擎控制 用混載微電腦。動作及2 0年放置溫度要求係例如爲接合 溫度在攝氏1 2 5度以上或者攝氏1 4 5度以上。 本發明之目的在於提供:特別是使用相變化材料之例 -10- 200527656 (7) 如高密度集成記憶體電路、及記憶體電路與邏輯電路設置 在同一半導體基板之邏輯混載型記憶體、及具有類比電路 之半導體積體電路裝置中,可以提升使用要求有長時間記 錄保持可靠性之相變化材料的記憶體單元元件之可靠性的 技術。 本發明之其他目的在於謀求半導體積體電路裝置的低 電壓動作。另外’本發明之其他目的在於謀求半導體積體 電路裝置的高溫度動作化。另外,本發明之其他目的在於 謀求半導體積體電路裝置之高溫度放置的長時間化。另外 ,本發明之其他目的在於謀求半導體積體電路裝置的高集 成化。另外,本發明之其他的目的在於謀求半導體積體電 路裝置的大容量化。另外,本發明之其他的目的在於謀求 半導體積體電路裝置的高速動作化。 由本說明書之記載及所附圖面,本發明之前述及其他 自的與新的特徵理應可以變得淸楚。 [解決課題用手段] 如簡單說明在本申請案所揭示發明中之代表性者的槪 荽,則如下述:在讀出動作中,於位元線施加設定所必要 之電壓,讀出資料,使全部的單元低阻抗化,關於高阻抗 萆元,進行再寫入動作。其結果爲,可使用破壞讀出法以 防止在高溫動作時所產生之錯誤設定及錯誤重置。 另外,藉由位元線施加高電壓,分別對高阻抗單元及 低阻抗單元進行再寫入動作。其結果爲,本發明可使用破 -11- 200527656 (8) 壞讀出法以防止基於相變化材料或者選擇電晶體 配線等之特性偏差,或者電源電壓的之偏差所產 設定及錯誤重置。 另外,本發明係利用"或”單元,即二個以上 的記憶體單元以進行掉落位元救濟以保持〗位元 本發明之結果爲,可以防止由於高溫長時間放置 元所產生之錯誤設定,得以提升相變化記憶體之 錄保持可靠性。 [發明之效果] 如簡單說明由本申請案所揭示發明中之代表性 得之效果,則如下述:特別是使用相變化材料之例 度集成記憶體電路,及記憶體電路與邏輯電路設置 半導體基板之邏輯混載型記憶體,及具有類比電路 體積體電路裝置中,可以提升要求長時間記錄保持 之使用相變化材料的記憶體單元元件之可靠性。 【實施方式】 <實施例1 > 第3圖係顯示本發明之相變化記億體單元之電 第3圖之記憶體單元部份係由:下部電極dwc、及 材料P C R、及上部電極u p c、及源極線δ L、及位另 、及例如由MISFET所成之選擇用電晶體Μτ'及 WL所構成。 者LSI 之錯誤 複數個 資訊。 掉落位 時間記 者所獲 如高密 在同一 之半導 可靠性 路圖。 相變化 :線B L 字元線 -12 - 200527656 (9) 第1 8圖係顯示相變化記憶體單元之剖面圖之例子。 在本記憶體單元中,相變化材料P C R係由上部電極u p c及 下部電極插塞d wc及層間膜IL所構成。相變化材料P C R 係與上部電極υ p c及下部電極插塞d w c電性連接。上部電 極up c係與位元線B L或者源極線S L電性連接。下部電極 插塞dwc例如與由MISFET所橙汁選擇用電晶體MT的源 極、汲極之一端電性連接。選擇電晶體之源極、汲極之另 一端係與源極線S L或者位元線B L中之未與上部電極連 接之配線電性連接。即記憶體單元之電路圖係變成如第3 (a )圖或者第3 ( b )圖般。另外,記億體單元構造之加 工係使用周知的方法進行。另外,與此種記憶體單元構造 有關聯者,係例如揭示在專利文獻1。 低電壓動作之相變化記憶體所使用之相變化材料P C R ’例如有G e - S b - T e系相變化材料、或者z η - T e系相變化 材料、或者於Zn-Te系相變化材料加上添加元素之Zn-X-Te系相變化材料。添加元素X例如可舉Sb。與Zn-X-ITe 系相變化材料有關聯者係例如揭示在專利文獻2。 下部電極插塞d w c所使用之材料例如可舉鎢。鎢由於 與相變化材料之界面特性良好故,爲適合本發明之目的之 —的低電壓且高速動作之材料。第19圖係比較Ge2Sb2Te5 及錫及氮化欽及矽之結晶晶格常數。如第1 9圖所示般, 守辱知G^SbJe5之結晶晶格常數與鎢之結晶晶格常數幾乎 相同。此結果爲’下部電極使用鎢之相變化記憶體的相變 化所需要之電流變小。第2 〇圖矽顯示下部電極使用鎢與 -13- 200527656 (10) 氮化欽之情形的G e 2 S b 2 T e 5相變化材料由結晶狀態相變化 爲非晶質狀態所需要之重置電流。如第2 0圖所示般,下 部電極使用鎢之情形的重置電流比使用氮化鈦之情形的重 置電流小。此結果爲,藉由下部電極材料使用鎢,相變化 所需要之電流變小的結果,相變化記憶體之低電壓動作也 同時成爲可能。但是,基於相變化記憶體於低電壓動作, 存在有讀出電壓及設定電壓及重置電壓之差的餘裕變小之 問題。 另外,相變化記憶體於低電壓動作之例子,可舉相變 化材料爲薄膜之情形。以下說明藉由使用薄膜之相變化材 料以實現相變化記憶體之理由。例如,相變化材料相變化 爲結晶狀態所需要之每單位體積之電力P,如使用歐姆近 似來求得時,則表示如以下之式1般。 [數1]As a result of Jt Dagger, the long-term reliability of the phase change memory used in the highly integrated memory circuit and logic mixed memory may deteriorate. Examples of products that require high-temperature operation with phase-change memory include hybrid microcomputers for automotive engine control. The operation and 20-year storage temperature requirements are, for example, a joining temperature of 125 ° C or more or 145 ° C or more. An object of the present invention is to provide: in particular, an example of using a phase change material -10- 200527656 (7) such as a high-density integrated memory circuit, and a logic-hybrid type memory in which the memory circuit and the logic circuit are provided on the same semiconductor substrate, and In a semiconductor integrated circuit device having an analog circuit, it is possible to improve the reliability of a memory cell element using a phase change material that requires long-term record-keeping reliability. Another object of the present invention is to achieve a low voltage operation of a semiconductor integrated circuit device. Another object of the present invention is to increase the temperature of a semiconductor integrated circuit device. Another object of the present invention is to increase the temperature of the semiconductor integrated circuit device for a long period of time. Another object of the present invention is to achieve high integration of a semiconductor integrated circuit device. Another object of the present invention is to increase the capacity of a semiconductor integrated circuit device. Another object of the present invention is to achieve high-speed operation of a semiconductor integrated circuit device. From the description of this specification and the attached drawings, the foregoing and other features of the present invention should become clear. [Means for Solving the Problem] If the representative of the representative of the invention disclosed in the present application is briefly described, as follows: In a read operation, a voltage necessary for setting is applied to a bit line to read data, All the cells are made low-impedance, and the re-write operation is performed on the high-impedance cells. As a result, the destruction readout method can be used to prevent erroneous setting and erroneous reset caused by high-temperature operation. In addition, by applying a high voltage to the bit line, rewriting operations are performed on the high-resistance cell and the low-resistance cell, respectively. As a result, the present invention can use the -11-200527656 (8) bad readout method to prevent deviations in characteristics based on phase change materials or selection of transistor wiring, or deviations in power supply voltages, resulting in incorrect resets. In addition, the present invention uses " or " units, that is, two or more memory units to perform drop bit relief to maintain the bit position. The result of the present invention is that errors caused by long-term high temperature placement of elements can be prevented. The setting can improve the reliability of the phase change memory. [Effects of the invention] If the representative effects of the invention disclosed in this application are briefly explained, it is as follows: In particular, the example integration using phase change materials Memory circuits, and logic-mixed memories in which semiconductor circuits are provided with a semiconductor substrate for the memory circuits and logic circuits, and in volume circuit devices with analog circuits, which can improve the reliability of memory cell elements using phase-change materials that require long-term record retention [Embodiment] < Example 1 > Fig. 3 shows the phase change of the present invention, and the memory cell part of Fig. 3 is composed of: the lower electrode dwc, and the material PCR, and The upper electrode upc, the source line δ L, and the potential are composed of, for example, a selection transistor Mτ ′ and WL formed by a MISFET. Several pieces of information are mistaken. The reporter ’s semi-reliable reliability road map obtained by the reporter at the time of the drop is as follows. Phase change: line BL character line -12-200527656 (9) Figure 18 shows the phase change memory cell An example of a cross-sectional view. In this memory unit, the phase change material PCR is composed of the upper electrode upc, the lower electrode plug d wc, and the interlayer film IL. The phase change material PCR is connected to the upper electrode υ pc and the lower electrode. The plug dwc is electrically connected. The upper electrode up c is electrically connected to the bit line BL or the source line SL. The lower electrode plug dwc is electrically connected to, for example, one of the source and the drain of the orange selection transistor MT selected by MISFET. Select the source of the transistor and the other end of the drain to be electrically connected to the wiring of the source line SL or bit line BL that is not connected to the upper electrode. That is, the circuit diagram of the memory cell becomes as shown in Figure 3. (a) or FIG. 3 (b). In addition, the processing of the memory cell structure is performed using a known method. In addition, those related to such a memory cell structure are disclosed in Patent Document 1, for example. Low voltage operation The phase change material PCR used in the phase change memory includes, for example, a G e-S b-T e phase change material, or a z η-T e phase change material, or a Zn-Te phase change material. Zn-X-Te based phase change material with added element. For example, Sb can be added as the added element. Those related to Zn-X-ITe based phase change material are disclosed in Patent Document 2, for example. Used for lower electrode plug dwc Examples of the material include tungsten. Tungsten is a low-voltage and high-speed material suitable for the purpose of the present invention because of its good interface characteristics with phase change materials. Figure 19 compares the crystal lattice constants of Ge2Sb2Te5, tin, cyanide, and silicon. As shown in Fig. 19, the crystal lattice constant of G ^ SbJe5 is almost the same as that of tungsten. As a result, the current required for the phase change of the phase change memory using tungsten as the lower electrode becomes smaller. Figure 2 〇 The silicon shows that the lower electrode uses tungsten and -13- 200527656 (10) G e 2 S b 2 T e 5 phase change in the case of Nitride is required to change the material from crystalline phase to amorphous state. Placing current. As shown in Fig. 20, the reset current in the case where tungsten is used for the lower electrode is smaller than the reset current in the case where titanium nitride is used. As a result, by using tungsten as the lower electrode material, the current required for the phase change becomes smaller, and the low voltage operation of the phase change memory becomes possible at the same time. However, since the phase change memory operates at a low voltage, there is a problem that the margin of the difference between the read voltage, the set voltage, and the reset voltage becomes small. An example of the phase change memory operating at low voltage is the case where the phase change material is a thin film. The reason for using the film phase change material to realize the phase change memory will be described below. For example, if the electric power P per unit volume required for the phase change of the phase change material to be in a crystalline state is obtained using ohmic approximation, it is expressed as shown in Equation 1 below. [Number 1]

ATAT

…(式1) 此處,I s e t係非晶質狀態之相變化材料相變化爲結晶 狀態時所需要之設定電流,R係相變化材料之阻抗値,3 保相變化材料之阻抗率,A係下部電極面積,τ爲相變化 材料之膜厚。求解式】以求得設定電壓Vset時,則變成 以下之式2。 -14 - 200527656 (11) [數2] V - x/pr * τ (式2 ) set 基於式2,知道設定電壓V s e t與相變化材料之膜厚成 正比。其結果爲,藉由使相變化材料之膜厚變薄,知道可 以實現相變化記憶體之低電壓動作。式1及式2係表示相 變化材料由非晶質狀態相變化爲結晶狀態之設定動作。式 1及式2在表示相變化材料由結晶狀態結晶狀態相變化爲 非晶質狀態之重置動作的情形,也可以近似地使用。但是 ,式1及式2係只使用歐姆近似而所求得,在考慮焦耳熱 之產生及擴散之情形,則相變化材料相變化時所需要之電 力變得比以式]及式2所求得之値還大。 另外’在本發明中,係假定源極線與位元線之電位差 的絕對値之最大値在1 · 8 V以下。在此情形,選擇用開關 之電壓降低推測在G . 6 V以上故,施加於相變化材料之電 壓假定成爲1 . 2 V以下。 第2 1圖係顯示相變化材料由結晶狀態相變化爲非晶 質狀悲日寸之重置電壓與相變化材料之膜厚的實驗資料。在 使用G^SbsTe5過成之相變化材料以進行uv動作之情形 膜厚例如需要在 20^m 以下。另外,在使用 1 . 2 V動作之情形,膜厚令… (Equation 1) Here, I set is the set current required when the phase change material in the amorphous state changes to the crystalline state, R is the impedance of the phase change material 値, 3 Impedance of the phase change material, A The area of the lower electrode, τ is the film thickness of the phase change material. Solving formula] When the set voltage Vset is obtained, it becomes Equation 2 below. -14-200527656 (11) [Eq. 2] V-x / pr * τ (Equation 2) set Based on Equation 2, we know that the set voltage V s e t is proportional to the film thickness of the phase change material. As a result, by reducing the film thickness of the phase change material, it is known that the low voltage operation of the phase change memory can be realized. Equations 1 and 2 show the setting operation of the phase change material changing from an amorphous phase to a crystalline phase. Equations 1 and 2 can also be used approximately in the case where the reset operation of the phase change material changes from a crystalline state to a crystalline state to an amorphous state. However, Equation 1 and Equation 2 are obtained using only the ohmic approximation. When considering the generation and diffusion of Joule heat, the power required for the phase change of the phase-change material becomes more than that obtained by Equation] and Equation 2. Dezhi is still big. In addition, in the present invention, it is assumed that the maximum value of the absolute value of the potential difference between the source line and the bit line is 1.8 V or less. In this case, the voltage drop of the selection switch is estimated to be G. 6 V or more. Therefore, the voltage applied to the phase change material is assumed to be 1.2 V or less. Figure 21 shows the experimental data of the reset voltage and phase change material of the phase change material from the crystalline phase to the amorphous phase. When using a G ^ SbsTe5 phase change material for UV operation, the film thickness must be 20 ^ m or less, for example. In addition, when using 1.2 V operation, the film thickness order

ZnnSbuTew相變化材料以進行 如假定需要在6 0 n m以下 有關連之理由是,相變化 ’在前述之膜厚零之下限 由是,在相變化材料相織 。前述膜厚與相變化材料之組成 材料之阻抗率不同之關係。另外 値中,重置電壓不成爲〇v之理 化時所需要之電力也包含焦耳熱 -15- 200527656 (12) 之產生及擴散之貢獻部份故。 相變化記憶體在高溫度動作及高溫度長時間放置所使 用之例子,則有高融點之相變化材料、Z^Te系相變化材 料、或者在Zn-Te系相變化材料加上添加元素之Zn-X-Te 系相變化材料。與Zn-X-Te系相變化材料有關聯者例如揭 示在專利文獻2。 本發明之相變化材料雖舉 G e S b Te系相變化材料,或 者Z η - T e系相變化材料、或者於z η - T e系相變化材料加上 添加元素之Z η - X - T e系相變化材料,但是,也可以適用於 此外之相變化材料。在此情形,可提升相變化元件之資料 保持可靠性之同時,也可以防止在低電壓之動作速度的降 低。另外,動作電壓雖假定爲].2 V之程度,但是,也可 以適用於1 . 8 V之動作。在此情形下,也具有提升動作餘 裕,可改善動作速度之效果。 進而,本發明係期望使用在加工尺寸爲使用〇 . 1 3 m 以下之加工技術之半導體。微細化進步之同時,動作電壓 之降低也向前進展故,動作餘裕之降低變成問題,藉由適 用本發明’可以提升動作餘裕。另外,本發明也可以適用 於單體記憶體及邏輯混載記憶體。藉由適用於這些,可以 補救資料可靠性、記憶體單元不良,得以實現產品率之提 升。另外,特別是在邏輯混載記憶體中,可以提升在高溫 動作之資料可靠性故,可以實現能夠實現在廣溫度範圍之 動作的半導體裝置。 以下,利用圖面詳細說明本發明之實施例。構成實施 - 16- 200527656 (13) 例之各功能方塊之電路元件並無特別限制,係藉由周知之 CMOS (互補型MOS電晶體)等之積體電路技術而形成在 如單晶矽之半導體基板上。圖面中,對p Μ 〇 S電晶體之本 體上付與箭頭之記號,以與Ν Μ Ο S電晶體區別。圖面上, Μ〇S電晶體之基板電位的連接雖無特別明白記載,但是, 只要是MOS電晶體可正常動作之範圍,其連接方法並無 特別限定。另外,在無特別說明之情形,設訊號之低位準 爲’’ 0 ’’,高位準爲’’ 1 ’’。 在本實施例中,於使陣列動作電壓爲低電壓化時,讀 出電壓範圍變窄,可解決動作餘裕降低之問題。在習知之 讀出動作中,係抑制施加電壓爲低電壓,以使高阻抗狀態 或低阻抗狀態之相變化元件不因讀出時之電流而引起相變 化.。其結果爲,讀出電流變小故,讀出訊號量降低,會擔 心動作速度之降低、動作餘裕之降低。相對於此,在本發 明中,於讀出動作時’使感測放大器產生充分之訊號量而 使施加電壓變大之同時’關於基於讀出動作而有引起相變 化之虞的單元,進行再寫入動作’以提升資料可靠性。以 下,顯示本發明之實施例。 在本構造中’讀出動作之位元線預先充電位準係爲設 定狀態之相變化元件不引起相變化’且重置狀態之相變化 元件一定相變化爲設定狀態之電壓之V s e t以上、V r e s e t 以下之構造。第]圖係顯示實現本動作之記憶體單元陣列 MCA與感測放大器方塊 SAB與行解碼器/字元驅動器 RDEC之圖。 -17 - 200527656 (14) 首先,說明記憶體單元陣列MCA。第2圖係顯示記憶 體單元陣列MCA之構造例。記憶體單元MC係設置在字 元線 WL0 ' WL1、WL2、WL3、…及位元線 BL0、BL] ' B L 2、B L 3、…之交點。另外,設置有源極線 S L 0 1、S L 2 3 、…。源極線例如係連接於接地電壓 V S S。各記憶體單元 MC係藉由相變化阻抗PCR與記憶體單元電晶體MT所構 成。第3圖係顯示2種之記憶體單元構造。在(a )中, 相變化阻抗PCR之一端係連接於位元線BL,另一端係連 接在記憶體單元電晶體MT之源極、汲極之一方。記憶體 單兀電晶體之源極、汲極之另一方係連接於源極線,聞極 係連接於字元線。在本構造中,於寫入時,使位元線B L 比源極線S L爲高電位,例如,在.1 .2 V驅動之情形,可取 得大的記憶體單元電晶體MT之驅動力故,比較優異。在 (b )中,係使(a )之相變化阻抗PCR與記憶體單元電晶 體MT之連接關係相反之構造。在本構造中,與源極線SL 相比,係使位元線在低電位驅動之方式,例如,源極線 SL之電位爲1 .2V,位元線BL爲0V驅動之情形,可取得 大之記憶體單元電晶體Μ T的驅動力故,較爲優異。進而 ,在讀出、寫入動作中,即使位元線受到驅動,於非選擇 單元中,不流通充放電記憶體單元電晶體ΜΤ之擴散層的 電流故,可以防止資料破壞。另外,此處,作爲記憶體單 元電晶體雖顯示NMOS電晶體,但是也可以使用PM〇s電 晶體或雙載子電晶體。但是’由高集成化之觀點而言,期 望爲MOS電晶體,與PMOS電晶體相比,以導通狀態之 -18 - 200527656 (15) 通道阻抗小之NMOS電晶體比較合適。在以下中,在作爲 記憶體單元電晶體爲使用NMOS電晶體之情形的電壓關係 來說明動作等。另外,位元線也稱爲資料線。此處,雖然 爲了簡化而未圖示出,但是,因應需要,也可在記憶體單 元陣列MCA設置產生讀出時之參考訊號甩之虛擬單元。 感測放大器方塊SAB係由:位元線選擇器BLSEL與 感測放大器S A與寫入驅動器WD所形成。第4圖係顯示 位元線選擇器BLSEL之構造例。於位元線選擇器BLSET 係配置有從記憶體陣列之位元線BL0、BL1、…而連接於 感測放大器用之選擇開關。這些開關係藉由列選擇訊號訊 號 C0t/b、Clt/b、…所控制。進而,配置有在所期望之期 間,將記憶體陣列側之位元線與感測.放大器側位元線 BLS A預先充電爲所期望之位準之預先充電電晶體。配置 有與位元線選擇器鄰接之感測放大器方塊。感測放大器係 感測感測放大器位元線之訊號而輸出於外部,或者暫時保 持來自外部之資料。第5 ( b )圖係顯示感測放大器之構造 例。在本構造中,係由比較感測放大器位元線B L S A之位 準與參照位準VREF,放大至電源電壓VWE爲止之交叉耦 合放大電路所形成。第5 ( a )圖係顯示寫入驅動器W D之 構造例。寫入驅動器WD係依據來自外部之寫入資料或者 讀出於感測放大器 SA之資料而驅動感測放大器位元線 BLSA。在本實施例中,寫入驅動器WD係只以使記憶體 單元之相變化元件成爲高阻抗狀態用之驅動器所構成。圖 中,於位元線4條B L 0、B L ]、B L 2、B L 3雖連接有]個感 -19- 200527656 (16) 測放大器位元線B L S A與感測放大器S A、寫入驅動器WD ’但是’位元線之數目並無限制。藉由設爲多數,動作之 感測放大器數可以降低故,能夠抑制不需要之消耗電力的 增加。另一方面,如設爲少數,則輸出之位元數變多故, 適合於輸入輸出高速且大量之資料。 接著,說明本陣列構造之讀出動作。 第6圖係讀出動作之時序圖。依據讀出指令,對應所 輸入之位址之列選擇線C0t/b被活化。之後,連接於感測 放大器SA之位元線,圖中爲位元線BL0與感測放大器內 位元線BLSA —同被設定爲位元線預先充電位準 VR。在 本實施例中,預先充電位準VR與記憶體單元MC之源極 線 S L間的電位差係設定爲相變化元件由高阻抗狀態相變 化爲低阻抗狀態所必要之電流得以流通。例如,在圖之例 子中,將源極線SL設定爲0V,將預先充電位準VR設定 爲0.6V之程度。之後,預先充電訊號PRE成爲非選擇狀 態之同時,字元線W L受到選擇。依據此,位元線B L及 感測放大器內位元線BLSA藉由記憶體單元電晶體MT、 相變化元件P C R而放電。此時,在記憶體單元之相變化元 件PCR爲低阻抗狀態時,被急速放電。另一方面,阻抗在 高阻抗狀態時,被慢慢放電。在感測放大器中’出限於位 元線之微小訊號被放大至電源電壓。依據此讀出動作’高 阻抗狀態之相變化元件因讀出電流之發熱’由高阻抗狀態 而相變化爲低阻抗狀態,讀出於感測放大器之單元全部成 爲低阻抗化。在感測放大器中,放大讀出於位元線之訊號 -20- 200527656 (17) ,而輸出於外部故,輸出於1/0。在此之前後,於讀出記 憶體單元之相變化元件爲高阻抗狀態之資料的感測放大器 中,活化寫入驅動器。在被活化之寫入驅動器中,於重置 動作所必要之時間,藉由寫入驅動訊號WRE而對位元線 施加高電壓,將重置動作所必要之電流藉由位元線、記憶 體單元電晶體而流入相變化元件。之後,藉由遮斷電流, 相變化元件被急冷,而相變化爲高阻抗狀態。之後,字元 線WL及列選擇線C0t/b轉爲非選擇位準,讀出週期結束 〇 接著,說明寫入動作。第7圖係寫入動作之時序圖。 依據寫入指令,寫入位址被送至。與讀出動作相同,列選 擇線C 0 t / b被活化,與此同時,進彳7位兀線之預先充電動 作。之後,對應位址之字元線WL被選擇,位元線藉由記 憶體單元電晶體、相變化元件而放電。此時,相變化元件 藉由讀出電流而發熱,由高阻抗狀態而相變化爲低阻抗狀 態。此結果爲,連接在感測放大器之全部的記憶體單元之 相變化元件相變化爲低阻抗狀態。在此動作之間,寫入資 料被轉送於感測放大器。此處,在改寫讀出之資料後,活 化在感測放大器列中只對應保持記憶體單元之相變化元件 的高阻抗狀態之資料的感測放大器之寫入驅動器。之後, 在被活化之寫入驅動器中,於重置動作所必要之時間中, 藉由寫入啓動訊號,對位元線施加高電壓,將重置動作所 必要之電流藉由位元線、記憶體單元電晶體而流於相變化 兀件。之後’藉由遮斷電流,相變化元件被急冷而相變化 - 21 - 200527656 (18) 爲高阻抗狀態。之後,字元線WL及列選擇線C0t/b轉變 爲非選擇位準,讀出週期結束。 在本構造中,選擇字元線而讀出記憶體單元之資料時 ,將記憶體單元之資料全部設定在低阻抗狀態,再寫入高 阻抗狀態。藉此之優點係如下:(1 )讀出時,可設定位 元線預先充電位準在高位準,可使讀出於感測放大器之訊 號量變大故,可實現高速、穩定之讀出動作。(2 )習知 上,需要設定、重置驅動器之寫入驅動器可只以重置驅動 器構成,電路構造可簡單化之同時,可以降低佈置面積及 晶片面積。(3 )藉由於讀出時,再度寫入高阻抗狀態’ 可以降低基於讀出動作時之資料破壞所致之資料可靠性降 低。(4 )相變化元件之記錄保持特性劣化之例如攝氏125 度以上之高速動作及長時間放置變成可能。 <實施例2 > 接著,說明實施例2。另外,實施例2之記憶體單元 之電路及剖面構造係與第3圖及第1 8圖相同,省略其之 說明。 本構造係在讀出時之位元線預先充電位準利用比相變 化元件不引起相變化之電壓Vset或者Vreset高之電壓的 方式。在本動作中,爲了使讀出訊號量變大,雖將位元線 預先充電位準設定爲高位準’但是,基於讀出動作’相變 化元件之相狀態有被破瓌之可能性故,進行設定及重置之 再寫入動作。 •22- 200527656 (19) 第 8圖係顯示本實施例之感測放大器方塊 SAB之構 造。記憶體單元陣列MCA及字元驅動器RDEC係與前述 之實施例相同。感測放大器方塊S AB係由位元線選擇器 BLSEL及設定、重置相變化元件之寫入驅動器WD及放大 、資料保持感測放大器位元線BLSA之感測放大器SA所 成。第9圖係顯示寫入驅動器WD之電路構造。寫入驅動 器WD係依據設定啓動訊號WSE與重置啓動訊號WRE及 感測放大器S A之資料,而藉由感測放大器位元線B L S A 、記憶體單元電晶體而將設定、重置所必要之電流供應給 相變化元件。寫入驅動器之構造與前述之實施例不同,係 配置有將相變化元件進行高阻抗化及低阻抗化用之寫入驅 動器。 接著,說明本陣列構造之讀出動作。 第1 〇圖係讀出動作之時序圖。與前述之實施例相同 ,依據讀出指令,對應所輸入之位址的列選擇線C Ot/b被 活化。之後,連接於感測放大器S A之位元線,圖中爲位 元線B L 0與感測放大器內位元線B L S A —同被設定爲位元 線預先充電位準VR。在本實施例中,預先充電位準VR與 記憶體單元MC之源極線SL間之電位差可以是流通相變 化元件由高阻抗狀態相變化爲低阻抗狀態所必要之電流的 電壓’而且也可以是低阻抗狀態變成高阻抗狀態之電壓。 另外,反之,也可以是高阻抗狀態確實低阻抗化之電壓附 近的電壓。在此情形,不一定要引起相變化元件不一定要 由高阻抗狀態相變化爲低阻抗狀態。例如,在圖之例子中 -23- 200527656 (20) ,預先充電訊號PRE成爲非選擇狀態之同時’字元線WL 受到選擇。依據此’位元線 BL及感測放大器內位元線 BLSA藉由記憶體單元電晶體MT、相變化阻抗PCR而放 電。此時,記憶體單元之相變化阻抗PCR爲低阻抗狀態時 ,被急速放電。另一方面’在阻抗爲高阻抗狀態時’慢馒 被放電。在感測放大器中’將出現於位元線之微小訊號放 大至電源電壓。依據此讀出動作’連接於感測放大器之記 憶體單元的相變化元件之阻抗値變成不一定要保持讀出前 之阻抗狀態。即藉由讀出動作’記憶資料被破壞。此間, 在感測放大器中,放大讀出於位元線之訊號,輸出於外部 。在此之前後,於讀出記憶體單元之相變化元件爲高阻抗 狀態之資料的感測放大器中,活.化寫入驅動器。在被活化 之寫入驅動器中,於重置動作所必要之時間,藉由寫入驅 動訊號而對位元線施加高電壓,將重置動作所必要之電流 藉由位元線、記憶體單兀電晶體而流入相變化元件。之後 ,藉由遮斷電流,相變化元件被急冷,而相變化爲高阻抗 狀態。之後,列選擇線COt/b、字元線WL轉變爲非選擇 位準,讀出週期結束。 接著,說明寫入動作。第1 1圖係寫入動作之時序圖 。依據寫入指令,寫入位址被送至。與讀出動作相同,列 選擇線c 01 / b被活化,與此同時,進行位元線之預先充電 動作。之後,對應位址之字元線WL被選擇,位元線藉由 記憶體單元電晶體、相變化元件而放電。此時,相變化元 件藉由讀出電流而發熱,由高阻抗狀態而相變化爲低阻抗 -24- 200527656 (21) 狀態’且由低阻抗狀態引起相變化爲高阻抗狀態,讀出前 之狀態被破壞。在此動作之間,寫入資料被送往感測放大 器。此處,在改寫讀出之資料後,在感測放大器列中保持 對應記憶體單元之相變化元件的高阻抗狀態之資料的感測 放大器中,選擇寫入驅動器內之重置驅動器。另一方面, 在感測放大器列中保持對應記憶體單元之相變化元件的低 阻抗狀態之資料的感測放大器中,選擇寫入驅動器內之設 定驅動器。之後,在被活化之寫入驅動器中,於重置動作 所必要之時間中,藉由重置及設定寫入啓動訊號,對位元 線施加高電壓,將重置及設定動作所必要之電流藉由位元 線、記憶體單元電晶體而流於相變化元件。之後,藉由遮 斷電流,相變化元件被急冷而相變化爲高阻抗狀態或者相 變化爲低阻抗狀態。之後,列選擇線C0t/b、字元線WL 轉變爲非選擇位準,寫入週期結束。 在本構造中,於選擇字元線而讀出記憶體單元之資料 時,藉由將記憶體單元之資料全部設定爲低阻抗狀態,具 有以下之優點:(1 )讀出時,可將位元線預先充電位準 設定爲高位準,可使讀出於感測放大器之訊號量變大故, 可以實現高速、穩定之讀出動作。(2 )預先充電位準之 設定範圍具有自由度,電源設計變得容易之同時,也可以 應付基於雜訊等之電源變動。(3 )藉由再寫入讀出之資 料,可以降低基於讀出動作之資料可靠性降低。(4 )相 變化元件之記錄保持特性劣化之例如攝氏1 2 5度以上之高 速動作及長時間放置變成可能。 -25- 200527656 (22) 在實施例1及2中,讀出電壓雖設爲相變化元件之相 狀態改變之Vset以上或者Vreset以上之電壓,但是,在 以比此低之電壓使之動作之情形,如實施例1及2般,即 使進行再寫入動作亦可。另外,在此情形,不需要爲了讀 出動作而進行再寫入故,可在特定之次數,例如可讀出次 數之]/ 1 〇次程度,或者每經過特定之動作時間後進行再 寫入動作亦可。在此情形下,與實施例1及2相同,於可 以防止基於熱千擾及動作時之干擾所引起之資料破壞之優 點外,與讀出次數相比可降低改寫次數,具有可以提升相 變化元件之改寫耐受性之優點。 <實施例3 > 接著,敘述貫現資料可靠性提升之陣列構造。如前述 般,重置狀態之相變化元件基於讀出動作或高常溫下之動 作,承受熱干擾而有往設定狀態引起相變化之可能性。另 一方面,設定狀態之相變化元件往重置狀態引起相變化之 可能性認爲比重置狀態之相變化元件往設定狀態引起相變 化之可能性相當小。因此,藉由使複數之記憶體單元保有 冗長性而使記憶1位元之資料,可使相變化元件提升記憶 資料之可靠性。 第1 2圖係本發明之實施例。位元線B L 0 0、B L 0 ]、 BL02、BL03..·及 8乙]0、6乙11、8乙12、3乙13...分5[[連接 於與前述第2圖之記憶體單元陣列MCA同樣構造之記億 體單元陣列M C A 0、M C A 1。連接有位元線B L 0 0、B L 0 ]、 -26 - 200527656 (23) B L 0 2、B L 0 3…之感測放大器方塊S A B 0及連接有位元線 BL10、BL11、BL12、BL13之感測放大器方塊SAB]可以 是前述任一實施例之感測放大器方塊SAB的電路構造° 資料輸入輸出線1/00由感測放大器方塊SAB0、資料輸入 輸出線I/O 1由感測放大器方塊SAB 1分別當成互補之訊號 (t/b )而被輸出。所輸出之訊號線係輸入於邏輯和方塊 〇R B。邏輯和方塊〇 RB係利用這些之輸入訊號而輸出外部 輸出資料DOt/b。另外,邏輯和方塊ORB係將來自外部之 寫入資料DIt/b傳達給感測放大器方塊SABO及SAB 1。 接著,說明在本實施例之讀出動作。記憶體單元陣列 M C A 0及M C A 1係與一個之位址被輸入之同時而被活化。 由此時所指定位址的記憶體單元M c所讀出之訊號分別爲 ,由記憶體單元陣列M C A 0之記憶體單元M C所讀出之訊 號係由感測放大器方塊SAB0所感測、放大,由記憶體單 元陣列MCA 1之記憶體單元MCT所讀出之訊號係由感測放 大器方塊SAB 1所感測、放大。此時’在感測放大器方塊 中,依據第1 3圖之記憶體單元MC的相狀態與所輸出之 互補之訊號I/〇*t、l/0*b之輸出電壓的關係而輸出資料。 即相狀態爲高阻抗狀態(Reset )之情形,輸入輸出訊號 I / Ο 01及I / Ο 1 t成爲Η ’狀態,在低阻抗狀態(S e t )時’輸 入輸出訊號I / 〇 〇 t、I / Ο ] 6成爲L :狀態。而且’在接受這 些之輸入輸出訊號的邏輯和方塊〇RB中,進行輸入輸出 訊號I / 〇 0 t與I / 〇 1 t之邏輯和’輸出外部輸出資料D 01/b ° 第]3圖係顯示輸入輸出訊號】及I/0] t與外部輸出資 -27- 200527656 (24) 料D〇t之關係。如此圖般,在輸入輸出訊號I/〇〇t及 I /〇11之其中一方或者兩方爲Η,狀態時,外部輸出資料成 爲Η ’狀態。此如改換爲記憶體單元之相變化元件的狀態 時,即是讀出之記憶體單元陣列M C A 0或者M C A 1之記憶 體單元之其中一方或者兩方爲高阻抗狀態(Res e〇時, 則外部輸出資料D 0 t成爲Η,。 接著’說明本構造之寫入動作。在寫入時,寫入資料 藉由外部輸入資料訊號DIt/b而輸入於邏輯和方塊ORB。 在邏輯和方塊ORB中,將外部輸入資料訊號DIt/b藉由開 關而轉送給輸入輸出訊號I/O 〇t、I/O Ob及輸入輸出訊號 I/O It ' I/Olb。這些之輸入輸出訊號分別被送往感測放大 器方塊S A B 0、S A B 1。在感測放大器方塊S A B 0、S A B 1中 ,與前述之實施例之感測放大器方塊SAB相同,對位在 記億體單元陣列MCA0及MCA1之記憶體單元進行寫入資 料之動作。 接著,說明本構造之優點。在相變化記憶體中,可以 防止基於高溫待機,或者連續之讀出動坐等之相變化所致 之資料破壞,或者不良位元或掉落位元等所致之資料可靠 性之降低。相變化元件之記錄保持特性劣化之例如攝氏 1 2 5度以上之高速動作及長時間放置變成可能。 另外,此處,雖使2個之記憶體單元MC記億1位元 ,但是,也可以是記憶在2個以上之記憶體單元M C,輸 出取得該讀出結果之邏輯和者之構造。在此情形’ 3個之 中只要有]個爲高阻抗狀態,藉由可以輸出Η ’,便能提 -28- 200527656 (25) 升資料的可靠性。 在如目前爲止所說明之第1 〇圖、第1 1圖般之動作中 ’可靠性雖大幅提升,但是,讀出電壓設爲相變化元件之 相狀態改變之Vset以上或Vreset以上之電壓故,讀出動 作時,一定需要再寫入動作,每一週期之消耗電力變大。 在接著說明之實施例中,於同樣之電路構造下,爲了低消 耗電力化,說明設讀出電壓爲相變化元件之相狀態改變之 Vset、Vreset以下之電壓的情形。在此情形下,即使進行 讀出動作,資料不會在每一讀出動作被破壞,可在特定之 動作週期中進行再寫入動作即可故,可以實現低消耗電力 。即使在此情形,可防止由於熱干擾及動作時之干擾所致 之資料破壞外,與讀出次數相比,可使改寫次數更降低, 能提升相變化元件之改寫耐受性。另外,電路構造可以是 前述之實施例1 ' 2、3之其中一種。即只在特定之週期進 行再寫入動作故,可藉由只在特定之週期使個別之實施例 的重置啓動訊號W R E與設定啓動訊號W S E活化而加以實 現。例如,藉由使用如第2 2圖之邏輯電路,產生進行再 寫入動作之訊號重置寫入訊號WRE與設定寫入訊號WSE ,在特定之動作中,實現再寫入動作。在本圖中,再寫入 啓動訊號RW係顯示對於選擇字元線上之列選擇記憶體單 元進行再寫入動作之訊號。記憶墊選擇訊號M S B係解碼 所輸入之位址,顯示特定之位址範圍的訊號,不管讀出動 作、寫入動作,對應所輸入之位址,記憶體陣列上之其一 之記憶墊選擇訊號MSB受到選擇。重置時間規定脈衝 -29- 200527656 (26) ITReset係規定重置寫入動作之寫入時間之脈衝。同棧 設定時間規定脈衝TSet係規定設定寫入動作之寫7 之脈衝。第2 3圖係顯示本電路構造之動作例。如第 般,記憶墊選擇訊號M S B轉變爲活化狀態,例如此 低電位狀態後,再寫入啓動訊號一被活化時,藉由這 號及重置時間規定脈衝TReset,重置啓動訊號WRE 化。同樣地,藉由設定時間規定脈衝TSet,設定啓動 WSE被活化。反之,在再寫入啓動訊號RW爲非活化 之情形’即使記憶墊選擇訊號MSB成爲活化狀態, 啓動訊號WRE、設定啓動訊號WSE之任一種都未被 。即再寫入動作係可藉由此再寫入啓動訊號RW所控ί 說明本構造之優點。不每次讀出動作時進行再寫 作’只在特定之再寫入啓動訊號被活化時進行,藉此 以降低改寫次數,得以提升相變化膜之可靠性。另外 讀出動作中’不會引起資料破壞之情形,於讀出動作 伴隨再寫入動作故,具有週期時間可以縮短之優點。 ,再寫入動作之消耗電力可去掉一部份故,也可實現 耗電力。進而,與只進行非破壞讀出動作.之情形相比 由在特定之期間進行再寫入動作,具有可以提升記憶 之可靠性之優點。 接著’針對此再寫入啓動訊號RW之產生方法及 在前述之特定週期進行再寫入動作之實施例做說明。 第2 4圖係顯示在通常之讀取、寫入指令之外, 行再寫入動作REF用之輸入接腳或指令之記憶體晶片 :地, .時間 23圖 處爲 些訊 被活 訊號 狀態 重置 活化 入動 ,可 ,在 不會 進而 低消 ,藉 資料 關於 有實 的簡 -30- 200527656 (27) 單方塊圖。記憶體陣列Μ A係由複數之記憶體單元陣列 M C A所形成,與個別之記憶體單元陣列M C A鄰接而配置 有感測放大器方塊SAB。在記憶體陣列MA之一端配置有 驅動控制行解碼器RDEC用之位址線的前置解碼器RPDEC ,及輸出列選擇訊號用之列解碼器CDEC,於列解碼器配 置有對陣列轉送由記憶體陣列MA所輸出之資料的外部輸 出或由外部所輸入之資料用之資料控制部I/O-CTL。於記 憶體Chip配置有暫時保持由外部所輸入之位址AO、A 1… 或指令用之位址緩衝器INPUT Buffer,及進行與外部之資 料的輸入輸出之D Q B U f f e r,及由外部電壓V C C與接地電 位GND以產生內部電壓字元線選擇位準VWH、字元線非 選擇位準 VWL、感測放大器電源 VDL、重置寫入電壓 VfWR、設定寫入電壓 VWS、周邊電路電源電壓 VCL、接 地位準VSS、源極電位VS之內部電源產生電路VG。在本 構造中,其特徵爲在輸入指令中包含有進行再寫入動作用 之再寫入指令REF或者再寫入用接腳REF。第24圖係感 測放大器方塊及記憶體單元陣列MCA係與前述之第1圖 及第2圖相同。接著,說明本實施例之動作。 第25圖係於第24圖之感測放大器方塊SAB中適用 第1圖之構造的動作例。一由外部輸入有讀取指令Read 時,依據同時所輸入之位址,列選擇訊號被活化。另外’ 對應位址之感測放大器方塊之預先充電訊號PRE被活化。 藉此,位元線被預先充電爲讀出位準VR。同時,連接感 測放大器SA與讀出位元線BLSA之位元線分離訊號也成 -31 - 200527656 (28) 爲高電位狀態。之後,位元線預先充電訊號P R E被非活化 之同時,依據輸入位址,字兀線W L由非選擇狀態之V W L 轉變爲選擇狀態之V W Η。此時,記憶體單元M C之相變化 元件的阻抗狀態爲低阻抗狀態時,如圖中之虛線般,急遽 轉變爲源極線S L電位V S。另一方面,在高阻抗狀態時, 維持位元線讀出位準V R附近。在經過特定期間後,於感 測放大器如產生足夠之訊號時,位元線分離訊號BLI轉變 爲低電壓 V S S,分離感測放大器與讀出位元線B L S Α。之 後,感測放大器SA藉由感測放大器活化訊號SE/SEB活 化,將由記憶體單元MC所讀出之微小訊號放大至感測放 大器電源VDL。之後,被轉送於I/O控制、DQ緩衝器。 在此之前,後,活化狀態之字元線 WL .轉變爲非選擇位準 V WL。之後,感測放大器藉由使感測放大器活化訊號成爲 非活化,而轉變爲待機狀態。與此幾乎同時,列選擇訊號 轉變爲非選擇狀態,讀出週期結束。接著,說明再寫入指 令REF被輸入時之動作。與指令同時所輸入之位址或者以 記憶體晶片CHIP內之位址計數器ADD-C所產生之位址被 活化,直到被讀出於感測放大器之動作爲止,與前述之讀 出動作相同。此處,依據再寫入指令R E F,再寫入啓動訊 號R W被活化爲高電位狀態。如第2 3圖之動作波形圖般 ,再寫入啓動訊號RW —被活化,藉由對應選擇位址之記 憶墊選擇訊號MSB與重置時間規定脈衝TRe set,重置啓 動訊號WRE被活化。重置啓動訊號一被活化,在保持在 感測放大器之資料係對應高電位狀態之情形,即Ι/Ot設定 -32 - 200527656 (29) 爲高阻抗狀態,I/Ob設定爲低電位狀態時,在寫入驅 WD中,重置電壓藉由感測放大器位元線BLSA、位 BL0而施加於記憶體單元MC,流通寫入所必要之電 重置啓動訊號只在以重置時間規定脈衝 TReset所決 時間被活化後,轉變爲低電位狀態,重置動作結束。 動作結束後之動作係與前述之讀出動作相同。在本動 ,設再寫入動作只是寫入時間短之重置動作。此係著 ,相變化記憶體之熱干擾或讀出動作之干擾,以重置 之元件變成設定狀態之元件之錯誤設定比由設定狀態 重置狀態之錯誤重置容易產生之觀點。因此,在本動 ,與讀出週期tRC相比,進行再寫入之週期tRC7雖 .. 進行再寫入動作份,但是,只進行寫入時間短之重置 故,可使週期時間之延長份減少。 說明本實施例之優點。在通常之讀取、寫入動作 藉由設置再寫入動作,於基於讀出動作之資料破壞前 以進行再寫入動作,能提升資料可靠性。進而,在再 動作中,只進行重置動作故,具有可使基於進行再寫 作之動作延長量變小之優點。 接著,針對於前述之第24圖的感測放大器方塊 適用第8圖之感測放大器方塊之情形的動作。第2 5 顯示本構造之動作例。本構造之特徵係依據從外部所 之指令,作爲特定位址之記憶體單元資料的再寫入動 進行重置動作與設定動作之兩種動作。關於輸入有讀 令時之讀取週期,係與前述之第2 5圖相同。接著, 動器 元線 流。 定之 寫入 作中 眼於 狀態 變成 作中 長了 動作 外, ,可 寫入 入動 S AB 圖係 輸入 作而 取指 說明 -33 - 200527656 (30) 輸入有再寫入指令REF時之動作。與指令同時所輸入之位 址或者以記憶體晶片CHIP內之位址計數器ADD-C所產生 之位址被活化,直到被讀出於感測放大器之動作爲止,與 前述之第25圖相同。此處,依據再寫入指令REF,再寫 入啓動訊號RW被活化爲高電位狀態。如第2 3圖之動作 波形圖般,再寫入啓動訊號RW —被活化,藉由對應選擇 位址之記憶墊選擇訊號MSB與重置時間規定脈衝TReset ,重置啓動訊號WRE被活化。重置啓動訊號一被活化, 在保持在感測放大器之資料係對應高電位狀態之情形,即 Ι/Ot設定爲高阻抗狀態,I/Ob設定爲低電位狀態時,在寫 入驅動器W D中,重置電壓藉由感測放大器位元線b L S A 、位元線B L 0而施加於記憶體單元M C,流通寫入所必要 之電流。重置啓動訊號只在以重置時間規定脈衝TRe set 所決定之時間被活化後,轉變爲低電位狀態,重置動作結 束。同樣地,如第2 3圖之動作波形般,再寫入啓動訊號 RW —被活化,藉由對應選擇位址之記憶墊選擇訊號MSB 與設定時間規定脈衝T S e t,設定啓動訊號W S E被活化。 設定啓動訊號W S E —被活化,在對應保持於感測放大器 之資料爲低阻抗狀態之情形,即I/〇t設定爲低電位狀態, I / 0 b g受疋爲闻電位狀態時,在寫入驅動器w D中,設定電 壓藉由感測放大器位元線B L S A、位元線B L 0而施加於記 憶體單元MC,流通寫入所必要之電流。設定啓動訊號 w S E在只以設定時間規定脈衝丁 s e t所決定之時間被活化 後’轉變爲低電位狀態,設定動作結束。寫入動作結束後 -34 - 200527656 (31) 之動作’係與前述之讀出動作相同。在本動作中,與讀出 週期t R C相比,進行再寫入動作之週期t R c,不單只是重 置也進行設定故,需要比較長之時間,例如5 〇ns至]“ < 之程度。 說明本實施例之優點。在通常之讀取、寫入動作外, 藉由設置再寫入動作,於基於讀出動作之資料破壞前,可 以進行再寫入動作,能提升資料可靠性。進而,在再寫入 動作中’不單重置動作,也藉由進行設定動作,與前述實 施例相比’具有兩資料之可靠性得以提升之優點。 接著,利用實施例說明在記憶體晶片CHIP上藉由記 憶體單兀資料之錯誤預測、檢測功能以進行再寫入動作之 構造。第2 7圖係在記憶體晶片上附加錯誤檢測功能之記 憶體晶片的方塊圖例子。與前述之第2 4圖相比,其特徵 爲可以省去位址計數器。其他之構造係與前述之第2 4圖 相同。第2 8圖係顯示記憶體單元陣列M C A與其之周邊電 路之方塊圖。與前述之第I圖相同,與記憶體單元陣列 MCA鄰接,藉由驅動字元線WL0、WL1、WL2、…之行解 碼器R D E C、位兀線B L 0、B L 1、B L 2、…而配置有讀取記 億在記憶體單元之資料用的感測放大器方塊SAB。進而, 在本構造中,於記憶體單元陣列MCA內配置有與位元線 BL0、BL ]、BL2、…鄰接而配置之複製位元線 BL —REP。 進而,對應複製位元線而配置有複製位元線用感測放大器 方塊電路 SAB_REP。複製位元線用感測放大器方塊 SAB_REP係輸出成爲再寫入啓動訊號RW之原始訊號之 -35- 200527656 (32) RW0。再寫入啓動訊號RW係由再寫入啓動原始訊號RWO 被轉換爲如第2 9圖之脈衝寬度而被輸出。第3 0圖係顯示 第28圖之記憶體單元陣列MCA的構造例。對於複製用位 元線,對全部之字元線配置有複製用記憶體單元MC_REP 。複製用記憶體單元MC_REP例如係採用與如第3圖之通 常的記憶體單元M C相同之構造。但是,其特徵爲,位元 線上之全部的記憶體單元內之相變化元件係被設定爲高阻 抗狀態。第3 1圖係顯示前述之複製用感測放大器方塊 SAB — REP之方塊圖例子。位元線預先充電電路BLPC係在 讀出動作中,將位元線預先充電爲所期望之位準VR之電 路,例如,由預先充電爲如第32圖之VR之MOS電晶體 ’及待機時,設定爲源極線電位VS之MOS電晶體所成。 寫入驅動器WD係與前述之第5 ( a )圖相同之構造。感測 放大器電路SA_REP係將被讀出於位元線BLSA之微小訊 號放大至感測放大器電源 V D L振幅爲止,而輸出再寫入 啓動原始訊號RWO與對於寫入驅動器 WD之寫入資料用 之電路。第33圖係顯示感測放大器SA_REP之電路構造 例。在本感測放大器中,作爲參照位準係使用複製用參照 VREF-REP。VREF — REP與在前述之感測放大器方塊 S AB 所使用之VREF相比,係設定在高位準。藉由如此,與通 常之感測放大器方塊相比,即使在呼叫比較高阻抗狀態之 記憶體單元之情形,也可以低阻抗狀態而容易讀出,能夠 檢測高阻抗狀態之讀出資料破壞。在本感測放大器中,進 而在讀出低阻抗狀態之情形,參照側之位元線係藉由反相 -36 - 200527656 (33) 器而當成再寫入啓動原始訊號R W 0而被輸出。說明本構 造之優點。藉由將複製用之記憶體單元配置在與通常之記 憶體單元相同的記憶體單元,可使偏差之影響變小,藉由 具有與通常之記憶體單元相同之特性的記憶體單元,具有 可以觀測資料保持特性之優點。藉由將複製用之感測放大 器參照位準置於高阻抗側,通常在記憶體單元基於讀出動 坐等’由高阻抗狀態成爲低阻抗狀態而引起資料破壞前, 以複製記憶體單元可加以檢測故,具有記憶資料之可靠性 得以提升之優點。 接者’利用第3 4圖說明使用在實施例3說明之〇 R單 元陣列之再寫入啓動訊號產生方法。第3 4圖係顯示前述 之第]2圖的記憶體單元陣列MCA及感測放大器方塊S AB 與OR邏輯方塊ORB2。OR邏輯方塊〇RB2係與前述之實 施例3相同,藉由對於讀出資料取得〇 R邏輯,可以降低 基於高阻抗狀態轉變爲低阻抗狀態所致之錯誤。在本構造 中,其特徵爲,進而在讀出之2個之資料1/00、I/O】之間 資料不同之情形,附加將高阻抗狀態寫入2個之記憶體單 元用之再寫入啓動原始訊號RW0之輸出電路。其他之構 造係與前述之實施例3相同。說明本構造之優點。在本_ 造中,不使用複製記憶體單元,使用記憶實際的資料之言己 憶體單元故,可不受到單元間之特性的偏差影響而做資料 錯誤之檢測。進而’藉由於2個之記憶體單元記憶相同之 資料,藉由採用〇 R邏輯,不單可以輸出正確之資料’也 可再寫入正確之資料,可以實現記憶資料之高可靠性。通 -37 - 200527656 (34) 常,在使用2個之記憶體單元,藉由檢測其之資料不同以 檢測錯誤之情形,很難檢測到底哪個記憶體單元記憶有正 確之資訊。但是,在使用相變化元件之情形,相變化元件 之阻抗狀態基本上以重置狀態(高阻抗狀態)轉變爲設定 狀態(低阻抗狀態)之錯誤爲主。因此,在2個之記憶體 單元之阻抗値不同,而檢測出錯誤之情形,可知道2個中 成爲設定狀態之記憶體單元係發生資料錯誤。 利用第3 5圖說明使用第2 8圖之電路構造之情形的動 作。輸入讀取指令,沒有檢測出錯誤時之動作,係與前述 之第25圖相同。另一方面,在第35圖之第2週期之動作 中,係顯示與讀出動作之同時,有檢測出錯誤之情形。首 先,由輸入指令至資料被讀出於位元線,於感測放大器保 持資料爲止,係與通常之讀出動作相同。此處,複製記憶 體單元之相變化元件在由高阻抗狀態轉變爲低阻抗狀態之 情形,讀出複製位元線之複製感測放大器的輸出節點 I/0_REPt/b係檢測到低阻抗狀態。一檢測出低阻抗狀態時 ,再寫入啓動原始訊號RW0被活化,再寫入啓動訊號RW 被活化。再寫入活化訊號RW —被活化,感知重置啓動訊 號WRE與複製位元線用感測放大器輸出I/0_REPb,由寫 入驅動器WD對於位元線施加重置寫入電壓VWR。重置寫 入電壓只在重置啓動訊號 WRE被活化之期間中施加,即 刻下降。藉此,複製記億體單元被改寫爲高阻抗狀態。與 此動作相同,對於記憶資料之記憶體單元MC,也對於讀 出阻抗狀態爲高阻抗狀態之記憶體單元,與對於複製記億 -38 - 200527656 (35) 體單兀之重置寫入動作相同,進行重置寫入動作。藉此, 記憶資料之記憶體單元之高阻抗記憶相變化元件也進行再 寫入動作,資料保持特性得以提升。說明本動作之優點。 在本動作中’只進fr易入時間短之重置寫入動作故,可在 通常之讀取動作之週期時間內進行再寫入動作,具有可遮 蔽基於進行再寫入動作所致之不能存取的優點。 接者’說明與則述之第2 7圖之實施例相同,使記憶 體晶片CHIP上具有錯誤檢測功能,進而,具有於再寫入 動作中,防止外部記憶體控制器對於記憶體晶片CHIP發 行存取要求用之忙線接腳WAIT之構造。第3 6圖之特徵 爲,對於前述之第2 7圖之構造,作爲輸出接腳而具有忙 線接腳WAIT。此以外之構造係與前述之第27圖相同。本 構造係與前述之實施例不同,適合於伴隨再寫入動作之讀 取週期中,週期時間比通常之讀取週期長之情形。第37 圖係顯示忙線接腳WAIT之輸出方法的方塊圖。忙線接腳 W A I T係藉由接受再寫入啓動訊號,而由高電位狀態成爲 低電位狀態,對於外部記憶體控制器’進行傳達記憶體不 能使用之功能。藉此,與讀取動作相比’即使再寫入動作 所必要之時間長之情形中,藉由對記憶體控制器傳達狀態 ,具有可以防止資料之衝突、資料之遺失的優點。利用第 3 8圖說明本構造之動作波形圖例子。本動作係使用具有如 前述之實施例的第28圖般之複製記憶體單元之記憶體單 元陣列MCA與其之周邊電路方塊之情形的動作波形圖例 子。關於圖之最初的週期之沒有再寫入的讀取動作’係與 -39- 200527656 (36) 前述實施例相同。接著,在第2週期中,係伴隨讀出動作 而進行再寫入動作之例子。在本動作中,直到將由記億體 單元所讀出之訊號保持在感測放大器爲止,係與前述實施 例相同。如前述之第2 8圖之動作波形圖例子之第3 5圖般 ,複製位元線上之記憶體單元之讀出資料由高阻抗狀態被 讀出爲低阻抗狀態時,則低阻抗狀態之訊號被輸出於感測 放大器之輸出節點之I/O —REPt。藉此,再寫入啓動訊號 RW被活化。再寫入啓動訊號RW —被活化,重置啓動訊 號 WRE被活化,對讀出重置狀態之單元進行重置寫入動 作。同時,設定啓動訊號 WSE也被活化,對讀出設定狀 態之單元進行設定寫入動作。重置啓動訊號 WRE在經過 重置寫入時間後,成爲非活化狀態。另一方面,在設定寫 入動作中,需要50ns〜1 μ s以上之寫入時間,在其間,設 定啓動訊號維持活化狀態。在經過特定之期間後,設定啓 動訊號 WSE被非活化,成爲待機狀態。在此寫入期間之 間,記憶體晶片無法由外部存取故,爲了將其傳達給控制 器,使忙線接腳WAIT轉變爲低電位狀態。藉此,來自外 部控制器之動作指令的發行得以避免。說明本構造之優點 。在再寫入動作中,不單重置寫入,也藉由進行設定寫入 ,可以提升兩資料之可靠性。進而,藉由設置忙線接腳, 在記憶體晶片無法存取之期間,可抑制來自控制器之指令 發行,資料衝突、消失得以防止。 接著,利用第3 9圖說明前述實施例之變形例。在本 構造中’作爲寫入動作,只進行重置動作,此係其特徵。 -40 _ 200527656 (37) 在前述之寫入動作中,只有重置啓動訊號 WRE被活化, 對於讀出重置狀態之記憶體單元進行重置寫入動作。另一 方面,對於讀出設定狀態之記憶體單元,不進行寫入動作 。在進行重置寫入動作之間,爲了不令外部控制器發行指 令,使忙線接腳WAIT轉變爲低電位狀態。藉此,外部控 制器不對記憶體晶片進行存取。說明本構造之優點。在藉 由設置忙線接腳之資料衝突、消失之防止外,於本構造中 ,以50ns程度之比較短的寫入時間即可完成只是重置動 作之再寫入動作故,可使記憶體晶片爲忙線狀態之時間變 短,具有可使不能存取時間變短之優點。 接著,說明組合多値記憶體與〇 R單元之情形的實施 .例。第 4 0圖係顯示使用··相變化元件以進行多値記憶之情 形的阻抗値之分布。由高阻抗狀態分配爲阻抗狀態R3 5 1 1 ’ 、阻抗狀態R2’10’、阻抗狀態R] 5 0 0 ’、阻抗狀態RO’Ol ; 。如此加以分配時,具有即使轉變爲鄰接狀態,2位元皆 成爲錯誤之可能性變小之優點。在使用相變化元件之情形 ,相變化元件之阻抗狀態基本上係以重置狀態(高阻抗狀 態)轉變爲設定狀態(低阻抗狀態)之錯誤爲主。因此, 使用於2個單元記憶相同資料之OR單元陣列,以實現能 實現高資料可靠性之陣列。第4 1圖係顯示2個之記憶體 單元陣列MCA 0與MCA]之同一位址的記億體單元之相變 化元件的阻抗狀態與記憶資料MLBt/MSBt之關係。如先 前說明般,成爲在2個之記憶體單元中,以高阻抗狀態之 記憶體單元之資料爲真値而予以輸出之構造。例如,記億 -41 - 200527656 (38) 體單元陣列MC A0之記憶體單元之狀態爲R3之情形’即 使記憶體單元陣列MCA 1之記憶體單元之狀態爲任一種’ 輸出資料M LB t/M S B t也成爲,1,/,1 ’。說明實現此之陣列 構造。第4 2圖係顯示記憶體單元陣列周邊電路方塊圖。 配置有記憶體單元陣列MCA 1及MCA0、感測放大器方塊 S AB — M、S AB — M、OR邏輯部ORB —Μ。第43圖係感測放 大器方塊S A Β —Μ之方塊圖例子。與前述之實施例相同’ 配置有位元線選擇電路BLSEL與寫入驅動器WD_M與感 測放大器電路SA,於輸入輸出部配置有轉換讀出資料而 予以輸出之I 〇閘I 〇 G。另外,感測放大器電路係可以问 時讀出區分多値故,配置有使用3個之參照位準VREF0、 VREF1、VREF2之3個之感測放大器電路。第4 4圖係顯 示配置於感測放大器方塊SAB_M之寫入驅動器WD_M之 電路構造。成爲藉由對應記憶體單元之阻抗狀態之I/0 0、 I/O 1、1/0 2、1/03而決定寫入電壓,以寫入啓動訊號 W0 、W]、W3決定寫入期間之電路構造。在1〇閘中,參照 這些3個感測放大器SA之SA01t/b、SA01t/b、SA2t/b, 對應記憶體單元之阻抗狀態,於輸出節點I/O 〇、1/〇]、 1/02、1/03之其一輸出第46圖係顯不OR邏輯部之 方塊圖。讀取方塊RE_M係對於由2個之記憶體單元陣列 M C A 0、M C A 1所讀出之資料,檢測錯誤,輸出似乎正確 資料之電路方塊。寫入方塊W E — M係在寫回由外部所輸入 之資料,或者藉由錯誤檢測而寫入正確資料時,由所輸入 之資料對於記憶體單元陣列MCA0 ’輸出對應阻抗狀態之 200527656 (39) 訊號I / Ο ] 1、I / Ο 0 1、I / Ο 〇 2、I / Ο 0 3,及對於記憶體單元陣 歹丨」MCA],輸出對應阻抗狀態之訊號1/010、I/O Π、1/012 、I/O 1 3。錯誤檢測電路DET係藉由比較由記憶體單元陣 歹IJ MCA所讀出之資料,檢測錯誤之有無,在有錯誤之情 形,輸出再寫入啓動原始訊號RW0。第47圖係顯示讀取 方塊 RE_M之具體的電路構造例。如圖般,最上位位元 MLBt係取得1/000與1/010之NOR邏輯,及1/001與 1/011之NOR邏輯之NAND邏輯者。同樣地,最下位位元 MSBt係取得1/〇〇3與1/013之NAND邏輯之輸出與1/0 00 與1/010之NOR邏輯之輸出的NAND邏輯者。藉此,可 以實現滿足第4 1圖之表格之轉換。第4 8圖係顯示寫入方 塊 WE_M之電路構造例。這些係進行前述之讀取方塊 R:E —Μ之相反轉換。第49圖係顯示錯誤檢測電路DET之 電路構造例。爲將在記憶體單元陣列MCA0與MCA1之間 ,對應之輸出訊號1/000與1/010及I/O] 0與1/01 1、及 1/0 02與I/O〗2之Ex-OR邏輯之輸出予以進行OR邏輯所 取得者。藉此,在某一之輸出訊號不一致之情形,變成再 寫入啓動原始訊號RW 0會被活化。說明本構造之優點, 在餘裕變小之多値記憶方式中,藉由組合於複數之記憶體 單元記憶相同資料之 OR單元陣列,記憶資料之可靠性得 以提升’可使保持時間變長。另外,附加錯誤檢測電路故 ’藉由在錯誤檢出時,進行再寫入,可以校正·記億體單元 資料之錯誤,可以提升資料之可靠性。 說明電壓條件。字元線選擇位準可以是與外部電壓 - 43- 200527656 (40) VCC相等之].8V或者1.5V,也可以是經過內部昇壓之 2.5V或3.0V,藉由使用高電壓,記憶體單元電晶體之電 流驅動力變強故’即使記憶體單元電晶體之尺寸小,也可 以確保改寫電流故,具有可以實現小記憶體單圓面積之優 底。感測放大器電源 V D L、及周邊電路電源V C .L可以是 1 . 8 V或者1 . 5 V、1 . 2 V。藉由低電壓化,可以實現低消耗 電力化。重置寫入電壓VWR設爲與外部電壓VCC相等之 電位’在降低消耗電力上更爲理想。 【圖式簡單說明】 第1圖係本發明實施例1之陣列及周邊電路之構造圖 〇 弟2圖係記憶體單元陣列之構造圖。 第3圖係記憶體單元之構造圖。 第4圖係位元線選擇器之電路構造例。 第5圖係寫入驅動器及感測放大器之電路構造例。 第6圖係本發明實施例1之讀出動作波形圖。 第7圖係本發明實施例1之寫入動作波形圖。 第8圖係本發明實施例2之感測放大器方塊的電路構 造。 第9圖係寫入驅動器之電路構造例。 第1 0圖係本發明實施例2之讀出動作波形圖。 第1 ]圖係本發明實施例2之寫入動作波形圖。 第1 2圖係本發明實施例3之陣列及周邊電路構造圖 -44 - 200527656 (41) 第1 3圖係顯示本發明實施例3之記憶體單元資料與 輸出資料之關係表格。 第1 4圖係相變化記憶體之電流一電壓圖。 第1 5圖係位元線之預先充電位準及電壓降低之動作 波形圖。 第1 6圖係相變化記憶體之電流一電壓圖。 第1 7圖係相變化記憶體之電流一電壓圖。 第1 8圖係本發明實施例1之相變化記憶體之記憶體 單元之剖面圖。 第19圖係Ge2Sb2Te5相變化材料與下部電極材料之 晶格常數。 第2 0圖係重置電流與下部電極材料之關係。 胃2 1圖係相變化材料由結晶狀態相變化爲非晶質狀 態時之重置電壓與相變化材料之膜厚的關係。 胃 2 2 Η係顯示重置啓動訊號與設定啓動訊號之控制 方法圖。 第2 3圖第顯示第2 2圖之動作波形圖例。 第24圖係具有再寫入指令之記憶體的方塊圖例。 第2 5圖係第24圖之記憶體之動作波形圖例。 第26圖係第24圖之記憶體之別的動作波形圖例。 ^ 2 7圖係具有自我再寫入判定動作功能之記憶體之 方塊圖例。 第2 8圖係第2 7圖之記憶體的記憶體陣列主要部位之 ^45- 200527656 (42) 方塊圖。 第2 9圖係寫入啓動訊號產生電路之構造例與動作波 形圖。 第3 0圖係第2 7圖之記億體單元陣列之構造例。 第3 1圖係複製位元線用感測放大器方塊構造例。 第3 2圖係預先充電電路構造例。 第3 3圖係複製位元線用感測放大器電路構造例。 第3 4圖係使用Ο R單元陣列之寫入啓動訊號產生方法 之構造例。 第3 5圖係具有自我再寫入判定功能之記憶體的動作 波形圖例。 第3 6圖係具有自我再寫入判定功能與狀態輸出接腳 之記憶體之方塊圖例。 第3 7圖係忙線輸出接腳輸出電路方塊圖例。 第3 8圖係第3 6圖之記憶體之動作波形圖例。 第3 9圖係第3 6圖之記憶體之別的動作波形圖例。 第4 0圖係顯示於相變化元件進行多値記憶之情形的 阻抗分布及資料轉移之方向圖。 第4 1圖係顯示使用2個多値記憶元件以構成OR單元 陣列之情形的資料映射例圖。 第42圖係顯示組合多値記憶元件與〇R單元陣列時之 記憶體單元陣列與感測放大器方塊、及0 R邏輯部圖。 第4 3圖係第4 2圖之感測放大器方塊電路構造例。 第44圖係第43圖之寫入驅動器之電路構造例。 - 46 - 200527656 (43) 第4 5圖係顯示第4 3圖之輸入輸出電路構造例圖。 第46圖係第42圖之OR邏輯部方塊圖。 第4 7圖係顯示第4 6圖之讀出資料構造方塊圖。 第4 8圖係顯示第4 6圖之寫入資料構造方塊圖。 第4 9圖係顯示第4 6圖之錯誤檢測電路之構造例圖。 【主要元件之符號說明】 upc :上部電極, dwc:下部電極插塞, RDEC :行解碼器/字元驅動器, WL、WL0、WL1、WL2、WL3 …:字元線, BL、BL0、BL1、BL2、BL3、BL00、BL01、BL02、 BL0 3、BL] 0、BL1 1、BL12、BL] 3 …:位元線, BLSA :感測放大器內位元線, PRE :預先充電訊號, WRE :重置寫入啓動訊號, W S E :設定啓動訊號, SE : NMOS感測放大器啓動訊號, SEB : PMOS感測放大器啓動訊號, I/〇t、I/Ob、l/〇0t、l/〇0b、I/〇lt、I/〇lb:輸入輸出 資料線, WD :寫入驅動器, S A :感測放大器, S A B、S A B 0、S A B ]:感測放大器方塊, -47 - 200527656 (44) BLSEL :位元線選擇器, M C A、M C A 0、M C A 1 :記憶體單元陣歹lj, VREF :參照位準, COt〜C3t、COb〜C3b :歹ij選擇雲只號, MT :記憶體單元電晶體, P C R :相變化元件, BLI :位元線分離訊號, VWR:重置寫入電壓, VWS:設定寫入電壓, ORB :邏輯和方塊, DIt/b…:外部輸入資料線, D〇t/b :外部輸出資料線, V p、V R :位元線預先充電位準, TReset :重置期間規定脈衝, TSet :設定期間規定脈衝, MSB :記憶墊選擇訊號, RW :再寫入啓動訊號, RPDEC :行前置解碼器, INPUT Buffer :輸入緩衝器, V G :內部電源輸出電路, DQ Buffer :輸入輸出資料緩衝器, I/O CTL :輸入輸出資料控制器, MA :記憶體陣列, REF :再寫入外部指令, -48- 200527656 (45) tRW :再寫入啓動訊號脈衝寬, BL — REP :複製位元線, SA —REP :複製位元線用感測放大器方塊, RW — GEN :再寫入啓動訊號產生方塊, R W 0 :再寫入啓動原始訊號., MC — REP :複製用言己憶體單元, B LP C :位元線預先充電電路方塊, VREF_REP :複製用感測放大器參照位準, I/O —REPt ·•複製用感測放大器輸出, WAIT :忙線輸出接腳, WAIT_B :忙線輸出接腳輸出緩衝器, R0、Rl、R2、R3…:相變化元件阻抗狀態, MLBt/b :最上位位元, MSBt/b :最下位位元, ORB_M : OR邏輯方塊 -49-ZnnSbuTew phase change material to perform If it is assumed that it is below 60 nm, the reason for the correlation is that the phase change ′ is below the aforementioned film thickness of zero. Therefore, the phase change material is woven. The relationship between the aforementioned film thickness and the resistivity of the composition material of the phase change material is different. In addition, the power required when the reset voltage does not become 0V is included in the generation and diffusion of Joule heat -15- 200527656 (12). Examples of phase change memory used in high temperature operation and high temperature long-term storage include high melting point phase change materials, Z ^ Te phase change materials, or Zn-Te phase change materials with added elements Zn-X-Te series phase change material. Related materials related to the Zn-X-Te-based phase change material are disclosed in Patent Document 2, for example. Although the phase change material of the present invention is a G e S b Te-based phase change material, or a Z η-T e-based phase change material, or a z η-T e-based phase change material plus an additive element of Z η-X- T e is a phase change material, but it can also be applied to other phase change materials. In this case, while maintaining the reliability of the data of the phase change element, it is also possible to prevent a decrease in the operating speed at low voltages. In addition, although the operating voltage is assumed to be about .2 V, it can also be applied to 1.8 V operation. In this case, it also has the effect of increasing the operating margin and improving the operating speed. Furthermore, the present invention is intended to use a semiconductor having a processing size of 0.13 m or less. At the same time as the miniaturization progresses, the decrease of the operating voltage also progresses. Therefore, the decrease of the operating margin becomes a problem. By applying the present invention, the operating margin can be increased. In addition, the present invention can also be applied to a single memory and a logic mixed memory. By applying these methods, data reliability and memory unit defects can be remedied, and the product rate can be improved. In addition, especially in a logic hybrid memory, the reliability of data operating at high temperatures can be improved, and a semiconductor device capable of operating over a wide temperature range can be realized. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The circuit elements constituting each functional block of the implementation-16- 200527656 (13) example are not particularly limited, and are formed on a semiconductor such as single crystal silicon by a well-known integrated circuit technology such as CMOS (Complementary MOS Transistor). On the substrate. In the drawing, the p MOS transistor body is marked with an arrow to distinguish it from the NM MOS transistor. Although the connection of the substrate potential of the MOS transistor is not specifically described in the drawing, the connection method is not particularly limited as long as it is within a range where the MOS transistor can operate normally. In addition, unless otherwise specified, the low level of the signal is set to '' 0 '' and the high level is set to '' 1 ''. In this embodiment, when the operating voltage of the array is reduced, the read-out voltage range is narrowed, which can solve the problem of lowering the operating margin. In the conventional read operation, the applied voltage is suppressed to a low voltage so that a phase change element in a high impedance state or a low impedance state does not cause a phase change due to a current during reading. As a result, as the read current becomes smaller, the amount of read signal decreases, and there is concern about a decrease in operation speed and a decrease in operation margin. On the other hand, in the present invention, during the readout operation, “the sensor amplifier generates a sufficient signal amount and increases the applied voltage, and at the same time,” the unit that may cause a phase change due to the readout operation is reprocessed Write action 'to improve data reliability. Examples of the present invention are shown below. In this structure, 'the pre-charge level of the bit line of the read operation is that the phase change element in the set state does not cause a phase change', and the phase change element in the reset state must have a phase change of V set above the voltage of the set state Structures below V reset. Figure] is a diagram showing a memory cell array MCA, a sense amplifier block SAB, and a row decoder / character driver RDEC that implement this operation. -17-200527656 (14) First, the memory cell array MCA will be described. Fig. 2 shows a configuration example of the memory cell array MCA. The memory cell MC is arranged at the intersection of the character lines WL0 'WL1, WL2, WL3, ... and the bit lines BL0, BL]' B L2, B L3, .... In addition, source lines S L 0 1, S L 2 3,... Are provided. The source line is connected to the ground voltage V S S, for example. Each memory cell MC is composed of a phase-change impedance PCR and a memory cell transistor MT. Figure 3 shows two types of memory cell structures. In (a), one end of the phase-change impedance PCR is connected to the bit line BL, and the other end is connected to one of the source and the drain of the memory cell transistor MT. The other side of the source and drain of the memory transistor is connected to the source line, and the smell is connected to the word line. In this structure, the bit line BL is made to have a higher potential than the source line SL during writing. For example, in the case of .1.2 V driving, a large driving force of the memory cell transistor MT can be obtained. Is relatively excellent. In (b), the connection relationship between the phase-change impedance PCR of (a) and the memory cell transistor MT is reversed. In this structure, compared with the source line SL, the bit line is driven at a low potential. For example, when the potential of the source line SL is 1.2V and the bit line BL is driven at 0V, it can be obtained. The driving force of the large memory cell transistor MT is excellent. Furthermore, even during the read and write operations, even if the bit line is driven, the current in the non-selected cell does not flow through the diffusion layer of the charge-discharge memory cell transistor MT, which can prevent data destruction. Here, although the NMOS transistor is shown as the memory cell transistor, a PMOS transistor or a bipolar transistor may be used. However, from the viewpoint of high integration, MOS transistors are expected. Compared with PMOS transistors, -18-200527656 (15) NMOS transistors with smaller channel impedance are more suitable. In the following, the operation and the like will be described with respect to the voltage relationship when the NMOS transistor is used as the memory cell transistor. The bit line is also called a data line. Here, although it is not shown in the figure for the sake of simplicity, a virtual unit that generates a reference signal for reading when the memory unit array MCA is generated may be provided as needed. The sense amplifier block SAB is formed by a bit line selector BLSEL, a sense amplifier SA and a write driver WD. Fig. 4 shows a configuration example of the bit line selector BLSEL. The bit line selector BLSET is provided with bit switches BL0, BL1,... Of the memory array and connected to a selection switch for a sense amplifier. These relationships are controlled by the column selection signals C0t / b, Clt / b, .... Furthermore, a pre-charged transistor that charges the bit line of the memory array side and the sensing line and the bit line of the amplifier side BLS A to a desired level in advance is arranged. A sense amplifier block is provided adjacent to the bit line selector. The sense amplifier senses the signal of the bit line of the sense amplifier and outputs it to the outside, or temporarily holds the data from the outside. Figure 5 (b) shows a configuration example of the sense amplifier. In this configuration, it is formed by a cross-coupling amplifier circuit that compares the level of the sense amplifier bit line B L S A with the reference level VREF and amplifies it to the power supply voltage VWE. Fig. 5 (a) shows a configuration example of the write driver W D. The write driver WD drives the sense amplifier bit line BLSA based on data written from outside or data read from the sense amplifier SA. In this embodiment, the write driver WD is constituted only by a driver for making the phase change element of the memory cell into a high impedance state. In the figure, 4 BL 0, BL], BL 2, BL 3 are connected to the bit line]] Sense -19- 200527656 (16) Sense amplifier bit line BLSA, sense amplifier SA, and write driver WD '' But the number of 'bit lines' is not limited. By setting a large number, the number of sense amplifiers to be operated can be reduced, and an increase in unnecessary power consumption can be suppressed. On the other hand, if it is set to a small number, the number of bits to be output will increase, which is suitable for inputting and outputting high-speed and large-volume data. Next, a read operation of the array structure will be described. Fig. 6 is a timing chart of the read operation. According to the read command, the column selection line C0t / b corresponding to the inputted address is activated. After that, it is connected to the bit line of the sense amplifier SA. In the figure, the bit line BL0 and the bit line BLSA in the sense amplifier are also set as the bit line precharge level VR. In this embodiment, the potential difference between the pre-charge level VR and the source line SL of the memory cell MC is set such that the current necessary for the phase change element to change from a high impedance state to a low impedance state can flow. For example, in the example shown in the figure, the source line SL is set to 0V, and the precharge level VR is set to approximately 0.6V. After that, while the precharge signal PRE is in a non-selected state, the word line W L is selected. According to this, the bit line BL and the bit line BLSA in the sense amplifier are discharged by the memory cell transistor MT and the phase change element P CR. At this time, when the phase change element PCR of the memory cell is in a low impedance state, it is rapidly discharged. On the other hand, when the impedance is in a high impedance state, it is gradually discharged. In the sense amplifier, the tiny signal limited to the bit line is amplified to the power supply voltage. According to this readout operation, the phase change element in the high-impedance state generates heat due to the read current. The phase changes from the high-impedance state to the low-impedance state, and all the cells read out in the sense amplifier become low-impedance. In the sense amplifier, the signal read out on the bit line is amplified -20- 200527656 (17), and the output is external, so it is output at 1/0. Before that, the write driver is activated in a sense amplifier that reads out the data in which the phase change element of the memory unit is in a high impedance state. In the activated write driver, a high voltage is applied to the bit line by the write drive signal WRE at the time necessary for the reset operation, and the current necessary for the reset operation is passed through the bit line and the memory. The unit transistor flows into the phase change element. Thereafter, by interrupting the current, the phase change element is rapidly cooled, and the phase changes to a high impedance state. After that, the word line WL and the column selection line C0t / b are switched to the non-selection level, and the read cycle ends. Next, the write operation will be described. Fig. 7 is a timing chart of the write operation. According to the write instruction, the write address is sent to. Similar to the read operation, the column selection line C 0 t / b is activated, and at the same time, the precharging operation of the 7-bit line is performed. After that, the word line WL corresponding to the address is selected, and the bit line is discharged by the memory cell transistor and the phase change element. At this time, the phase change element generates heat by a read current, and changes phase from a high impedance state to a low impedance state. As a result, the phase change elements of all the memory cells connected to the sense amplifier change to a low impedance state. During this operation, the written data is transferred to the sense amplifier. Here, after rewriting the read data, the write driver of the sense amplifier that only corresponds to the data holding the high-impedance state of the phase change element of the memory cell in the sense amplifier row is activated. After that, in the activated write driver, a high voltage is applied to the bit line by a write start signal during the time necessary for the reset operation, and the current necessary for the reset operation is passed through the bit line, The memory cell transistor flows in the phase change element. After that, by switching off the current, the phase change element is rapidly cooled to change phase-21-200527656 (18) is in a high impedance state. After that, the word line WL and the column selection line C0t / b transition to the non-selection level, and the readout period ends. In this structure, when the word line is selected to read the data of the memory cell, all the data of the memory cell are set to the low impedance state, and then written to the high impedance state. The advantages of this are as follows: (1) When reading, the bit line pre-charging level can be set to a high level, which can increase the amount of signal read from the sense amplifier, and can achieve high-speed and stable read operations. . (2) Conventionally, the write driver that needs to set and reset the driver can only be composed of the reset driver, while the circuit structure can be simplified, and the layout area and chip area can be reduced. (3) Since the high-impedance state is written again during reading, the reliability of the data due to data destruction during the reading operation can be reduced. (4) Degradation of the record-keeping characteristics of the phase-change element, such as high-speed operation at 125 ° C or higher and long-term storage, becomes possible. < Embodiment 2 > Next, Embodiment 2 will be described. The circuit and cross-sectional structure of the memory cell of the second embodiment are the same as those of Figs. 3 and 18, and descriptions thereof are omitted. In this structure, the bit line precharge level at the time of reading uses a voltage higher than the voltage Vset or Vreset which does not cause a phase change in the phase change element. In this operation, in order to increase the read signal amount, although the bit line pre-charge level is set to a high level, 'the phase state of the phase change element may be broken based on the read operation'. Set and reset again. • 22- 200527656 (19) Figure 8 shows the structure of the sense amplifier block SAB of this embodiment. The memory cell array MCA and the character driver RDEC are the same as those in the previous embodiment. The sense amplifier block SAB is formed by a bit line selector BLSEL and a write driver WD for setting and resetting phase change elements and amplification, and a data amplifier sense bit SA of a bit line BLSA. FIG. 9 shows the circuit configuration of the write driver WD. The write driver WD is based on the data of the set enable signal WSE and the reset enable signal WRE and the sense amplifier SA, and the current necessary for setting and resetting is sensed by the sense amplifier bit line BLSA and the memory cell transistor. Supply to phase change element. The structure of the write driver is different from that of the aforementioned embodiment, and it is provided with a write driver for increasing and decreasing the resistance of the phase change element. Next, a read operation of the array structure will be described. Figure 10 is a timing diagram of the read operation. As in the previous embodiment, the column selection line C Ot / b corresponding to the input address is activated according to the read command. After that, it is connected to the bit line of the sense amplifier SA. In the figure, the bit line B L 0 and the bit line B L S A in the sense amplifier are both set as the bit line precharge level VR. In this embodiment, the potential difference between the precharge level VR and the source line SL of the memory cell MC may be a voltage that circulates a current necessary for the phase change element to change from a high-impedance state to a low-impedance state. It is a voltage at which a low impedance state becomes a high impedance state. Conversely, the voltage may be a voltage near a voltage in which the high impedance state is indeed reduced. In this case, it is not necessary to cause the phase change element to change from a high impedance state phase to a low impedance state. For example, in the example of the figure -23- 200527656 (20), the pre-charging signal PRE becomes a non-selected state while the 'character line WL is selected. According to this bit line BL and the bit line BLSA in the sense amplifier, the memory cell transistor MT and the phase-change impedance PCR are used to discharge electricity. At this time, when the phase change impedance PCR of the memory cell is in a low impedance state, it is rapidly discharged. On the other hand, "when the impedance is in a high impedance state," it is slowly discharged. In the sense amplifier ', the tiny signal appearing on the bit line is amplified to the power supply voltage. According to this readout operation, the impedance 値 of the phase change element of the memory cell unit connected to the sense amplifier does not necessarily maintain the impedance state before readout. That is, the memory data is destroyed by the reading action. Meanwhile, in the sense amplifier, the signal read out from the bit line is amplified and output to the outside. Before this, the driver is activated in a sense amplifier that reads out the data of the phase change element of the memory cell in a high impedance state. In the activated write driver, a high voltage is applied to the bit line by writing a drive signal at a time necessary for the reset operation, and the current necessary for the reset operation is passed through the bit line and the memory unit. The transistor flows into the phase change element. After that, by blocking the current, the phase change element is quenched, and the phase changes to a high impedance state. After that, the column selection line COt / b and the word line WL are changed to non-selection levels, and the readout period ends. Next, a write operation will be described. Figure 11 is a timing diagram of the write operation. According to the write instruction, the write address is sent to. Similar to the read operation, the column selection line c 01 / b is activated, and at the same time, the bit line is precharged. After that, the word line WL corresponding to the address is selected, and the bit line is discharged by the memory cell transistor and the phase change element. At this time, the phase change element generates heat by reading the current, the phase changes from the high impedance state to the low impedance -24- 200527656 (21) state ', and the phase change from the low impedance state to the high impedance state, the state before reading destroyed. Between this action, the written data is sent to the sense amplifier. Here, after the read-out data is rewritten, the reset driver written in the driver is selected among the sense amplifiers that hold data corresponding to the high-impedance state of the phase change element of the memory cell in the sense amplifier column. On the other hand, among the sense amplifiers which hold the data of the low-impedance state of the phase change element corresponding to the memory cell in the sense amplifier row, a set driver written in the driver is selected. After that, in the activated write driver, in the time necessary for the reset operation, by resetting and setting the write start signal, a high voltage is applied to the bit line, and the current necessary for the reset and setting operation is The bit line and the memory cell transistor flow through the phase change element. Thereafter, by blocking the current, the phase change element is quenched and the phase changes to a high impedance state or the phase changes to a low impedance state. After that, the column selection line C0t / b and the word line WL are changed to the non-selection level, and the writing cycle ends. In this structure, when the word line is selected to read the data of the memory cell, by setting all the data of the memory cell to a low impedance state, it has the following advantages: (1) When reading, the bit can be set The pre-charging level of the element line is set to a high level, which can increase the amount of signals read out from the sense amplifier, and can achieve high-speed and stable read-out operations. (2) The setting range of the pre-charging level has degrees of freedom, while the power supply design becomes easy, it can also cope with power supply changes based on noise and so on. (3) By rewriting the read data, the reliability of the data based on the read operation can be reduced. (4) Deterioration of the record-keeping characteristics of the phase change element, such as high-speed operation at a temperature of 125 ° C or higher and long-term storage, are possible. -25- 200527656 (22) In the first and second embodiments, although the read voltage is set to a voltage higher than Vset or higher than Vreset in the phase state change of the phase change element, it is operated at a voltage lower than this. In this case, as in Examples 1 and 2, it is possible to perform a rewrite operation. In addition, in this case, it is not necessary to rewrite for the reading operation, so it can be rewritten at a specific number of times, for example, the number of times that can be read] / 10 times, or after a specific operation time has passed Action is also possible. In this case, as in Embodiments 1 and 2, it can prevent the destruction of data caused by thermal interference and interference during operation, and can reduce the number of rewrites compared with the number of reads. It can also improve the phase change. Advantages of component rewrite tolerance. < Embodiment 3 > Next, a description will be given of an array structure in which reliability of existing data is improved. As described above, the phase change element in the reset state is subject to thermal interference and may cause a phase change to the set state based on a read operation or an action at a high normal temperature. On the other hand, the possibility that the phase change element in the set state causes a phase change to the reset state is considered to be considerably less than the possibility that the phase change element in the reset state causes a phase change to the set state. Therefore, by keeping the redundancy of plural memory cells and storing 1 bit of data, the phase change element can improve the reliability of the stored data. Fig. 12 is an embodiment of the present invention. Bit lines BL 0 0, BL 0], BL02, BL03 .... and 8B] 0, 6B11, 8B12, 3B13 ... points 5 [[connected to the memory of the previous Figure 2 The body cell array MCA is also constructed of the billion cell body arrays MCA 0 and MCA 1. Bit lines BL 0 0, BL 0], -26-200527656 (23) BL 0 2, BL 0 3 ... sense amplifier block SAB 0 and bit lines BL10, BL11, BL12, BL13 are connected The sense amplifier block SAB] may be the circuit structure of the sense amplifier block SAB of any of the foregoing embodiments. Data input and output lines 1/00 are provided by the sense amplifier block SAB0, and data input and output lines I / O 1 are provided by the sense amplifier block SAB. 1 is output as a complementary signal (t / b). The output signal line is input to the logic sum block ORB. Logic and block 0 RB uses these input signals to output external output data DOt / b. In addition, the logic OR block ORB transmits the externally written data DIt / b to the sense amplifier blocks SABO and SAB 1. Next, a read operation in this embodiment will be described. The memory cell arrays MCA 0 and MCA 1 are activated at the same time as one address is input. The signals read by the memory cell M c at the specified addresses at this time are: the signals read by the memory cell MC of the memory cell array MCA 0 are sensed and amplified by the sense amplifier block SAB0, The signal read by the memory cell MCT of the memory cell array MCA 1 is sensed and amplified by the sense amplifier block SAB 1. At this time, in the sense amplifier block, data is output according to the relationship between the phase state of the memory cell MC in FIG. 13 and the output voltages of the complementary signals I / 0 * t and l / 0 * b. That is, when the phase state is a high-impedance state (Reset), the input / output signals I / OO 01 and I / Ο 1 t are in a 状态 'state, and in the low-impedance state (S et), the input / output signals I / 〇 t, I / Ο] 6 becomes L: state. And 'in the logic and block 〇RB that accepts these input and output signals, perform the logical sum of the input and output signals I / 〇0 t and I / 〇1 t' and output the external output data D 01 / b ° Figure 3 Display the input and output signals] and I / 0] t and the relationship between the external output data -27- 200527656 (24) data D0t. As shown in the figure, when one or both of the input / output signals I / 〇〇t and I / 〇11 are Η, the state of the external output data is Η ′. If the state of the phase change element of the memory cell is changed, one or both of the memory cells of the read memory cell array MCA 0 or MCA 1 are in a high-impedance state (when Res e0, then The external output data D 0 t becomes Η. Next, the writing operation of this structure will be described. At the time of writing, the written data is input to the logic OR block ORB by an external input data signal DIt / b. The logic OR block ORB In the process, the external input data signal DIt / b is transmitted to the input / output signal I / O 〇t, I / O Ob, and the input / output signal I / O It 'I / Olb through switches. These input and output signals are sent separately. To the sense amplifier blocks SAB 0 and SAB 1. In the sense amplifier blocks SAB 0 and SAB 1, the same as the sense amplifier block SAB of the previous embodiment, the memory is aligned with the memory cell arrays MCA0 and MCA1. The unit performs the operation of writing data. Next, the advantages of this structure will be explained. In the phase change memory, it is possible to prevent the destruction of data caused by the phase change due to high temperature standby or continuous readout, etc., or defective bits. Lowered the reliability of the data caused by the temperature drop or bit drop, etc. It is possible to perform high-speed operation and long-term storage of the phase change element whose record retention characteristics are deteriorated, such as 1 2 5 ° C or more. Here, although 2 Each memory cell MC records 100 million bits, but it can also be a structure that stores in more than two memory cell MCs and outputs the logical sum of the read result. In this case, only 3 There is a high-impedance state, and by outputting Η ', the reliability of -28- 200527656 (25) liters of data can be improved. The operations shown in Fig. 10 and Fig. 11 as described so far Although the reliability is greatly improved, the read voltage is set to a voltage higher than Vset or higher than Vreset when the phase state of the phase change element is changed. Therefore, the read operation must be performed again during the read operation, and the power consumption of each cycle In the embodiment described next, in the same circuit structure, in order to reduce power consumption, the case where the read voltage is set to a voltage lower than Vset, Vreset of the phase state of the phase change element will be described. In this case Even if the reading operation is performed, the data will not be destroyed in each reading operation, and the rewriting operation can be performed in a specific operation cycle. Therefore, low power consumption can be achieved. Even in this case, it can be prevented from being caused by heat. In addition to the destruction of data caused by interference and interference during operation, compared with the number of readouts, the number of rewrites can be reduced, and the rewrite resistance of the phase change element can be improved. In addition, the circuit structure can be the aforementioned embodiment 1 ' One of 2 and 3. That is, the rewrite operation is performed only in a specific period, so it can be achieved by activating the reset enable signal WRE and the set enable signal WSE of individual embodiments only in a specific period. For example, by using a logic circuit as shown in FIG. 22, a reset signal WRE and a set write signal WSE are generated to perform a rewrite operation, and the rewrite operation is realized in a specific operation. In this figure, the rewrite enable signal RW indicates a signal for performing a rewrite operation on a select memory cell on a select character line. The memory pad selection signal MSB is to decode the input address and display the signal in a specific address range. Regardless of the read operation and write operation, corresponding to the input address, one of the memory pad selection signals on the memory array. The MSB is chosen. Reset time specified pulse -29- 200527656 (26) ITReset is a pulse that specifies the write time to reset the write operation. The same stack setting time specified pulse TSet is a pulse of write 7 which defines the setting write operation. Fig. 23 shows an operation example of the circuit structure. As usual, the memory pad selection signal M S B is changed to the active state. For example, after this low-potential state, when the write start signal is activated, the pulse TReset is specified by this signal and reset time to reset the start signal WRE. Similarly, the set-start WSE is activated by setting the time-set pulse TSet. Conversely, in the case where the rewrite activation signal RW is inactive ', even if the memory pad selection signal MSB becomes activated, neither the activation signal WRE nor the activation signal WSE is set. That is, the rewrite operation can be controlled by the rewrite start signal RW to illustrate the advantages of this structure. Rewrite is not performed every time a read operation is performed 'only when a specific rewrite start signal is activated, thereby reducing the number of rewrites and improving the reliability of the phase change film. In addition, in the reading operation, there is no possibility that the data will be destroyed. Since the reading operation is accompanied by the rewriting operation, the cycle time can be shortened. The power consumption of the re-write operation can be removed, so it can also achieve power consumption. Furthermore, compared with a case where only a non-destructive read operation is performed, a rewrite operation in a specific period has an advantage that the reliability of the memory can be improved. Next, "the method for generating the rewrite enable signal RW and the embodiment in which the rewrite operation is performed in the aforementioned specific cycle will be described. Fig. 24 shows the memory chip of the input pins or instructions used for the REF operation in addition to the normal read and write instructions: ground, time, and time. Fig. 23 shows the status of some signals being activated. Reset activation and activation can be, but will not further reduce, borrow the information about the actual Jane 30-200527656 (27) single block diagram. The memory array M A is formed by a plurality of memory cell arrays MC A, and is adjacent to the individual memory cell arrays MC A and is provided with a sense amplifier block SAB. On one end of the memory array MA, a pre-decoder RPDEC for driving and controlling an address line for the row decoder RDEC and a column decoder CDEC for outputting a column selection signal are arranged. The column decoder is provided with an array transfer memory. External output of data output from the volume array MA or data input section I / O-CTL for data input from the outside. The memory chip is provided with an externally input address AO, A 1 ... or an instruction address buffer INPUT Buffer, and a DQBU ffer for inputting and outputting external data, and an external voltage VCC and Ground potential GND to generate internal voltage word line selection level VWH, word line non-selection level VWL, sense amplifier power VDL, reset write voltage VfWR, set write voltage VWS, peripheral circuit power voltage VCL, The internal power supply generating circuit VG, which has a potential of approximately VSS and a source potential VS. This structure is characterized in that the input command includes a rewrite command REF or a rewrite pin REF for performing a rewrite operation. Fig. 24 is a block diagram of a sense amplifier and a memory cell array MCA, which are the same as Figs. 1 and 2 described above. Next, the operation of this embodiment will be described. Fig. 25 is an operation example in which the structure of Fig. 1 is applied to the sense amplifier block SAB of Fig. 24. When a read command Read is input from the outside, the column selection signal is activated according to the address input at the same time. In addition, the pre-charge signal PRE of the sense amplifier block corresponding to the address is activated. As a result, the bit line is precharged to the read level VR. At the same time, the bit line separation signal connecting the sense amplifier SA and the sense bit line BLSA also becomes -31-200527656 (28) in a high potential state. After that, while the bit line precharge signal P R E is deactivated, the word line W L is changed from the non-selected state V W L to the selected state V W 依据 according to the input address. At this time, when the phase change element of the memory cell MC is in a low-impedance state, as shown by the dotted line in the figure, it suddenly changes to the source line SL potential VS. On the other hand, in the high-impedance state, the bit line readout level is maintained near V R. After a certain period has elapsed, when the sense amplifier generates a sufficient signal, the bit line separation signal BLI is changed to a low voltage V S S, and the sense amplifier and the sense bit line B L S Α are separated. After that, the sense amplifier SA activates the signal SE / SEB through the sense amplifier, and amplifies the tiny signal read by the memory cell MC to the sense amplifier power VDL. After that, it is transferred to the I / O control and DQ buffer. Before and after, the activated character line WL... Changes to the non-selection level V WL. After that, the sense amplifier becomes inactive by making the sense amplifier activation signal inactive. At the same time, the column selection signal is switched to the non-selection state, and the readout period ends. Next, the operation when the rewrite command REF is input will be described. The address input at the same time as the instruction or the address generated by the address counter ADD-C in the memory chip CHIP is activated until it is read out in the sense amplifier, which is the same as the previous read operation. Here, the rewrite start signal R W is activated to a high potential state in accordance with the rewrite command R E F. As shown in the operation waveform diagram in Figure 23, the write start signal RW is activated, and the reset start signal WRE is activated by the memory pad selection signal corresponding to the selected address and the reset time prescribed pulse TRe set. Once the reset enable signal is activated, the data held in the sense amplifier corresponds to a high-potential state, that is, I / Ot setting -32-200527656 (29) is a high-impedance state and I / Ob is set to a low-potential state In the write drive WD, the reset voltage is applied to the memory cell MC through the sense amplifier bit line BLSA and bit BL0, and the electrical reset start signal necessary for the circulation write only specifies the pulse at the reset time. After the time determined by TReset is activated, it transitions to a low potential state and the reset operation ends. The operation after the operation is the same as the aforementioned reading operation. In this operation, it is assumed that the rewrite operation is only a reset operation with a short write time. This is because the thermal interference of phase change memory or the interference of reading action, the error setting of the resetting component into the setting state is more likely to occur than the wrong resetting of the setting state and the resetting state. Therefore, compared with the read cycle tRC, the rewrite cycle tRC7 is performed in this operation. Although the rewrite operation is performed, only the reset of the write time is short, so the cycle time can be extended. Shares are reduced. The advantages of this embodiment will be described. In the normal read and write operations, by setting the rewrite operation, the rewrite operation can be performed before the data based on the read operation is destroyed, which can improve the reliability of the data. Further, since only the reset operation is performed during the reoperation, there is an advantage that the amount of extension of the operation due to the rewrite operation can be reduced. Next, the operation of the case where the sense amplifier block of FIG. 8 is applied to the sense amplifier block of FIG. 24 described above. The 2nd 5th shows the operation example of this structure. The feature of this structure is to perform two operations of a reset operation and a set operation based on a command from the outside as a rewrite operation of the memory cell data at a specific address. Regarding the read cycle when a read command is input, it is the same as that in Fig. 25. Next, the actuator streamed. Write in the action. The state changes to the action. In addition to the action, you can write into the S AB picture system. Input operation and fetch instruction. Explanation -33-200527656 (30) The action when the rewrite command REF is input. The address input at the same time as the instruction or the address generated by the address counter ADD-C in the memory chip CHIP is activated until it is read out in the operation of the sense amplifier, which is the same as the aforementioned Fig. 25. Here, according to the rewrite command REF, the rewrite start signal RW is activated to a high potential state. As shown in the operation waveform diagram in Fig. 23, the write start signal RW is activated again, and the reset start signal WRE is activated by selecting the MSB signal corresponding to the memory pad at the selected address and the reset time prescribed pulse TReset. Once the reset enable signal is activated, when the data held in the sense amplifier corresponds to a high-potential state, that is, when I / Ot is set to a high-impedance state and I / Ob is set to a low-potential state, it is written into the drive WD The reset voltage is applied to the memory cell MC through the sense amplifier bit line b LSA and bit line BL 0, and a current necessary for writing is passed. The reset start signal is only activated after the time determined by the reset time prescribed pulse TRe set, and then it is switched to the low potential state, and the reset operation ends. Similarly, as in the operation waveform of FIG. 23, the start signal RW is re-written. The signal is activated by setting the corresponding signal MSB of the selected address and the set time specified pulse T S e t to activate the set signal W S E. Set start signal WSE — Activated, in the case where the data held in the sense amplifier is in a low impedance state, that is, I / 〇t is set to a low-potential state, and I / 0 bg is affected when it is set to a high-potential state. In the driver w D, a set voltage is applied to the memory cell MC through the sense amplifier bit line BLSA and the bit line BL 0, and a current necessary for writing is passed. The setting start signal w S E is activated to a low-potential state after the time determined by the set pulse time s s t is activated only, and the setting operation ends. After the writing operation is completed -34-200527656 (31) The operation 'is the same as the previous reading operation. In this operation, as compared with the read cycle t R C, the cycle t R c for performing the rewrite operation is not only reset but also set. Therefore, a relatively long time is required, for example, 50 ns to] " < The advantages of this embodiment will be described. In addition to the normal read and write operations, by setting the rewrite operation, before the data based on the read operation is destroyed, the rewrite operation can be performed, which can improve the reliability of the data. Furthermore, in the rewrite operation, 'not only the reset operation but also the setting operation, compared with the foregoing embodiment' has the advantage that the reliability of both data is improved. Next, a structure for performing a rewrite operation on the memory chip CHIP by using an error prediction and detection function of the memory unit data will be described using an embodiment. Fig. 27 is an example of a block diagram of a memory chip with an error detection function added to the memory chip. Compared with the foregoing Fig. 24, it is characterized in that the address counter can be omitted. The other structures are the same as those in Fig. 24. Figure 28 is a block diagram showing the memory cell array MCA and its peripheral circuits. Same as the first figure, it is adjacent to the memory cell array MCA, and is arranged by driving the row decoders RDEC, bit lines BL 0, BL 1, BL 2, ... of word lines WL0, WL1, WL2, ... There is a sense amplifier block SAB for reading data recorded in a memory cell. Furthermore, in this structure, a copy bit line BL_REP which is arranged adjacent to the bit lines BL0, BL], BL2,... Is arranged in the memory cell array MCA. Furthermore, a sense amplifier block circuit SAB_REP for a replicated bit line is arranged corresponding to the replicated bit line. The copy of the sense amplifier block SAB_REP for the bit line output is -35- 200527656 (32) RW0, which is the original signal of the rewrite enable signal RW. The rewrite enable signal RW is converted from the rewrite enable original signal RWO to a pulse width as shown in FIG. 29 and output. FIG. 30 shows a configuration example of the memory cell array MCA of FIG. 28. Regarding the bit lines for copying, all the memory cell lines MC_REP are arranged for the word lines. The copying memory cell MC_REP has, for example, the same structure as the conventional memory cell MC in Fig. 3. However, it is characterized in that the phase change elements in all the memory cells on the bit line are set to a high impedance state. Fig. 31 shows an example of a block diagram of the above-mentioned replication sense amplifier block SAB-REP. The bit line pre-charging circuit BLPC is a circuit that pre-charges the bit line to a desired level VR during a read operation, for example, by pre-charging the MOS transistor of VR as shown in FIG. 32 and during standby , Set to MOS transistor with source line potential VS. The write drive WD has the same structure as the aforementioned FIG. 5 (a). The sense amplifier circuit SA_REP is a circuit that amplifies the tiny signal read out on the bit line BLSA to the amplitude of the sense amplifier power VDL, and outputs the rewrite to start the original signal RWO and write data to the driver WD. . Fig. 33 shows a circuit configuration example of the sense amplifier SA_REP. In this sense amplifier, a reference VREF-REP for reproduction is used as a reference level. VREF — REP is set at a high level compared to the VREF used in the aforementioned sense amplifier block S AB. As a result, compared with the usual sense amplifier block, even in the case of calling a memory cell with a relatively high impedance state, it can be easily read in a low impedance state, and it is possible to detect the destruction of read data in a high impedance state. In the present sense amplifier, in the case of reading a low impedance state, the bit line on the reference side is outputted as a rewrite start signal R W 0 by an inverter -36-200527656 (33). Describe the advantages of this construction. By arranging the memory unit for copying in the same memory unit as the usual memory unit, the influence of the deviation can be reduced, and the memory unit having the same characteristics as the ordinary memory unit can be used. Advantages of observation data retention characteristics. By setting the reference level of the sense amplifier for copying to the high-impedance side, it is usually possible to detect the data by copying the memory cell before the memory cell is changed from a high-impedance state to a low-impedance state based on readout. Therefore, it has the advantage of improving the reliability of the memory data. The receiver 'will use FIG. 34 to describe a method for generating a rewrite start signal using the RR cell array described in the third embodiment. Figures 3 and 4 show the memory cell array MCA and the sense amplifier block S AB and OR logic block ORB 2 of the previous Figure 2]. The OR logic block ORB2 is the same as that in the foregoing embodiment 3. By acquiring OR logic for reading data, errors caused by the transition from the high-impedance state to the low-impedance state can be reduced. In this structure, it is characterized in that if the data between the two read data 1/00, I / O] is different, the high-impedance state is written to the two memory cells and then rewritten. Enter the output circuit of the original signal RW0. The other structures are the same as those of the third embodiment. The advantages of this configuration will be explained. In this design, the copy memory unit is not used. Instead, the memory unit is used to memorize the actual data. Therefore, the data error detection can be performed without being affected by the characteristics of the units. Furthermore, 'the two memory units memorize the same data, and by using OR logic, not only can the correct data be output', but also the correct data can be written, which can achieve high reliability of the memorized data. General -37-200527656 (34) Often, when two memory units are used, it is difficult to detect which memory unit has the correct information by detecting different data to detect the error. However, in the case of using a phase change element, the impedance state of the phase change element is basically an error in which the reset state (high impedance state) is changed to the set state (low impedance state). Therefore, if the impedances of the two memory cells are different, and an error is detected, it can be known that a data error has occurred in the memory cells that are in the set state. The operation using the circuit structure of Fig. 28 will be described with reference to Figs. When a read command is input, the operation when no error is detected is the same as that in the above-mentioned Fig. 25. On the other hand, in the operation in the second cycle of Fig. 35, an error may be detected at the same time as the display and reading operations. First, from the input command until the data is read on the bit line, until the sense amplifier holds the data, it is the same as the normal read operation. Here, when the phase change element of the duplicated memory cell changes from a high-impedance state to a low-impedance state, the output node I / 0_REPt / b of the duplicated sense amplifier that reads the duplicated bit line detects a low-impedance state. When a low-impedance state is detected, the rewrite enable original signal RW0 is activated, and the rewrite enable signal RW is activated. Rewrite activation signal RW—is activated, senses the reset activation signal WRE and the sense amplifier output I / 0_REPb for copying the bit line, and the write driver WD applies a reset write voltage VWR to the bit line. The reset write voltage is applied only during the period during which the reset enable signal WRE is activated, and it drops immediately. As a result, the copy memory unit is rewritten to a high-impedance state. This operation is the same. For the memory cell MC that stores data, but also for the memory cell whose read impedance state is high impedance state, and the reset write action for copying the memory unit -38-200527656 (35) Similarly, a reset write operation is performed. As a result, the high-impedance memory phase change element of the memory unit that stores data also performs a rewrite operation, and the data retention characteristics are improved. Describe the advantages of this action. In this operation, only the reset write operation with a short fring time can be entered. Therefore, the rewrite operation can be performed within the cycle time of the normal read operation, and it is possible to mask the failure caused by the rewrite operation. The advantages of access. The description of the “receiver” is the same as the embodiment shown in FIG. 27, so that the memory chip CHIP has an error detection function, and further has a rewrite operation to prevent the external memory controller from issuing the memory chip CHIP. The structure of the busy pin WAIT for access request. Fig. 36 is characterized in that the structure shown in Fig. 27 is provided with a busy pin WAIT as an output pin. The structure other than this is the same as that of FIG. 27 described above. This structure is different from the foregoing embodiment, and is suitable for a case where the cycle time is longer than a normal read cycle in a read cycle accompanied by a rewrite operation. Figure 37 is a block diagram showing the output method of the busy pin WAIT. The busy pin W A I T is a high-potential state and a low-potential state by receiving a rewrite enable signal, and it is used for the external memory controller 'to convey that the memory cannot be used. Therefore, compared with the read operation, even when the time required for the rewrite operation is long, the state is transmitted to the memory controller, which has the advantage of preventing data conflicts and data loss. An example of the operation waveform diagram of this structure will be described with reference to Figs. This operation is an example of operation waveforms in the case of using the memory cell array MCA and its surrounding circuit blocks with the duplicated memory cells as shown in Fig. 28 of the foregoing embodiment. The read operation without rewriting in the first cycle of the figure is the same as in the previous embodiment -39- 200527656 (36). Next, in the second cycle, an example of performing a rewrite operation in conjunction with a read operation. In this operation, it is the same as the previous embodiment until the signal read out by the memory unit is kept in the sense amplifier. As shown in Figure 35 of the example of the operation waveform diagram of Figure 28 above, when the read data of the memory cell on the copy bit line is read from the high impedance state to the low impedance state, the signal of the low impedance state I / O-REPt, which is output at the output node of the sense amplifier. Thereby, the rewrite enable signal RW is activated. Rewrite start signal RW — is activated, reset start signal WRE is activated, and the reset read operation is performed on the unit that reads the reset status. At the same time, the setting start signal WSE is also activated, and the setting writing operation is performed on the unit that reads the setting status. Reset start signal WRE becomes inactive after the reset write time. On the other hand, in the setting writing operation, a writing time of 50 ns to 1 μs or more is required, during which the setting start signal is maintained to be activated. After a certain period of time has elapsed, the setup enable signal WSE is deactivated and becomes standby. During this writing period, the memory chip cannot be accessed externally. In order to communicate it to the controller, the busy pin WAIT is changed to a low potential state. This prevents the issuance of action instructions from the external controller. Describe the advantages of this structure. In the rewrite operation, not only the reset write, but also the setting data can be used to improve the reliability of the two data. Furthermore, by setting the busy pin, it is possible to suppress the issuing of instructions from the controller during a period when the memory chip cannot be accessed, and data conflicts and disappearance can be prevented. Next, a modification of the foregoing embodiment will be described with reference to Figs. In this structure, '' is a write operation and only a reset operation is performed, which is a characteristic of this. -40 _ 200527656 (37) In the aforementioned write operation, only the reset start signal WRE is activated, and the reset write operation is performed on the memory cell that reads the reset state. On the other hand, for the memory cell that reads the set state, no write operation is performed. In order to prevent the external controller from issuing a command between reset and write operations, the busy pin WAIT is changed to a low potential state. As a result, the external controller does not access the memory chip. The advantages of this configuration will be explained. In addition to the prevention of data conflict and disappearance by setting the busy pin, in this structure, it can be completed with a relatively short write time of about 50ns. Only the reset operation and the rewrite operation can be performed, so that the memory can be made. The time during which the chip is in the busy state becomes shorter, which has the advantage of shortening the inaccessible time. Next, a description will be given of an example of a case where multiple memory and OR units are combined. Figure 40 shows the distribution of the impedance 値 in the case of using a phase change element for multiple memory. A high-impedance state is assigned to an impedance state R3 5 1 1 ′, an impedance state R2′10 ′, an impedance state R] 5 0 0 ′, and an impedance state RO′Ol;. When allocated in this manner, there is an advantage that even if it is changed to the adjacent state, the possibility of both bits becoming errors is reduced. In the case of using a phase change element, the impedance state of the phase change element is basically an error in which the reset state (high impedance state) changes to the set state (low impedance state). Therefore, an OR cell array in which two cells store the same data is used to realize an array capable of achieving high data reliability. Figure 41 shows the relationship between the impedance state of the phase change element of the two memory cell arrays MCA 0 and MCA], and the memory data MLBt / MSBt. As explained earlier, it is a structure in which the data of a memory cell in a high-impedance state is output as true in two memory cells. For example, remembering that the state of the memory cell of the cell unit array MC A0 is R3, even though the state of the memory cell of the memory cell array MC A 1 is any one of the types of the output data M LB t / MSB t also becomes, 1, /, 1 '. The structure of the array to achieve this will be described. Figure 42 shows a block diagram of the peripheral circuit of the memory cell array. A memory cell array MCA 1 and MCA0, a sense amplifier block S AB — M, SA B — M, and an OR logic part ORB — M are arranged. Figure 43 is an example of a block diagram of a sensor amplifier block SB-M. The same as in the previous embodiment, a bit line selection circuit BLSEL, a write driver WD_M, and a sense amplifier circuit SA are provided. The input / output section is provided with an I ○ gate I 〇 G that converts and reads data. In addition, the sense amplifier circuit can be read at different times, and is configured with three sense amplifier circuits using three reference levels VREF0, VREF1, and VREF2. Fig. 4 shows the circuit structure of the write driver WD_M arranged in the sense amplifier block SAB_M. The write voltage is determined by I / 0 0, I / O 1, 1/0 2, 1/03 corresponding to the impedance state of the memory cell, and the write period is determined by the write enable signals W0, W], and W3. The circuit construction. In the 10 gate, referring to the three sense amplifiers SA01t / b, SA01t / b, and SA2t / b, corresponding to the impedance state of the memory cell, at the output node I / O 〇, 1 / 〇], 1 / One of the outputs of 02, 1/03. Figure 46 is a block diagram of the logic part of the OR. The read block RE_M is a circuit block that detects the data read by the two memory cell arrays M C A 0 and M C A 1 and outputs incorrect data. Write block WE — M is 200527656 (39) when the data input from the outside is written back, or the correct data is written by error detection, the corresponding impedance state is output to the memory cell array MCA0 ' Signal I / Ο] 1, I / 〇 0 1, I / 〇 〇2, I / Ο 0 3, and for the memory cell array 歹 "MCA], output signals corresponding to the impedance status 1/010, I / O Π, 1/012, I / O 1 3. The error detection circuit DET detects the presence or absence of errors by comparing the data read by the memory cell array 歹 IJ MCA. In the case of errors, the output is re-written to start the original signal RW0. Fig. 47 shows a specific circuit configuration example of the read block RE_M. As shown in the figure, the most significant bit MLBt is a NAND logic that obtains NOR logic of 1/000 and 1/010 and a NAND logic of 1/001 and 1/011. Similarly, the least significant bit MSBt is a NAND logic that obtains the output of NAND logic of 1/003 and 1/013 and the output of NOR logic of 1/00 and 1/010. In this way, the conversion that satisfies the table of Fig. 41 can be realized. Figures 4 and 8 show an example of the circuit structure of the write block WE_M. These are the reverse conversions of the previously read blocks R: E-M. Fig. 49 shows a circuit configuration example of the error detection circuit DET. For the memory cell arrays MCA0 and MCA1, the corresponding output signals 1/000 and 1/010 and I / O] 0 and 1/01 1 and 1/0 02 and I / O〗 2 Ex- The output of OR logic is obtained by performing OR logic. As a result, in the case where a certain output signal is inconsistent, the original signal RW 0 which becomes the rewrite start is activated. Explain the advantages of this structure. In the multi-memory memory method where margins become smaller, by combining OR cell arrays that store the same data in a plurality of memory cells, the reliability of the memory data can be improved 'and the retention time can be made longer. In addition, an additional error detection circuit is added. By rewriting when an error is detected, it is possible to correct and record the errors of the data of the billion-body unit, thereby improving the reliability of the data. Describe the voltage conditions. The word line selection level can be equal to the external voltage-43- 200527656 (40) VCC]. 8V or 1.5V, or 2.5V or 3.0V after internal boost. By using high voltage, the memory The current driving force of the unit transistor becomes stronger, so that even if the size of the memory unit transistor is small, the current can be rewritten, so it has an excellent bottom that can realize a small single-area area of the memory. The sense amplifier power V D L and the peripheral circuit power V C .L can be 1.8 V, 1.5 V, or 1.2 V. By reducing the voltage, power consumption can be reduced. Setting the reset write voltage VWR to a potential equal to the external voltage VCC is more desirable in reducing power consumption. [Brief description of the drawings] Figure 1 is a structural diagram of an array and peripheral circuits according to Embodiment 1 of the present invention. Figure 2 is a structural diagram of a memory cell array. Figure 3 is a structural diagram of a memory unit. Fig. 4 is a circuit configuration example of a bit line selector. Fig. 5 is a circuit configuration example of a write driver and a sense amplifier. Fig. 6 is a waveform diagram of a read operation according to the first embodiment of the present invention. FIG. 7 is a waveform diagram of a write operation in Embodiment 1 of the present invention. Fig. 8 is a circuit configuration of a sense amplifier block in Embodiment 2 of the present invention. Fig. 9 is a circuit configuration example of a write driver. Fig. 10 is a waveform diagram of a readout operation according to the second embodiment of the present invention. FIG. 1 is a waveform diagram of a write operation in Embodiment 2 of the present invention. Fig. 12 is a diagram showing the structure of the array and its peripheral circuits in Embodiment 3 of the present invention -44-200527656 (41) Fig. 13 is a table showing the relationship between the memory cell data and output data in Embodiment 3 of the present invention. Figure 14 is a current-voltage diagram of the phase change memory. Figure 15 is a waveform diagram of the bit line's pre-charging level and voltage reduction action. Figure 16 is a current-voltage diagram of the phase change memory. Figure 17 is a current-voltage diagram of the phase change memory. Fig. 18 is a cross-sectional view of a memory cell of a phase change memory according to the first embodiment of the present invention. Figure 19 shows the lattice constants of the Ge2Sb2Te5 phase change material and the lower electrode material. Figure 20 shows the relationship between the reset current and the material of the lower electrode. Stomach 2 1 shows the relationship between the reset voltage and the film thickness of the phase change material when the phase change material changes from a crystalline phase to an amorphous state. Stomach 2 2 is a control method diagram showing reset activation signal and setting activation signal. Figure 2 3 shows the operation waveform legend of Figure 2 2. Figure 24 is a block diagram of a memory with a rewrite command. Fig. 25 is an example of the operation waveforms of the memory in Fig. 24. Fig. 26 is another example of waveforms of operation of the memory of Fig. 24; ^ 2 7 is a block diagram of the memory with self-rewrite judgment action function. Figure 28 is a block diagram of the main part of the memory array of Figure 27 in ^ 45- 200527656 (42). Fig. 29 is a structural example and operation waveform diagram of the write enable signal generating circuit. Fig. 30 is an example of the structure of the billion-body array in Fig. 27. Fig. 31 is an example of a block structure of a sense amplifier for copying bit lines. Figure 32 shows an example of a pre-charge circuit structure. Fig. 33 shows an example of a circuit structure of a sense amplifier for copying bit lines. Figures 3 and 4 are examples of the method of generating a write enable signal using a 0 R cell array. Figures 3 and 5 are examples of waveforms of the operation of the memory with self-rewrite judgment function. Figure 36 is a block diagram of the memory with self-rewrite judgment function and status output pins. Figure 37 is a block diagram of the busy line output pin output circuit. Figure 38 is an example of the waveforms of the memory operation in Figure 36. Fig. 39 is an example of another operation waveform of the memory of Fig. 36. Figure 40 is a diagram showing the impedance distribution and data transfer in the case where the phase change element performs multiple memory. Fig. 41 is a diagram showing an example of data mapping in a case where two multi-memory memory elements are used to form an OR cell array. Fig. 42 is a block diagram of a memory cell array and a sense amplifier and a logic section of 0 R when a multi-chip memory element and an OR cell array are combined. Figure 43 is a block circuit configuration example of the sense amplifier in Figure 42. Fig. 44 is a circuit configuration example of the write driver in Fig. 43. -46-200527656 (43) Figures 4 and 5 show examples of the input and output circuit structure shown in Figures 4 and 3. Fig. 46 is a block diagram of the OR logic section of Fig. 42; Fig. 47 is a block diagram showing the structure of the read data of Fig. 46. Fig. 48 is a block diagram showing the structure of writing data in Fig. 46. Fig. 49 is a diagram showing a configuration example of the error detection circuit of Fig. 46. [Symbol description of main components] upc: upper electrode, dwc: lower electrode plug, RDEC: row decoder / character driver, WL, WL0, WL1, WL2, WL3 ...: word line, BL, BL0, BL1, BL2, BL3, BL00, BL01, BL02, BL0 3, BL] 0, BL1 1, BL12, BL] 3…: bit line, BLSA: bit line in the sense amplifier, PRE: pre-charge signal, WRE: heavy Write start signal, WSE: Set start signal, SE: NMOS sense amplifier start signal, SEB: PMOS sense amplifier start signal, I / 〇t, I / Ob, 1 / 〇0t, 1 / 〇0b, I / 〇lt, I / 〇lb: input and output data lines, WD: write driver, SA: sense amplifier, SAB, SAB 0, SAB]: sense amplifier block, -47-200527656 (44) BLSEL: bit Line selector, MCA, MCA 0, MCA 1: memory cell array 歹 lj, VREF: reference level, COt ~ C3t, COb ~ C3b: 歹 ij select cloud number, MT: memory cell transistor, PCR: Phase change element, BLI: bit line separation signal, VWR: reset write voltage, VWS: set write voltage, ORB: logic sum block, DIt / b…: external input data line, D〇t / b: external output data line, V p, VR: bit line precharge level, TReset: specified pulse during reset, TSet: specified pulse during set, MSB: memory Pad selection signal, RW: rewrite enable signal, RPDEC: line pre-decoder, INPUT Buffer: input buffer, VG: internal power output circuit, DQ Buffer: input / output data buffer, I / O CTL: input / output Data controller, MA: memory array, REF: rewrite external command, -48- 200527656 (45) tRW: rewrite start signal pulse width, BL — REP: copy bit line, SA — REP: copy bit Sensing amplifier block for element line, RW — GEN: Rewrite enable signal generation block, RW 0: Rewrite enable original signal., MC — REP: Copy memory unit, B LP C: Bit line Pre-charge circuit block, VREF_REP: Reference level of sense amplifier for copying, I / O —REPt · • Output of sense amplifier for copying, WAIT: Busy output pin, WAIT_B: Busy output pin output buffer, R0 , Rl, R2, R3 ...: Phase change element Device impedance status, MLBt / b: Most significant bit, MSBt / b: Most significant bit, ORB_M: OR logic block -49-

Claims (1)

200527656 ⑴ 十、申請專利範圍 1 · 一種半導體裝置,其特徵爲:具有, 複數之字元線,及 複數之位元線,及 包含設置在前述複數之字元線與前述複數之位元線之 特定的交點之相變化材料之複數的記憶體單元,及 連接在前述位元線之感測放大器,及 連接於前述感測放大器,將第1資訊寫入前述記億體 單元之第1寫入驅動器; 在讀出動作之後,將前述第1資訊寫入前述記憶體單 元之其一。 2.如申請專利範圍第1項所載之半導體裝置’其 中,前述第1資訊係前述相變化材料之相狀態以非晶質狀 態所被記憶。 3 ·如申請專利範圍第1項所記載之半導體裝置,其 中,前述半導體裝置進而具有:連接於前述感測放大器, 將第2資訊寫入記憶體單元之第2寫入驅動器。 4 .如申請專利範圍第3項所記載之半導體裝置,其 中,前述第1資訊係前述相變化材料之相狀態以非晶質狀 態所被記憶,前述第2資訊係前述相變化材料之相狀態以 結晶化狀態所被記憶。 5 .如申請專利範圍第3項所記載之半導體裝置,其 中,在讀出動作之後,進行將第2資訊寫入於某一前述記 憶體單元之寫入動作。 -50- 200527656 (2) 6 . —種半導體裝置,其特徵爲:具有, 複數之字元線,及 複數之位元線,及 包含設置在前述複數之字元線與前述複數之位元線之 特定的交點之相變化材料之複數的記憶體單元,及 共通連接於前述各記憶體單元之源極線,及 第1資訊寫入時之源極線與位元線之電位差的絕對値 之第1電壓,及 讀出時之源極線與位元線之電位差的絕對値之第3電 壓; 前述第3電壓係比前述第1電壓高。 7.如申請專利範圍第6項所記載之半導體裝置,其 中,以感測放大器將讀出時之第1資訊予以讀出,對前述 記憶體單元進行再寫入。 8 .如申請專利範圍第 6項所記載之半導體裝置,其 中,前述第]資訊係前述相變化材料之相狀態以非晶質狀 態所被記憶。 9 .如申請專利範圍第6項所記載之半導體裝置,其 中,前述第1資訊係前述相變化材料之相狀態以結晶狀態 所被記憶。 10.如申請專利範圍第6項所記載之半導體裝置,其 中,具有前述第2資訊寫入時之源極線與位元線之電位差 的絕對値之第2電壓,第3電壓係比第]電壓及第2電壓 之兩者都高。 -51 - 200527656 (3) 1 1 .如申請專利範圍第6項所記載之半導體裝置,其 中,具有前述第2資訊寫入時之源極線與位元線之電位差 的絕對値之第2電壓,第3電壓係比第]電壓高,而比第 2電壓小。 ]2· —種半導體裝置,其特徵爲:具有, 複數之字元線,及 複數之位元線,及 包含設置在前述複數之字元線與前述複數之位元線之 特定的交點之相變化材料之複數的記憶體單元,及 包含前述複數之記憶體單元之第1記憶體單元陣列及 第2記憶體單元陣列,及 自前述第1記憶體單元陣列讀出資料之第〃 1感測放大 器方塊,及 自前述第1感測放大器方塊將資料輸出於外部之第] 資料輸出線,及 自前述第2記憶體單元陣列讀出資料之第2感測放大 器方塊,及 自前述第2感測放大器方塊將資料輸出於外部之第2 資料輸出線。 13. 如申請專利範圍第1 2項所記載之半導體裝置, 其中,具有取得前述第1資料輸出線與前述第2資料輸出 線之邏輯和之第1邏輯和電路。 14. 如申請專利範圍第I 2項所記載之半導體裝置, 其中,前述第1資訊係前述相變化材料之相狀態以非晶質 - 52 - 200527656 (4) 狀態所被記憶。 /·如申請專利範圍]項或第6項或第12項所記載 之半W目反衣置,其中,則述#请、體單元係由相變化材料與 選擇用開關所成。 16.如申請專利範圍第15項所記載之半導體裝置, 其中,源極線與位元線之電位_的絕對値之最大値,係在 1 . 8 V以下。 1 7 .如申請專利範圍第1 5項所記載之半導體裝置, 其中,前述相變化材料係包含Sb (銻)之材料,其膜厚 在 όΟηιτη以下 〇 18.如申請專利範圍第17項所記載之半導體裝置, 其中,前述相變化材料係包含Ge (鍺)、Sb (銻)及以 (蹄)之材料,膜厚在20nm以下。 ]9 .如申sra專利範圍地1 5項所記載之半導體裝置, 其中,電性連接前述相變化材料與前述選擇開關之電極材 料係使用鎢。 2 0 .如申請專利範圍第1 5項所記載之半導體裝置, 其中’在攝氏125度以上之周邊溫度中動作。 2 1. 一種半導體裝置’其特徵爲:具備有, 複數之字元線,及 與前述複數之字元線交叉之複數的第]位元線,及 與前述複數之字元線交叉,與前述複數之第1位元線 平行配置之第2位元線,及 配置在前述複數之字元線與前述複數之第]位元線之 -53 - 200527656 (5) 特定的交點之第1記憶體單元,及 配置在前述複數之字元線與前述第2位元線之特定的 交點之第2記憶體單元,及 配置在前述複數之第1位元線之各特定的線數之第1 感測放大器,及 配置在前述第2位元線之第2感測放大器; 前述第1感測放大器係比較第1參照位準,及前述複 數之第1位元線中相對應之位元線之訊號位準; 前述第2感測放大器係比較與前述第1參照位準不同 之第2參照位準,及前述第2位元線之訊號位準。 22.如申請專利範圍第 2 1項所記載之半導體裝置, 其中,前述第]參照位準係比前述第2參照位準低。 2 3.如申請專利範圍第 2 1項所記載之半導體裝置, 其中,前述第].及第2記憶體單元係包含第1導電型之 MIS FET (金屬絕緣半導體場效應電晶體)與相變化元件 〇 2 4.如申請專利範圍第 23項所記載之半導體裝置, 其中,前述第2記憶體單元之相變化元件係高阻抗狀態。 2 5.如申請專利範圍第2 1項所記載之半導體裝置, 其中,前述第1感測放大器係具有,於前述第1記憶體單 元寫入第1記憶資訊用之第].寫入電路; 前述第2感測放大器係具有,於前述第2記憶體單元 寫入前述第1記憶資訊用之第2寫入電路。 2 6.如申請專利範圍第2 5項所記載之半導體裝置, -54 - 200527656 (6) 其中’前述第1寫入電路係依據前述第2感測放大器之輸 出資料而進行寫入動作。 2 7.如申請專利範圍第2 5項所記載之半導體裝置, 其中’前述第]感測放大器係具有,於前述第1記憶體單 元寫入第2記憶資訊用之第2寫入電路; 前述第1及前述第2寫入電路係依據前述第2感測放 大器之輸出資料而進行寫入動作。 2 8·如申請專利範圍第2 6項所記載之半導體裝置, 其中’前述半導體裝置係具有顯示不可利用狀態之第丨輸 出接腳; 在前述第1或者第2寫入電路被活化之間,由前述第 1輸出、接腳輸出顯示不可利用狀態之訊號。 29. —種半導體裝置,其特徵爲:具有, 複數之子兀線,及 與前述複數之字元線交叉之複數的第1位元線,及 包含第1導電型MISFET (金屬絕緣半導體場效應電 晶體)與相變化元件,而配置在前述複數之字元線與前述 複數之第1位元線之特定的交點之第]記憶體單元,及 設置在前述複數之第1位元線之所期望的各線數之第 1感測放大器,及 配置在前述第1感測放大器,依據由外部所輸入之指 令,將由前述第]記憶體所讀出之第]資訊寫入前述第1 記億體單元用之第1寫入電路。 3 0. 一種半導體裝置,其特徵爲:具有, -55- 200527656 (7) 複數之第1字元線,及 與前述複數之字元線交叉之複數的第1位元線’及 配置在前述複數之第1字元線與前述複數之第1位元 線之所期望的交點之複數的第]記憶體單元’及 複數之第2字元線,及 與前述複數之第2字元線交叉之複數的第2位元線, 及 配置在前述複數之第2字元線與前述複數之第2位元 線之所期望的交點之複數的第2記憶體單元,及 配置在前述複數之各第1記憶體單元之第1相變化元 件,及 配置在前述複數之各第2記憶體單元之第2相變化元 件,及 對於由外部所寫入之資料,對應寫入資料,在前述第 1及第2記憶體單元寫入相同之阻抗狀態。 31.如申請專利範圍第3 0項所記載之半導體裝置, 其中,前述半導體裝置進而具有, 設置在前述複數之第I位元線之各特定的線數之第1 感測放大器,及 設置在前述複數之第2位元線之各特定的線數之第2 感測放大器,及 將配置在前述第1感測放大器之前述第]記憶體單元 之前述第]相變化元件設定在第]阻抗狀態之第1寫入電 路,及 -56- 200527656 (8) 將配置在前述第]感測放大器之前述第1記憶體單元 之前述第1相變化元件設定在第2阻抗狀態之第2寫入電 路,及 將配置在前述第]感測放大器之前述第1記憶體單元 之前述第1相變化元件設定在第3阻抗狀態之第3寫入電 路,及 將配置在前述第1感測放大器之前述第1記憶體單元 之前述第1相變化元件設定在第4阻抗狀態之第4寫入電 路,及 將配置在前述第2感測放大器之前述第2記憶體單元 之前述第2相變化元件設定在第1阻抗狀態之第5寫入電 路,及 將配置在前述第2感測放大器之前述第2記憶體單元 之前述第2相變化元件設定在第2阻抗狀態之第6寫入電 路,及 將配置在前述第2感測放大器之前述第2記憶體單元 之前述第2相變化元件設定在第3阻抗狀態之第7寫入電 路,及 將配置在前述第2感測放大器之前述第2記憶體單元 之前述第2相變化元件設定在第4阻抗狀態之第8寫入電 路; 前述第1寫入電路與前述第5寫入電路係同時被活化 前述第2寫入電路與前述第6寫入電路係同時被活化 -57 - 200527656 (9) 刖述弟3寫入電路與前述第7寫入電路係同時被活化 θϋ述第4寫入電路與前述第8寫入電路係同時被活化 〇 "2*如申請專利範圍第3 0項所記載之半導體裝置, 其中 Θ11述半_鳍裝置係具有,設置在前述複數之第1位 元線之各特定的線數之第1感測放大器,及 設置在前述複數之第2位元線之各特定的線數之第2 感測放大器; 具有,由前述第1記憶體單元而藉由前述第1位元線 被讀出,保持在前述第1感測放大器之第1資料,及 由前述第2記億體單元而藉由前述第2位元線被讀出 ,保持在前述第2感測放大器之第2資料; 在前述第I資料與前述第2資料中,將對應高阻抗狀 態之資料寫入記憶體單元。200527656 十 X. Patent application scope 1 · A semiconductor device characterized by having: a plurality of word lines, a plurality of bit lines, and a line including the word lines provided in the plurality and the bit lines provided in the plurality A plurality of memory cells with phase change materials at specific intersections, a sense amplifier connected to the bit line, and a sense amplifier connected to the sense amplifier, and write the first information into the first write of the memory cell Drive; after the reading operation, write the first information into one of the memory cells. 2. In the semiconductor device 'as described in item 1 of the scope of the patent application, the aforementioned first information is that the phase state of the aforementioned phase change material is memorized in an amorphous state. 3. The semiconductor device according to item 1 of the patent application scope, wherein the semiconductor device further includes a second write driver connected to the sense amplifier and writing the second information into the memory unit. 4. The semiconductor device described in item 3 of the scope of the patent application, wherein the first information is that the phase state of the phase change material is stored in an amorphous state, and the second information is the phase state of the phase change material. It is memorized in a crystalline state. 5. The semiconductor device according to item 3 of the scope of patent application, wherein after the reading operation, the writing operation of writing the second information into one of the aforementioned memory cells is performed. -50- 200527656 (2) 6. — A semiconductor device characterized by having: a plurality of word lines, a plurality of bit lines, and a plurality of word lines including the plurality of word lines and the plurality of bit lines The specific number of phase change materials of the plurality of memory cells, and the source line that is commonly connected to each of the memory cells, and the absolute difference between the potential difference between the source line and the bit line when the first information is written The first voltage and the third voltage which is the absolute difference between the potential difference between the source line and the bit line during reading; the third voltage is higher than the first voltage. 7. The semiconductor device according to item 6 of the scope of patent application, wherein the first information at the time of reading is read by a sense amplifier, and the aforementioned memory cell is rewritten. 8. The semiconductor device according to item 6 of the scope of the patent application, wherein the above-mentioned information] is that the phase state of the phase change material is memorized in an amorphous state. 9. The semiconductor device according to item 6 of the scope of patent application, wherein the first information is memorized in a crystalline state in a phase state of the phase change material. 10. The semiconductor device according to item 6 of the scope of the patent application, wherein the second voltage having an absolute value of the potential difference between the source line and the bit line at the time of writing the second information described above is the third voltage. Both the voltage and the second voltage are high. -51-200527656 (3) 1 1. The semiconductor device described in item 6 of the scope of patent application, wherein the second voltage has the absolute voltage of the potential difference between the source line and the bit line when the second information is written. The third voltage is higher than the second voltage and lower than the second voltage. [2] —A semiconductor device, comprising: a plurality of character lines, a plurality of bit lines, and a phase including a specific intersection of the plurality of character lines and the plurality of bit lines. A plurality of memory cells of varying materials, a first memory cell array and a second memory cell array including the aforementioned plurality of memory cells, and a first sensing unit reading data from the aforementioned first memory cell array Amplifier block, and a second data output line that outputs data from the aforementioned first sense amplifier block, and a second sense amplifier block that reads data from the aforementioned second memory cell array, and from the aforementioned second sense amplifier block The sense amplifier block outputs data to an external second data output line. 13. The semiconductor device according to item 12 of the scope of the patent application, further comprising a first logical sum circuit for obtaining a logical sum of the first data output line and the second data output line. 14. The semiconductor device described in item 12 of the scope of patent application, wherein the first information is that the phase state of the phase change material is stored in an amorphous state-52-200527656 (4). / · If the scope of the patent application] or the item 6 or item 12 is the half-membrane reversing device, the above description, please, the body unit is made of a phase change material and a selection switch. 16. The semiconductor device according to item 15 of the scope of patent application, wherein the maximum value of the absolute value of the potential _ between the source line and the bit line is 1.8 V or less. 17. The semiconductor device as described in item 15 of the scope of patent application, wherein the phase change material is a material containing Sb (antimony), and the film thickness thereof is less than 〇0ιιτη. 18. As described in item 17 of the scope of patent application In the semiconductor device, the phase change material is a material including Ge (germanium), Sb (antimony), and (hoof), and the film thickness is 20 nm or less. [9] The semiconductor device according to item 15 in the scope of the SRA patent, wherein tungsten is used as an electrode material for electrically connecting the phase change material and the selection switch. 20. The semiconductor device described in item 15 of the scope of patent application, wherein '' operates at an ambient temperature of 125 ° C or higher. 2 1. A semiconductor device, characterized by having: a plurality of character lines, a plurality of bit lines that intersect the plurality of character lines, and a plurality of character lines that intersect with the plurality of character lines, and The second bit line where the first bit line of the plural is arranged in parallel, and the -53-200527656 (5) at the specific intersection of the first bit line arranged between the plural word line and the plural] bit line. A unit, a second memory unit arranged at a specific intersection of the plurality of character lines and the second bit line, and a first sense of each specific line number arranged at the first plurality of bit lines A sense amplifier, and a second sense amplifier arranged on the second bit line; the first sense amplifier compares the first reference level with the corresponding bit line in the plurality of first bit lines; Signal level; The second sense amplifier is compared with a second reference level that is different from the first reference level, and a signal level of the second bit line. 22. The semiconductor device according to item 21 of the scope of patent application, wherein the aforementioned [reference] level is lower than the aforementioned second reference level. 2 3. The semiconductor device described in item 21 of the scope of the patent application, wherein the aforementioned [] and the second memory cell include the first conductivity type MIS FET (Metal Insulated Semiconductor Field Effect Transistor) and phase change Element 02. The semiconductor device according to item 23 of the scope of patent application, wherein the phase change element of the second memory cell is in a high impedance state. 2 5. The semiconductor device described in item 21 of the scope of the patent application, wherein the first sense amplifier has a first write-in circuit for writing the first memory information in the first memory unit]. Writing circuit; The second sense amplifier includes a second writing circuit for writing the first memory information in the second memory unit. 2 6. The semiconductor device described in item 25 of the scope of the patent application, -54-200527656 (6) where 'the first write circuit performs a write operation based on the output data of the aforementioned second sense amplifier. 2 7. The semiconductor device described in item 25 of the scope of the patent application, wherein the 'the aforementioned] sensing amplifier has a second writing circuit for writing the second memory information in the aforementioned first memory unit; The first and second writing circuits perform a writing operation based on the output data of the second sense amplifier. 28. The semiconductor device described in item 26 of the scope of patent application, wherein the aforementioned semiconductor device has a first output pin indicating an unusable state; between the aforementioned first or second writing circuit is activated, The above-mentioned first output and pin output indicate a signal that is not available. 29. A semiconductor device, comprising: a plurality of child lines, a plurality of first bit lines crossing the plurality of word lines, and a first conductive type MISFET (Metal Insulated Semiconductor Field Effect Circuit) Crystal) and phase change elements, and the memory cells arranged at specific intersections of the plural word lines and the plural bit lines of the plural numbers, and the desired arrangement of the plural bit lines and the plural bit lines The first sense amplifier of each line number and the first sense amplifier are arranged in accordance with a command input from the outside, and the first information read from the first memory is written into the first memory unit. Use the first write circuit. 3 0. A semiconductor device, comprising: -55- 200527656 (7) a plurality of first word lines and a plurality of first bit lines that intersect the plurality of word lines, and are disposed in the foregoing Plural] memory cells' and plural second character lines intersecting with the plural first character lines and the aforementioned plural first bit lines, and intersecting with the plural plural character lines The second bit line of the plural number, and the second memory cell of the plural number arranged at a desired intersection between the second word line of the plural number and the second bit line of the plural number, and each of the plurality of memory cells arranged in the plural number The first phase change element of the first memory unit, and the second phase change element arranged in each of the plurality of second memory units, and for the data written from the outside, corresponding to the written data, in the first Write the same impedance state as the second memory cell. 31. The semiconductor device described in item 30 of the scope of the patent application, wherein the semiconductor device further includes a first sense amplifier provided at each specific number of lines of the plurality of first bit lines, and provided at The second sense amplifier of each specific line number of the plurality of second bit lines, and the first] phase change element of the first memory cell arranged in the first sense amplifier are set to the first impedance State first write circuit, and -56- 200527656 (8) Set the first phase change element of the first memory unit of the first sense amplifier to the second write of the second impedance state Circuit, and a third writing circuit that sets the first phase change element of the first memory unit of the first sensing amplifier to a third impedance state, and a third writing circuit of the first memory unit that is disposed in the first sensing amplifier, and The first phase change element of the first memory unit is set to a fourth write circuit in a fourth impedance state, and the second phase change element of the second memory unit arranged in the second sense amplifier set up The fifth writing circuit in the first impedance state, and the sixth writing circuit in which the second phase change element disposed in the second memory unit of the second sense amplifier is set to the second impedance state, and A seventh write circuit in which the second phase change element arranged in the second memory unit of the second sense amplifier is set to a third impedance state, and the second memory arranged in the second sense amplifier The eighth writing circuit of the second phase change element of the body unit is set to a fourth impedance state; the first writing circuit and the fifth writing circuit are activated at the same time. The second writing circuit and the sixth writing are activated at the same time. The input circuit system is activated at the same time -57-200527656 (9) The 3rd write circuit and the 7th write circuit system are activated at the same time. The 4th write circuit and the 8th write circuit system are activated at the same time. " 2 * The semiconductor device described in item 30 of the scope of patent application, wherein the half-fin device described in Θ11 is a first sense amplifier having a specific number of lines provided in the aforementioned plurality of first bit lines , And set in the plural The second sense amplifier with a specific number of lines of the second bit line; the second memory line is read out by the first memory cell through the first bit line, and is held at the second position of the first sense amplifier. 1 data, and the 2nd data of the 2 billionth body unit is read out through the 2nd bit line, and kept in the 2nd data of the 2nd sense amplifier; in the 1st data and the 2nd data, The data corresponding to the high-impedance state is written into the memory unit.
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