TW200527656A - Semiconductor device - Google Patents

Abstract

To improve recording/holding reliability in the case of operating a phase change memory at a low voltage and at a high temperature, or leaving it as it is. A high-speed operation is performed with a read voltage above set and reset voltages, and after a read operation, the status prior to the read operation is rewritten. That is, a so-called destructive read is performed. Alternatively, a so-called "OR-cell", in which a plurality of cells are used to record 1-bit information, is used to improve the reliability in the case of operating a phase change memory at a high temperature or leaving it as it is. There are used circuit arrangement and operation scheme required by the phase change memory using the destructive read and OR-cell.

Description

200527656 (1) IX. Description of the invention [Technical field to which the invention belongs] The present invention relates to semiconductor devices, and in particular, to high-density integrated memory circuits formed by use of phase change materials, or memory circuits and logic circuits. An effective technique for logic-mixed memory or semiconductor integrated circuit devices with analog circuits installed on the same semiconductor substrate. [Prior technology] The memory (phase change memory) using an impedance element made of a phase change material uses electrical pulses to make the phase change material reversibly phase-convert between the amorphous state and the crystalline state to change the amorphous state. The difference in impedance between the qualitative state (reset) and the crystalline state (set) is treated as information for nonvolatile memory. That is, the high impedance of the amorphous phase of the phase change material and the low impedance of the crystalline phase, respectively, do not need to be completely amorphous and completely crystalline. Therefore, a high impedance state of the completely amorphous state can be used. Arbitrary 値 between Φ and the low-impedance state of the perfect crystalline state. Hereinafter, the operation mechanism of the phase change memory will be described in detail using FIG. 14. Fig. 14 is an example of the current-voltage characteristics of a phase-change material that realizes the recording operation of the phase-change material. If the voltage applied across the phase change material in an amorphous state is gradually increased from zero, the phase change material in an amorphous state will phase change to a crystalline state. The voltage that causes a phase change from an amorphous state to a crystalline state is defined as a set voltage (Vset). (2) The impedance of a phase change material that changes from an amorphous state to a crystalline state changes from a high-impedance state to a low-impedance state. In addition, if the voltage applied to both ends of the phase change material in a crystalline state is gradually increased from zero, the phase change material in a crystalline state will phase change to an amorphous state. The voltage that causes the crystalline state to change to the amorphous state is defined as the reset voltage (Vreset). The phase resistance of a phase-change material that changes from a crystalline state to an amorphous state is difficult to change from a low-resistance state to a high-resistance state. The phase-change memory system treats the low-resistance state of the crystalline state as a π 〇π state. The high impedance of the qualitative state is regarded as a "1" state to record information. Information is read by adding a read voltage (Vread) across the phase change material. As shown in FIG. 14, by applying the read voltage Vread, a current generated in a crystalline state having a low resistance 値 is larger than a current generated in an amorphous state having a high resistance 値. The information recorded in the phase change memory is read by sensing the voltage drop of the bit line electrically connected to one end of the phase change material. Fig. 15 is a model diagram showing a voltage drop of a bit line electrically connected to a phase change material. In the initial state of the bit line at the time of reading, the bit line is set to the precharge level Vp. In Fig. 15, the precharge level Vp of the bit line is set to 0.3 V. As shown in FIG. 15, the bit lines electrically connected to the phase-change material in the amorphous state with high impedance 値 are more electrically connected to the bit lines of the phase-change material in the crystalline state with low resistance 値The line 'does voltage drop at low speed. The reason is that the speed at which the charge accumulated in the bit line flows into the phase-change material is that the phase-change material having a high resistance 値 is slower than the phase-change material having a low resistance 値. -6- 200527656 (3) The state of the phase change memory and the "1" state are read out by using the read voltage to sense the speed of the voltage drop of the bit line. That is, in the present invention, although the crystal state Low impedance: "0 M state" In addition, "high impedance in the amorphous state" is "1π state" but "You can also set high impedance in the amorphous state" to "state" and set low impedance in the crystalline state The state is "1". [Patent Document 1] Japanese Patent Application No. 2003-1 45 3 05 [Patent Literature 2] Japanese Patent Application No. 2003 -08 1 724 [Inventive Content] [Inventive Solution [Problem] In the phase change memory, there is a problem of a so-called erroneous setting in which an erroneous phase is changed from an amorphous state to a crystalline state. The erroneous setting is prone to occur when excessive power is input during low-voltage operation or during high-speed operation. .The reason for causing the wrong setting is, for example, physical property deviation or electrical characteristics deviation or dimensional deviation. In addition, for example, phase change materials or selection of transistor or LSI wiring, etc. Variations in operating voltage or power supply voltage can also cause erroneous settings. The following 'describes in detail the phenomenon of erroneous settings during read operation. As shown in Figure 14 in the conventional method The read voltage is set below the set voltage. By setting the read voltage below the set voltage, it is possible to prevent the phase change material in an amorphous state from being mistakenly changed to a crystalline state based on the read operation. But ' When a low-voltage operation is required for a phase-change memory, 200527656 (4) a problem occurs in which the margin between the set voltage and the readout voltage becomes small. For example, it is used in mobile phones, mobile information terminals, or IC cards. In the case of low power consumption products, phase change memory is required to operate at low power. In addition, in the case of microcomputer mixed memory used as low voltage operation, phase change memory is also required to operate at low voltage. The reason why the margin of the set voltage and the readout voltage in the change memory becomes smaller is to make the reading smaller than the set voltage. It is difficult to make the output voltage smaller. The reason why it is difficult to make the read voltage smaller is that the read current becomes smaller together with the read voltage, and the operating speed of the phase change memory decreases. Use Figure 16 The relationship between the readout voltage and the readout current of the phase change memory is shown. As shown in Figure 16, the readout current in the crystalline state obtained by the readout voltage Vreadl is Iread 1. In contrast, the ratio of The crystalline state read current obtained by a small read voltage Vread 1 becomes Iread2, which is smaller than Ireadl. As the read current decreases, the discharge speed of the bit line decreases, and the phase sensed by the sense amplifier As a result of the decrease in the speed of the amorphous state and the crystalline state of the material, the speed of the phase change memory decreases. In the case where the margin between the set voltage and the readout voltage becomes small, the recording retention reliability of the phase change memory _ is degraded. For example, if the characteristics of the phase change memory are too large, the set voltage will be smaller and smaller than the readout voltage. This result is a phenomenon in which the phase change material is erroneously set from the amorphous state to the crystalline state due to the read operation. Incorrect setting occurs in two cases: the reset voltage shown in Figure 4 is larger than the set voltage, and the reset voltage is smaller than the set voltage as shown in 200517656 (5) in Figure 17. Possibility. In the case where the phase change memory operates at a low voltage ', the margin between the read voltage and the set voltage becomes small. Therefore, a small amount of phase change material or a characteristic deviation in the selection of the transistor may cause incorrect setting. In addition, in the case where the phase change memory operates at low voltage, the margin between the set voltage and the reset voltage becomes smaller. Therefore, based on a small amount of phase change material or the characteristic deviation of the transistor, an incorrect setting will occur during the reset operation. 〇 In addition, if the impedance 重置 of the reset state is changed based on the accumulated readout, the energy input will be changed accordingly, and an incorrect setting may occur. In addition, in the case of increasing the capacity of the phase change memory, a small product failure due to the wiring process and the like may cause incorrect setting of dropped bits. In addition, in order to read out the phase change memory at high speed, When the voltage is large, the margin between the read voltage and the set voltage becomes small, and an incorrect setting occurs. In addition, the phase change memory has a problem of a so-called erroneous reset in which a crystalline state is erroneously changed to an amorphous state and a phase change is performed. In the case where the phase change memory is required to operate at a low voltage, the margin of the reset voltage and the read voltage also becomes smaller. Therefore, when the characteristic variation of the phase change memory is large, there is a possibility that the reset voltage becomes smaller and becomes smaller than the read voltage. This result is a phenomenon in which the phase change material is erroneously reset from the crystalline state to the amorphous state due to the read operation. Winter 200527656 (6) There are two cases where the reset voltage is greater than the set voltage as shown in Table 14 and the two cases where the reset voltage is lower than the set voltage as shown in Figure 17 There is a possibility of it happening. In the case where the phase change memory operates at a low voltage, the margin between the read voltage and the reset voltage becomes smaller. Therefore, a small amount of phase change material or the characteristic deviation of the selected transistor will cause an erroneous reset. In addition, when the phase change memory operates at a low voltage, the margin between the set voltage and the reset voltage becomes smaller. Therefore, based on a small amount of phase change material or the characteristic deviation of the transistor, an incorrect reset will occur during the set operation. 〇 In addition, in order to read the phase-change memory at high speed, when the read voltage is set to be large, the margin between the read voltage and the reset voltage becomes small. Therefore, an erroneous reset may occur during reading. In addition, since the amorphous state of the phase change material is a quasi-stable state, the erroneous setting of the phase change memory may be operated or placed at a high ambient temperature or a high junction temperature. Based on erroneous settings caused by high temperature and long-term storage, it can be seen in large-capacity memories such as DRAM (Dynamic Random Access Memory), and it is observed with the so-called "drop bit phenomenon",

As a result of Jt Dagger, the long-term reliability of the phase change memory used in the highly integrated memory circuit and logic mixed memory may deteriorate. Examples of products that require high-temperature operation with phase-change memory include hybrid microcomputers for automotive engine control. The operation and 20-year storage temperature requirements are, for example, a joining temperature of 125 ° C or more or 145 ° C or more. An object of the present invention is to provide: in particular, an example of using a phase change material -10- 200527656 (7) such as a high-density integrated memory circuit, and a logic-hybrid type memory in which the memory circuit and the logic circuit are provided on the same semiconductor substrate, and In a semiconductor integrated circuit device having an analog circuit, it is possible to improve the reliability of a memory cell element using a phase change material that requires long-term record-keeping reliability. Another object of the present invention is to achieve a low voltage operation of a semiconductor integrated circuit device. Another object of the present invention is to increase the temperature of a semiconductor integrated circuit device. Another object of the present invention is to increase the temperature of the semiconductor integrated circuit device for a long period of time. Another object of the present invention is to achieve high integration of a semiconductor integrated circuit device. Another object of the present invention is to increase the capacity of a semiconductor integrated circuit device. Another object of the present invention is to achieve high-speed operation of a semiconductor integrated circuit device. From the description of this specification and the attached drawings, the foregoing and other features of the present invention should become clear. [Means for Solving the Problem] If the representative of the representative of the invention disclosed in the present application is briefly described, as follows: In a read operation, a voltage necessary for setting is applied to a bit line to read data, All the cells are made low-impedance, and the re-write operation is performed on the high-impedance cells. As a result, the destruction readout method can be used to prevent erroneous setting and erroneous reset caused by high-temperature operation. In addition, by applying a high voltage to the bit line, rewriting operations are performed on the high-resistance cell and the low-resistance cell, respectively. As a result, the present invention can use the -11-200527656 (8) bad readout method to prevent deviations in characteristics based on phase change materials or selection of transistor wiring, or deviations in power supply voltages, resulting in incorrect resets. In addition, the present invention uses " or " units, that is, two or more memory units to perform drop bit relief to maintain the bit position. The result of the present invention is that errors caused by long-term high temperature placement of elements can be prevented. The setting can improve the reliability of the phase change memory. [Effects of the invention] If the representative effects of the invention disclosed in this application are briefly explained, it is as follows: In particular, the example integration using phase change materials Memory circuits, and logic-mixed memories in which semiconductor circuits are provided with a semiconductor substrate for the memory circuits and logic circuits, and in volume circuit devices with analog circuits, which can improve the reliability of memory cell elements using phase-change materials that require long-term record retention [Embodiment] < Example 1 > Fig. 3 shows the phase change of the present invention, and the memory cell part of Fig. 3 is composed of: the lower electrode dwc, and the material PCR, and The upper electrode upc, the source line δ L, and the potential are composed of, for example, a selection transistor Mτ ′ and WL formed by a MISFET. Several pieces of information are mistaken. The reporter ’s semi-reliable reliability road map obtained by the reporter at the time of the drop is as follows. Phase change: line BL character line -12-200527656 (9) Figure 18 shows the phase change memory cell An example of a cross-sectional view. In this memory unit, the phase change material PCR is composed of the upper electrode upc, the lower electrode plug d wc, and the interlayer film IL. The phase change material PCR is connected to the upper electrode υ pc and the lower electrode. The plug dwc is electrically connected. The upper electrode up c is electrically connected to the bit line BL or the source line SL. The lower electrode plug dwc is electrically connected to, for example, one of the source and the drain of the orange selection transistor MT selected by MISFET. Select the source of the transistor and the other end of the drain to be electrically connected to the wiring of the source line SL or bit line BL that is not connected to the upper electrode. That is, the circuit diagram of the memory cell becomes as shown in Figure 3. (a) or FIG. 3 (b). In addition, the processing of the memory cell structure is performed using a known method. In addition, those related to such a memory cell structure are disclosed in Patent Document 1, for example. Low voltage operation The phase change material PCR used in the phase change memory includes, for example, a G e-S b-T e phase change material, or a z η-T e phase change material, or a Zn-Te phase change material. Zn-X-Te based phase change material with added element. For example, Sb can be added as the added element. Those related to Zn-X-ITe based phase change material are disclosed in Patent Document 2, for example. Used for lower electrode plug dwc Examples of the material include tungsten. Tungsten is a low-voltage and high-speed material suitable for the purpose of the present invention because of its good interface characteristics with phase change materials. Figure 19 compares the crystal lattice constants of Ge2Sb2Te5, tin, cyanide, and silicon. As shown in Fig. 19, the crystal lattice constant of G ^ SbJe5 is almost the same as that of tungsten. As a result, the current required for the phase change of the phase change memory using tungsten as the lower electrode becomes smaller. Figure 2 〇 The silicon shows that the lower electrode uses tungsten and -13- 200527656 (10) G e 2 S b 2 T e 5 phase change in the case of Nitride is required to change the material from crystalline phase to amorphous state. Placing current. As shown in Fig. 20, the reset current in the case where tungsten is used for the lower electrode is smaller than the reset current in the case where titanium nitride is used. As a result, by using tungsten as the lower electrode material, the current required for the phase change becomes smaller, and the low voltage operation of the phase change memory becomes possible at the same time. However, since the phase change memory operates at a low voltage, there is a problem that the margin of the difference between the read voltage, the set voltage, and the reset voltage becomes small. An example of the phase change memory operating at low voltage is the case where the phase change material is a thin film. The reason for using the film phase change material to realize the phase change memory will be described below. For example, if the electric power P per unit volume required for the phase change of the phase change material to be in a crystalline state is obtained using ohmic approximation, it is expressed as shown in Equation 1 below. [Number 1]

AT

… (Equation 1) Here, I set is the set current required when the phase change material in the amorphous state changes to the crystalline state, R is the impedance of the phase change material 値, 3 Impedance of the phase change material, A The area of the lower electrode, τ is the film thickness of the phase change material. Solving formula] When the set voltage Vset is obtained, it becomes Equation 2 below. -14-200527656 (11) [Eq. 2] V-x / pr * τ (Equation 2) set Based on Equation 2, we know that the set voltage V s e t is proportional to the film thickness of the phase change material. As a result, by reducing the film thickness of the phase change material, it is known that the low voltage operation of the phase change memory can be realized. Equations 1 and 2 show the setting operation of the phase change material changing from an amorphous phase to a crystalline phase. Equations 1 and 2 can also be used approximately in the case where the reset operation of the phase change material changes from a crystalline state to a crystalline state to an amorphous state. However, Equation 1 and Equation 2 are obtained using only the ohmic approximation. When considering the generation and diffusion of Joule heat, the power required for the phase change of the phase-change material becomes more than that obtained by Equation] and Equation 2. Dezhi is still big. In addition, in the present invention, it is assumed that the maximum value of the absolute value of the potential difference between the source line and the bit line is 1.8 V or less. In this case, the voltage drop of the selection switch is estimated to be G. 6 V or more. Therefore, the voltage applied to the phase change material is assumed to be 1.2 V or less. Figure 21 shows the experimental data of the reset voltage and phase change material of the phase change material from the crystalline phase to the amorphous phase. When using a G ^ SbsTe5 phase change material for UV operation, the film thickness must be 20 ^ m or less, for example. In addition, when using 1.2 V operation, the film thickness order

ZnnSbuTew phase change material to perform If it is assumed that it is below 60 nm, the reason for the correlation is that the phase change ′ is below the aforementioned film thickness of zero. Therefore, the phase change material is woven. The relationship between the aforementioned film thickness and the resistivity of the composition material of the phase change material is different. In addition, the power required when the reset voltage does not become 0V is included in the generation and diffusion of Joule heat -15- 200527656 (12). Examples of phase change memory used in high temperature operation and high temperature long-term storage include high melting point phase change materials, Z ^ Te phase change materials, or Zn-Te phase change materials with added elements Zn-X-Te series phase change material. Related materials related to the Zn-X-Te-based phase change material are disclosed in Patent Document 2, for example. Although the phase change material of the present invention is a G e S b Te-based phase change material, or a Z η-T e-based phase change material, or a z η-T e-based phase change material plus an additive element of Z η-X- T e is a phase change material, but it can also be applied to other phase change materials. In this case, while maintaining the reliability of the data of the phase change element, it is also possible to prevent a decrease in the operating speed at low voltages. In addition, although the operating voltage is assumed to be about .2 V, it can also be applied to 1.8 V operation. In this case, it also has the effect of increasing the operating margin and improving the operating speed. Furthermore, the present invention is intended to use a semiconductor having a processing size of 0.13 m or less. At the same time as the miniaturization progresses, the decrease of the operating voltage also progresses. Therefore, the decrease of the operating margin becomes a problem. By applying the present invention, the operating margin can be increased. In addition, the present invention can also be applied to a single memory and a logic mixed memory. By applying these methods, data reliability and memory unit defects can be remedied, and the product rate can be improved. In addition, especially in a logic hybrid memory, the reliability of data operating at high temperatures can be improved, and a semiconductor device capable of operating over a wide temperature range can be realized. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The circuit elements constituting each functional block of the implementation-16- 200527656 (13) example are not particularly limited, and are formed on a semiconductor such as single crystal silicon by a well-known integrated circuit technology such as CMOS (Complementary MOS Transistor). On the substrate. In the drawing, the p MOS transistor body is marked with an arrow to distinguish it from the NM MOS transistor. Although the connection of the substrate potential of the MOS transistor is not specifically described in the drawing, the connection method is not particularly limited as long as it is within a range where the MOS transistor can operate normally. In addition, unless otherwise specified, the low level of the signal is set to '' 0 '' and the high level is set to '' 1 ''. In this embodiment, when the operating voltage of the array is reduced, the read-out voltage range is narrowed, which can solve the problem of lowering the operating margin. In the conventional read operation, the applied voltage is suppressed to a low voltage so that a phase change element in a high impedance state or a low impedance state does not cause a phase change due to a current during reading. As a result, as the read current becomes smaller, the amount of read signal decreases, and there is concern about a decrease in operation speed and a decrease in operation margin. On the other hand, in the present invention, during the readout operation, “the sensor amplifier generates a sufficient signal amount and increases the applied voltage, and at the same time,” the unit that may cause a phase change due to the readout operation is reprocessed Write action 'to improve data reliability. Examples of the present invention are shown below. In this structure, 'the pre-charge level of the bit line of the read operation is that the phase change element in the set state does not cause a phase change', and the phase change element in the reset state must have a phase change of V set above the voltage of the set state Structures below V reset. Figure] is a diagram showing a memory cell array MCA, a sense amplifier block SAB, and a row decoder / character driver RDEC that implement this operation. -17-200527656 (14) First, the memory cell array MCA will be described. Fig. 2 shows a configuration example of the memory cell array MCA. The memory cell MC is arranged at the intersection of the character lines WL0 'WL1, WL2, WL3, ... and the bit lines BL0, BL]' B L2, B L3, .... In addition, source lines S L 0 1, S L 2 3,... Are provided. The source line is connected to the ground voltage V S S, for example. Each memory cell MC is composed of a phase-change impedance PCR and a memory cell transistor MT. Figure 3 shows two types of memory cell structures. In (a), one end of the phase-change impedance PCR is connected to the bit line BL, and the other end is connected to one of the source and the drain of the memory cell transistor MT. The other side of the source and drain of the memory transistor is connected to the source line, and the smell is connected to the word line. In this structure, the bit line BL is made to have a higher potential than the source line SL during writing. For example, in the case of .1.2 V driving, a large driving force of the memory cell transistor MT can be obtained. Is relatively excellent. In (b), the connection relationship between the phase-change impedance PCR of (a) and the memory cell transistor MT is reversed. In this structure, compared with the source line SL, the bit line is driven at a low potential. For example, when the potential of the source line SL is 1.2V and the bit line BL is driven at 0V, it can be obtained. The driving force of the large memory cell transistor MT is excellent. Furthermore, even during the read and write operations, even if the bit line is driven, the current in the non-selected cell does not flow through the diffusion layer of the charge-discharge memory cell transistor MT, which can prevent data destruction. Here, although the NMOS transistor is shown as the memory cell transistor, a PMOS transistor or a bipolar transistor may be used. However, from the viewpoint of high integration, MOS transistors are expected. Compared with PMOS transistors, -18-200527656 (15) NMOS transistors with smaller channel impedance are more suitable. In the following, the operation and the like will be described with respect to the voltage relationship when the NMOS transistor is used as the memory cell transistor. The bit line is also called a data line. Here, although it is not shown in the figure for the sake of simplicity, a virtual unit that generates a reference signal for reading when the memory unit array MCA is generated may be provided as needed. The sense amplifier block SAB is formed by a bit line selector BLSEL, a sense amplifier SA and a write driver WD. Fig. 4 shows a configuration example of the bit line selector BLSEL. The bit line selector BLSET is provided with bit switches BL0, BL1,... Of the memory array and connected to a selection switch for a sense amplifier. These relationships are controlled by the column selection signals C0t / b, Clt / b, .... Furthermore, a pre-charged transistor that charges the bit line of the memory array side and the sensing line and the bit line of the amplifier side BLS A to a desired level in advance is arranged. A sense amplifier block is provided adjacent to the bit line selector. The sense amplifier senses the signal of the bit line of the sense amplifier and outputs it to the outside, or temporarily holds the data from the outside. Figure 5 (b) shows a configuration example of the sense amplifier. In this configuration, it is formed by a cross-coupling amplifier circuit that compares the level of the sense amplifier bit line B L S A with the reference level VREF and amplifies it to the power supply voltage VWE. Fig. 5 (a) shows a configuration example of the write driver W D. The write driver WD drives the sense amplifier bit line BLSA based on data written from outside or data read from the sense amplifier SA. In this embodiment, the write driver WD is constituted only by a driver for making the phase change element of the memory cell into a high impedance state. In the figure, 4 BL 0, BL], BL 2, BL 3 are connected to the bit line]] Sense -19- 200527656 (16) Sense amplifier bit line BLSA, sense amplifier SA, and write driver WD '' But the number of 'bit lines' is not limited. By setting a large number, the number of sense amplifiers to be operated can be reduced, and an increase in unnecessary power consumption can be suppressed. On the other hand, if it is set to a small number, the number of bits to be output will increase, which is suitable for inputting and outputting high-speed and large-volume data. Next, a read operation of the array structure will be described. Fig. 6 is a timing chart of the read operation. According to the read command, the column selection line C0t / b corresponding to the inputted address is activated. After that, it is connected to the bit line of the sense amplifier SA. In the figure, the bit line BL0 and the bit line BLSA in the sense amplifier are also set as the bit line precharge level VR. In this embodiment, the potential difference between the pre-charge level VR and the source line SL of the memory cell MC is set such that the current necessary for the phase change element to change from a high impedance state to a low impedance state can flow. For example, in the example shown in the figure, the source line SL is set to 0V, and the precharge level VR is set to approximately 0.6V. After that, while the precharge signal PRE is in a non-selected state, the word line W L is selected. According to this, the bit line BL and the bit line BLSA in the sense amplifier are discharged by the memory cell transistor MT and the phase change element P CR. At this time, when the phase change element PCR of the memory cell is in a low impedance state, it is rapidly discharged. On the other hand, when the impedance is in a high impedance state, it is gradually discharged. In the sense amplifier, the tiny signal limited to the bit line is amplified to the power supply voltage. According to this readout operation, the phase change element in the high-impedance state generates heat due to the read current. The phase changes from the high-impedance state to the low-impedance state, and all the cells read out in the sense amplifier become low-impedance. In the sense amplifier, the signal read out on the bit line is amplified -20- 200527656 (17), and the output is external, so it is output at 1/0. Before that, the write driver is activated in a sense amplifier that reads out the data in which the phase change element of the memory unit is in a high impedance state. In the activated write driver, a high voltage is applied to the bit line by the write drive signal WRE at the time necessary for the reset operation, and the current necessary for the reset operation is passed through the bit line and the memory. The unit transistor flows into the phase change element. Thereafter, by interrupting the current, the phase change element is rapidly cooled, and the phase changes to a high impedance state. After that, the word line WL and the column selection line C0t / b are switched to the non-selection level, and the read cycle ends. Next, the write operation will be described. Fig. 7 is a timing chart of the write operation. According to the write instruction, the write address is sent to. Similar to the read operation, the column selection line C 0 t / b is activated, and at the same time, the precharging operation of the 7-bit line is performed. After that, the word line WL corresponding to the address is selected, and the bit line is discharged by the memory cell transistor and the phase change element. At this time, the phase change element generates heat by a read current, and changes phase from a high impedance state to a low impedance state. As a result, the phase change elements of all the memory cells connected to the sense amplifier change to a low impedance state. During this operation, the written data is transferred to the sense amplifier. Here, after rewriting the read data, the write driver of the sense amplifier that only corresponds to the data holding the high-impedance state of the phase change element of the memory cell in the sense amplifier row is activated. After that, in the activated write driver, a high voltage is applied to the bit line by a write start signal during the time necessary for the reset operation, and the current necessary for the reset operation is passed through the bit line, The memory cell transistor flows in the phase change element. After that, by switching off the current, the phase change element is rapidly cooled to change phase-21-200527656 (18) is in a high impedance state. After that, the word line WL and the column selection line C0t / b transition to the non-selection level, and the readout period ends. In this structure, when the word line is selected to read the data of the memory cell, all the data of the memory cell are set to the low impedance state, and then written to the high impedance state. The advantages of this are as follows: (1) When reading, the bit line pre-charging level can be set to a high level, which can increase the amount of signal read from the sense amplifier, and can achieve high-speed and stable read operations. . (2) Conventionally, the write driver that needs to set and reset the driver can only be composed of the reset driver, while the circuit structure can be simplified, and the layout area and chip area can be reduced. (3) Since the high-impedance state is written again during reading, the reliability of the data due to data destruction during the reading operation can be reduced. (4) Degradation of the record-keeping characteristics of the phase-change element, such as high-speed operation at 125 ° C or higher and long-term storage, becomes possible. < Embodiment 2 > Next, Embodiment 2 will be described. The circuit and cross-sectional structure of the memory cell of the second embodiment are the same as those of Figs. 3 and 18, and descriptions thereof are omitted. In this structure, the bit line precharge level at the time of reading uses a voltage higher than the voltage Vset or Vreset which does not cause a phase change in the phase change element. In this operation, in order to increase the read signal amount, although the bit line pre-charge level is set to a high level, 'the phase state of the phase change element may be broken based on the read operation'. Set and reset again. • 22- 200527656 (19) Figure 8 shows the structure of the sense amplifier block SAB of this embodiment. The memory cell array MCA and the character driver RDEC are the same as those in the previous embodiment. The sense amplifier block SAB is formed by a bit line selector BLSEL and a write driver WD for setting and resetting phase change elements and amplification, and a data amplifier sense bit SA of a bit line BLSA. FIG. 9 shows the circuit configuration of the write driver WD. The write driver WD is based on the data of the set enable signal WSE and the reset enable signal WRE and the sense amplifier SA, and the current necessary for setting and resetting is sensed by the sense amplifier bit line BLSA and the memory cell transistor. Supply to phase change element. The structure of the write driver is different from that of the aforementioned embodiment, and it is provided with a write driver for increasing and decreasing the resistance of the phase change element. Next, a read operation of the array structure will be described. Figure 10 is a timing diagram of the read operation. As in the previous embodiment, the column selection line C Ot / b corresponding to the input address is activated according to the read command. After that, it is connected to the bit line of the sense amplifier SA. In the figure, the bit line B L 0 and the bit line B L S A in the sense amplifier are both set as the bit line precharge level VR. In this embodiment, the potential difference between the precharge level VR and the source line SL of the memory cell MC may be a voltage that circulates a current necessary for the phase change element to change from a high-impedance state to a low-impedance state. It is a voltage at which a low impedance state becomes a high impedance state. Conversely, the voltage may be a voltage near a voltage in which the high impedance state is indeed reduced. In this case, it is not necessary to cause the phase change element to change from a high impedance state phase to a low impedance state. For example, in the example of the figure -23- 200527656 (20), the pre-charging signal PRE becomes a non-selected state while the 'character line WL is selected. According to this bit line BL and the bit line BLSA in the sense amplifier, the memory cell transistor MT and the phase-change impedance PCR are used to discharge electricity. At this time, when the phase change impedance PCR of the memory cell is in a low impedance state, it is rapidly discharged. On the other hand, "when the impedance is in a high impedance state," it is slowly discharged. In the sense amplifier ', the tiny signal appearing on the bit line is amplified to the power supply voltage. According to this readout operation, the impedance 値 of the phase change element of the memory cell unit connected to the sense amplifier does not necessarily maintain the impedance state before readout. That is, the memory data is destroyed by the reading action. Meanwhile, in the sense amplifier, the signal read out from the bit line is amplified and output to the outside. Before this, the driver is activated in a sense amplifier that reads out the data of the phase change element of the memory cell in a high impedance state. In the activated write driver, a high voltage is applied to the bit line by writing a drive signal at a time necessary for the reset operation, and the current necessary for the reset operation is passed through the bit line and the memory unit. The transistor flows into the phase change element. After that, by blocking the current, the phase change element is quenched, and the phase changes to a high impedance state. After that, the column selection line COt / b and the word line WL are changed to non-selection levels, and the readout period ends. Next, a write operation will be described. Figure 11 is a timing diagram of the write operation. According to the write instruction, the write address is sent to. Similar to the read operation, the column selection line c 01 / b is activated, and at the same time, the bit line is precharged. After that, the word line WL corresponding to the address is selected, and the bit line is discharged by the memory cell transistor and the phase change element. At this time, the phase change element generates heat by reading the current, the phase changes from the high impedance state to the low impedance -24- 200527656 (21) state ', and the phase change from the low impedance state to the high impedance state, the state before reading destroyed. Between this action, the written data is sent to the sense amplifier. Here, after the read-out data is rewritten, the reset driver written in the driver is selected among the sense amplifiers that hold data corresponding to the high-impedance state of the phase change element of the memory cell in the sense amplifier column. On the other hand, among the sense amplifiers which hold the data of the low-impedance state of the phase change element corresponding to the memory cell in the sense amplifier row, a set driver written in the driver is selected. After that, in the activated write driver, in the time necessary for the reset operation, by resetting and setting the write start signal, a high voltage is applied to the bit line, and the current necessary for the reset and setting operation is The bit line and the memory cell transistor flow through the phase change element. Thereafter, by blocking the current, the phase change element is quenched and the phase changes to a high impedance state or the phase changes to a low impedance state. After that, the column selection line C0t / b and the word line WL are changed to the non-selection level, and the writing cycle ends. In this structure, when the word line is selected to read the data of the memory cell, by setting all the data of the memory cell to a low impedance state, it has the following advantages: (1) When reading, the bit can be set The pre-charging level of the element line is set to a high level, which can increase the amount of signals read out from the sense amplifier, and can achieve high-speed and stable read-out operations. (2) The setting range of the pre-charging level has degrees of freedom, while the power supply design becomes easy, it can also cope with power supply changes based on noise and so on. (3) By rewriting the read data, the reliability of the data based on the read operation can be reduced. (4) Deterioration of the record-keeping characteristics of the phase change element, such as high-speed operation at a temperature of 125 ° C or higher and long-term storage, are possible. -25- 200527656 (22) In the first and second embodiments, although the read voltage is set to a voltage higher than Vset or higher than Vreset in the phase state change of the phase change element, it is operated at a voltage lower than this. In this case, as in Examples 1 and 2, it is possible to perform a rewrite operation. In addition, in this case, it is not necessary to rewrite for the reading operation, so it can be rewritten at a specific number of times, for example, the number of times that can be read] / 10 times, or after a specific operation time has passed Action is also possible. In this case, as in Embodiments 1 and 2, it can prevent the destruction of data caused by thermal interference and interference during operation, and can reduce the number of rewrites compared with the number of reads. It can also improve the phase change. Advantages of component rewrite tolerance. < Embodiment 3 > Next, a description will be given of an array structure in which reliability of existing data is improved. As described above, the phase change element in the reset state is subject to thermal interference and may cause a phase change to the set state based on a read operation or an action at a high normal temperature. On the other hand, the possibility that the phase change element in the set state causes a phase change to the reset state is considered to be considerably less than the possibility that the phase change element in the reset state causes a phase change to the set state. Therefore, by keeping the redundancy of plural memory cells and storing 1 bit of data, the phase change element can improve the reliability of the stored data. Fig. 12 is an embodiment of the present invention. Bit lines BL 0 0, BL 0], BL02, BL03 .... and 8B] 0, 6B11, 8B12, 3B13 ... points 5 [[connected to the memory of the previous Figure 2 The body cell array MCA is also constructed of the billion cell body arrays MCA 0 and MCA 1. Bit lines BL 0 0, BL 0], -26-200527656 (23) BL 0 2, BL 0 3 ... sense amplifier block SAB 0 and bit lines BL10, BL11, BL12, BL13 are connected The sense amplifier block SAB] may be the circuit structure of the sense amplifier block SAB of any of the foregoing embodiments. Data input and output lines 1/00 are provided by the sense amplifier block SAB0, and data input and output lines I / O 1 are provided by the sense amplifier block SAB. 1 is output as a complementary signal (t / b). The output signal line is input to the logic sum block ORB. Logic and block 0 RB uses these input signals to output external output data DOt / b. In addition, the logic OR block ORB transmits the externally written data DIt / b to the sense amplifier blocks SABO and SAB 1. Next, a read operation in this embodiment will be described. The memory cell arrays MCA 0 and MCA 1 are activated at the same time as one address is input. The signals read by the memory cell M c at the specified addresses at this time are: the signals read by the memory cell MC of the memory cell array MCA 0 are sensed and amplified by the sense amplifier block SAB0, The signal read by the memory cell MCT of the memory cell array MCA 1 is sensed and amplified by the sense amplifier block SAB 1. At this time, in the sense amplifier block, data is output according to the relationship between the phase state of the memory cell MC in FIG. 13 and the output voltages of the complementary signals I / 0 * t and l / 0 * b. That is, when the phase state is a high-impedance state (Reset), the input / output signals I / OO 01 and I / Ο 1 t are in a 状态 'state, and in the low-impedance state (S et), the input / output signals I / 〇 t, I / Ο] 6 becomes L: state. And 'in the logic and block 〇RB that accepts these input and output signals, perform the logical sum of the input and output signals I / 〇0 t and I / 〇1 t' and output the external output data D 01 / b ° Figure 3 Display the input and output signals] and I / 0] t and the relationship between the external output data -27- 200527656 (24) data D0t. As shown in the figure, when one or both of the input / output signals I / 〇〇t and I / 〇11 are Η, the state of the external output data is Η ′. If the state of the phase change element of the memory cell is changed, one or both of the memory cells of the read memory cell array MCA 0 or MCA 1 are in a high-impedance state (when Res e0, then The external output data D 0 t becomes Η. Next, the writing operation of this structure will be described. At the time of writing, the written data is input to the logic OR block ORB by an external input data signal DIt / b. The logic OR block ORB In the process, the external input data signal DIt / b is transmitted to the input / output signal I / O 〇t, I / O Ob, and the input / output signal I / O It 'I / Olb through switches. These input and output signals are sent separately. To the sense amplifier blocks SAB 0 and SAB 1. In the sense amplifier blocks SAB 0 and SAB 1, the same as the sense amplifier block SAB of the previous embodiment, the memory is aligned with the memory cell arrays MCA0 and MCA1. The unit performs the operation of writing data. Next, the advantages of this structure will be explained. In the phase change memory, it is possible to prevent the destruction of data caused by the phase change due to high temperature standby or continuous readout, etc., or defective bits. Lowered the reliability of the data caused by the temperature drop or bit drop, etc. It is possible to perform high-speed operation and long-term storage of the phase change element whose record retention characteristics are deteriorated, such as 1 2 5 ° C or more. Here, although 2 Each memory cell MC records 100 million bits, but it can also be a structure that stores in more than two memory cell MCs and outputs the logical sum of the read result. In this case, only 3 There is a high-impedance state, and by outputting Η ', the reliability of -28- 200527656 (25) liters of data can be improved. The operations shown in Fig. 10 and Fig. 11 as described so far Although the reliability is greatly improved, the read voltage is set to a voltage higher than Vset or higher than Vreset when the phase state of the phase change element is changed. Therefore, the read operation must be performed again during the read operation, and the power consumption of each cycle In the embodiment described next, in the same circuit structure, in order to reduce power consumption, the case where the read voltage is set to a voltage lower than Vset, Vreset of the phase state of the phase change element will be described. In this case Even if the reading operation is performed, the data will not be destroyed in each reading operation, and the rewriting operation can be performed in a specific operation cycle. Therefore, low power consumption can be achieved. Even in this case, it can be prevented from being caused by heat. In addition to the destruction of data caused by interference and interference during operation, compared with the number of readouts, the number of rewrites can be reduced, and the rewrite resistance of the phase change element can be improved. In addition, the circuit structure can be the aforementioned embodiment 1 ' One of 2 and 3. That is, the rewrite operation is performed only in a specific period, so it can be achieved by activating the reset enable signal WRE and the set enable signal WSE of individual embodiments only in a specific period. For example, by using a logic circuit as shown in FIG. 22, a reset signal WRE and a set write signal WSE are generated to perform a rewrite operation, and the rewrite operation is realized in a specific operation. In this figure, the rewrite enable signal RW indicates a signal for performing a rewrite operation on a select memory cell on a select character line. The memory pad selection signal MSB is to decode the input address and display the signal in a specific address range. Regardless of the read operation and write operation, corresponding to the input address, one of the memory pad selection signals on the memory array. The MSB is chosen. Reset time specified pulse -29- 200527656 (26) ITReset is a pulse that specifies the write time to reset the write operation. The same stack setting time specified pulse TSet is a pulse of write 7 which defines the setting write operation. Fig. 23 shows an operation example of the circuit structure. As usual, the memory pad selection signal M S B is changed to the active state. For example, after this low-potential state, when the write start signal is activated, the pulse TReset is specified by this signal and reset time to reset the start signal WRE. Similarly, the set-start WSE is activated by setting the time-set pulse TSet. Conversely, in the case where the rewrite activation signal RW is inactive ', even if the memory pad selection signal MSB becomes activated, neither the activation signal WRE nor the activation signal WSE is set. That is, the rewrite operation can be controlled by the rewrite start signal RW to illustrate the advantages of this structure. Rewrite is not performed every time a read operation is performed 'only when a specific rewrite start signal is activated, thereby reducing the number of rewrites and improving the reliability of the phase change film. In addition, in the reading operation, there is no possibility that the data will be destroyed. Since the reading operation is accompanied by the rewriting operation, the cycle time can be shortened. The power consumption of the re-write operation can be removed, so it can also achieve power consumption. Furthermore, compared with a case where only a non-destructive read operation is performed, a rewrite operation in a specific period has an advantage that the reliability of the memory can be improved. Next, "the method for generating the rewrite enable signal RW and the embodiment in which the rewrite operation is performed in the aforementioned specific cycle will be described. Fig. 24 shows the memory chip of the input pins or instructions used for the REF operation in addition to the normal read and write instructions: ground, time, and time. Fig. 23 shows the status of some signals being activated. Reset activation and activation can be, but will not further reduce, borrow the information about the actual Jane 30-200527656 (27) single block diagram. The memory array M A is formed by a plurality of memory cell arrays MC A, and is adjacent to the individual memory cell arrays MC A and is provided with a sense amplifier block SAB. On one end of the memory array MA, a pre-decoder RPDEC for driving and controlling an address line for the row decoder RDEC and a column decoder CDEC for outputting a column selection signal are arranged. The column decoder is provided with an array transfer memory. External output of data output from the volume array MA or data input section I / O-CTL for data input from the outside. The memory chip is provided with an externally input address AO, A 1 ... or an instruction address buffer INPUT Buffer, and a DQBU ffer for inputting and outputting external data, and an external voltage VCC and Ground potential GND to generate internal voltage word line selection level VWH, word line non-selection level VWL, sense amplifier power VDL, reset write voltage VfWR, set write voltage VWS, peripheral circuit power voltage VCL, The internal power supply generating circuit VG, which has a potential of approximately VSS and a source potential VS. This structure is characterized in that the input command includes a rewrite command REF or a rewrite pin REF for performing a rewrite operation. Fig. 24 is a block diagram of a sense amplifier and a memory cell array MCA, which are the same as Figs. 1 and 2 described above. Next, the operation of this embodiment will be described. Fig. 25 is an operation example in which the structure of Fig. 1 is applied to the sense amplifier block SAB of Fig. 24. When a read command Read is input from the outside, the column selection signal is activated according to the address input at the same time. In addition, the pre-charge signal PRE of the sense amplifier block corresponding to the address is activated. As a result, the bit line is precharged to the read level VR. At the same time, the bit line separation signal connecting the sense amplifier SA and the sense bit line BLSA also becomes -31-200527656 (28) in a high potential state. After that, while the bit line precharge signal P R E is deactivated, the word line W L is changed from the non-selected state V W L to the selected state V W 依据 according to the input address. At this time, when the phase change element of the memory cell MC is in a low-impedance state, as shown by the dotted line in the figure, it suddenly changes to the source line SL potential VS. On the other hand, in the high-impedance state, the bit line readout level is maintained near V R. After a certain period has elapsed, when the sense amplifier generates a sufficient signal, the bit line separation signal BLI is changed to a low voltage V S S, and the sense amplifier and the sense bit line B L S Α are separated. After that, the sense amplifier SA activates the signal SE / SEB through the sense amplifier, and amplifies the tiny signal read by the memory cell MC to the sense amplifier power VDL. After that, it is transferred to the I / O control and DQ buffer. Before and after, the activated character line WL... Changes to the non-selection level V WL. After that, the sense amplifier becomes inactive by making the sense amplifier activation signal inactive. At the same time, the column selection signal is switched to the non-selection state, and the readout period ends. Next, the operation when the rewrite command REF is input will be described. The address input at the same time as the instruction or the address generated by the address counter ADD-C in the memory chip CHIP is activated until it is read out in the sense amplifier, which is the same as the previous read operation. Here, the rewrite start signal R W is activated to a high potential state in accordance with the rewrite command R E F. As shown in the operation waveform diagram in Figure 23, the write start signal RW is activated, and the reset start signal WRE is activated by the memory pad selection signal corresponding to the selected address and the reset time prescribed pulse TRe set. Once the reset enable signal is activated, the data held in the sense amplifier corresponds to a high-potential state, that is, I / Ot setting -32-200527656 (29) is a high-impedance state and I / Ob is set to a low-potential state In the write drive WD, the reset voltage is applied to the memory cell MC through the sense amplifier bit line BLSA and bit BL0, and the electrical reset start signal necessary for the circulation write only specifies the pulse at the reset time. After the time determined by TReset is activated, it transitions to a low potential state and the reset operation ends. The operation after the operation is the same as the aforementioned reading operation. In this operation, it is assumed that the rewrite operation is only a reset operation with a short write time. This is because the thermal interference of phase change memory or the interference of reading action, the error setting of the resetting component into the setting state is more likely to occur than the wrong resetting of the setting state and the resetting state. Therefore, compared with the read cycle tRC, the rewrite cycle tRC7 is performed in this operation. Although the rewrite operation is performed, only the reset of the write time is short, so the cycle time can be extended. Shares are reduced. The advantages of this embodiment will be described. In the normal read and write operations, by setting the rewrite operation, the rewrite operation can be performed before the data based on the read operation is destroyed, which can improve the reliability of the data. Further, since only the reset operation is performed during the reoperation, there is an advantage that the amount of extension of the operation due to the rewrite operation can be reduced. Next, the operation of the case where the sense amplifier block of FIG. 8 is applied to the sense amplifier block of FIG. 24 described above. The 2nd 5th shows the operation example of this structure. The feature of this structure is to perform two operations of a reset operation and a set operation based on a command from the outside as a rewrite operation of the memory cell data at a specific address. Regarding the read cycle when a read command is input, it is the same as that in Fig. 25. Next, the actuator streamed. Write in the action. The state changes to the action. In addition to the action, you can write into the S AB picture system. Input operation and fetch instruction. Explanation -33-200527656 (30) The action when the rewrite command REF is input. The address input at the same time as the instruction or the address generated by the address counter ADD-C in the memory chip CHIP is activated until it is read out in the operation of the sense amplifier, which is the same as the aforementioned Fig. 25. Here, according to the rewrite command REF, the rewrite start signal RW is activated to a high potential state. As shown in the operation waveform diagram in Fig. 23, the write start signal RW is activated again, and the reset start signal WRE is activated by selecting the MSB signal corresponding to the memory pad at the selected address and the reset time prescribed pulse TReset. Once the reset enable signal is activated, when the data held in the sense amplifier corresponds to a high-potential state, that is, when I / Ot is set to a high-impedance state and I / Ob is set to a low-potential state, it is written into the drive WD The reset voltage is applied to the memory cell MC through the sense amplifier bit line b LSA and bit line BL 0, and a current necessary for writing is passed. The reset start signal is only activated after the time determined by the reset time prescribed pulse TRe set, and then it is switched to the low potential state, and the reset operation ends. Similarly, as in the operation waveform of FIG. 23, the start signal RW is re-written. The signal is activated by setting the corresponding signal MSB of the selected address and the set time specified pulse T S e t to activate the set signal W S E. Set start signal WSE — Activated, in the case where the data held in the sense amplifier is in a low impedance state, that is, I / 〇t is set to a low-potential state, and I / 0 bg is affected when it is set to a high-potential state. In the driver w D, a set voltage is applied to the memory cell MC through the sense amplifier bit line BLSA and the bit line BL 0, and a current necessary for writing is passed. The setting start signal w S E is activated to a low-potential state after the time determined by the set pulse time s s t is activated only, and the setting operation ends. After the writing operation is completed -34-200527656 (31) The operation 'is the same as the previous reading operation. In this operation, as compared with the read cycle t R C, the cycle t R c for performing the rewrite operation is not only reset but also set. Therefore, a relatively long time is required, for example, 50 ns to] " < The advantages of this embodiment will be described. In addition to the normal read and write operations, by setting the rewrite operation, before the data based on the read operation is destroyed, the rewrite operation can be performed, which can improve the reliability of the data. Furthermore, in the rewrite operation, 'not only the reset operation but also the setting operation, compared with the foregoing embodiment' has the advantage that the reliability of both data is improved. Next, a structure for performing a rewrite operation on the memory chip CHIP by using an error prediction and detection function of the memory unit data will be described using an embodiment. Fig. 27 is an example of a block diagram of a memory chip with an error detection function added to the memory chip. Compared with the foregoing Fig. 24, it is characterized in that the address counter can be omitted. The other structures are the same as those in Fig. 24. Figure 28 is a block diagram showing the memory cell array MCA and its peripheral circuits. Same as the first figure, it is adjacent to the memory cell array MCA, and is arranged by driving the row decoders RDEC, bit lines BL 0, BL 1, BL 2, ... of word lines WL0, WL1, WL2, ... There is a sense amplifier block SAB for reading data recorded in a memory cell. Furthermore, in this structure, a copy bit line BL_REP which is arranged adjacent to the bit lines BL0, BL], BL2,... Is arranged in the memory cell array MCA. Furthermore, a sense amplifier block circuit SAB_REP for a replicated bit line is arranged corresponding to the replicated bit line. The copy of the sense amplifier block SAB_REP for the bit line output is -35- 200527656 (32) RW0, which is the original signal of the rewrite enable signal RW. The rewrite enable signal RW is converted from the rewrite enable original signal RWO to a pulse width as shown in FIG. 29 and output. FIG. 30 shows a configuration example of the memory cell array MCA of FIG. 28. Regarding the bit lines for copying, all the memory cell lines MC_REP are arranged for the word lines. The copying memory cell MC_REP has, for example, the same structure as the conventional memory cell MC in Fig. 3. However, it is characterized in that the phase change elements in all the memory cells on the bit line are set to a high impedance state. Fig. 31 shows an example of a block diagram of the above-mentioned replication sense amplifier block SAB-REP. The bit line pre-charging circuit BLPC is a circuit that pre-charges the bit line to a desired level VR during a read operation, for example, by pre-charging the MOS transistor of VR as shown in FIG. 32 and during standby , Set to MOS transistor with source line potential VS. The write drive WD has the same structure as the aforementioned FIG. 5 (a). The sense amplifier circuit SA_REP is a circuit that amplifies the tiny signal read out on the bit line BLSA to the amplitude of the sense amplifier power VDL, and outputs the rewrite to start the original signal RWO and write data to the driver WD. . Fig. 33 shows a circuit configuration example of the sense amplifier SA_REP. In this sense amplifier, a reference VREF-REP for reproduction is used as a reference level. VREF — REP is set at a high level compared to the VREF used in the aforementioned sense amplifier block S AB. As a result, compared with the usual sense amplifier block, even in the case of calling a memory cell with a relatively high impedance state, it can be easily read in a low impedance state, and it is possible to detect the destruction of read data in a high impedance state. In the present sense amplifier, in the case of reading a low impedance state, the bit line on the reference side is outputted as a rewrite start signal R W 0 by an inverter -36-200527656 (33). Describe the advantages of this construction. By arranging the memory unit for copying in the same memory unit as the usual memory unit, the influence of the deviation can be reduced, and the memory unit having the same characteristics as the ordinary memory unit can be used. Advantages of observation data retention characteristics. By setting the reference level of the sense amplifier for copying to the high-impedance side, it is usually possible to detect the data by copying the memory cell before the memory cell is changed from a high-impedance state to a low-impedance state based on readout. Therefore, it has the advantage of improving the reliability of the memory data. The receiver 'will use FIG. 34 to describe a method for generating a rewrite start signal using the RR cell array described in the third embodiment. Figures 3 and 4 show the memory cell array MCA and the sense amplifier block S AB and OR logic block ORB 2 of the previous Figure 2]. The OR logic block ORB2 is the same as that in the foregoing embodiment 3. By acquiring OR logic for reading data, errors caused by the transition from the high-impedance state to the low-impedance state can be reduced. In this structure, it is characterized in that if the data between the two read data 1/00, I / O] is different, the high-impedance state is written to the two memory cells and then rewritten. Enter the output circuit of the original signal RW0. The other structures are the same as those of the third embodiment. The advantages of this configuration will be explained. In this design, the copy memory unit is not used. Instead, the memory unit is used to memorize the actual data. Therefore, the data error detection can be performed without being affected by the characteristics of the units. Furthermore, 'the two memory units memorize the same data, and by using OR logic, not only can the correct data be output', but also the correct data can be written, which can achieve high reliability of the memorized data. General -37-200527656 (34) Often, when two memory units are used, it is difficult to detect which memory unit has the correct information by detecting different data to detect the error. However, in the case of using a phase change element, the impedance state of the phase change element is basically an error in which the reset state (high impedance state) is changed to the set state (low impedance state). Therefore, if the impedances of the two memory cells are different, and an error is detected, it can be known that a data error has occurred in the memory cells that are in the set state. The operation using the circuit structure of Fig. 28 will be described with reference to Figs. When a read command is input, the operation when no error is detected is the same as that in the above-mentioned Fig. 25. On the other hand, in the operation in the second cycle of Fig. 35, an error may be detected at the same time as the display and reading operations. First, from the input command until the data is read on the bit line, until the sense amplifier holds the data, it is the same as the normal read operation. Here, when the phase change element of the duplicated memory cell changes from a high-impedance state to a low-impedance state, the output node I / 0_REPt / b of the duplicated sense amplifier that reads the duplicated bit line detects a low-impedance state. When a low-impedance state is detected, the rewrite enable original signal RW0 is activated, and the rewrite enable signal RW is activated. Rewrite activation signal RW—is activated, senses the reset activation signal WRE and the sense amplifier output I / 0_REPb for copying the bit line, and the write driver WD applies a reset write voltage VWR to the bit line. The reset write voltage is applied only during the period during which the reset enable signal WRE is activated, and it drops immediately. As a result, the copy memory unit is rewritten to a high-impedance state. This operation is the same. For the memory cell MC that stores data, but also for the memory cell whose read impedance state is high impedance state, and the reset write action for copying the memory unit -38-200527656 (35) Similarly, a reset write operation is performed. As a result, the high-impedance memory phase change element of the memory unit that stores data also performs a rewrite operation, and the data retention characteristics are improved. Describe the advantages of this action. In this operation, only the reset write operation with a short fring time can be entered. Therefore, the rewrite operation can be performed within the cycle time of the normal read operation, and it is possible to mask the failure caused by the rewrite operation. The advantages of access. The description of the “receiver” is the same as the embodiment shown in FIG. 27, so that the memory chip CHIP has an error detection function, and further has a rewrite operation to prevent the external memory controller from issuing the memory chip CHIP. The structure of the busy pin WAIT for access request. Fig. 36 is characterized in that the structure shown in Fig. 27 is provided with a busy pin WAIT as an output pin. The structure other than this is the same as that of FIG. 27 described above. This structure is different from the foregoing embodiment, and is suitable for a case where the cycle time is longer than a normal read cycle in a read cycle accompanied by a rewrite operation. Figure 37 is a block diagram showing the output method of the busy pin WAIT. The busy pin W A I T is a high-potential state and a low-potential state by receiving a rewrite enable signal, and it is used for the external memory controller 'to convey that the memory cannot be used. Therefore, compared with the read operation, even when the time required for the rewrite operation is long, the state is transmitted to the memory controller, which has the advantage of preventing data conflicts and data loss. An example of the operation waveform diagram of this structure will be described with reference to Figs. This operation is an example of operation waveforms in the case of using the memory cell array MCA and its surrounding circuit blocks with the duplicated memory cells as shown in Fig. 28 of the foregoing embodiment. The read operation without rewriting in the first cycle of the figure is the same as in the previous embodiment -39- 200527656 (36). Next, in the second cycle, an example of performing a rewrite operation in conjunction with a read operation. In this operation, it is the same as the previous embodiment until the signal read out by the memory unit is kept in the sense amplifier. As shown in Figure 35 of the example of the operation waveform diagram of Figure 28 above, when the read data of the memory cell on the copy bit line is read from the high impedance state to the low impedance state, the signal of the low impedance state I / O-REPt, which is output at the output node of the sense amplifier. Thereby, the rewrite enable signal RW is activated. Rewrite start signal RW — is activated, reset start signal WRE is activated, and the reset read operation is performed on the unit that reads the reset status. At the same time, the setting start signal WSE is also activated, and the setting writing operation is performed on the unit that reads the setting status. Reset start signal WRE becomes inactive after the reset write time. On the other hand, in the setting writing operation, a writing time of 50 ns to 1 μs or more is required, during which the setting start signal is maintained to be activated. After a certain period of time has elapsed, the setup enable signal WSE is deactivated and becomes standby. During this writing period, the memory chip cannot be accessed externally. In order to communicate it to the controller, the busy pin WAIT is changed to a low potential state. This prevents the issuance of action instructions from the external controller. Describe the advantages of this structure. In the rewrite operation, not only the reset write, but also the setting data can be used to improve the reliability of the two data. Furthermore, by setting the busy pin, it is possible to suppress the issuing of instructions from the controller during a period when the memory chip cannot be accessed, and data conflicts and disappearance can be prevented. Next, a modification of the foregoing embodiment will be described with reference to Figs. In this structure, '' is a write operation and only a reset operation is performed, which is a characteristic of this. -40 _ 200527656 (37) In the aforementioned write operation, only the reset start signal WRE is activated, and the reset write operation is performed on the memory cell that reads the reset state. On the other hand, for the memory cell that reads the set state, no write operation is performed. In order to prevent the external controller from issuing a command between reset and write operations, the busy pin WAIT is changed to a low potential state. As a result, the external controller does not access the memory chip. The advantages of this configuration will be explained. In addition to the prevention of data conflict and disappearance by setting the busy pin, in this structure, it can be completed with a relatively short write time of about 50ns. Only the reset operation and the rewrite operation can be performed, so that the memory can be made. The time during which the chip is in the busy state becomes shorter, which has the advantage of shortening the inaccessible time. Next, a description will be given of an example of a case where multiple memory and OR units are combined. Figure 40 shows the distribution of the impedance 値 in the case of using a phase change element for multiple memory. A high-impedance state is assigned to an impedance state R3 5 1 1 ′, an impedance state R2′10 ′, an impedance state R] 5 0 0 ′, and an impedance state RO′Ol;. When allocated in this manner, there is an advantage that even if it is changed to the adjacent state, the possibility of both bits becoming errors is reduced. In the case of using a phase change element, the impedance state of the phase change element is basically an error in which the reset state (high impedance state) changes to the set state (low impedance state). Therefore, an OR cell array in which two cells store the same data is used to realize an array capable of achieving high data reliability. Figure 41 shows the relationship between the impedance state of the phase change element of the two memory cell arrays MCA 0 and MCA], and the memory data MLBt / MSBt. As explained earlier, it is a structure in which the data of a memory cell in a high-impedance state is output as true in two memory cells. For example, remembering that the state of the memory cell of the cell unit array MC A0 is R3, even though the state of the memory cell of the memory cell array MC A 1 is any one of the types of the output data M LB t / MSB t also becomes, 1, /, 1 '. The structure of the array to achieve this will be described. Figure 42 shows a block diagram of the peripheral circuit of the memory cell array. A memory cell array MCA 1 and MCA0, a sense amplifier block S AB — M, SA B — M, and an OR logic part ORB — M are arranged. Figure 43 is an example of a block diagram of a sensor amplifier block SB-M. The same as in the previous embodiment, a bit line selection circuit BLSEL, a write driver WD_M, and a sense amplifier circuit SA are provided. The input / output section is provided with an I ○ gate I 〇 G that converts and reads data. In addition, the sense amplifier circuit can be read at different times, and is configured with three sense amplifier circuits using three reference levels VREF0, VREF1, and VREF2. Fig. 4 shows the circuit structure of the write driver WD_M arranged in the sense amplifier block SAB_M. The write voltage is determined by I / 0 0, I / O 1, 1/0 2, 1/03 corresponding to the impedance state of the memory cell, and the write period is determined by the write enable signals W0, W], and W3. The circuit construction. In the 10 gate, referring to the three sense amplifiers SA01t / b, SA01t / b, and SA2t / b, corresponding to the impedance state of the memory cell, at the output node I / O 〇, 1 / 〇], 1 / One of the outputs of 02, 1/03. Figure 46 is a block diagram of the logic part of the OR. The read block RE_M is a circuit block that detects the data read by the two memory cell arrays M C A 0 and M C A 1 and outputs incorrect data. Write block WE — M is 200527656 (39) when the data input from the outside is written back, or the correct data is written by error detection, the corresponding impedance state is output to the memory cell array MCA0 ' Signal I / Ο] 1, I / 〇 0 1, I / 〇 〇2, I / Ο 0 3, and for the memory cell array 歹 "MCA], output signals corresponding to the impedance status 1/010, I / O Π, 1/012, I / O 1 3. The error detection circuit DET detects the presence or absence of errors by comparing the data read by the memory cell array 歹 IJ MCA. In the case of errors, the output is re-written to start the original signal RW0. Fig. 47 shows a specific circuit configuration example of the read block RE_M. As shown in the figure, the most significant bit MLBt is a NAND logic that obtains NOR logic of 1/000 and 1/010 and a NAND logic of 1/001 and 1/011. Similarly, the least significant bit MSBt is a NAND logic that obtains the output of NAND logic of 1/003 and 1/013 and the output of NOR logic of 1/00 and 1/010. In this way, the conversion that satisfies the table of Fig. 41 can be realized. Figures 4 and 8 show an example of the circuit structure of the write block WE_M. These are the reverse conversions of the previously read blocks R: E-M. Fig. 49 shows a circuit configuration example of the error detection circuit DET. For the memory cell arrays MCA0 and MCA1, the corresponding output signals 1/000 and 1/010 and I / O] 0 and 1/01 1 and 1/0 02 and I / O〗 2 Ex- The output of OR logic is obtained by performing OR logic. As a result, in the case where a certain output signal is inconsistent, the original signal RW 0 which becomes the rewrite start is activated. Explain the advantages of this structure. In the multi-memory memory method where margins become smaller, by combining OR cell arrays that store the same data in a plurality of memory cells, the reliability of the memory data can be improved 'and the retention time can be made longer. In addition, an additional error detection circuit is added. By rewriting when an error is detected, it is possible to correct and record the errors of the data of the billion-body unit, thereby improving the reliability of the data. Describe the voltage conditions. The word line selection level can be equal to the external voltage-43- 200527656 (40) VCC]. 8V or 1.5V, or 2.5V or 3.0V after internal boost. By using high voltage, the memory The current driving force of the unit transistor becomes stronger, so that even if the size of the memory unit transistor is small, the current can be rewritten, so it has an excellent bottom that can realize a small single-area area of the memory. The sense amplifier power V D L and the peripheral circuit power V C .L can be 1.8 V, 1.5 V, or 1.2 V. By reducing the voltage, power consumption can be reduced. Setting the reset write voltage VWR to a potential equal to the external voltage VCC is more desirable in reducing power consumption. [Brief description of the drawings] Figure 1 is a structural diagram of an array and peripheral circuits according to Embodiment 1 of the present invention. Figure 2 is a structural diagram of a memory cell array. Figure 3 is a structural diagram of a memory unit. Fig. 4 is a circuit configuration example of a bit line selector. Fig. 5 is a circuit configuration example of a write driver and a sense amplifier. Fig. 6 is a waveform diagram of a read operation according to the first embodiment of the present invention. FIG. 7 is a waveform diagram of a write operation in Embodiment 1 of the present invention. Fig. 8 is a circuit configuration of a sense amplifier block in Embodiment 2 of the present invention. Fig. 9 is a circuit configuration example of a write driver. Fig. 10 is a waveform diagram of a readout operation according to the second embodiment of the present invention. FIG. 1 is a waveform diagram of a write operation in Embodiment 2 of the present invention. Fig. 12 is a diagram showing the structure of the array and its peripheral circuits in Embodiment 3 of the present invention -44-200527656 (41) Fig. 13 is a table showing the relationship between the memory cell data and output data in Embodiment 3 of the present invention. Figure 14 is a current-voltage diagram of the phase change memory. Figure 15 is a waveform diagram of the bit line's pre-charging level and voltage reduction action. Figure 16 is a current-voltage diagram of the phase change memory. Figure 17 is a current-voltage diagram of the phase change memory. Fig. 18 is a cross-sectional view of a memory cell of a phase change memory according to the first embodiment of the present invention. Figure 19 shows the lattice constants of the Ge2Sb2Te5 phase change material and the lower electrode material. Figure 20 shows the relationship between the reset current and the material of the lower electrode. Stomach 2 1 shows the relationship between the reset voltage and the film thickness of the phase change material when the phase change material changes from a crystalline phase to an amorphous state. Stomach 2 2 is a control method diagram showing reset activation signal and setting activation signal. Figure 2 3 shows the operation waveform legend of Figure 2 2. Figure 24 is a block diagram of a memory with a rewrite command. Fig. 25 is an example of the operation waveforms of the memory in Fig. 24. Fig. 26 is another example of waveforms of operation of the memory of Fig. 24; ^ 2 7 is a block diagram of the memory with self-rewrite judgment action function. Figure 28 is a block diagram of the main part of the memory array of Figure 27 in ^ 45- 200527656 (42). Fig. 29 is a structural example and operation waveform diagram of the write enable signal generating circuit. Fig. 30 is an example of the structure of the billion-body array in Fig. 27. Fig. 31 is an example of a block structure of a sense amplifier for copying bit lines. Figure 32 shows an example of a pre-charge circuit structure. Fig. 33 shows an example of a circuit structure of a sense amplifier for copying bit lines. Figures 3 and 4 are examples of the method of generating a write enable signal using a 0 R cell array. Figures 3 and 5 are examples of waveforms of the operation of the memory with self-rewrite judgment function. Figure 36 is a block diagram of the memory with self-rewrite judgment function and status output pins. Figure 37 is a block diagram of the busy line output pin output circuit. Figure 38 is an example of the waveforms of the memory operation in Figure 36. Fig. 39 is an example of another operation waveform of the memory of Fig. 36. Figure 40 is a diagram showing the impedance distribution and data transfer in the case where the phase change element performs multiple memory. Fig. 41 is a diagram showing an example of data mapping in a case where two multi-memory memory elements are used to form an OR cell array. Fig. 42 is a block diagram of a memory cell array and a sense amplifier and a logic section of 0 R when a multi-chip memory element and an OR cell array are combined. Figure 43 is a block circuit configuration example of the sense amplifier in Figure 42. Fig. 44 is a circuit configuration example of the write driver in Fig. 43. -46-200527656 (43) Figures 4 and 5 show examples of the input and output circuit structure shown in Figures 4 and 3. Fig. 46 is a block diagram of the OR logic section of Fig. 42; Fig. 47 is a block diagram showing the structure of the read data of Fig. 46. Fig. 48 is a block diagram showing the structure of writing data in Fig. 46. Fig. 49 is a diagram showing a configuration example of the error detection circuit of Fig. 46. [Symbol description of main components] upc: upper electrode, dwc: lower electrode plug, RDEC: row decoder / character driver, WL, WL0, WL1, WL2, WL3 ...: word line, BL, BL0, BL1, BL2, BL3, BL00, BL01, BL02, BL0 3, BL] 0, BL1 1, BL12, BL] 3…: bit line, BLSA: bit line in the sense amplifier, PRE: pre-charge signal, WRE: heavy Write start signal, WSE: Set start signal, SE: NMOS sense amplifier start signal, SEB: PMOS sense amplifier start signal, I / 〇t, I / Ob, 1 / 〇0t, 1 / 〇0b, I / 〇lt, I / 〇lb: input and output data lines, WD: write driver, SA: sense amplifier, SAB, SAB 0, SAB]: sense amplifier block, -47-200527656 (44) BLSEL: bit Line selector, MCA, MCA 0, MCA 1: memory cell array 歹 lj, VREF: reference level, COt ~ C3t, COb ~ C3b: 歹 ij select cloud number, MT: memory cell transistor, PCR: Phase change element, BLI: bit line separation signal, VWR: reset write voltage, VWS: set write voltage, ORB: logic sum block, DIt / b…: external input data line, D〇t / b: external output data line, V p, VR: bit line precharge level, TReset: specified pulse during reset, TSet: specified pulse during set, MSB: memory Pad selection signal, RW: rewrite enable signal, RPDEC: line pre-decoder, INPUT Buffer: input buffer, VG: internal power output circuit, DQ Buffer: input / output data buffer, I / O CTL: input / output Data controller, MA: memory array, REF: rewrite external command, -48- 200527656 (45) tRW: rewrite start signal pulse width, BL — REP: copy bit line, SA — REP: copy bit Sensing amplifier block for element line, RW — GEN: Rewrite enable signal generation block, RW 0: Rewrite enable original signal., MC — REP: Copy memory unit, B LP C: Bit line Pre-charge circuit block, VREF_REP: Reference level of sense amplifier for copying, I / O —REPt · • Output of sense amplifier for copying, WAIT: Busy output pin, WAIT_B: Busy output pin output buffer, R0 , Rl, R2, R3 ...: Phase change element Device impedance status, MLBt / b: Most significant bit, MSBt / b: Most significant bit, ORB_M: OR logic block -49-

Claims (1)

200527656 十 X. Patent application scope 1 · A semiconductor device characterized by having: a plurality of word lines, a plurality of bit lines, and a line including the word lines provided in the plurality and the bit lines provided in the plurality A plurality of memory cells with phase change materials at specific intersections, a sense amplifier connected to the bit line, and a sense amplifier connected to the sense amplifier, and write the first information into the first write of the memory cell Drive; after the reading operation, write the first information into one of the memory cells. 2. In the semiconductor device 'as described in item 1 of the scope of the patent application, the aforementioned first information is that the phase state of the aforementioned phase change material is memorized in an amorphous state. 3. The semiconductor device according to item 1 of the patent application scope, wherein the semiconductor device further includes a second write driver connected to the sense amplifier and writing the second information into the memory unit. 4. The semiconductor device described in item 3 of the scope of the patent application, wherein the first information is that the phase state of the phase change material is stored in an amorphous state, and the second information is the phase state of the phase change material. It is memorized in a crystalline state. 5. The semiconductor device according to item 3 of the scope of patent application, wherein after the reading operation, the writing operation of writing the second information into one of the aforementioned memory cells is performed. -50- 200527656 (2) 6. — A semiconductor device characterized by having: a plurality of word lines, a plurality of bit lines, and a plurality of word lines including the plurality of word lines and the plurality of bit lines The specific number of phase change materials of the plurality of memory cells, and the source line that is commonly connected to each of the memory cells, and the absolute difference between the potential difference between the source line and the bit line when the first information is written The first voltage and the third voltage which is the absolute difference between the potential difference between the source line and the bit line during reading; the third voltage is higher than the first voltage. 7. The semiconductor device according to item 6 of the scope of patent application, wherein the first information at the time of reading is read by a sense amplifier, and the aforementioned memory cell is rewritten. 8. The semiconductor device according to item 6 of the scope of the patent application, wherein the above-mentioned information] is that the phase state of the phase change material is memorized in an amorphous state. 9. The semiconductor device according to item 6 of the scope of patent application, wherein the first information is memorized in a crystalline state in a phase state of the phase change material. 10. The semiconductor device according to item 6 of the scope of the patent application, wherein the second voltage having an absolute value of the potential difference between the source line and the bit line at the time of writing the second information described above is the third voltage. Both the voltage and the second voltage are high. -51-200527656 (3) 1 1. The semiconductor device described in item 6 of the scope of patent application, wherein the second voltage has the absolute voltage of the potential difference between the source line and the bit line when the second information is written. The third voltage is higher than the second voltage and lower than the second voltage. [2] —A semiconductor device, comprising: a plurality of character lines, a plurality of bit lines, and a phase including a specific intersection of the plurality of character lines and the plurality of bit lines. A plurality of memory cells of varying materials, a first memory cell array and a second memory cell array including the aforementioned plurality of memory cells, and a first sensing unit reading data from the aforementioned first memory cell array Amplifier block, and a second data output line that outputs data from the aforementioned first sense amplifier block, and a second sense amplifier block that reads data from the aforementioned second memory cell array, and from the aforementioned second sense amplifier block The sense amplifier block outputs data to an external second data output line. 13. The semiconductor device according to item 12 of the scope of the patent application, further comprising a first logical sum circuit for obtaining a logical sum of the first data output line and the second data output line. 14. The semiconductor device described in item 12 of the scope of patent application, wherein the first information is that the phase state of the phase change material is stored in an amorphous state-52-200527656 (4). / · If the scope of the patent application] or the item 6 or item 12 is the half-membrane reversing device, the above description, please, the body unit is made of a phase change material and a selection switch. 16. The semiconductor device according to item 15 of the scope of patent application, wherein the maximum value of the absolute value of the potential _ between the source line and the bit line is 1.8 V or less. 17. The semiconductor device as described in item 15 of the scope of patent application, wherein the phase change material is a material containing Sb (antimony), and the film thickness thereof is less than 〇0ιιτη. 18. As described in item 17 of the scope of patent application In the semiconductor device, the phase change material is a material including Ge (germanium), Sb (antimony), and (hoof), and the film thickness is 20 nm or less. [9] The semiconductor device according to item 15 in the scope of the SRA patent, wherein tungsten is used as an electrode material for electrically connecting the phase change material and the selection switch. 20. The semiconductor device described in item 15 of the scope of patent application, wherein '' operates at an ambient temperature of 125 ° C or higher. 2 1. A semiconductor device, characterized by having: a plurality of character lines, a plurality of bit lines that intersect the plurality of character lines, and a plurality of character lines that intersect with the plurality of character lines, and The second bit line where the first bit line of the plural is arranged in parallel, and the -53-200527656 (5) at the specific intersection of the first bit line arranged between the plural word line and the plural] bit line. A unit, a second memory unit arranged at a specific intersection of the plurality of character lines and the second bit line, and a first sense of each specific line number arranged at the first plurality of bit lines A sense amplifier, and a second sense amplifier arranged on the second bit line; the first sense amplifier compares the first reference level with the corresponding bit line in the plurality of first bit lines; Signal level; The second sense amplifier is compared with a second reference level that is different from the first reference level, and a signal level of the second bit line. 22. The semiconductor device according to item 21 of the scope of patent application, wherein the aforementioned [reference] level is lower than the aforementioned second reference level. 2 3. The semiconductor device described in item 21 of the scope of the patent application, wherein the aforementioned [] and the second memory cell include the first conductivity type MIS FET (Metal Insulated Semiconductor Field Effect Transistor) and phase change Element 02. The semiconductor device according to item 23 of the scope of patent application, wherein the phase change element of the second memory cell is in a high impedance state. 2 5. The semiconductor device described in item 21 of the scope of the patent application, wherein the first sense amplifier has a first write-in circuit for writing the first memory information in the first memory unit]. Writing circuit; The second sense amplifier includes a second writing circuit for writing the first memory information in the second memory unit. 2 6. The semiconductor device described in item 25 of the scope of the patent application, -54-200527656 (6) where 'the first write circuit performs a write operation based on the output data of the aforementioned second sense amplifier. 2 7. The semiconductor device described in item 25 of the scope of the patent application, wherein the 'the aforementioned] sensing amplifier has a second writing circuit for writing the second memory information in the aforementioned first memory unit; The first and second writing circuits perform a writing operation based on the output data of the second sense amplifier. 28. The semiconductor device described in item 26 of the scope of patent application, wherein the aforementioned semiconductor device has a first output pin indicating an unusable state; between the aforementioned first or second writing circuit is activated, The above-mentioned first output and pin output indicate a signal that is not available. 29. A semiconductor device, comprising: a plurality of child lines, a plurality of first bit lines crossing the plurality of word lines, and a first conductive type MISFET (Metal Insulated Semiconductor Field Effect Circuit) Crystal) and phase change elements, and the memory cells arranged at specific intersections of the plural word lines and the plural bit lines of the plural numbers, and the desired arrangement of the plural bit lines and the plural bit lines The first sense amplifier of each line number and the first sense amplifier are arranged in accordance with a command input from the outside, and the first information read from the first memory is written into the first memory unit. Use the first write circuit. 3 0. A semiconductor device, comprising: -55- 200527656 (7) a plurality of first word lines and a plurality of first bit lines that intersect the plurality of word lines, and are disposed in the foregoing Plural] memory cells' and plural second character lines intersecting with the plural first character lines and the aforementioned plural first bit lines, and intersecting with the plural plural character lines The second bit line of the plural number, and the second memory cell of the plural number arranged at a desired intersection between the second word line of the plural number and the second bit line of the plural number, and each of the plurality of memory cells arranged in the plural number The first phase change element of the first memory unit, and the second phase change element arranged in each of the plurality of second memory units, and for the data written from the outside, corresponding to the written data, in the first Write the same impedance state as the second memory cell. 31. The semiconductor device described in item 30 of the scope of the patent application, wherein the semiconductor device further includes a first sense amplifier provided at each specific number of lines of the plurality of first bit lines, and provided at The second sense amplifier of each specific line number of the plurality of second bit lines, and the first] phase change element of the first memory cell arranged in the first sense amplifier are set to the first impedance State first write circuit, and -56- 200527656 (8) Set the first phase change element of the first memory unit of the first sense amplifier to the second write of the second impedance state Circuit, and a third writing circuit that sets the first phase change element of the first memory unit of the first sensing amplifier to a third impedance state, and a third writing circuit of the first memory unit that is disposed in the first sensing amplifier, and The first phase change element of the first memory unit is set to a fourth write circuit in a fourth impedance state, and the second phase change element of the second memory unit arranged in the second sense amplifier set up The fifth writing circuit in the first impedance state, and the sixth writing circuit in which the second phase change element disposed in the second memory unit of the second sense amplifier is set to the second impedance state, and A seventh write circuit in which the second phase change element arranged in the second memory unit of the second sense amplifier is set to a third impedance state, and the second memory arranged in the second sense amplifier The eighth writing circuit of the second phase change element of the body unit is set to a fourth impedance state; the first writing circuit and the fifth writing circuit are activated at the same time. The second writing circuit and the sixth writing are activated at the same time. The input circuit system is activated at the same time -57-200527656 (9) The 3rd write circuit and the 7th write circuit system are activated at the same time. The 4th write circuit and the 8th write circuit system are activated at the same time. " 2 * The semiconductor device described in item 30 of the scope of patent application, wherein the half-fin device described in Θ11 is a first sense amplifier having a specific number of lines provided in the aforementioned plurality of first bit lines , And set in the plural The second sense amplifier with a specific number of lines of the second bit line; the second memory line is read out by the first memory cell through the first bit line, and is held at the second position of the first sense amplifier. 1 data, and the 2nd data of the 2 billionth body unit is read out through the 2nd bit line, and kept in the 2nd data of the 2nd sense amplifier; in the 1st data and the 2nd data, The data corresponding to the high-impedance state is written into the memory unit.