JP2014154201A - Nonvolatile semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the load on memory cells so as to suppress degradation in data holding characteristics.SOLUTION: A memory cell array comprises memory cells that are arranged at intersections between a plurality of parallelly arranged first wiring lines and a plurality of second wiring lines arranged so as to intersect with the first wiring lines. The memory cells include a variable resistive element. A first driver circuit 1 for a set operation supplies voltage to the first wiring lines when the set operation for switching from a high-resistance state to a low resistance state is executed to the memory cells. A first driver circuit 1 for a reset operation supplies voltage to the first wiring lines when the reset operation for switching from a low-resistance state to a high resistance state is executed to the memory cells. The length of wiring line between the first driver circuit for the set operation and the memory cell array is longer than the length of wiring line between the first driver circuit for the reset operation and the memory cell array.

Description

  Embodiments described in this specification relate to a nonvolatile semiconductor memory device.

  In recent years, resistance change memory has attracted attention as a successor candidate of flash memory. A memory cell of the resistance change memory includes a variable resistance element, changes between a high resistance state and a low resistance state, and stores data based on the resistance state.

  In many cases, the anti-change memory is configured by disposing memory cells having such variable resistance elements at intersections of a plurality of bit lines and a plurality of word lines (cross point type).

  In such a cross-point resistance change memory, the parasitic resistance changes depending on the distance between the selected memory cell and the driver circuit that are the target of the write operation (set operation) and the erase operation (reset operation), and voltage application is performed. There is a problem that the conditions are different. Such a difference in voltage application conditions increases the load on the memory cell, degrades the data retention characteristics, and lowers the performance of the memory device.

JP 2011-44193 A

  Embodiments described below provide a nonvolatile semiconductor memory device that can reduce a burden on a memory cell and suppress deterioration in data retention characteristics.

  A memory cell array of a nonvolatile semiconductor memory device according to an embodiment described below includes a plurality of first wirings arranged in parallel and a plurality of second wirings arranged so as to cross the first wiring. The memory cell arranged in the part is provided. The memory cell includes a variable resistance element. The first driver circuit for set operation supplies a voltage to the first wiring when executing the set operation for switching the memory cell from the high resistance state to the low resistance state. The first driver circuit for reset operation supplies a voltage to the first wiring when executing a reset operation for switching the memory cell from the low resistance state to the high resistance state. The length of the wiring between the first driver circuit for set operation and the memory cell array is longer than the length of the wiring between the first driver circuit for reset operation and the memory cell array.

1 is an example of a block diagram of a nonvolatile memory according to a first embodiment. FIG. 2 is an example of a perspective view of a part of a memory cell array 110. FIG. 2 is an example of a perspective view of a part of a memory cell array 110. FIG. FIG. 3 is an example of a cross-sectional view of one memory cell taken along the line II ′ in FIG. 2 and viewed in the direction of the arrow. 3 is an example of a circuit diagram of a main row decoder 120. FIG. FIG. 3 is an example of a circuit diagram of a row driver 130 (a row driver for setting operation 130S and a row driver for reset operation 130R). 2 is an example of a cross-sectional view showing a specific structure of a row driver 130. FIG. 3 is an example of a circuit diagram of a write drive line driver 140. FIG. 3 is an example of a circuit diagram of a column decoder 160. FIG. It is an example of a circuit diagram of a column driver 170 (a column driver for setting operation 170S and a column driver for reset operation 170R). FIG. 3 is a schematic diagram illustrating a layout related to a wiring L according to the first embodiment. FIG. 10A is a schematic cross-sectional view taken along a dotted line a in FIG. 10A. It is the schematic which shows another layout regarding the wiring L of 1st Embodiment. FIG. 10D is a schematic cross-sectional view taken along a dotted line b in FIG. 10D. It is an example of the graph explaining the effect of 1st Embodiment. It is an example of the block diagram of the non-volatile memory which concerns on 2nd Embodiment. FIG. 13 is a cross-sectional view in the vicinity of a contact ZiaN in FIG. 12.

  Hereinafter, embodiments of the nonvolatile semiconductor memory device according to the present embodiment will be described in detail with reference to the drawings.

[First Embodiment]
First, the nonvolatile semiconductor device according to the first embodiment will be described in detail with reference to the drawings.

[overall structure]
FIG. 1 is an example of a block diagram of the nonvolatile memory according to the first embodiment.

  The nonvolatile memory includes a memory cell array core unit 100 surrounded by a dotted line in FIG. 1 and a power supply circuit 200 that generates and supplies a voltage used for the memory cell array core unit 100.

  The memory cell array core unit 100 includes a memory cell array 110, a row control circuit, and a column control circuit. The memory cell array 110 is provided at the intersection of a plurality of word lines WL extending in the row direction, a plurality of bit lines BL extending in the column direction intersecting the word lines WL, and the word lines WL and the bit lines BL. It consists of a plurality of memory cells MC. In FIG. 1, the memory cell array core unit 100 is configured by arranging four memory cell arrays 110 in a matrix, but the arrangement of a plurality of memory cell arrays is not limited to this.

  The word lines WL are divided into a predetermined number of groups by main word lines (not shown in FIG. 1). Similarly, the bit lines BL are divided into a predetermined number of groups by column selection lines (not shown in FIG. 1).

  The memory cell array core unit 100 selects a predetermined memory cell in the memory cell array 110 based on an address signal (Add) and a control signal (Cntr) supplied from the outside, and performs each set / reset / read operation. A row control circuit and a column control circuit to be executed are provided.

  The row-related control circuit includes a main row decoder 120, a row driver 130, a write drive line (WDRV) driver 140, and a row-related peripheral circuit 150. The main row decoder 120 selects a predetermined main word line based on the address signal. The row driver 130 supplies a voltage necessary for a set operation or the like to a predetermined number of word lines corresponding to the main word line according to the selected / unselected state of the main word line. The write drive line driver 140 prepares a voltage that the word line driver 130 supplies to the word line based on the address signal. The row-related peripheral circuit 150 includes other necessary row-related circuits.

  The row driver 130 includes a set operation row driver 130S and a reset operation row driver 130R. The set operation row driver 130S supplies a voltage necessary for the set operation to a predetermined number of word lines during the set operation. The reset operation row driver 130R supplies a voltage necessary for the reset operation to a predetermined number of word lines during the reset operation. The set operation row driver 130 </ b> S and the reset operation row driver 130 </ b> R selectively operate based on a control signal supplied to the row peripheral circuit 150. The set operation row driver 130S is disposed farther from the memory cell array 110 than the reset operation row driver 130R. That is, the length Ls of the wiring L between the set operation row driver 130S and the memory cell array 110 is longer than the length Lr of the wiring L between the reset operation row driver 130R and the memory cell array 110. Here, the definition of the length of the wiring L will be described later. The reason for adopting such a layout is to reduce the burden on the memory cells during the set operation. Details will be described later.

  In the example of FIG. 1, a plurality of memory cell arrays 110 are provided in one memory cell array core unit 100, and a set operation row driver 130S and a reset operation row driver 130R are provided in an area between the plurality of memory cell arrays 110. Is provided. The set operation row driver 130 </ b> S is shared by the plurality of memory cell arrays 110. On the other hand, the reset operation row driver 130 </ b> R is provided for each memory cell array 110. This is based on the fact that the relationship between the distances Lr and Ls described above is Ls> Lr.

  On the other hand, the column-related control circuit includes a column decoder 160, a column driver 170, a sense amplifier / write buffer 180, and a column-related peripheral circuit 190. The column decoder 160 selects a predetermined column selection line based on the address signal. The column driver 170 performs data input / output with respect to a predetermined number of bit lines corresponding to the column selection line according to the selection / non-selection state of the column selection line. The sense amplifier / write buffer 180 outputs the data input via the data input / output signal (I / O) to the column driver 170 or the data appearing on the bit line received from the column driver 170 as the data input / output signal. Or send it to the outside. The column peripheral circuit 190 has other necessary column circuits.

  The column driver 170 includes a set operation column driver 170S and a reset operation column driver 170R. The set operation column driver 170S supplies a voltage necessary for the set operation to a predetermined number of bit lines BL during the set operation. The column driver 170R for reset operation supplies a voltage necessary for the reset operation to a predetermined number of bit lines BL during the reset operation. The set operation column driver 170S and the reset operation column driver 170R selectively operate based on a control signal supplied to the column peripheral circuit 190.

  The set operation column driver 170S is disposed farther from the memory cell array 110 than the reset operation column driver 170R. That is, the length Ls ′ of the wiring between the set operation column driver 170S and the memory cell array 110 is longer than the length Lr ′ of the wiring between the reset operation column driver 170R and the memory cell array 110. The reason is the same as in the case of the row driver 130.

  In the example of FIG. 1, a plurality of memory cell arrays 110 are provided in one memory cell array core unit 100, and a set operation column driver 170S and a reset operation column driver 170R are provided in an area between the plurality of memory cell arrays 110. Is provided. The set operation column driver 170S is shared by the plurality of memory cell arrays 110. On the other hand, the reset operation column driver 170R is provided for each memory cell array 110. This is based on the fact that the relationship between the distances Lr ′ and Ls ′ described above is Ls ′> Lr ′.

[Memory cell array]
2A is an example of a perspective view of a part of the memory cell array 110, and FIG. 3 is an example of a cross-sectional view of one memory cell taken along line II ′ in FIG.

  A plurality of second lines, word lines WL0-WL2, are arranged in parallel, and a plurality of first lines, bit lines BL0-BL2, are arranged in parallel. Memory cells MC are arranged so as to be sandwiched between both wirings. The first and second wirings are preferably made of a material that is resistant to heat and has a low resistance value. For example, W, WSi, NiSi, CoSi, or the like can be used. As shown in FIG. 2B, four memory cell arrays 110 can be stacked to form a four-layer memory block. Note that the number of memory cell array layers is not limited to four.

As shown in FIG. 3, the memory cell MC includes a series connection circuit of a variable resistance element VR and a non-ohmic element NO.
As the variable resistance element VR, the resistance value can be changed by applying voltage, through current, heat, chemical energy, etc., and electrodes EL1 and EL2 functioning as a barrier metal and an adhesive layer are arranged above and below. . As the electrode material, Pt, Au, Ag, TiAlN, SrRuO, Ru, RuN, Ir, Co, Ti, TiN, TaN, LaNiO, Al, PtIrOx, PtRhOx, Rh / TaAlN, or the like is used. It is also possible to insert a metal film that makes the orientation uniform. It is also possible to insert a buffer layer, a barrier metal layer, an adhesive layer, etc. separately.

  The variable resistance element VR has a resistance value changed by a phase transition between a crystalline state and an amorphous state, such as chalcogenide (PCRAM), and forms a bridging (conducting bridge) between electrodes by depositing metal cations. Or by changing the resistance value by ionizing the deposited metal and breaking the bridge (CBRAM), or by changing the resistance value by applying voltage or current (ReRAM) (trap in the charge trap existing at the electrode interface) And the like in which the resistance change occurs depending on the presence or absence of the generated charge, and the one in which the resistance change occurs depending on the presence or absence of the conduction path due to oxygen deficiency or the like.

[Specific configuration of each circuit]
Hereinafter, a specific configuration of each circuit will be described. An example in which the memory cell array 110 includes memory cells MC of 2K bits (= 2048 bits) in the word line direction and 512 bits in the bit line direction will be described.

[Row control circuit]
FIG. 4 is an example of a circuit diagram of the main row decoder 120. The main row decoder 120 is a predecoder and receives a row address and selects one of 256 pairs of main word lines MWLx and MWLbx (x = <255: 0>). The main row decoder 120 includes the circuit shown in FIG. 4 for each of the 256 pairs of main word lines MWLx and MWLbx.

  As shown in FIG. 4, one main row decoder 120 includes an NAND gate G121 that receives an address signal (Address), a level shifter L / S that shifts the output of the NAND gate G121, and an output signal of the level shifter L / S. As an input signal, and an inverter IV122 using the output signal of the inverter IV121 as an input signal. The output terminals of the inverters IV121 and IV122 are connected to the main word lines MWLx and MWLbx, respectively. The main row decoder 120 selects a predetermined x based on an address signal (Address), supplies voltages VSSROW (“H”) and VWR (“L”) to the selected main word lines MWLx and MWLbx, Voltages VWR and VSSROW are supplied to unselected main word lines MWLx and MWLbx, respectively.

  FIG. 5 is an example of a circuit diagram of the row driver 130 (set operation row driver 130S, reset operation row driver 130R). Since both the set operation row driver 130S and the reset operation row driver 130R can adopt the same circuit configuration, the structure of the set operation row driver 130S will be described below.

  The set operation row driver 130S shown in FIG. 5 is connected to one of the word lines WLx <7: 0> via the wiring L, and 256 pairs of main word lines MWLx, MWLbx (x = <255: 0>).

  As shown in FIG. 5, the set operation row driver 130 </ b> S includes two transistors QP <b> 131 and QN <b> 131. The transistors QP131 and QN131 are connected between the write drive line WDRV <7: 0> and the word line WLx <7: 0>, and the main word lines MWLbx and MWLx are connected to the gates, respectively. The set operation row driver 130S includes a transistor QP132. The transistor QP132 is connected between the power supply line of the unselected word line voltage VUX and the word line WLx <7: 0>, and the main word line MWLx is connected to the gate thereof.

  When the set operation is performed, the set operation row driver 130S supplies the write drive line WDRV <7: 0> or the power supply line of the unselected word line voltage VUX according to the selected / unselected state of the main word line MWLx. Is connected to the word line WLx <7: 0>. As a result, either the selected word line voltage VSSROW or the unselected word line voltage VUX is supplied to the word lines WLx <7: 0>.

  On the other hand, the reset operation row driver 130R has the same configuration. When the reset operation is performed, the row driver 130R for reset operation uses the power line of the write drive line WDRV <7: 0> or the unselected word line voltage VUX depending on the selected / unselected state of the main word line MWLx. Is connected to the word line WLx <7: 0> through the wiring L.

  Note that the row driver 130 is formed in common on the same P-type substrate as the other peripheral circuits, but in order to apply a selection word line voltage VSSROW (for example, −0.8 V) that is a negative voltage, The triple well structure shown in FIG. Specifically, there is a P-type substrate having a ground voltage VSS as a well voltage, and an N-type well of the second conductivity type having a non-selected word line voltage VUX as a well voltage on the P-type substrate. A P-type well having a selected word line voltage VSSROW as a well voltage is sequentially formed on the well, and an NMOS transistor is formed on the P-type well.

  FIG. 7 is an example of a circuit diagram of the write drive line driver 140. The write drive line circuit 140 includes a NAND gate G141 that receives an address signal (Address), a level shifter L / S that shifts the output of the NAND gate G141, and an inverter IV141 that receives the output of the level shifter L / S. Is done. The inverter IV141 is provided between the unselected word line voltage VUX and the selected word line voltage VSSROW, and its output terminal is connected to the write drive line WDRV. The write drive line circuit 140 supplies the selected word line voltage VSSROW to the write drive line WDRV <127: 0> corresponding to the input address signal, and unselected words to the other write drive lines WDRV <127: 0>. Supply line voltage VUX. The voltage of the write drive line WDRV is supplied to the word line WLx via the row driver 130. The main row decoder 120, the row driver 130, and the write drive line driver 140 having the above configuration supply the selected word line voltage VSSROW only to the word line WLx selected by the address signal, and the other word lines WL are not selected. The word line voltage VUX is supplied.

[Column control circuit]
FIG. 8 is an example of a circuit diagram of the column decoder 160. The column decoder 160 receives a column address and selects one of 128 pairs of column selection lines CSLy and CSLby (y = <127: 0>). Note that the column decoder 160 has a circuit as shown in FIG. 8 for each of 128 pairs of column selection lines CSLy and CSLby. As shown in FIG. 8, one column decoder 160 receives a NAND gate G161 that receives an address signal (Address), a level shifter L / S that shifts the output of the NAND gate G161, and outputs the level shifter L / S. The inverter IV161 is an input and the inverter IV162 is an output of the inverter IV161. Here, the output terminals of the inverters IV161 and IV162 are connected to the column selection lines CSLy and CSLby, respectively. The column decoder 160 selects a predetermined y based on an address signal (Address), supplies voltages VWR (“H”) and VSS (“L”) to the selected column selection lines CSLy and CLLby, respectively. The voltages VSS and VWR are supplied to the selected column selection lines CSLy and CSLby, respectively.

  FIG. 9 is an example of a circuit diagram of the column driver 170 (set operation column driver 170S, reset operation column driver 170R). Since both the set operation column driver 170S and the reset operation column driver 170R can adopt the same configuration, the structure of the set operation column driver 170S will be described below. One set of 128 pairs of column selection lines CSLy and CSLby (y = <127: 0>) is input to the column driver 170S for set operation in FIG. As shown in FIG. 9, the set operation column driver 170S is provided between the local data lines LDQ <7: 0> and the bit lines BLy <7: 0>, and is controlled by the column selection lines CSLy and CSLby, respectively. Two transistors QP171 and QN171 and a transistor QN172 provided between the power supply line of the unselected bit line voltage VUB and the bit line BLy <7: 0> and controlled by the column selection line CSLby are provided.

  The set operation column driver 170S connects the power line of the local data line LDQ <7: 0> / unselected bit line voltage VUB and the bit line BLy according to the selection / non-selection state of the column selection line CSCy. To do. Here, the voltage of the local data line LDQ <7: 0> is a voltage VSS corresponding to the selected bit line voltage VWR or the unselected bit line voltage VUB supplied from the sense amplifier / write buffer 180. As a result, either the selected bit line voltage VWR or the unselected bit line voltage VUB is supplied to the bit lines BLy <7: 0>.

  Next, the length Ls (Ls0, Ls1,... Lsn) of the wiring L (L0, L1... Ln) between the set operation row driver 130S and the memory cell array 110 is set to the reset operation row driver 130R. The reason why a layout that is longer than the length Lr (Lr0, Lr1,... Lrn) of the wiring L between the memory cell array 110 and the memory cell array 110 is employed will be described. The length Ls ′ of the wiring L between the set operation column driver 170S and the memory cell array 110 is longer than the length Lr ′ of the wiring L between the reset operation column driver 170R and the memory cell array 110. The reason why the layout is adopted is the same, so the following explanation will be made mainly on the former reason.

  In the memory cell array 11, a plurality of memory cells MC are arranged in a matrix, and a memory cell MC (hereinafter referred to as a near bit) and a distant memory cell MC (hereinafter referred to as a far bit) from the set operation row driver 130S. Bit (referred to as Far Bit)) (see FIG. 10A). At this time, if the length Ls is small, there is a problem that in the near bit, the variation in the on-current Icell after the set operation is larger than that of the far bit (the width of the current distribution is large) (see FIG. 11). FIG. 11 shows the distribution of the on-current Icell in the comparative example, and the length Ls ′ and the length Lr ′ of the wiring L are substantially equal. Referring to FIG. 11, it can be seen that after the set operation, the distribution of the on-current Icell of the plurality of memory cells belonging to the near bit is wider than the distribution of the on-current Icell of the plurality of memory cells belonging to the far bit.

  The reason why the variation of the on-current Icell increases in the near bit will be described. As described above, the set operation is an operation of switching the resistance value of the variable resistance element of the memory cell MC from the high resistance state to the low resistance state. When the resistance value of the variable resistance element of the memory cell is switched to the low resistance state by voltage application, the current flowing through the memory cell MC increases rapidly. Such a sudden increase in current causes the memory cell that has completed the set operation to be reset (erroneous reset operation), places an unnecessary burden on the memory cell MC, and reduces the data retention characteristics of the memory cell MC. There are problems such as deterioration. On the other hand, the reset operation is an operation for switching the resistance value of the variable resistance element of the memory cell MC from the low resistance state to the high resistance state, and thus the above-described problem hardly occurs.

  Therefore, in the present embodiment, as shown in FIG. 10A, the length Ls of the wiring L between the set operation row driver 130S and the memory cell array 110 is set between the reset operation row driver 130R and the memory cell array 110. A layout that is longer than the length Lr of the wiring L is employed. Here, memory cells MC are arranged in a matrix in the memory cell array 110. In FIG. 10A, the memory cell MC connected to the 0th word line WL0 from the upper side is referred to as Bit0, and the memory cell MC connected to the nth word line WLn is referred to as Bitn. Note that n is an integer of 2 or more. A plurality of memory cells MC are connected to each of the word lines WL0 to WLn. Among them, a memory cell MC located far from the reset operation row decoder 130R and the set operation row decoder 130S is a far bit Far Bit0. ˜n. On the other hand, the memory cell MC located near the reset operation row decoder 130R and the set operation row decoder 130S is referred to as near bits Near Bits 0 to n.

The word lines WL0 to n are connected to the wirings L0 to Ln, respectively. The wirings L0 to Ln straddle the reset operation row driver 130R, and extend in the column direction (Col) so as to reach the set operation row driver 130S. Contacts ZiaR0 to ZiaRn are arranged in the reset operation row driver 130R. Further, contacts ZiaS0 to ZiaSn are arranged in the set operation row driver 130S.
Contacts ZiaR0 to ZiaRn are connected to word lines WL0 to WLn via wiring L, respectively. Contacts ZiaS0 to ZiaSn are connected to word lines WL0 to WLn via wiring L, respectively. In other words, one contact ZiaRi and one contact ZiaSi are connected to the word line WLi (i = 0 to n) via the wiring L. Here, the length Lsi of the wiring Li (i = 0 to n) is the distance from the end of the memory cell array 110 (the end on the set operation row driver 130S side) to the contact ZiaSi. The length Lri of the wiring Li is the distance from the end of the memory cell array 110 (the end on the reset operation row driver 130R side) to the contact ZiaRi. Further, in each word line WLi, a relationship of wiring length Lsi> Lri is established. That is, the wiring lengths Ls0> Lr0, Ls1> Lr1,... Lsn> Lrn. Furthermore, the lengths of the wirings Ls0 and Lrn have a relationship of Ls0> Lrn.

Here, an example of a cross-sectional view taken along the dotted line a in FIG. 10A is shown in FIG. 10B.
As shown in FIG. 10B, the word line WL has a stacked structure from the 0th layer to the tth layer. T is an integer of 2 or more. Similarly, the wiring Ln has a laminated structure from the 0th layer to the tth layer (the wiring Ln is composed of wirings Ln0 to Lnt). The wirings Ln0 to Lnt are connected to the word lines WLn0 to WLnt, respectively. Here, the word lines WLn0 to WLnt overlap when FIG. 10A is viewed from above. That is, the wirings Ln0 to Lnt illustrated in FIG. 10B overlap when the top view of FIG. 10A is viewed.

The contact ZiaRn extends in the direction Lam, which is the stacking direction, so as to penetrate each of the wirings Ln0 to Lnt. Here, the contact ZiaRn extends downward from the opening At formed in the uppermost wiring Lnt in the direction Lam. That is, the contact with the side face of the opening At of the wiring Lnt is electrically connected to the wiring Lnt. Similarly, the contact ZiaRn extending downward from the opening At in the direction Lam can be similarly connected to the wirings Ln (t−1),... Ln0 arranged below the wiring Lnt.
Here, the contact ZiaRn extending in the Lam direction from the opening A0 of the wiring Ln0 arranged in the lowermost layer is connected to the wiring M0. The wiring M0 is connected to the diffusion layers of the transistors QP131 and QN131 by lower layer contacts UC, respectively.

  The set operation row driver 130S also has the same contact ZiaSn as the reset row driver 130R. The contact ZiaSn is also connected to the wirings Ln0 to t in the same manner as the contact ZiaRn. Although not shown, ZiaSn is also connected to a wiring at the same level as the wiring M0, and is connected to the diffusion layers of the transistors QP131 and QN131 in the set operation row driver 130S, respectively.

  The voltage to be supplied to the memory cell MC is supplied from the transistors QP131 and QN131 to the memory cell MC via the contacts ZiaR and ZiaS and the wiring L. As a result, the length Ls of the wiring L is increased, so that the wiring resistance between the set operation row driver 130S and the memory cell array 110 is increased. Since the increase in the wiring resistance of the wiring L suppresses an increase in the on-current Icell flowing through the memory cell MC after the completion of the set operation, the data retention characteristics of the memory cell MC can be maintained. Note that the resistance of the contacts ZiaR and ZiaS is smaller than the resistance of the wiring L. Further, the length of the wiring M0 is smaller than the lengths Ls and Lr of the wiring. Therefore, the wiring resistance between the transistors QP131 and QN131 and the memory cell array 110 is largely governed by the lengths Ls and Lr of the wiring L.

  As shown in FIG. 10C, four contacts ZiaRi_1, ZiaRi_2, ZirSi_1, and ZiaSi_2 can be arranged in each of the wirings L0 to Ln (i is an integer of 0 to n, and so on). Here, ZiaRi_1 and ZiaRi_2 are arranged in the reset row driver 130R, and ZiaSi_1 and ZiaSi_2 are arranged in the setting row driver 130S.

  The lengths Ls and Lr of the wiring L are defined by contacts ZiaRi_1 and ZiaSi_1 close to the memory cell array 110 from the end of the memory cell array 110 (end on the set operation row driver 130S side). An example of a cross-sectional view taken along broken line b in FIG. 10C is shown in FIG. 10D. Further, the structures of the contacts ZiaRn_1, ZiaRn_2, ZirSn_1, and ZiaSn_2 are the same as the structure shown in FIG.

  Contact ZiaRn_1 is connected to the diffusion layer of transistor QP131. Contact ZiaRn_2 is connected to the diffusion layer of transistor QN131. In FIG. 10D, unlike FIG. 10B, the contact Zia is directly connected to the diffusion layer of the transistor without using the wiring M0. However, the present invention is not limited to this. Since the column driver 170 has the same layout as the row driver 130, the description thereof is omitted.

[Second Embodiment]
Next, the nonvolatile semiconductor device according to the second embodiment will be described in detail with reference to the drawings. FIG. 12 is a block diagram of a nonvolatile memory according to the second embodiment. The same components as those of the first embodiment are denoted by the same reference numerals in FIG. 12, and detailed description thereof will be omitted below. In this embodiment, a set operation row driver 130S and a reset operation row driver 130R are formed immediately below a semiconductor substrate (not shown) on which the memory cell array 110 is formed. The row driver 130S for set operation and the row driver 130R for reset operation are connected to the memory cell array 110 via a contact CL formed in the via CL and the via contact region 210 and extending perpendicularly to the semiconductor substrate. A plurality of contacts ZiaL0 to ZiaLn and ZiaR0 to ZiaRn are arranged in the via contact region 210. Here, the contacts ZiaL0 to ZiaLn are contacts connected to the wirings LL0 to LLn extending from the memory cell array 110 arranged on the left side in the column direction (Col). The contacts ZiaR0 to ZiaRn are contacts connected to wirings LR0 to LRn extending from the memory cell array arranged on the right side in the column direction (Col).

  The wirings LL0 to LLn are respectively connected to the word lines WL0 to WLn of the memory cell array 110 arranged on the left side in the column direction (Col). The wirings LR0 to LRn are respectively connected to word lines WL0 to WLn of the memory cell array arranged on the right side in the column direction (Col).

  Here, the contact ZiaLn will be described as an example. Specifically, as shown in FIG. 13, the bottom surface of the contact ZiaLn is connected to the wiring M0. The wiring M0 is connected to the transistors QN131 and QP131 of the set operation row driver 130S by the lower layer contact UC, and is connected to the transistors QN131 and QP131 of the reset operation row driver 130R, respectively. Here, the length Ls of the wiring L is the distance from the position where the contact ZiaLn and the wiring M0 are in contact to the lower layer contact UC of the set operation row driver 130S. The length Lr of the wiring L is the distance from the position where the contact ZiaLn and the wiring M0 are in contact to the lower layer contact UC of the reset operation row driver 130R. Here, the two contacts UC are arranged in the reset operation row driver 130R and the set operation row driver 130S. The distances Lr and Ls of the wiring L are defined as distances from the contact UC closer to the contact ZiaLn. The

  Note that the resistance of the contact wiring is smaller than the resistance of the word line WL and the wiring CL. As in the first embodiment, the length Ls of the wiring L between the set operation row driver 130S and the memory cell array 110 is equal to the length of the wiring L between the reset operation row driver 130R and the memory cell array 110. A layout that is longer than the length Lr is employed. 12 illustrates an example in which the set operation row driver 130S and the reset operation row driver 130S are formed immediately below the semiconductor substrate. Instead, the set operation column driver is directly below the semiconductor substrate. 170S and reset operation column driver 170R may be formed. Further, all of the set operation row driver 130S, the reset operation row driver 130R, the set operation column driver 170S, and the reset operation column driver 170R may be formed directly under the semiconductor substrate.

As mentioned above, although several embodiment of this invention was described, these embodiment is shown as an example and is not intending limiting the range of invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.
(Appendix 1)
Furthermore, the memory cell array has a block in which a plurality of layers are arranged,
5. The nonvolatile semiconductor memory device according to claim 4, wherein the contact wirings are connected in common to the wirings that overlap when viewed from above.
(Appendix 2)
8. The nonvolatile semiconductor memory device according to claim 7, wherein the two contact wirings connect the plurality of wirings to the first driver circuit for set operation or the first driver circuit for reset operation.

DESCRIPTION OF SYMBOLS 100 ... Memory cell array core part 110 ... Memory cell array 120 ... Main row decoder 130 ... Row driver 130S ... Set operation row driver 130R ... Reset operation row driver 140 ... write drive line (WDRV) driver, 150 ... row system peripheral circuit, 160 ... column decoder, 170 ... column driver, 180 ... sense amplifier / write buffer, 190 ... Column peripheral circuit.

Claims (7)

A memory cell array in which memory cells including variable resistance elements arranged at intersections between a plurality of first wirings arranged in parallel and a plurality of second wirings arranged so as to cross the first wiring are arranged When,
A first driver circuit for setting operation for supplying a voltage to the first wiring when executing a set operation for switching the memory cell from a high resistance state to a low resistance state; A reset operation first driver circuit for supplying a voltage to the first wiring when executing a reset operation for switching to
The length of the wiring between the first driver circuit for set operation and the memory cell array is longer than the length of the wiring between the first driver circuit for reset operation and the memory cell array. Nonvolatile semiconductor memory device. A second driver circuit for set operation for supplying a voltage to the second wiring when the set operation is performed on the memory cell;
A reset operation second driver circuit for supplying a voltage to the second wiring when the reset operation is performed on the memory cell;
The length of the wiring between the second driver circuit for set operation and the memory cell array is longer than the length of the wiring between the second driver circuit for reset operation and the memory cell array. The nonvolatile semiconductor memory device according to claim 1. The first driver circuit for set operation and the first driver circuit for reset operation are formed in a region between the plurality of memory cell arrays,
The first driver circuit for set operation is shared by the plurality of memory cell arrays,
The nonvolatile semiconductor memory device according to claim 1, wherein the first driver circuit for reset operation is provided so as to correspond to each of the plurality of memory cell arrays. A contact wiring extending in a direction perpendicular to the semiconductor substrate on which the memory cell array is formed and connected to the first wiring;
The first driver circuit for set operation and the first driver circuit for reset operation are formed in a region immediately below the memory cell array,
4. The nonvolatile device according to claim 1, wherein the first driver circuit for set operation and the first driver circuit for reset operation are connected to the first wiring via the contact wiring. 5. Semiconductor memory device.   The nonvolatile semiconductor memory device according to claim 4, wherein a resistance of the contact wiring is smaller than a resistance of the wiring. A via contact region in which a plurality of the contact wirings are disposed;
A lower layer wiring connected to each of the plurality of contact wirings;
A plurality of lower layer contacts connected to the lower layer wiring;
Further comprising
The first driver circuit for set operation and the first driver circuit for reset operation are commonly connected to the lower layer wiring,
Of the plurality of lower layer contacts, a first lower layer contact connects the first driver circuit for set operation and the lower layer wiring,
The second lower layer contact of the plurality of lower layer contacts connects the first driver circuit for reset operation and the lower layer wiring,
The length of the wiring between the first driver circuit for set operation and the memory cell array is the distance of the lower layer wiring from the contact wiring to the first lower layer contact,
5. The length of the wiring between the first driver circuit for reset operation and the memory cell array is a distance of the lower layer wiring from the contact wiring to the second lower layer contact. Nonvolatile semiconductor memory device. Further, a block in which the memory cell array is arranged in a plurality of layers,
Contact wiring,
The contact wiring commonly connects a plurality of overlapping wirings when viewed from above.
One contact wiring connects the plurality of wirings to the first driver circuit for set operation or the first driver circuit for reset operation,
The length of the wiring between the first driver circuit for set operation and the memory cell array is arranged in the first driver circuit for set operation from the end on the first driver circuit side for set operation of the memory cell array. The distance of the wiring to the contact wiring;
The length of the wiring between the first driver circuit for reset operation and the memory cell array is arranged in the first driver circuit for reset operation from the end of the memory cell array on the first driver circuit side for set operation The nonvolatile semiconductor memory device according to claim 1, wherein the distance is a distance of the wiring to the contact wiring.

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