JP5492245B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device, in particular, a high-density integrated memory circuit formed using a phase change material, or a logic-embedded memory in which a memory circuit and a logic circuit are provided on the same semiconductor substrate, or an analog circuit. The present invention relates to a technique effective when applied to a semiconductor integrated circuit device.

  A memory (phase change memory) using a resistance element made of a phase change material reversibly changes phase between an amorphous state and a crystalline state using an electric pulse, and the amorphous state (reset) ) And the resistance value of the crystalline state (set) is recorded as information. Incidentally, the high resistance value in the amorphous state and the low resistance value in the crystalline state of the phase change material do not necessarily need to be in a completely amorphous state and a completely crystalline state, respectively. It is possible to take an arbitrary value intermediate between a certain high resistance state and a low resistance state which is a complete crystal state.

The operation mechanism of the phase change memory will be described in detail below with reference to FIG. FIG. 14 is an example of current-voltage characteristics of the phase change material that realizes the recording operation of the phase change memory. When the voltage applied to both ends of the phase change material in the amorphous state is gradually increased from zero, the phase change material in the amorphous state changes to the crystalline state. The voltage at which the phase change from the amorphous state to the crystalline state occurs is the set voltage
(Vset). The resistance value of the phase change material changed from the amorphous state to the crystalline state changes from the high resistance state to the low resistance state.

  Further, when the voltage applied to both ends of the phase change material in the crystalline state is gradually increased from zero, the phase change material in the crystalline state changes to an amorphous state. The voltage at which the phase change from the crystalline state to the amorphous state occurs is defined as a reset voltage (Vreset). The resistance value of the phase change material changed from the crystalline state to the amorphous state changes from the low resistance state to the high resistance state.

The phase change memory records information with the low resistance value in the crystalline state as the “0” state and the high resistance value in the amorphous state as the “1” state. Information is read out by applying a read voltage (Vread) across the phase change material. As shown in FIG. 14, the current generated in the crystalline state having a low resistance value is larger than the current generated in the amorphous state having a high resistance value due to the printing pressure of the read voltage Vread.

  Information recorded in the phase change memory is read by sensing a voltage drop across a bit line electrically connected to one end of the phase change material. FIG. 15 schematically shows the voltage drop of the bit line electrically connected to the phase change material. The bit line is set to the precharge level Vp in the initial state at the time of reading. In FIG. 15, the precharge level Vp of the bit line is set to 0.3V. As shown in FIG. 15, a bit line electrically connected to a phase change material in an amorphous state having a high resistance value is a bit line electrically connected to a phase change material in a crystalline state having a low resistance value. The voltage drops at a lower speed than the line. This is because the phase change material having a high resistance value has a slower rate of charge accumulated in the bit line flowing into the phase change material than the phase change material having a low resistance value.

  By sensing the voltage drop speed of the bit line using the read voltage, the “0” state and the “1” state of the phase change memory are read. Incidentally, in the present invention, the low resistance value in the crystalline state is set to the “0” state and the high resistance value in the amorphous state is set to the “1” state. However, the high resistance value in the amorphous state is set to the “0” state. The low resistance value in the crystal state may be set to the “1” state.

Japanese Patent Application No. 2003-145305 Specification Japanese Patent Application No. 2003-081724

  The phase change memory has a problem of so-called erroneous setting, in which an amorphous state is erroneously changed into a crystalline state. An erroneous set is likely to occur when excessive electrical energy is input during low-voltage operation, or during high-speed operation. Factors that cause erroneous setting are, for example, physical property value variations, electrical property variations, or dimensional variations. In addition, for example, variation in characteristics such as phase change material, selection transistor, or LSI wiring, variation in operating voltage, variation in power supply voltage, and the like are also factors that cause erroneous setting.

  Hereinafter, a phenomenon in which an erroneous set occurs during a read operation will be described in detail. As shown in FIG. 14, in the conventional method, the read voltage is set to be equal to or lower than the set voltage. By setting the read voltage below the set voltage, it was possible to prevent the phase change material in the amorphous state from being erroneously set to the crystalline state by the read operation.

  However, when a low voltage operation is required for the phase change memory, there arises a problem that the margin between the set voltage and the read voltage is reduced. For example, when used in a low power consumption product such as a mobile phone, a mobile personal digital assistant, or an IC card, the phase change memory is required to have a low power operation. Also, when used as a microcomputer embedded memory that operates at a low voltage, the phase change memory is required to operate at a low voltage.

  The reason why the margin between the set voltage and the read voltage is small in the phase change memory operating at a low voltage is that it is difficult to reduce the read voltage with respect to the small set voltage. The reason why it is difficult to reduce the read voltage is that the read current decreases with the read voltage, and the operation speed of the phase change memory decreases.

  The relationship between the read voltage and read current of the phase change memory will be described with reference to FIG. As shown in FIG. 16, the read current in the crystalline state obtained by the read voltage Vread1 is Iread1. In contrast, the read current in the crystalline state obtained by a read voltage smaller than the read voltage Vread1 is Iread2, which is smaller than Iread1. When the read current is small, the discharge speed of the bit line is reduced, and the speed of sensing the amorphous state and the crystalline state of the phase change material by the sense amplifier is reduced. As a result, the operation speed of the phase change memory is reduced.

When the margin between the set voltage and the read voltage is small, the record retention reliability of the phase change memory deteriorates. For example, when the variation in characteristics of the phase change memory is large, the set voltage varies and becomes small, which may be smaller than the read voltage. As a result, the read operation causes a phenomenon that the phase change material is erroneously set from the amorphous state to the crystalline state. The erroneous setting can occur both when the reset voltage as shown in FIG. 14 is larger than the set voltage and when the reset voltage as shown in FIG. 17 is smaller than the set voltage.
When the phase change memory operates at a low voltage, the margin between the read voltage and the set voltage becomes small, so that an erroneous set occurs due to a slight variation in the characteristics of the phase change material or the select transistor.

In addition, when the phase change memory operates at a low voltage, the margin between the set voltage and the reset voltage becomes small, and therefore, an erroneous setting occurs during the reset operation due to a slight variation in the characteristics of the phase change material or the selection transistor.
In addition, when the resistance value in the reset state changes due to cumulative reading, the energy input changes, so that an erroneous set occurs.
Further, when the capacity of the phase change memory is increased, an erroneous set of dropped bits occurs due to a slight yield failure such as a wiring process.
Further, when the read voltage is increased in order to read out the phase change memory at a high speed, a margin between the read voltage and the set voltage is reduced, so that erroneous setting occurs.
Further, the phase change memory has a problem of so-called erroneous reset, in which the crystal state erroneously changes to the amorphous state. When a low voltage operation is required for the phase change memory, the margin between the reset voltage and the read voltage is also reduced. Therefore, when the characteristic variation of the phase change memory is large, the reset voltage varies and becomes small, which may be smaller than the read voltage. As a result, a phenomenon occurs in which the phase change material is erroneously reset from the crystalline state to the amorphous state by the read operation.

An erroneous reset can occur both when the reset voltage as shown in FIG. 14 is larger than the set voltage and when the reset voltage as shown in FIG. 17 is smaller than the set voltage.
When the phase change memory operates at a low voltage, a margin between the read voltage and the reset voltage becomes small, and thus erroneous reset occurs due to a slight variation in characteristics of the phase change material or the selection transistor.

In addition, when the phase change memory operates at a low voltage, the margin between the set voltage and the reset voltage becomes small, and therefore, an erroneous reset occurs during the set operation due to a slight variation in the characteristics of the phase change material or the selection transistor.
In addition, when the read voltage is increased in order to read out the phase change memory at a high speed, a margin between the read voltage and the reset voltage is reduced, so that an erroneous reset occurs at the time of reading.
In addition, an erroneous setting of the phase change memory also occurs when the phase change material is operated or left at a high ambient temperature or a high junction temperature because the amorphous state of the phase change material is a quasi-stationary state. Missets caused by standing at high temperature for a long time are observed as a so-called “falling bit phenomenon” seen in large-capacity memories such as DRAMs. As a result, phase change memory used for highly integrated memory circuits and logic embedded memories There is a problem in that the long-term record retention reliability deteriorates. An example of a product that requires high-temperature operation of the phase change memory is an automobile engine control embedded microcomputer. The operating and 20 year standing temperature requirements are, for example, 125 degrees Celsius or higher, or 145 degrees Celsius or higher at the junction temperature.

  An object of the present invention is, in particular, in a high-density integrated memory circuit using a phase change material, a logic embedded memory in which a memory circuit and a logic circuit are provided on the same semiconductor substrate, and a semiconductor integrated circuit device having an analog circuit Another object of the present invention is to provide a technique capable of improving the reliability of a memory cell element using a phase change material that requires long-term recording retention reliability.

  Another object of the present invention is to reduce the operation of a semiconductor integrated circuit device. Another object of the present invention is to increase the temperature of a semiconductor integrated circuit device. Another object of the present invention is to extend the temperature of a semiconductor integrated circuit device for a long time. Another object of the present invention is to achieve high integration of a semiconductor integrated circuit device. Another object of the present invention is to increase the capacity of a semiconductor integrated circuit device. Another object of the present invention is to increase the operation speed of a semiconductor integrated circuit device.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows. In the read operation, a voltage necessary for setting is applied to the bit line to read data to reduce the resistance of all the cells, and the high resistance cell is rewritten. As a result, it is possible to prevent erroneous setting and erroneous reset that occur during high-temperature operation using the destructive readout method.

Further, a high voltage is applied to the bit line for reading, and a rewriting operation is performed on the high resistance cell and the low resistance cell, respectively. As a result, according to the present invention, it is possible to prevent the erroneous setting and the erroneous reset caused by the characteristic variation of the phase change material, the selection transistor, the LSI wiring, or the like, or the variation of the power supply voltage, by using the destructive reading method.
In addition, the present invention retains 1-bit information by using an or-cell, that is, two or more memory cells, for missing bit relief. As a result of the present invention, it is possible to prevent erroneous setting caused by leaving at high temperature for a long time or falling bits, and improving the long-term record retention reliability of the phase change memory.

  The effects obtained by the representative ones of the inventions disclosed by the present application will be briefly described as follows. In particular, for example, in a high-density integrated memory circuit using a phase change material, a logic embedded memory in which the memory circuit and the logic circuit are provided on the same semiconductor substrate, and a semiconductor integrated circuit device having an analog circuit, long-term record retention reliability Thus, the reliability of the memory cell element using the phase change material required for the property can be improved.

It is a block diagram of the array and peripheral circuit of Example 1 of this invention. It is a block diagram of a memory cell array. It is a block diagram of a memory cell. 3 is a circuit configuration example of a bit line selector. 3 is a circuit configuration example of a write driver and a sense amplifier. It is a read-out operation | movement waveform diagram of Example 1 of this invention. It is a write-in operation | movement waveform diagram of Example 1 of this invention. 4 is a circuit configuration of a sense amplifier block according to Embodiment 2 of the present invention. 3 is a circuit configuration example of a write driver. It is a read-out operation | movement waveform diagram of Example 2 of this invention. It is a write-in operation | movement waveform diagram of Example 2 of this invention. It is an array and peripheral circuit block diagram of Example 3 of this invention. It is the table | surface which showed the relationship between the memory cell data in this invention Example 3, and output data. It is a current-voltage diagram of a phase change memory. It is an operation waveform diagram of the precharge level and voltage drop of the bit line. It is a current-voltage diagram of a phase change memory. It is a current-voltage diagram of a phase change memory. It is sectional drawing of the memory cell of the phase change memory of Example 1 of this invention. Ge ₂ Sb ₂ Te ₅ phase change material and lower electrode material lattice constant. Relationship between reset current and lower electrode material. The relationship between the reset voltage and the film thickness of the phase change material when the phase change material undergoes a phase change from the crystalline state to the amorphous state. It is a figure which shows the control method of a reset enable signal and a set enable signal. It is a figure which shows the example of an operation | movement waveform figure of FIG. FIG. 3 is an example block diagram of a memory having a rewrite command. FIG. 25 is an operation waveform diagram example of the memory of FIG. 24. FIG. 25 is another operation waveform diagram example of the memory of FIG. 24. It is an example of a block diagram of a memory having a self-rewrite determination operation function. It is a block diagram of the memory array main part of the memory of FIG. FIG. 6 is a configuration example and an operation waveform diagram of a write enable signal generation circuit. It is a structural example of the memory cell array of FIG. It is an example of a sense amplifier block configuration for a replica bit line. It is a precharge circuit structural example. 2 is a configuration example of a sense bit circuit for a replica bit line. 2 is a configuration example of a write enable signal generation method using an OR cell array. It is an example of an operation waveform diagram of a memory having a self-rewrite determination function. It is an example of a block diagram of a memory having a self-rewrite determination function and a status output pin. It is an example of a weight pin output circuit block diagram. FIG. 37 is an operation waveform diagram example of the memory of FIG. 36. FIG. 37 is another operation waveform diagram example of the memory of FIG. 36, and shows waveform diagrams (with replica cell) determination cycle non-holding Set / Reset when rewriting is performed and not. It is the figure which showed the resistance distribution and the direction of data transfer in the case of performing multi-value storage in the phase change element. It is the figure which showed the example of data mapping at the time of comprising the OR cell array using two multi-value storage elements. FIG. 4 is a diagram showing a memory cell array, a sense amplifier block, and an OR logic unit when a multi-value storage element and an OR cell array are combined. 43 is a configuration example of a sense amplifier block circuit in FIG. 44 is a circuit configuration example of a write driver in FIG. 43. It is the figure which showed the example of input-output circuit structure in FIG. FIG. 43 is a block diagram of an OR logic unit in FIG. 42. It is the figure which showed the read data structure block in FIG. FIG. 47 is a diagram showing a write data configuration block in FIG. 46. FIG. 47 is a diagram showing a configuration example of an error detection circuit in FIG. 46.

<Example 1>
A circuit diagram of the phase change memory cell of the present invention is shown in FIG. The memory cell portion of FIG. 3 includes a lower electrode dwc, a phase change material PCR, an upper electrode upc, a source line SL, a bit line BL, and a selection transistor MT including, for example, a MISFET, and a word line WL. The
An example of a cross-sectional view of a phase change memory cell is shown in FIG. In this memory cell, the phase change material PCR is composed of an upper electrode upc, a lower electrode plug dwc, and an interlayer film IL. The phase change material PCR is electrically connected to the upper electrode upc and the lower electrode plug dwc. The upper electrode upc is electrically connected to the bit line BL or the source line SL. The lower electrode plug dwc is electrically connected to one end of the source / drain of the selection transistor MT made of, for example, MISFET. The other end of the source / drain of the selection transistor is electrically connected to a wiring of the source line SL or the bit line BL that is not connected to the upper electrode. That is, the circuit diagram of the memory cell is as shown in FIG. The memory cell structure is processed using a known method. For example, Patent Document 1 discloses a device related to this type of memory cell structure.

For example, Ge-Sb-Te phase change material, Zn-Te phase change material, or Zn-Te phase change material is added with an additional element in phase change material PCR used for phase change memory operating at a low voltage. Zn-X-Te phase change materials. Examples of the additive element X include Sb. As a thing relevant to a Zn-X-Te system phase change material, it is indicated by patent documents 2, for example.
An example of the material used for the lower electrode plug dwc is tungsten. Tungsten is a material suitable for low voltage and high speed operation, which is one of the objects of the present invention, because it has good interface characteristics with the phase change material. FIG. 19 compares the crystal lattice constants of Ge ₂ Sb ₂ Te ₅ and tungsten, titanium nitride, and silicon. As shown in FIG. 19, it can be seen that the crystal lattice constant of Ge ₂ Sb ₂ Te ₅ is substantially the same as the crystal lattice constant of tungsten. As a result, the current required for the phase change of the phase change memory using tungsten for the lower electrode is reduced. FIG. 20 shows the reset current required for the Ge ₂ Sb ₂ Te ₅ phase change material to change from the crystalline state to the amorphous state when tungsten and titanium nitride are used for the lower electrode. As shown in FIG. 20, the reset current when tungsten is used for the lower electrode is smaller than the reset current when titanium nitride is used. As a result, by using tungsten as the lower electrode material, the current required for the phase change is reduced, so that the low voltage operation of the phase change memory is also possible. However, there is a problem that the margin which is the difference between the read voltage, the set voltage, and the reset voltage is reduced due to the low voltage operation of the phase change memory.

  An example where the phase change memory operates at a low voltage is when the phase change material is a thin film. The reason why a phase change memory is realized by using a thin phase change material will be described below. For example, when the electric power p per unit volume required for the phase change material to change into a crystalline state is obtained using an ohmic approximation, it can be expressed as the following Expression 1.

ここで、Ｉsetは非晶質状態の相変化材料が結晶状態に相変化する時に要するセット電流、Ｒは相変化材料の抵抗値、ｒは相変化材料の抵抗率、Ａは下部電極面積、Ｔは相変化材料の膜厚である。式１を解いてセット電圧Vsetを求めると以下の式２のようになる。

Here, Iset is a set current required when a phase change material in an amorphous state changes to a crystalline state, R is a resistance value of the phase change material, r is a resistivity of the phase change material, A is a lower electrode area, T Is the film thickness of the phase change material. When the set voltage Vset is obtained by solving the equation 1, the following equation 2 is obtained.

式２より、セット電圧Ｖsetが相変化材料の膜厚に比例することがわかる。その結果、相変化材料の膜厚が薄くなることによって、相変化メモリの低電圧動作が実現できることがわかる。式１および式２は、相変化材料が非晶質状態から結晶状態に相変化するセット動作を表している。式１および式２は、相変化材料が結晶状態から非晶質状態に相変化するリセット動作を表す場合も、近似的に用いることが可能である。ただし、式１および式２は、オーミック近似のみを用いて求められたものであり、ジュール熱の発生および拡散を考慮した場合、相変化材料が相変化する時に要する電力は、式１および式２で求められる値よりも大きくなる。
また、本発明では、ソース線とビット線の電位差の絶対値の最大値が１．８Ｖ以下であることを想定している。この場合選択用スイッチでの電圧低下が０．６Ｖ以上見込まれるので、相変化材料に印加される電圧は１．２Ｖ以下になると想定される。

From Equation 2, it can be seen that the set voltage Vset is proportional to the film thickness of the phase change material. As a result, it can be seen that the low voltage operation of the phase change memory can be realized by reducing the film thickness of the phase change material. Equations 1 and 2 represent a set operation in which the phase change material undergoes a phase change from an amorphous state to a crystalline state. Equations 1 and 2 can also be used approximately when the phase change material represents a reset operation in which the phase change from the crystalline state to the amorphous state. However, Formula 1 and Formula 2 are obtained using only ohmic approximation, and when generation and diffusion of Joule heat are taken into consideration, the power required when the phase change material undergoes phase change is expressed by Formula 1 and Formula 2. It becomes larger than the value obtained by.
In the present invention, it is assumed that the maximum absolute value of the potential difference between the source line and the bit line is 1.8 V or less. In this case, since the voltage drop at the selection switch is expected to be 0.6V or more, the voltage applied to the phase change material is assumed to be 1.2V or less.

FIG. 21 shows experimental data of the reset voltage and the film thickness of the phase change material when the phase change material undergoes a phase change from the crystalline state to the amorphous state. When a 1.2 V operation is performed using a phase change material having a Ge ₂ Sb ₂ Te ₅ composition, the film thickness needs to be 20 nm or less, for example. _When performing a 1.2V operation using Zn ₃₅ Sb 15 _{Te 50} phase change material, the film thickness is assumed that it is necessary, for example, 60nm or less. The reason why the film thickness depends on the composition of the phase change material is that the resistivity of the phase change material is different. The reason why the reset voltage does not become 0 V in the lower limit value of zero film thickness is that the electric power required when the phase change material undergoes a phase change includes the contribution of Joule heat generation and diffusion.
Examples of the phase change memory used in high temperature operation and high temperature long-time standing include a high melting point phase change material, a Zn-Te phase change material, or Zn-Te phase change material with an additive element added There are -X-Te phase change materials. As a thing relevant to a Zn-X-Te system phase change material, it is indicated by patent documents 2, for example.

  The present invention includes a GeSbTe phase change material, a Zn—Te phase change material, or a Zn—X—Te phase change material obtained by adding an additive element to a Zn—Te phase change material as a phase change material. However, it can be applied to other phase change materials. In this case, it is possible to improve the data retention reliability of the phase change element and to prevent a decrease in operating speed at a low voltage. Further, although an operating voltage of about 1.2V is assumed, the present invention can be applied to an operation at 1.8V. Even in this case, the operation margin can be improved and the operation speed can be improved.

  Furthermore, the present invention is desirably used for a semiconductor using a processing technique having a processing dimension of 0.13 μm or less. As the miniaturization progresses and the operating voltage decreases, the operating margin decreases, and by applying the present invention, the operating margin can be improved. The present invention can also be applied to a single memory and a logically mixed memory. By applying to these, data reliability and memory cell defects can be remedied, and yield can be improved. In particular, a logic embedded memory can improve data reliability in a high-temperature operation, so that a semiconductor device capable of operating in a wide temperature range can be realized.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The circuit elements constituting each functional block in the embodiment are not particularly limited, but are formed on a semiconductor substrate such as single crystal silicon by a known integrated circuit technology such as a CMOS (complementary MOS transistor). In the drawing, the PMOS transistor is distinguished from the NMOS transistor by attaching an arrow symbol to the body. Although the connection of the substrate potential of the MOS transistor is not particularly specified in the drawing, the connection method is not particularly limited as long as the MOS transistor can operate normally. Unless otherwise noted, the signal low level is set to “0” and the high level is set to “1”.

  This embodiment solves the problem that when the array operating voltage is lowered, the read voltage range is narrowed and the operating margin is lowered. In a conventional read operation, the applied voltage is kept low so that a phase change element in a high resistance state or a low resistance state does not cause a phase change due to a current during reading. As a result, since the read current becomes small, there is a concern that the read signal amount is reduced, the operation speed is lowered, and the operation margin is lowered. In contrast, in the present invention, in the read operation, the applied voltage is increased so that the signal amount is sufficiently generated in the sense amplifier, and the rewrite operation is performed on the cell that may cause a phase change by the read operation. Go and improve data reliability. Examples of the present invention are shown below.

  In this configuration, the bit line precharge level of the read operation does not change in the phase change element in the set state, and the phase change element in the reset state always causes a phase change in the set state and is not less than Vset and not more than Vreset It is the composition which is. FIG. 1 is a diagram showing a memory cell array MCA, a sense amplifier block SAB, and a row decoder / word driver RDEC that realize this operation.

  First, the memory cell array MCA will be described. A configuration example of the memory cell array MCA is shown in FIG. Memory cells MC are provided at the intersections of the word lines WL0, WL1, WL2, WL3,... And the bit lines BL0, BL1, BL2, BL3,. Further, source lines SL01, SL23,... Are provided. The source line is connected to the ground voltage VSS, for example. Each memory cell MC includes a phase change resistor PCR and a memory cell transistor MT. Two types of memory cell configurations are shown in FIG. In (a), one end of the phase change resistor PCR is connected to the bit line BL, and the other end is connected to one of the source and drain of the memory cell transistor MT. The other of the source and drain of the memory cell transistor is connected to the source line, and the gate is connected to the word line. This configuration is advantageous because the driving power of the memory cell transistor MT can be increased when the bit line BL is driven to a higher potential than the source line SL, for example, 1.2 V, during writing. In (b), the connection relationship between the phase change resistor PCR and the memory cell transistor MT in (a) is reversed. In this configuration, when the bit line is driven at a lower potential than the source line SL, for example, when the potential of the source line SL is 1.2 V and the bit line BL is driven to 0 V, the driving power of the memory cell transistor MT can be increased. Therefore, it is superior. Further, even when the bit line is driven by the read / write operation, the current for charging / discharging the diffusion layer of the memory cell transistor MT does not flow in the non-selected cell, so that data destruction can be prevented. Further, although an NMOS transistor is shown here as a memory cell transistor, a PMOS transistor or a bipolar transistor can also be used. However, a MOS transistor is desirable from the viewpoint of high integration, and an NMOS transistor having a smaller channel resistance in the on state than the PMOS transistor is preferable. Hereinafter, the operation and the like will be described in terms of voltage when an NMOS transistor is used as the memory cell transistor. The bit line is also called a data line. Although not shown here for simplicity, the memory cell array MCA is also provided with a dummy cell for generating a reference signal at the time of reading, if necessary.

  The sense amplifier block SAB includes a bit line selector BLSEL, a sense amplifier SA, and a write driver WD. FIG. 4 shows a configuration example of the bit line selector BLSEL. In the bit line selector BLSEL, selection switches for connecting the bit lines BL0, BL1,... Of the memory array to the sense amplifier are arranged. These switches are controlled by column selection signals C0t / b, C1t / b,. Further, a precharge transistor is provided for precharging the memory array side bit line and the sense amplifier side bit line BLSA to a desired level for a desired period. A sense amplifier block is arranged adjacent to the bit line selector. The sense amplifier senses the signal of the sense amplifier bit line and outputs it to the outside or temporarily holds data from the outside. FIG. 5B shows a configuration example of the sense amplifier. In this configuration, the level of the sense amplifier bit line BLSA and the reference level VREF are compared, and a cross-couple amplifier circuit that amplifies to the power supply voltage VWE is formed. FIG. 5A shows a configuration example of the write driver WD. The write driver WD drives the sense amplifier bit line BLSA in accordance with external write data or data read to the sense amplifier SA. In this embodiment, the write driver WD is composed only of a driver for bringing the phase change element of the memory cell into a high resistance state. In the figure, one sense amplifier bit line BLSA, sense amplifier SA, and write driver WD are connected to four bit lines BL0, BL1, BL2, and BL3, but the number of bit lines is not limited. By increasing the number, the number of operating sense amplifiers can be reduced, and an increase in unnecessary power consumption can be suppressed. On the other hand, if the number is small, the number of bits to be output increases, which is suitable for inputting and outputting large amounts of data at high speed.

Next, the read operation in this array configuration will be described.
FIG. 6 is a timing chart of the read operation. In accordance with the read command, the column selection line C0t / b corresponding to the input address is activated. Thereafter, the bit line connected to the sense amplifier SA, in the figure, the bit line BL0 is set to the bit line precharge level VR together with the sense amplifier bit line BLSA. In this embodiment, the potential difference between the precharge level VR and the source line SL of the memory cell MC is set so that a current necessary for the phase change element to change phase from the high resistance state to the low resistance state flows. . For example, in the illustrated example, the source line SL is set to 0V, and the bit line precharge level VR is set to about 0.6V. Thereafter, the precharge signal PRE is deselected and the word line WL is selected. Accordingly, the bit line BL and the sense amplifier bit line BLSA are discharged via the transistor MT of the memory cell and the phase change element PCR. At this time, when the phase change element PCR of the memory cell is in a low resistance state, it is rapidly discharged. On the other hand, when the resistance is in a high resistance state, it is slowly discharged. In the sense amplifier, a minute signal appearing on the bit line is amplified to the power supply voltage. By this read operation, the phase change element in the high resistance state undergoes a phase change from the high resistance state to the low resistance state due to heat generated by the read current, and all the cells read out to the sense amplifier are reduced in resistance. The sense amplifier amplifies the signal read to the bit line and outputs it to the I / O for output to the outside. Before and after that, the write driver is activated in the sense amplifier from which the phase change element of the memory cell has read the data in the high resistance state. In the activated write driver, a high voltage is applied to the bit line by the write enable signal WRE for the time required for the reset operation, and the current required for the reset operation is applied to the phase change element via the bit line and the memory cell transistor. Shed. Thereafter, by interrupting the current, the phase change element is rapidly cooled to change into a high resistance state. Thereafter, the word line WL and the column selection line C0t / b transition to the non-selection level, and the read cycle ends.

  Next, the write operation will be described. FIG. 7 is a timing chart of the write operation. A write address is sent according to the write command. Similar to the read operation, the column select line C0t / b corresponding to the address is activated, and at the same time, the bit line precharge operation is performed. Thereafter, the word line WL corresponding to the address is selected, and the bit line is discharged through the memory cell transistor and the phase change element. At this time, the phase change element generates heat due to the read current and causes a phase change from the high resistance state to the low resistance state. As a result, the phase change elements of all the memory cells connected to the sense amplifier change to a low resistance state. Write data is transferred to the sense amplifier during this operation. Here, after rewriting the read data, the write driver corresponding to only the sense amplifier holding the data corresponding to the high resistance state of the phase change element of the memory cell in the sense amplifier row is activated. After that, in the activated write driver, a high voltage is applied to the bit line by a write enable signal for a time required for the reset operation, and a current required for the reset operation is supplied to the phase change element via the bit line and the memory cell transistor. Shed. Thereafter, by interrupting the current, the phase change element is rapidly cooled to change into a high resistance state. Thereafter, the word line WL and the column selection line C0t / b transition to the non-selection level, and the read cycle ends.

  In this configuration, when the memory cell data is read by selecting the word line, all the memory cell data is set to the low resistance state and the high resistance state is rewritten. The advantages of this are as follows. (1) Since the bit line precharge level can be set high at the time of reading and the amount of signal read to the sense amplifier can be increased, a high-speed and stable reading operation can be realized. (2) The write driver, which conventionally requires a set / reset driver, can be configured with only the reset driver, which simplifies the circuit configuration and reduces the layout area and chip area. (3) By rewriting each time the high resistance state is read, it is possible to reduce data reliability degradation due to data destruction during the read operation. (4) The record retention characteristics of the phase change element are deteriorated. For example, high-speed operation at 125 degrees Celsius or higher and standing for a long time are possible.

<Example 2>
Next, Example 2 will be described. Note that the circuit and cross-sectional structure of the memory cell of Example 2 are the same as those in FIGS. 3 and 18, and a description thereof is omitted.
This configuration uses a voltage higher than the voltage Vset or Vreset at which the phase change element does not cause a phase change at the bit line precharge level at the time of reading. In this operation, the bit line precharge level is set high in order to increase the read signal amount. However, the read operation may destroy the phase state of the phase change element. Perform a write operation.

  FIG. 8 shows the configuration of the sense amplifier block SAB of this embodiment. The memory cell array MCA and the word driver RDEC are the same as those in the previous embodiment. The sense amplifier block SAB includes a bit line selector BLSEL, a write driver WD for setting / resetting a phase change element, and a sense amplifier SA for amplifying and holding data of the sense amplifier bit line BLSA. FIG. 9 shows a circuit configuration of the write driver WD. The write driver WD supplies a current required for setting and resetting to the phase change element via the sense amplifier bit line BLSA and the memory cell transistor according to the set enable signal WSE, the reset enable signal WRE, and the data of the sense amplifier SA. The configuration of the write driver is different from that of the above-described embodiment, and a write driver for increasing the resistance and decreasing the resistance of the phase change element is arranged.

Next, the read operation in this array configuration will be described.
FIG. 10 is a timing chart of the read operation. As in the previous embodiment, the column selection line C0t / b corresponding to the input address is activated according to the read command. Thereafter, the bit line connected to the sense amplifier SA, in the figure, the bit line BL0 is set to the bit line precharge level VR together with the sense amplifier bit line BLSA. In the present embodiment, the potential difference between the precharge level VR and the source line SL of the memory cell MC is such a voltage that a current necessary for the phase change element to change phase from the high resistance state to the low resistance state flows. In addition, a voltage at which the low resistance state becomes the high resistance state may be used. Conversely, a voltage in the vicinity of a voltage at which the high resistance state surely reduces the resistance may be used. In this case, the phase change element does not necessarily cause a phase change from the high resistance state to the low resistance state. For example, in the illustrated example, the source line SL is set to 0V, and the bit line precharge level VR is set to about 0.8V. Thereafter, the precharge signal PRE is deselected and the word line WL is selected. Accordingly, the bit line BL and the sense amplifier bit line BLSA are discharged via the transistor MT of the memory cell and the phase change element PCR. At this time, when the phase change element PCR of the memory cell is in a low resistance state, it is rapidly discharged. On the other hand, when the resistance is in a high resistance state, it is slowly discharged. In the sense amplifier, a minute signal appearing on the bit line is amplified to the power supply voltage. By this reading operation, the resistance value of the phase change element of the memory cell connected to the sense amplifier does not necessarily hold the resistance state before reading. That is, the stored data is destroyed by the read operation. During this period, the sense amplifier amplifies the signal read to the bit line and outputs it to the outside. Before and after that, the write driver is activated in the sense amplifier from which the phase change element of the memory cell has read the data in the high resistance state. In the activated write driver, a high voltage is applied to the bit line by a write enable signal for a time required for the reset operation, and a current necessary for the reset operation is passed to the phase change element via the bit line and the memory cell transistor. . Thereafter, by interrupting the current, the phase change element is rapidly cooled to change into a high resistance state. Thereafter, the column selection line C0t / b and the word line WL shift to the non-selection level, and the read cycle ends.

  Next, the write operation will be described. FIG. 11 is a timing chart of the write operation. A write address is sent according to the write command. Similar to the read operation, the column select line C0t / b corresponding to the address is activated, and at the same time, the bit line precharge operation is performed. Thereafter, the word line WL corresponding to the address is selected, and the bit line is discharged through the memory cell transistor and the phase change element. At this time, the phase change element generates heat due to the read current, causes a phase change from the high resistance state to the low resistance state or from the low resistance state to the high resistance state, and destroys the state before reading. Write data is transferred to the sense amplifier during this operation. Here, after rewriting the read data, the reset driver in the write driver is selected in the sense amplifier that holds the data corresponding to the high resistance state of the phase change element of the memory cell in the sense amplifier row. On the other hand, in the sense amplifier that holds data corresponding to the low resistance state of the phase change element of the memory cell in the sense amplifier row, the set driver in the write driver is selected. After that, in the activated write driver, a high voltage is applied to the bit line by the reset and set write enable signals for the time required for the reset operation, and the current required for the reset and set operation is applied to the bit line and the memory cell transistor. Through the phase change element. Thereafter, by interrupting the current, the phase change element is rapidly cooled and changes into a high resistance state or a low resistance state. Thereafter, the column selection line C0t / b word line WL changes to the non-selection level, and the write cycle ends.

  This configuration has the following advantages by setting all the memory cell data to the low resistance state when the word line is selected and the memory cell data is read. (1) Since the bit line precharge level can be set high at the time of reading and the amount of signal read to the sense amplifier can be increased, a high-speed and stable reading operation can be realized. (2) Precharge level setting range is flexible, facilitating power supply design and adapting to power supply fluctuations due to noise. (3) By rewriting the read data, it is possible to reduce data reliability degradation due to the read operation. (4) The record retention characteristics of the phase change element are deteriorated. For example, high-speed operation at 125 degrees Celsius or higher and standing for a long time are possible.

  In the first and second embodiments, the read voltage is equal to or higher than Vset at which the phase state of the phase change element changes or higher than Vreset. However, when the operation is performed at a voltage lower than this, as in the first and second embodiments. The rewrite operation may be performed. In this case, since it is not necessary to rewrite each time a read operation is performed, the rewrite operation is performed at a predetermined number of times, for example, about 1/10 of the possible number of times of reading or every elapse of a predetermined operation time. You can go. In this case, as in the first and second embodiments, there is an advantage that data destruction due to thermal disturbance and disturbance during operation can be prevented, and the number of times of rewriting can be reduced compared with the number of times of reading. There is an advantage that can be improved.

<Example 3>
Next, an array configuration for improving data reliability will be described. As described above, the phase-change element in the reset state may undergo a phase change to the set state due to thermal disturbance due to a read operation or an operation at a high normal temperature. On the other hand, the possibility that the phase change element in the set state causes the phase change to the reset state is considered to be sufficiently small that the phase change element in the reset state causes the phase change to the set state. Therefore, the reliability of stored data in the phase change element is improved by storing 1-bit data in a plurality of memory cells with redundancy.

  FIG. 12 shows an embodiment of the present invention. Bit lines BL00, BL01, BL02, BL03... And BL10, BL11, BL12, BL13... Are connected to memory cell arrays MCA0 and MCA1 having the same configuration as the memory cell array MCA of FIG. Yes. Sense amplifier block SAB0 to which bit lines BL00, BL01, BL02, BL03... Are connected. The sense amplifier block SAB1 to which the bit lines BL10, BL11, BL12.BL13 are connected may have the circuit configuration of the sense amplifier block SAB of any of the foregoing embodiments. The data input / output line I / O0 is output from the sense amplifier block SAB0 and the data input / output line I / O1 is output from the sense amplifier block SAB1 as complementary signals (t / b). The output signal line is input to the logical sum block ORB. The OR block ORB outputs external output data DOt / b using these input signals. The OR block ORB transmits external write data DIt / b to the sense amplifier blocks SAB0 and SAB1.

  Next, the reading operation in this embodiment will be described. The memory cell arrays MCA0 and MCA1 are activated simultaneously with the input of one address. At this time, the signal read from the memory cell MC at the specified address is sensed and amplified by the sense amplifier block SAB0, and the signal read from the memory cell MC of the memory cell array MCA0 is read from the memory cell MC ~ of the memory cell array MCA1. The read signal is sensed and amplified by the sense amplifier block SAB1. At this time, the sense amplifier block outputs data according to the relationship between the phase state of the memory cell MC as shown in FIG. 13 and the output voltages of the complementary signals I / O * t and I / O * b to be output. . That is, when the phase state is the high resistance state (Reset), the input / output signals I / O0t and I / O1t are in the H 'state, and when the phase state is the low resistance state (Set), the input / output signals I / O0t, I / O O1t is in the L ′ state. The logical sum block ORB that receives these input / output signals performs a logical sum of the input / output signals I / O0t and I / O1t, and outputs external output data DOt / b. FIG. 13 shows the relationship between the input / output signals I / O0t and I / O1t and the external output data DOt. As shown in this figure, when one or both of the input / output signals I / O0t and I / O1t are in the H ′ state, the external output data is in the H ′ state. When this is replaced with the state of the phase change element of the memory cell, the external output data DOt is H ′ if either one or both of the memory cells of the read memory cell array MCA0 or MCA1 are in the high resistance state (Reset). become.

  Next, the write operation in this configuration will be described. At the time of writing, write data is input to the OR block ORB via the external input data signal DIt / b. In the OR block ORB, the external input data signal DIt / b is transferred to the room input signals I / O0t and I / O0b and the input / output signals I / O1t and I / O1b through the switch. These input / output signals are sent to the sense amplifier blocks SAB0 and SAB1, respectively. In the sense amplifier blocks SAB0 and SAB1, similarly to the sense amplifier block SAB in the above-described embodiment, an operation of writing data to the memory cells MC in the memory cell arrays MCA0 and MCA1 is performed.

Next, advantages of this configuration will be described. In the phase change memory, it is possible to prevent data destruction due to phase change due to high-temperature standby, continuous read operation, etc., and deterioration of data reliability due to defective bits or missing bits. The record retention characteristics of the phase change element deteriorate, for example, high speed operation at 125 degrees Celsius or higher and long-time standing are possible.
Here, one bit is stored in two memory cells MC, but it may be configured to store two or more memory cells MC and output a logical sum of the read results. In this case, if at least one of the three is in a high resistance state, H ′ can be output and data reliability can be further improved.

  In the operations shown in FIGS. 10 and 11 described so far, the reliability is greatly improved. However, since the read voltage is set to a voltage equal to or higher than Vset at which the phase state of the phase change element changes or higher than Vreset, the read operation is performed. A rewrite operation is always required during operation, which increases power consumption. In the embodiment described below, a case will be described in which the read voltage is set to Vset or Vreset below which the phase state of the phase change element changes in order to reduce power consumption in the same circuit configuration. In this case, even if the read operation is performed, it is only necessary to perform the rewrite operation in a specific operation cycle, so that low power consumption can be realized. Even in this case, data destruction due to thermal disturbance and disturbance during operation can be prevented, and the number of rewrites can be reduced as compared with the number of reads, and the rewrite resistance of the phase change element can be improved. The circuit configuration can be any of the first, second, and third embodiments. That is, the rewrite operation only in a specific cycle is realized by activating the reset enable signal WRE and the set enable signal WSE in each embodiment only in a specific cycle. For example, by using a logic circuit as shown in FIG. 22, a signal reset write signal WRE and a set write signal WSE for performing a rewrite operation are generated, thereby realizing a rewrite operation in a specific operation. In this figure, a rewrite enable signal RW is a signal indicating that a rewrite operation is performed on a column selected memory cell on a selected word line. The mat selection signal MSB decodes the input address and indicates a specific address range. Regardless of the read operation or write operation, the mat select signal MSB is one of the mats on the memory array. Select signal MSB is selected. The reset time defining pulse TReset is a pulse that defines the write time of the reset write operation. Similarly, the set time defining pulse TSet is a pulse that defines the write time of the set write operation. An example of the operation of this circuit configuration is shown in FIG. As shown in FIG. 23, when the rewrite enable signal is activated after the mat select signal MSB transitions to the activated state, for example, the low potential state here, these signals and the reset time defining pulse TReset The reset enable signal WRE is activated. Similarly, the set enable signal WSE is activated by the set time defining pulse TSet. On the contrary, when the rewrite enable signal RW is inactive, neither the reset enable signal WRE nor the set enable signal WSE is activated even when the mat select signal MSB is activated. That is, the rewrite operation can be controlled by the rewrite enable signal RW.

  The advantages of this configuration will be described. By performing the rewrite operation only when a specific rewrite enable signal is activated without performing the rewrite operation for each read operation, the number of rewrites can be reduced, and the reliability of the phase change film is improved. Further, when data destruction does not occur in the read operation, there is an advantage that the cycle time can be shortened because the rewrite operation is not accompanied with the read operation. Furthermore, since the power consumption of the rewrite operation can be reduced, low power consumption can be realized. Furthermore, there is an advantage that the reliability of stored data can be improved by performing the rewrite operation in a specific period as compared with the case of performing only the nondestructive read operation.

Next, a method for generating the rewrite enable signal RW and an embodiment in which the rewrite operation is performed in the specific cycle described above will be described.
FIG. 24 shows a simple block diagram of a memory chip having an input pin or command for executing a rewrite operation REF in addition to normal read and write commands. The memory array MA includes a plurality of memory cell arrays MCA, and a sense amplifier block SAB is arranged adjacent to each memory cell array MCA. One end of the memory array MA includes a predecoder RPDEC that drives an address line for controlling the row decoder RDEC and a column decoder CDEC that outputs a column selection signal. A data control unit I / O-CTL is provided for external output of data and for transferring data input from the outside to the array. The memory chip has externally input addresses A0, A1,... And an address buffer INPUT Buffer for temporarily storing commands, an external input voltage VCC and ground level, an input / output buffer for data input / output Internally generates internal voltage word line selection level VWH, word line non-selection level VWL, sense amplifier power supply VDL, reset write voltage VWR, set write voltage VWS, peripheral circuit power supply voltage VCL, ground level VSS, source line potential VS from GND A power generation circuit VG is arranged. This configuration is characterized in that the rewrite command REF for performing the rewrite operation or the rewrite pin REF is included in the input command. The sense amplifier block and the memory cell array MCA in FIG. 24 are the same as those in FIGS.

Next, the operation of this embodiment will be described.
FIG. 25 is an operation example of a configuration in which FIG. 1 is applied to the sense amplifier block SAB in FIG. When a read command READ is input from the outside, the column selection signal is activated according to the address input at the same time. In addition, the precharge signal PRE of the sense amplifier block corresponding to the address is activated. As a result, the bit line is precharged to the read level VR. At the same time, the bit line isolation signal connecting the sense amplifier SA and the read bit line BLSA is in a high potential state. Thereafter, the bit line precharge signal PRE is deactivated, and the word line WL transits from the non-selected state VWL to the selected state VWH according to the input address. At this time, when the resistance state of the phase change element of the memory cell MC is in the low resistance state, the potential rapidly changes to the source line SL potential VS as shown by a broken line in the figure. On the other hand, in the high resistance state, the vicinity of the bit line read level VR is maintained. After a predetermined period, when a sufficient signal is generated in the sense amplifier, the bit line isolation signal BLI transitions to the low voltage VSS to separate the sense amplifier and the read bit line BLSA. Thereafter, the sense amplifier SA amplifies the minute signal read from the memory cell MC to the sense amplifier power supply VDL by the activation of the sense amplifier activation signal SE / SEB. Thereafter, the data is transferred to the I / O control unit and the DQ buffer. Before and after this, the activated word line WL transitions to the non-selection level VWL. Thereafter, the sense amplifier inactivates the sense amplifier activation signal to shift to a standby state. Almost simultaneously with this, the column selection signal transitions to the non-selected state, and the read cycle is completed.

  Next, the operation when the rewrite command REF is input will be described. The operation until the address input simultaneously with the command or the address generated by the address counter ADD-C in the memory chip CHIP is activated and read to the sense amplifier is the same as the above-described read operation. Here, the rewrite enable signal RW is activated to a high potential state according to the rewrite command REF. As shown in the operation waveform diagram of FIG. 23, when the rewrite enable signal RW is activated, the reset enable signal WRE is activated by the mat select signal MSB corresponding to the selected address and the reset time defining pulse TReset. When the reset enable signal is activated, if the data held in the sense amplifier corresponds to the high potential state, that is, if I / Ot is set to the high resistance state and I / Ob is set to the low potential state, In the driver WD, a reset voltage is applied to the memory cell MC via the sense amplifier bit line BLSA and the bit line BL0, and a current necessary for writing flows. The reset enable signal is activated for a time determined by the reset time defining pulse TReset, and then transitions to a low potential state, thus completing the reset operation. The operation after the write operation is completed is the same as the read operation described above. In this operation, the rewrite operation is only a reset operation with a short write time. This is because the thermal disturbance in the phase change memory and the disturbance in the read operation are focused on the fact that an erroneous set in which the reset state element becomes the set state element is more likely to occur than an erroneous reset in which the set state becomes the reset state. Therefore, in this operation, the cycle tRC ′ for performing rewriting is longer than the read cycle tRC for performing the rewriting operation, but only the reset operation with a short writing time is performed, so the penalty of the cycle time is reduced. I can do it.

  The advantages of this embodiment will be described. By providing a rewrite operation in addition to the normal read / write operation, the rewrite operation can be performed before the data destruction due to the read operation, and the data reliability can be improved. Further, since only the reset operation is performed in the rewrite operation, there is an advantage that the operation penalty due to the rewrite operation can be reduced.

  Next, the operation when the sense amplifier block of FIG. 8 is applied to the above-described sense amplifier block SAB of FIG. 24 will be described. FIG. 25 shows an operation example of this configuration. This configuration is characterized in that both a reset operation and a set operation are performed as a rewrite operation of memory cell data at a specific address in accordance with a command input from the outside. The read cycle when a read command is input is the same as in FIG. Next, an operation when the resume command REF is input will be described. The operation until the address input simultaneously with the command or the address generated by the address counter ADD-C in the memory chip CHIP is activated and read out to the sense amplifier is the same as in FIG. Here, the rewrite enable signal RW is activated to a high potential state according to the rewrite command REF.

  As shown in the operation waveform diagram of FIG. 23, when the rewrite enable signal RW is activated, the reset enable signal WRE is activated by the mat select signal MSB corresponding to the selected address and the reset time defining pulse TReset. When the reset enable signal is activated, if the data held in the sense amplifier corresponds to the high resistance state, that is, if I / Ot is set to the high potential state and I / Ob is set to the low potential state, the write In the driver WD, a reset voltage is applied to the memory cell MC via the sense amplifier bit line BLSA and the bit line BL0, and a current necessary for writing flows. The reset enable signal is activated for a time determined by the reset time defining pulse TReset, and then transitions to a low potential state, thus completing the reset operation. Similarly, as shown in the operation waveform diagram of FIG. 23, when the rewrite enable signal RW is activated, the set enable signal WSE is activated by the mat select signal MSB corresponding to the selected address and the set time defining pulse TSet. Is done. When the set enable signal WSE is activated, when the data held in the sense amplifier corresponds to the low resistance state, that is, when I / Ot is set to the low potential state and I / Ob is set to the high potential state, In the write driver WD, a set voltage is applied to the memory cell MC via the sense amplifier bit line BLSA and the bit line BL0, and a current necessary for writing flows. The set enable signal WSE is activated only for a time determined by the set time defining pulse TSet, and then transitions to a low potential state to complete the set operation. The operation after the write operation is completed is the same as the read operation described above. In this operation, compared to the read cycle tRC, the rewrite cycle tRC ′ requires not only reset but also set, and therefore requires a relatively long time, for example, about 100 ns to 1 us.

  The advantages of this embodiment will be described. By providing a rewrite operation in addition to the normal read / write operation, the data reliability can be improved by performing the rewrite operation before destroying the data by the read operation. Further, by performing not only the reset operation but also the set operation in the rewrite operation, there is an advantage that the reliability of both data can be improved as compared with the above-described embodiment.

  Next, a configuration in which a rewrite operation is performed by the memory cell data error prediction / detection function on the memory chip CHIP will be described using an embodiment. FIG. 27 is a block diagram of a memory chip in which an error detection function is added on the memory chip. A feature is that an address counter is omitted as compared with FIG. Other configurations are the same as those in FIG. FIG. 28 shows a block diagram of the memory cell array MCA and its peripheral circuits. Similar to FIG. 1, the memory cells are arranged adjacent to the memory cell array MCA via the row decoder RDEC for driving the word lines WL0, WL1, WL2,... And the bit lines BL0, BL1, BL2,. A sense amplifier block SAB for reading data stored in MC is arranged. Further, in this configuration, a replica bit line BL_REP arranged adjacent to the bit lines BL0, BL1, BL2,... Is arranged in the memory cell array MCA. Further, a replica bit line sense amplifier block circuit SAB_REP is arranged corresponding to the replica bit line. The replica bit line sense amplifier block SAB_REP outputs RW0 as an original signal of the rewrite enable signal RW. The rewrite enable signal RW is output from the rewrite enable source signal RW0 with the pulse width adjusted by a pulse width conversion circuit RW_GEN as shown in FIG. FIG. 30 shows a configuration example of the memory cell array MCA in FIG. Replica memory cells MC_REP are arranged for all word lines with respect to replica bit lines. The replica memory cell MC_REP has the same configuration as that of a normal memory cell MC as shown in FIG. 3, for example. However, the phase change elements in all the memory cells on the bit line are characterized by being set to a high resistance state. FIG. 31 shows a block diagram example of the replica sense amplifier block SAB_REP described above. The bit line precharge circuit BLPC is a circuit for precharging a bit line to a desired level VR in a read operation. For example, a MOS transistor precharged to VR as shown in FIG. 32 and a source line potential VS during standby are set. It consists of a MOS transistor. The write driver WD has the same configuration as that shown in FIG. The sense amplifier circuit SA_REP is a circuit for amplifying a minute signal read to the bit line BLSA to the sense amplifier power supply VDL amplitude and outputting write data to the rewrite enable source signal RW0 and the write driver WD. FIG. 33 shows a circuit configuration example of the sense amplifier SA_REP. In this sense amplifier, a replica reference VREF_REP is used as a reference level. VREF_REP is set to a higher level than VREF used in the above-described sense amplifier block SAB. This makes it easier to read the memory cell in a low resistance state even when a memory cell in a relatively high resistance state is called compared to a normal sense amplifier block, and it is possible to detect read data destruction in a high resistance state. In the sense amplifier, when the low resistance state is read, the reference-side bit line is output as the rewrite enable source signal RW0 via the inverter. The advantages of this configuration will be described. Distributing memory cells for replicas in the same memory cell as a normal memory cell can reduce the influence of variation, and the memory cell having the same characteristics as a normal memory cell has the advantage that data retention characteristics can be observed. . By placing the sense amplifier reference level for replicas on the high resistance side, normal memory cells can be detected by replica memory cells before data destruction from the high resistance state to the low resistance state due to read operations, etc. There is an advantage that reliability is improved.

  Next, a rewrite enable signal generation method using the OR cell array described in the third embodiment will be described with reference to FIG. FIG. 34 shows the memory cell array MCA, sense amplifier block SAB, and OR logic block ORB2 of FIG. The OR logic block ORB2 can reduce errors caused by the transition from the high resistance state to the low resistance state by performing OR logic on the read data as in the third embodiment. In this configuration, if the data is different between the two read data I / O0 and I / O1, the output circuit of the rewrite enable source signal RW0 for writing the high resistance state to the two memory cells is provided. It is a feature that is added. Other configurations are the same as those of the third embodiment. The advantages of this configuration will be described. In this configuration, since a memory cell that stores actual data is used without using a replica memory cell, a data error can be detected without being affected by variations in characteristics between cells. Furthermore, by storing the same data in the two memory cells, not only can the correct data be output by taking the OR logic, but the correct data can be rewritten, and high reliability of the stored data can be realized. Normally, when two memory cells are used and an error is detected by detecting that the data is different, it is difficult to detect which memory cell stores the correct information. However, when a phase change element is used, the error is detected because the resistance state of the phase change element is basically an error in which the reset state (high resistance state) transitions to the set state (low resistance state). In this case, it can be seen that the memory cell in the set state has caused a data error.

  The operation when the circuit configuration of FIG. 28 is used will be described with reference to FIG. The operation when a read command is input and no error is detected is the same as in FIG. On the other hand, the operation in the second cycle in FIG. 35 shows a case where an error is detected together with the read operation. First, it is the same as a normal read operation from when a command is input until data is read out to the bit line and held in the sense amplifier. Here, when the phase change element of the replica memory cell transitions from the high-resistance state to the low-resistance state, the output node I / O_REPt / b of the replica sense amplifier that has read the replica bit line detects the low-resistance state. When the low resistance state is detected, the rewrite enable source signal RW0 is activated and the rewrite enable signal RW is activated. When the rewrite activation signal RW is activated, the reset enable signal WRE and the replica bit line sense amplifier output I / O_REPb are sensed, and the reset write voltage VWR is applied to the bit line from the write driver WD. The reset write voltage is applied only while the reset enable signal WRE is activated, and falls immediately. As a result, the replica memory cell is rewritten to a high resistance state. Similar to this operation, the reset write operation is performed on the memory cell MC storing data and on the memory cell in which the read resistance state is high, similarly to the reset write operation on the replica memory cell. Done. As a result, the high resistance memory phase change element of the memory cell storing the data is also rewritten and the data retention characteristics are improved. The advantages of this operation will be described. In this operation, since only the reset write operation with a short write time is performed, the restart operation can be performed within the cycle time of the normal read operation, and there is an advantage that the access penalty due to the rewrite operation can be hidden. .

  Next, as in the embodiment of FIG. 27 described above, the memory chip CHIP has an error detection function, and further prevents the external memory controller from issuing an access request to the memory chip CHIP during the rewrite operation. A configuration having a busy pin WAIT for this purpose will be described. FIG. 36 is characterized in that a busy pin WAIT is provided as an output pin with respect to the configuration of FIG. 27 described above. Other configurations are the same as those in FIG. Unlike the above-described embodiment, this configuration is suitable when the cycle time is longer in a read cycle involving a rewrite operation than in a normal read cycle. FIG. 37 is a block diagram showing an output method of the busy pin WAIT. The busy pin WAIT functions to notify the external memory controller that the memory cannot be used by receiving the rewrite enable signal and changing from the high potential state to the low potential state. Accordingly, even when the time required for the rewrite operation is longer than that of the read operation, there is an advantage that data collision and data loss can be prevented by transmitting the state to the memory controller. An example of an operation waveform diagram of this configuration will be described with reference to FIG. This operation is an operation waveform diagram example in the case of using the memory cell array MCA having the replica memory cells as shown in FIG. The read operation without rewriting as in the first cycle in the figure is the same as in the above-described embodiment. Next, in the second cycle, a rewrite operation is performed along with the read operation. This operation is the same as that of the above-described embodiment until the signal read from the memory cell is held in the sense amplifier. When the read data of the memory cell on the replica bit line is read from the high resistance state to the low resistance state as shown in FIG. 35 which is an example of the operation waveform diagram of FIG. 28 described above, I / O_REPt of the output node of the sense amplifier A signal in a low resistance state is output. As a result, the rewrite enable signal RW is activated. When the rewrite enable signal RW is activated, the reset enable signal WRE is activated, and a reset write operation is performed on the cell that has read the reset state. At the same time, the set enable signal WSE is also activated, and a set write operation is performed on the cell from which the set state has been read. The reset enable signal WRE is inactivated after a reset write time.

  On the other hand, in the set write operation, a write time of 100 ns to 1 μs or more is required, and the set enable signal maintains the activated state during that time. After a predetermined period, the set enable signal WSE is deactivated and enters a standby state. During this writing period, the memory chip cannot be accessed from the outside, so the busy pin WAIT is shifted to a low potential state in order to transmit it to the controller. This avoids issuing an operation command from the external controller. The advantages of this configuration will be described. In the rewrite operation, not only the reset write but also the set write can be performed to improve the reliability of both data. Further, by providing a busy pin, command issuance from the controller can be suppressed during a period when the memory chip cannot be accessed, and data collision and loss can be prevented.

  Next, a modification of the above-described embodiment will be described with reference to FIG. This configuration is characterized in that only the reset operation is performed as the write operation. In the above write operation, only the reset enable signal WRE is activated, and the reset write operation is performed on the memory cell from which the reset state has been read. On the other hand, no write operation is performed on the memory cell from which the set state has been read. During the reset write operation, the busy pin WAIT transitions to a low potential state so that no command is issued from the external controller. As a result, the external controller does not access the memory chip. The advantages of this configuration will be described. In addition to preventing data collision / disappearance by providing a busy pin, this configuration requires a relatively short write time of about 50 ns and performs a rewrite operation with only a reset operation, thus shortening the time during which the memory chip is busy. There is an advantage that the access penalty can be reduced.

  Next, an embodiment in which a multi-level memory and an OR cell are combined will be described. FIG. 40 shows a distribution of resistance values when multi-value storage is performed using phase change elements. From the high resistance state to the resistance state R3 '11', the resistance state R2 10 ', the resistance state R1 00', and the resistance state R0 01 'are assigned. Although other allocation methods may be used, in particular, such allocation has the advantage that the possibility of an error in both bits can be reduced even when transitioning to an adjacent state. When the phase change element is used, the resistance state of the phase change element is mainly an error in which the reset state (high resistance state) transitions to the set state (low resistance state). Therefore, an array that realizes high data reliability is realized by using an OR cell array that stores the same data in two cells. FIG. 41 shows the relationship between the resistance state of the phase change element of the memory cell having the same address in the two memory cell arrays MCA0 and MCA1 and the stored data MLBt / MSBt. As described above, the data of the memory cell in the high resistance state out of the two memory cells is output as a true value. For example, when the state of the memory cell of the memory cell array MCA0 is R3, the output data MLBt / MSBt is “1” / 1 ”regardless of the state of the memory cell of the memory cell array MCA1.

  An array configuration for realizing this will be described. FIG. 42 shows a memory cell array peripheral circuit block diagram. Memory cell arrays MCA1 and MCA0, sense amplifier blocks SAB_M and SAB_M, and an OR logic unit ORB_M are arranged. FIG. 43 is a block diagram example of the sense amplifier block SAB_M. As in the previous embodiment, a bit line selection circuit BLSEL, a write driver WD_M, and a sense amplifier circuit SA are arranged, and an IO gate IOG that converts read data and outputs it is arranged in the input / output unit. In the sense amplifier circuit, three sense amplifier circuits using three reference levels VREF0, VREF1, and VREF2 are arranged in order to read out multiple values simultaneously. Accordingly, there is an advantage that it is possible to determine which level of the multi-values is in one reading operation and to increase the speed. FIG. 44 shows a circuit configuration of the write driver WD_M arranged in the sense amplifier block SAB_M. The circuit configuration is such that the write voltage is determined by I / O0, I / O1, I / O2, and I / O3 corresponding to the resistance state of the memory cell, and the write period is determined by the write enable signals W0, W1, W2, and W3. . In the IO gate, these three sense amplifiers SA mainly strongly refer to SAO0t / b, SAO1t / b, SA2t / b, corresponding to the resistance state of the memory cell, output nodes I / O0, I / O1, I Output “1” to either / O2 or I / O3. FIG. 46 shows a block diagram of the OR logic unit. The read block RE_M is a circuit block that detects an error in data read from the two memory cell arrays MCA0 and MCA1 and outputs plausible data. When the write block WE_M writes back externally input data or correct data by error detection, the signal I / O00, I / O01 corresponding to the resistance state is sent from the input data to the memory cell array MCA0. , I / O02, I / O03 and memory cell array MCA1 output signals I / O10, I / O11, I / O12, and I / O13 corresponding to the resistance state. The error detection circuit DET detects the presence or absence of an error by comparing data read from the memory cell array MCA, and outputs a rewrite enable source signal RW0 if there is an error. FIG. 47 shows a specific circuit configuration example of the read block RE_M. As shown in the figure, the most significant bit MLBt is a NAND logic of NOR logic of I / O00 and I / O10 and NOR logic of I / O01 and I / O11. Similarly, the least significant bit MSBt is the NAND logic of the NAND logic output of I / O03 and I / O13 and the NOR logic output of I / O00 and I / O10. Thereby, conversion satisfying the table of FIG. 41 can be realized. FIG. 48 shows a circuit configuration example of the write block WE_M. This is the reverse conversion of the above-described read block RE_M. FIG. 49 shows a circuit configuration example of the error detection circuit unit DET. Output of I / O00 and I / O10 and I / O10 and I / O11, and I / O02 and I / O12 Ex-OR logic corresponding to memory cell arrays MCA0 and MCA1 is OR logic It is. As a result, when any output signal does not match, the rewrite enable source signal RW0 is activated. In the multi-value storage system that reduces the margin, which describes the advantages of this configuration, the reliability of stored data is improved and the retention time can be increased by combining with an OR cell array that stores the same data in a plurality of memory cells. . In addition, since an error detection circuit is added, an error in the memory cell data can be corrected by performing rewriting when an error is detected, and the reliability of the data can be improved.

  The voltage condition will be described. The word line selection level may be 1.8V or 1.5V, which is equal to the external voltage VCC, or may be 2.5V or 3.0V that is boosted internally. By using a high voltage, the current driving capability of the memory cell transistor becomes strong. Therefore, since the rewrite current can be secured even if the size of the memory cell transistor is reduced, there is an advantage that a small memory cell area can be realized. The sense amplifier power supply VDL and the peripheral circuit power supply VCL may be 1.8V, 1.5V, or 1.2V. Lowering power consumption can be realized by lowering the voltage. The reset write voltage VWR is preferably set to a potential equal to one external voltage VCC in order to reduce power consumption.

  The present invention may be used for a memory-embedded microcomputer and a memory-dedicated chip used in a mobile phone, PDA, system home appliance, or ubiquitous information terminal. Further, the present invention may be used for a memory-mixed microcomputer mounted in an automobile, such as for engine control that requires high-temperature operation.

  upc ... upper electrode, dwc ... lower electrode plug, RDEC ... row decoder / word driver, WL, WL0, WL1, WL2, WL3 ... word line, BL, BL0, BL1, BL2, BL3, BL00, BL01, BL02, BL03, BL10, BL11, BL12, BL13 ... Bit line, BLSA ... Bit line in sense amplifier, PRE ... Precharge signal, WRE ... Reset write enable signal, WSE ... Set write enable signal, SE ... NMOS sense amplifier start signal, SEB ... PMOS Sense amplifier start signal, I / Ot, I / Ob, I / O0t, I / O0b, I / O1t, I / O1b ... Input / output data line, WD ... Write driver, SA ... Sense amplifier, SAB, SAB0, SAB1 ... Sense amplifier block, BLSEL ... Bit line selector, MCA, MCA0, MCA1 ... Memory cell array, VREF ... Reference level, C0t to C3t, C0b to C3b ... Column selection signal, SL, SL01, SL23 ... Source line, MT ... Memory cell Transistor, PCR ... Phase change element, BLI ... Bit line isolation signal, VWR ... Reset write voltage, VWS ... Write voltage, ORB ... OR block, DIt / b ... external input data line, DOt / b ... external output data line, Vp, VR ... bit line precharge level, TReset ... reset period specification pulse, TSet ... set period specification Pulse, MSB ... mat select signal, RW ... rewrite enable signal, RPDEC ... row predecoder, INPUT Buffer ... input buffer, VG ... internal power output circuit, DQ Buffer ... input / output data buffer, I / O-CTL ... input / output Data control, MA ... Memory array, REF ... Rewrite external command, tRW ... Rewrite enable signal pulse width, BL_REP ... Replica bit line, SA_REP ... Replica bit line sense amplifier block, RW_GEN ... Rewrite enable signal generation block, RW0 ... Rewrite enable source signal, MC_REP ... Replica memory cell, BLPC ... Bit line precharge circuit block, VREF_REP ... Replica sense Reference level, I / O_REPt ... Sense amplifier output for replica, WAIT ... Busy output pin, WAIT_B ... Busy output pin output buffer, R0, R1, R2, R3 ... Phase change element resistance state, MLBt / b ... Most significant bit, MSBt / b: Least significant bit, ORB_M: OR logical block.

Claims (9)

Multiple word lines,
Multiple bit lines,
A plurality of memory cells including phase change material disposed at desired intersections of the plurality of word lines and the plurality of bit lines;
A first memory cell array and a second memory cell array including the plurality of memory cells;
A first sense amplifier block for reading data from the first memory cell array;
A first data output line for outputting data from the first sense amplifier block to the outside;
A second sense amplifier block for reading data from the second memory cell array;
In the semiconductor device having a second data output line for outputting data from the second sense amplifier block to the outside,
A semiconductor device that outputs first information when at least one of a first data output line and a second data output line is first information.   The semiconductor device according to claim 1, further comprising a first OR circuit that takes a logical sum of the first data output line and the second data output line.   The semiconductor device according to claim 1, wherein the first information stores a phase state of the phase change material as an amorphous state.   The semiconductor device according to claim 1, wherein the memory cell includes a phase change material and a selection switch.   5. The semiconductor device according to claim 4, wherein the maximum absolute value of the potential difference between the source line and the bit line is 1.8 V or less.   5. The semiconductor device according to claim 4, wherein the phase change material is a material containing Sb and has a film thickness of 60 nm or less.   The semiconductor device according to claim 6, wherein the phase change material is a material containing Ge, Sb, and Te and has a film thickness of 20 nm or less.   5. The semiconductor device according to claim 4, wherein tungsten is used as an electrode material for electrically connecting the phase change material and the selection switch.   5. The semiconductor device according to claim 4, wherein the semiconductor device operates at an ambient temperature of 125 degrees Celsius or higher.

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