JP2009020998A - Multilevel phase change memory device to reduce read error, and readout method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a phase change memory device and a reading method thereof. <P>SOLUTION: This phase change memory device includes: a plurality of main cells programmed to have any one out of a plurality of resistance states corresponding to each of multi-bit data; a plurality of reference cells programmed to have at least two different resistance states among a plurality of the resistance states each time the main cells are programmed; and a reference voltage generation circuit which generates the reference voltage for sensing a plurality of reference cells, and identifying each of the plurality of the resistance states. The phase change memory device improves reliability of read operation while the resistance values of the phase change substance changes with time. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device, and more particularly, to a phase change memory device and a reading method thereof.

  Random access is possible, and the demand for semiconductor memory devices capable of realizing high concentration and large capacity is increasing. A typical example of such a semiconductor memory device is a flash memory that is mainly used for portable electronic devices. In addition, semiconductor memory devices in which DRAM capacitors are replaced with non-volatile materials have appeared. Ferroelectric RAM (FRAM) using a ferroelectric capacitor, magnetic RAM (Magnetic RAM; MRAM) using a TMR (TMR; Tunneling magneto-resistive) film, and a chalcogenide alloy Phase change memory devices. Particularly, the phase change memory device is a non-volatile memory device, and its manufacturing process is relatively simple, and a low-priced and large-capacity memory can be implemented.

  Phase change memory cells use materials that can be electrically changed between various structural states that represent different electrical read characteristics. For example, a memory device made of a chalcogenide material (hereinafter referred to as “GST substance”) which is a germanium / antimony / tellurium compound GST is known. The GST material is programmed between an amorphous state exhibiting a relatively high resistivity (Amorphous state) and a crystalline state representing a relatively low resistivity (Crystalline state). That is, the phase change memory cell is programmed by heating the GST material. The magnitude and duration of the heating determines whether the GST material remains in an amorphous or crystalline state. High and low resistivity represent programmed values '1' and '0', which can be sensed by measuring the resistivity of the GST material.

  In a general phase change memory device, a memory cell includes a resistance element and a switch element. 1A and 1B show memory cells of a phase change memory device. As shown in FIG. 1A, the memory cell 10 of the phase change memory device includes a variable resistor 11 that is a resistance element and an access transistor 12 that is a switch element. The variable resistor 11 is connected to the bit line BL. Access transistor 12 is connected between variable resistor 11 and ground. A word line WL is connected to the gate of the access transistor 12. When a predetermined voltage is applied to the word line WL, the access transistor 12 is turned on. When the access transistor 12 is turned on, a current Ic is supplied to the variable resistor 11 through the bit line BL. FIG. 1B shows a memory cell 20 of another form of phase change memory device. Another form of memory cell 20 includes a variable resistor 21 that is a resistive element and a diode 22 that is a switch element. The diode 22 is turned on (Turn-on) or turned off (Turn-off) by the word line WL voltage.

  The variable resistors 11 and 21 include a phase change material (not shown). The phase change material exists in any one of two stable states defined by a crystalline state and an amorphous state. The phase change material changes to a crystalline state or an amorphous state according to a current Ic supplied through the bit line BL. The phase change memory device programs data using such characteristics of the phase change material. The switch element can be implemented using various elements such as a MOS transistor and a diode.

  FIG. 2 is a graph for explaining the characteristics of the phase change material used in the variable resistor GST. In FIG. 2, a curve 1 indicates a temperature condition for phase-converting the phase change material into an amorphous state (Amorphous state). Curve 2 shows the temperature conditions for converting the phase change material to the crystalline state. As shown in curve 1, if the phase change material GST is heated at a temperature higher than the melting temperature (MelTiNg temperature; Tm) for a period of time T1 through the supply of a current pulse, the phase change material GST is not cooled. It becomes an amorphous state (Amorphous state). The amorphous state is called a normal reset state (Reset state) and corresponds to data ‘1’. In contrast, as shown in curve 2, the phase change material is heated for a time T2 that is higher than the crystallization temperature (Tc) and lower than the melting temperature Tm for a time T2 that is longer than the time T1, When it is gradually cooled, it enters a crystalline state. The crystal state is also called a normal set state (Set state), and corresponds to data ‘0’. The resistance of the memory cell varies depending on the amount of amorphous contained in the phase change material. The resistance of the memory cell is highest in the amorphous state and lowest in the crystalline state.

  Recently, a technique for storing data of 2 bits or more in one memory cell has been developed. Such a memory cell is called a multi-level cell (MLC). In the phase change memory device, the multi-level cell further includes an intermediate state between a reset state and a set state. A method of programming a phase change memory device having a multi-level cell is disclosed in Patent Document 1 under the title “Method and apparatus to program a phase change memory”, and is included in the reference of the present invention.

In phase change memory devices, multi-level cells provide a larger data storage capacity than conventional single-level cells. However, in order to read data from the multi-level cell, a read circuit having higher precision must be provided. That is, in order to realize a multi-level phase change memory device, a high-resolution sense amplification function that can distinguish various resistances of resistance elements is urgently required.
US Pat. No. 6,625,054

  An object of the present invention is to provide a multi-level phase change memory device having a high-resolution reading performance and a reading method thereof.

  According to another aspect of the present invention, there is provided a phase change memory device comprising: a plurality of main cells programmed to have any one of a plurality of resistance states corresponding to each of multi-bit data; Each time the main cell is programmed, the plurality of reference cells programmed to have at least two different resistance states among the plurality of resistance states, and the plurality of reference cells are sensed to detect the plurality of reference cells. A reference voltage generating circuit for generating a reference voltage for identifying each of the resistance states of the reference voltage.

  According to one embodiment, the plurality of main cells and the plurality of reference cells are connected to the same word line.

  According to an embodiment, the plurality of reference cells are programmed to have resistance values corresponding to two different states of the plurality of resistance states.

  According to one embodiment, each of the plurality of reference cells is programmed in any one of the first to fourth states having different resistance magnitudes. A first reference cell programmed in the second state; and a second reference cell programmed in a third state having a higher resistance than the second state.

  According to an embodiment, the reference voltage generating circuit senses a bit line of the first reference cell to identify the first state and the second state, and the second reference voltage. The second state and the third state voltage using a third reference voltage for sensing the bit line of the cell to distinguish the third state and the fourth state, and the levels of the first reference voltage and the third reference voltage. A second reference voltage for identifying the third state is generated.

  According to an embodiment, the second reference voltage is an arithmetic average of the first reference voltage and the third reference voltage.

  According to one embodiment, the plurality of reference cells are programmed to have a resistance value corresponding to each of the plurality of resistance states.

  According to an embodiment, the number of the plurality of reference cells corresponds to each of the plurality of resistance states.

  According to an embodiment, the plurality of reference cells have a resistance value corresponding to any one of the first to fourth states in which the plurality of main cells have different resistance magnitudes. A first reference cell programmed in the first state, a second reference cell programmed in the second state having a higher resistance value than the first state, and the second state A third reference cell programmed in the third state having a high resistance value; and a fourth reference cell programmed in the fourth state having a higher resistance value than the third state.

  According to an embodiment, the reference voltage generation circuit detects first to third reference voltages for identifying the first to fourth states by sensing bit lines of the first to fourth reference cells. Generate.

  According to an embodiment, each of the plurality of main cells and the plurality of reference cells includes a variable resistor having one of the plurality of resistance states and a selection signal provided to the word line. And a selection element that switches to be selected in response.

  According to one embodiment, the variable resistor is formed of a chalcogenide alloy.

  According to an embodiment, the variable resistor has a crystal state and a plurality of amorphous states corresponding to each of the plurality of resistance states.

  According to one embodiment, a sense amplifier circuit that compares the bit line voltage of each of the plurality of main cells with the reference voltage and reads multi-bit data stored in the plurality of main cells is further included.

  According to one embodiment, a write driver for programming the plurality of reference cells to have at least two different states among the plurality of resistance states each time the plurality of main cells are programmed. Including.

  According to one embodiment, a read method of a variable resistance memory device, each including a memory cell having one of a plurality of resistance states, includes a reference voltage using a bit line voltage sensed from the plurality of reference cells. And reading data programmed in the main cell with reference to the reference voltage.

  According to one embodiment, the method further includes programming the plurality of reference cells to have at least two of the plurality of resistance states.

  According to one embodiment, the plurality of reference cells and the main cell are connected to the same word line.

  According to one embodiment, the plurality of reference cells are programmed each time at least one of the main cells is programmed.

  According to an embodiment, the reference cell is programmed to have resistance values corresponding to two different states of the plurality of resistance states.

  According to an embodiment, in the step of generating the reference voltage, for identifying each of the plurality of resistance states using bit line voltages corresponding to two different states sensed from the reference cell. A plurality of reference voltages are generated.

  The plurality of reference cells include two reference cells programmed to have resistance values corresponding to the two different states.

  According to one embodiment, the plurality of reference cells are programmed to have a resistance value corresponding to each of the plurality of resistance states.

  According to one embodiment, the number of the plurality of reference cells corresponds to the plurality of resistance states.

  According to an embodiment, in the step of generating the reference voltage, a plurality of reference voltages for identifying each of the plurality of resistance states is generated using a bit line voltage of each of the plurality of reference cells. .

  According to one embodiment, a method for generating a reference voltage of a multi-level phase change memory device, each having any one of a plurality of resistance states, includes: a plurality of reference cells having at least two states among the plurality of resistance states; And programming a reference voltage using a bit line voltage sensed from the plurality of reference cells.

  In one embodiment, the step of programming the plurality of reference cells is performed each time at least one of the main cells connected to the same word line as the plurality of reference cells is programmed.

  According to one embodiment, the plurality of reference cells are programmed with resistance values corresponding to two different states of the plurality of resistance states.

  According to an embodiment, in the step of generating the reference voltage, a reference voltage for identifying each of the plurality of resistance states is generated using a bit line voltage corresponding to the two different states. .

  According to one embodiment, the plurality of reference cells comprise two phase change memory cells programmed to have resistance values corresponding to two different states, respectively.

  According to an embodiment, in the step of generating the reference voltage, a plurality of reference voltages for identifying the plurality of resistance states are generated using the bit line voltages of the two reference cells.

  According to one embodiment, the plurality of reference cells are programmed to have a resistance value corresponding to each of the plurality of resistance states.

  According to one embodiment, the plurality of reference cells include a number of phase change memory cells corresponding to the plurality of resistance states.

  According to an embodiment, in the step of generating the reference voltage, a plurality of reference voltages for identifying the plurality of resistance states are generated using the bit line voltages of each of the plurality of reference cells.

  As described in detail, the multi-level phase change memory device according to the present invention can reduce read errors by providing a variable reference voltage for correcting a change in resistance of a memory cell during a read operation.

  It should be appreciated that the foregoing general description and the following detailed description are to be regarded as illustrative and provide additional explanation of the claimed invention.

  Reference numerals are shown in detail in the preferred embodiments of the present invention, examples of which are shown in the reference drawings. In any case, the same reference numerals are used in the description and the drawings to refer to the same or similar parts.

  Hereinafter, a multi-level phase change memory device will be used as an example for explaining the features and functions of the present invention. However, those skilled in the art can readily appreciate other advantages and performances of the present invention as described herein. The present invention can be embodied or applied through other embodiments. The detailed description can be modified or changed according to the viewpoint and application without departing from the scope, technical idea, and other objects of the present invention.

  FIG. 3 is a cross-sectional view schematically showing a memory cell structure of the multilevel phase change memory device of the present invention. As shown in FIG. 3, the memory cell 10 includes a variable resistor 11 and an access transistor NT. The variable resistor 11 is connected to the bit line BL. Access transistor NT is connected between variable resistor 11 and ground. A word line WL is connected to the gate of the access transistor NT. When the access transistor NT is turned on, a current Ic is supplied to the variable resistor 11 through the bit line BL. It is obvious to those skilled in the art that the access transistor NT of FIG. 3 can be implemented in the form of a diode.

  Again, as shown in FIG. 3, the variable resistor 11 includes an upper electrode 13, a phase change material 14, a contact plug 15, and a lower electrode 16. The upper electrode 13 is connected to the bit line BL. The lower electrode 16 is connected between a contact plug (CP) 15 and the access transistor NT. The contact plug 15 is made of a conductive material (for example, TiN) and is also referred to as a heater plug. The phase change material 14 is formed between the upper electrode 13 and the contact plug 15. The state (Phase) of the phase change material 14 varies depending on the magnitude (Amplitude), width (Duration), and fall time (Fall time) of the current pulse to be supplied. A hatched portion 17 in FIG. 3 indicates an amorphous amount of the phase change material. As the amorphous state progresses from the amorphous state to the crystalline state, the amorphous amount decreases.

  The phase change material 14 may have more than one state due to a current pulse provided through the bit line BL. This is called a multi-state. The memory cell 10 has one of the multi states depending on the amorphous amount formed in the phase change material 14. The resistance of the variable resistor 11 is changed according to the amorphous amount of the phase change material 14 (Amorphous volume). That is, each of the amorphous quantities 17, 18, and 19 of the phase change material 14 formed by different current pulses corresponds to different multi-bit data. The variable resistor 14 is programmed by the current pulse in any one of the crystal state corresponding to the set state (Set state) and the reset states 17, 18, and 19 described in detail.

  FIG. 4A is a graph showing a change in resistance over time of a memory cell having an amorphous state. Here, the resistance of the resistance element can be increased over time due to various causes. In particular, the resistance value in the reset state (Reset state) increases with time as the initial resistance of the resistance element increases. As shown in FIG. 4, the horizontal axis of the graph indicates the time that elapses after the memory cell is programmed. The vertical axis of the graph indicates the resistance value of the memory cell. As shown in the figure, the resistance value of the resistance element cannot maintain a fixed value after being programmed, and increases with the passage of time. In a multi-level cell, such resistance element characteristics reduce the read margin. Therefore, in the case of data read after a certain time has elapsed since the program, there is a possibility that an error is included. The change in resistance over time acts as a limiting factor in implementing a multi-level phase change memory device.

  FIG. 4B is a graph showing a change in resistance due to thermal history of the resistance element of the phase change memory cell. The thermal history curve of FIG. 4B has been described with reference to a 2-bit multilevel cell 2-bit MLC. Taking the cells programmed with data in the '11' state and the '10' state, the problem due to the resistance change related to the thermal history will be described. The graph shows the resistance of the resistive element that varies with changes in temperature function (1 / kT, where k is Boltzmann's constant and T is absolute temperature). The thermal history indicates a change in the resistance value of the resistance element when the temperature is increased for a specific time and then returned to the original temperature. That is, the resistance values corresponding to the 2-bit data “11”, “10”, “01”, and “00” in the drawing have the rate of change of other resistances when the temperature increases and decreases. . Looking at the thermal history of the cell programmed with '10' data, the resistance change 30 curve when the temperature is raised does not match the resistance change 40 curve when the temperature is lowered again. Even if the temperature returns to the initial temperature, the resistance of the resistance element has a value different from the value before the temperature change due to the influence of the temperature change. Due to such characteristics, in an extreme case, the resistance value corresponding to ‘11’ and the resistance value corresponding to ‘10’ overlap, thereby reducing the reliability of the sensing operation. Such a current situation acts as a large technical barrier in a multi-level cell MLC for storing data of 2 bits or more within a limited resistance range.

  As described with reference to FIGS. 4A and 4B, a sensing scheme that takes into account a resistance value that varies according to the time or temperature of a resistive element is urgently needed to provide multi-level cell reliability. There is a real situation. Further, it is obvious to those skilled in the art that the variable resistance of the resistance element can be caused by various factors as well as the time and temperature described in detail. The present invention provides a method and an apparatus for providing a variable reference voltage capable of canceling a resistance change due to various factors described in detail.

  FIG. 5 is a block diagram illustrating a multi-level phase change memory device that schematically represents an embodiment of the present invention. As shown in FIG. 5, a plurality of bit line voltages are provided to the reference voltage generation circuit 140 from the memory cells in the reference region 120 during a read operation. The reference voltage generator 140 generates a reference voltage Vref with reference to a plurality of bit line voltages. The reference voltage Vref is provided to the sense amplifier circuit 130 as a reference value that can correct a change in the resistance value of the memory cell included in the main region 110.

  Main region 110 includes phase change memory cells storing multi-bit data. In addition, the phase change memory device 100 according to the present invention includes a reference region 120 including a reference cell.

  The sense amplifier circuit 130 senses data of the selected memory cell during the read operation. The sense amplifier circuit 130 compares the voltage of the sensing node connected to the bit line of the selected memory cell during the read operation with the reference voltage Vref. The sense amplifier circuit 130 outputs the compared result value SA0 as read data. Here, the sense amplifier circuit 130 according to the present invention is provided with a reference voltage Vref for correcting a change in the resistance value of the memory cell. The reference voltage Vref is provided from the reference voltage generation circuit 140.

  The reference voltage generation circuit 140 generates a reference voltage Vref for reading out the multi-level cell with reference to the bit line voltage provided from the reference cell during the read operation. As an example, in the case of a 2-bit multi-level cell, the reference voltage generation circuit 140 refers to a bit line voltage provided from at least two reference cells and determines a reference voltage Vref for identifying four resistance states. Can be generated. Alternatively, in the case of a 2-bit multi-level cell, the reference voltage generation circuit 140 refers to a bit line voltage provided from at least four reference cells and determines a reference voltage Vref for identifying four resistance states. Can be generated.

  The write driver 150 is controlled by the control logic 170 and supplies a write current to the bit line of the memory cell according to data provided through the input / output buffer circuit 160. In particular, the write driver 150 of the present invention shares a word line with a selected memory cell every time a pulse current for programming the memory cell of the selected main region 110 is provided during a write operation. The reference cell is programmed to predetermined data. During the write operation, the write driver 150 programs the reference cells connected to the selected word line WL at the same time as the memory cells in a predetermined selected main area.

  The input / output buffer 160 provides write data provided from outside during the write operation to the write driver 150. The input / output buffer 160 transmits the sense data SA0 transmitted from the sense amplifier circuit 130 to the outside during the read operation.

  The control logic 170 controls operations of the write driver 150 and the sense amplifier circuit 130 during a read operation and a write operation. In particular, the control logic 170 controls the write driver 150 so that the reference cells in the reference region 120 sharing the word line with the selected memory cell during the write operation are programmed.

  The address decoder 180 decodes an address ADDR provided from the outside in the write or read operation mode, and provides it to a selection circuit (not shown) for selecting a word line and a bit line of the memory cell. Although not shown in the drawing, a plurality of memory cells are arranged in rows (or word lines) and columns (or bit lines). Each memory cell includes a switch element and a resistance element. The switch element can be implemented using various elements such as a MOS transistor and a diode. The resistance element is configured to include a phase change film made of the GST material described above.

  Through the above configuration, the multi-level phase change memory device 100 of the present invention includes a main cell storing input / output data and a reference cell corresponding to the main cell. The reference cell is programmed to a specific resistance state each time the main cell is programmed. Therefore, the magnitude of the resistance drift of the GST material constituting the memory cell over time of the reference cell is synchronized with the main cell. The reference cell and the reference voltage generation circuit 140 can provide a reference voltage for correcting a resistance change of the main cell. Therefore, a highly reliable multilevel phase change memory device can be provided.

  FIG. 6 is a block diagram illustrating the reference cells RMC <1> and RMC <2> and the reference voltage generation circuit 140 according to an embodiment of the present invention. Here, in order to briefly explain the idea of the present invention, a multi-level phase change memory device in which 2-bit is stored in one memory cell will be described as an example. As shown in FIG. 6, two reference cells RMC <1> and RMC <2> are allocated to one word line. The reference cells RMC <1> and RMC <2> are programmed to have different resistance states each time data is written into the memory cells in the main area. During a read operation, a reference voltage Vref for identifying each of the multi-states is generated with reference to the bit line voltages provided from the reference cells RMC <1> and RMC <2>.

  As illustrated, the main cells MC <1> to MC <n> in the main region 110 and the reference cells RMC <1> and RMC <2> in the reference region 120 are connected to the same word line WL. The main cells MC <1> to MC <n> are composed of, for example, 16 memory cells corresponding to input / output units (for example, one word (Word)). The reference cells RMC <1> and RMC <2> are formed to share 16 memory cells and the word line WL. Each of the reference cells RMC <1> and RMC <2> is programmed with a different resistance state each time data is written in the main cells MC <1> to MC <n>. That is, the reference cells RMC <1> and RMC <2> are programmed each time at least one of the main cells sharing the word line is programmed. Each of the reference cells RMC <1> and RMC <2> is programmed with different multi-bit data, thereby having different cell resistances. The multi-bit data written in the reference cells RMC <1> and RMC <2> will be described in detail with reference to FIG.

  During the read operation, the word line WL is selected according to the address, and the data stored in the memory cells connected to the selected word line is stored in the bit lines BL <1> to BL <n>, RBL <1>, RBL <2>. Perceived by. More specifically, each bit line is precharged by a precharge circuit (not shown), and the sense amplifier circuit 130 senses the voltage of the precharged bit line and stores it in the memory cell. Determine the data. That is, the sense amplifier circuit 130 compares the potential sensed from the sense nodes of the bit lines BL <1> to BL <n> with the reference voltage Vref provided from the reference voltage generation circuit 140. Data stored in each of the memory cells selected according to the comparison result is sensed and output. In particular, the phase change memory device of the present invention generates the reference voltage Vref according to the potentials of the bit lines RBL <1> and RBL <2> of the reference cells RMC <1> and RMC <2>. The reference cells RMC <1> and RMC <2> are programmed in different states among the four multi states during the program operation. Therefore, the reference cells RMC <1> and RMC <2> have different resistance values. The main cells MC <1> to MC <n> and the reference cells RMC <1>, RMC <2> have the same programmed time. Therefore, the rate of change in resistance generated in the variable resistor GST between the main cells MC <1> to MC <n> and the reference cells RMC <1> and RMC <2> with the passage of time is the same.

  During the read operation, changes in the resistance values of the reference cells RMC <1> and RMC <2> are sensed through the bit lines RBL <1> and RBL <2>. The voltages V1 and V2 of the bit lines RBL <1> and RBL <2> are provided to the reference voltage generation circuit 140. The reference voltage generation circuit 140 generates a reference voltage Vref for correcting resistance drift with reference to a change in resistance sensed from the reference cells RMC <1> and RMC <2>. The generated reference voltage Vref is provided to the sense amplifier circuit 130. The sense amplifier circuit 130 compares the reference voltage Vref with the bit line voltages of the main cells MC <1> to MC <n> and outputs the result to the sense data SA0. Here, the program states of the reference cells RMC <1> and RMC <2> correspond to two different states among the four multi-states corresponding to 2-bit data. For example, the reference cell RMC <1> can be programmed in a state corresponding to the data ‘01’, and the reference cell RMC <2> can be programmed in a state corresponding to the data ‘10’.

  For example, FIG. 6 shows main cells MC <1> to MC <n> and reference cells RMC <1>, RMC <2> sharing one word line, but all the memories included in the cell array. The cell is constituted by the structure described above. Also, although a sense amplifier circuit 130 to which a plurality of bit line voltages are input is shown, the sense amplifier circuit 130 includes a sense amplifier corresponding to each of the bit lines. For example, when the bit structure is x8, the sense amplifier circuit 130 includes eight sense amplifiers. If the bit structure is x16, 16 sense amplifiers are required. However, it is obvious to those skilled in the art that the number of sense amplifiers and the like is not limited to the bit structure.

  Through the configuration described in detail and the programming of the reference cells RMC <1> and RMC <2>, the phase change memory device of the present invention can correct the influence of the resistance drift of the memory cell that occurs over time during the read operation. Accordingly, the reliability of the read operation can be improved in the multi-level phase change memory device.

  FIG. 7 is a diagram illustrating a method of programming the reference cells RMC <1> and RMC <2> of FIG. 6 described in detail and a method of generating a reference voltage. As shown in FIG. 7, each of the reference cells RMC <1>, RMC <2> has a phase among resistance states corresponding to 2-bit data '00', '01', '10', '11'. Each is programmed in two different states. During the read operation, the reference voltage generation circuit 140 generates reference voltages Vref1, Vref2, and Vref3 by referring to the bit line voltages of the reference cells RMC <1> and RMC <2>. Here, as an exemplary embodiment, the reference cell RMC <1> has a resistance value corresponding to the data '01', and the reference cell RMC <2> has a resistance value corresponding to the data '10'. Programmed to have. The programming operation of the reference cells RMC <1> and RMC <2> is the same as that when the main cells MC <1> to MC <n> connected to the same word line are programmed. The resistance value change of the main cells MC <1> to MC <n> moves from the state 210, 220, 230, 240 at the time of programming to the drift state 211, 221, 231, 241. Such a drift of the resistance value occurs in the same manner in the reference cells RMC <1> and RMC <2> programmed to the data ‘01’ and the data ‘10’, respectively. Immediately after being programmed, the resistance of the reference cell RMC <1> is included in the state 220 corresponding to the data ‘01’. Over time, the resistance of the reference cell RMC <1> is distributed in the drifted state 221. Immediately after being programmed, the resistance of the reference cell RMC <2> is included in the state 230 corresponding to the data ‘10’. Over time, the resistance of the reference cell RMC <2> is distributed in the drifted state 231.

  If a read command is input from the outside during a read operation, the bit line of the memory cell is precharged. Then, the word line WL is activated (for example, the word line voltage is changed to the “LOW” level). Data of the main cells MC <1> to MC <n> and the reference cells RMC <1> and RMC <2> connected to the selected word line are detected as a potential change of the precharged bit line BL. . The sense amplifier circuit 130 senses the bit line voltages of the main cells MC <1> to MC <n>. The reference voltage generation circuit 140 is supplied with the bit line voltages of the reference cells RMC <1> and RMC <2>. The reference voltage generation circuit 140 is provided with voltages V1 and V2 formed on the bit lines RBL <1> and RBL <2>.

  The reference voltage generation circuit 140 generates a reference voltage Vref1 for identifying the “00” state and the “01” state with reference to the level of the bit line voltage V1. That is, the reference voltage generation circuit 140 refers to the level of the bit line voltage V1 and generates the reference voltage Vref1 having a level that can provide a read margin (for example, ΔV). That is, the reference voltage generation circuit 140 determines the reference voltage Vref1 by referring to the drifted resistance value 221 sensed through the bit line voltage V1.

  Further, the reference voltage generation circuit 140 generates a reference voltage Vref3 for identifying the “10” state and the “11” state with reference to the level of the bit line voltage V2. The reference cell RMC <2> has a resistance value corresponding to the drifted state 231 programmed in the ‘10’ state. That is, the reference voltage generation circuit 140 determines the reference voltage Vref3 with reference to the drifted resistance value 231 sensed through the bit line voltage V2. That is, the reference voltage generation circuit 140 refers to the level of the bit line voltage V2 and generates the reference voltage Vref3 at a level that can provide a read margin (for example, ΔV).

  The reference voltage generation circuit 140 generates a reference voltage Vref2 for identifying the ‘01’ state and the ‘10’ state by using the already determined reference voltages Vref1 and Vref3. The reference voltage Vref2 can be determined by an arithmetic average value “(Vref1 + Vref3) / 2” of the reference voltage Vref1 and the reference voltage Vref3.

  Through the above operation of the reference voltage generation circuit 140, even when the resistance value of the memory cell drifts with time, the phase change memory device can perform a highly reliable read operation.

  FIG. 8 is a block diagram schematically illustrating another embodiment of the reference cells RMC <1>, RMC <2>, RMC <3>, RMC <4>, and the reference voltage generation circuit 140 in the reference region 120. Here, in order to briefly explain the idea of the present invention, a 2-bit multi-level phase change memory device in which 2-bit is stored in one memory cell will be described as an example. As shown in FIG. 8, at least four reference cells are assigned to one word line. Each of the reference cells is programmed with one of four states each time data is written to the memory cell in the main area. Each of the reference cells is programmed in a state corresponding to a different resistance value. During the read operation, the reference voltage generation circuit 140 generates a reference voltage Vref for identifying each of the multi-bits with reference to the bit line voltages V1, V2, V3, and V4 provided from the reference cells.

  As illustrated, the main cells MC <1> to MC <n> in the main region 110 and the reference cells RMC <1>, RMC <2>, RMC <3>, and RMC <4> in the reference region 120 are the same. Connected to the word line WL. The main cells MC <1> to MC <n> can be composed of, for example, 16 memory cells. The reference cells RMC <1>, RMC <2>, RMC <3>, RMC <4> are configured to share a word line with 16 memory cells. The reference cells RMC <1>, RMC <2>, RMC <3>, and RMC <4> are programmed each time data is written to the main cells MC <1> to MC <n>. The reference cells RMC <1>, RMC <2>, RMC <3>, RMC <4> are each programmed with a resistance value corresponding to different data. Data written in the reference cells RMC <1>, RMC <2>, RMC <3>, and RMC <4> will be described in detail with reference to FIG.

  During a read operation, a word line WL is selected by an address, and data stored in memory cells connected to the selected word line is stored in bit lines BL <1> to BL <n>, RBL <1>, RBL <. 2>, RBL <3>, RBL <4>. More specifically, each bit line is precharged by a precharge circuit (not shown), and the sense amplifier circuit 130 senses a change in potential of the precharged bit line and stores it in the memory cell. Determine the data. That is, the sense amplifier circuit 130 compares the voltage sensed from the sense nodes of the bit lines BL <1> to BL <n> with the reference voltage Vref provided from the reference voltage generation circuit 140. Data stored in each of the memory cells selected according to the comparison result is sensed and output. In particular, the phase change memory device of the present invention includes the bit lines RBL <1>, RBL <2>, RBL <3> of the reference cells RMC <1>, RMC <2>, RMC <3>, RMC <4>, The reference voltage Vref is generated by the RBL <4> potential. The reference cells RMC <1>, RMC <2>, RMC <3>, and RMC <4> are each in one of four different states of multi-bit data during a program operation. Programmed. Accordingly, each of the reference cells RMC <1>, RMC <2>, RMC <3>, RMC <4> has a different cell resistance. During the read operation, the bit lines RBL <1>, RBL <2>, RBL <3>, RBL <4 depending on the resistance values of the reference cells RMC <1>, RMC <2>, RMC <3>, RMC <4>. The sensing voltage formed in> is expressed differently. The main cells MC <1> to MC <n> MC <1> to MC <n> and the reference cells RMC <1>, RMC <2>, RMC <3>, RMC <4> are programmed at the same time. It was done. Therefore, it has the same time variable. The reference cells RMC <1>, RMC <2>, RMC <3>, and RMC <4> detect a change in resistance of the memory cell over time and provide it to the reference voltage generation circuit 140. The reference voltage generation circuit 140 refers to a change in resistance detected from the reference cells RMC <1>, RMC <2>, RMC <3>, RMC <4>, and a reference voltage Vref for correcting the passage of time. Is generated and provided to the sense amplifier circuit 130. The sense amplifier circuit 130 compares the reference voltage Vref with the bit line voltage of the phase change memory device in the main region 110, and outputs the result as sense data SA0. Here, each program state of the reference cells RMC <1>, RMC <2>, RMC <3>, RMC <4> corresponds to each of four states corresponding to 2-bit data. For example, the reference cell RMC <1> corresponds to the data “00”, the reference cell RMC <2> corresponds to the data “01”, and the reference cell RMC <3> corresponds to the data “10”. And the reference cell RMC <4> can be programmed in a state corresponding to data '00'.

  As described above, the reference cells RMC <1>, RMC <2>, RMC <3>, and RMC <4> are posted to a 2-bit multi-level phase change memory device having four states corresponding to 2-bit data. However, the present invention is not limited to this. For example, in the 3-bit multi-level phase change memory device, 8 reference cells are included to include cells programmed in all resistance states. For example, FIG. 8 shows main cells MC <1> to MC <n> sharing one word line and reference cells RMC <1>, RMC <2>, RMC <3>, RMC <4>. However, all the memory cells included in the cell array are configured identically to the described structure.

  Through the detailed configuration and the programming of the reference cells RMC <1>, RMC <2>, RMC <3>, RMC <4>, it is possible to correct the influence of the resistance drift of the memory cell caused by the passage of time during the read operation. Accordingly, the reliability of the read operation can be improved in the multi-level phase change memory device.

  FIG. 9 is a diagram illustrating a programming method and a reference voltage generation method for the reference cells RMC <1>, RMC <2>, RMC <3>, and RMC <4> of FIG. 8 described in detail. As shown in FIG. 9, the reference cells RMC <1>, RMC <2>, RMC <3>, and RMC <4> include 2-bit data “00”, “01”, “10”, and “11”. Each of the corresponding states is programmed in the corresponding state. During the read operation, the reference voltage generation circuit 140 refers to the bit line voltages of the reference cells RMC <1>, RMC <2>, RMC <3>, and RMC <4>, and references voltages Vref1, Vref2, and Vref3. Is generated.

  Each of the reference cells RMC <1>, RMC <2>, RMC <3>, RMC <4> can be programmed to correspond to each of the four resistance states. Here, in the exemplary embodiment, the reference cell RMC <2> corresponds to the data '01' so that the reference cell RMC <1> has a resistance value of the state 310 corresponding to the data '00'. The reference cell RMC <3> has a resistance value of state 330 corresponding to the data '10' so that it has a resistance value of state 320, and the reference cell RMC <4> corresponds to data '11'. Programmed to have a resistance value of state 340. The programming of the reference cells RMC <1>, RMC <2>, RMC <3>, RMC <4> is the same as when the main cells MC <1> to MC <n> are programmed. That is, every time the main cells MC <1> to MC <n> connected to the same word line WL are programmed, the reference cells RMC <1>, RMC <2>, RMC <3>, RMC <4>. Is programmed in the detailed manner. Therefore, the magnitude of the time drift of the resistance value generated in the resistance element of the memory cell is determined by the main cells MC <1> to MC <n> and the reference cells RMC <1>, RMC <2>, RMC <3>, RMC. It is the same in <4>. As time passes, the resistance values of the main cells MC <1> to MC <n> move from the states 310, 320, 330, and 340 at the time of programming to the states 311, 321, 331, and 341 that have drifted. Such a change in resistance value is also caused in the reference cells RMC <1>, RMC <2>, RMC <3>, and RMC <4> programmed with data “00”, “01”, “10”, and “11”. It occurs in the same way.

  When a read command is input from the outside, the bit line of the memory cell is precharged. Then, the word line is activated (for example, the word line voltage is changed to the LOW level). The data of the memory cells MC <1> to MC <n> of the main area connected to the selected word line and the reference cells RMC <1>, RMC <2>, RMC <3>, RMC <4> are: This is detected as a change in the potential of the precharged bit line BL. The sense amplifier circuit 130 senses the bit line potential of the main cells MC <1> to MC <n>. The reference voltage generation circuit 140 is supplied with the bit line potentials of the reference cells RMC <1>, RMC <2>, RMC <3>, and RMC <4>. The reference voltage generation circuit 140 is provided with voltages V1, V2, V3, and V4 formed on the bit lines RBL <1>, RBL <2>, RBL <3>, and RBL <4>. The reference voltage generation circuit 140 generates a reference voltage using the levels of the voltages V1, V2, V3, and V4. The reference voltage generation circuit 140 refers to the voltages V1, V2, V3, and V4, and generates reference voltages Vref1, Vref2, and Vref3 corresponding to each state in consideration of resistance drift. Compared to the case where two reference cells are included, the embodiment including the reference cells programmed with the resistance value corresponding to each state can reduce the burden on the reference voltage generation circuit 140. In this embodiment, reference cells RMC <1>, RMC <2>, RMC <3>, and RMC <4> are provided only for phase change memory devices having four resistance states for storing 2-bit data. It was explained that That is, four reference cells per word line must be provided. However, in the case of a multi-level cell storing 3-bit data, the number of reference cells to be provided per word line is eight.

  As described above, as shown in FIG. 9, the reference voltage generation circuit 140 of the present invention can provide a reference voltage that can provide the minimum read error regardless of the time drift of the resistance.

  FIG. 10 shows a variable reference voltage Vref1 using voltages V1, V2, V3, and V4 provided from the reference cells RMC <1>, RMC <2>, RMC <3>, and RMC <4> of FIG. , Vref2, Vref3 generation and / or calculation. Although not specifically described from FIG. 9 described in detail, the variable reference voltages Vref1, Vref2, and Vref3 can be determined through simple arithmetic operations. That is, the reference voltage Vref1 for separating the data '00' and the data '01' is provided as an arithmetic average (Median) of the voltages V1 and V2 provided from the reference cells RMC <1> and RMC <2>. . The reference voltage Vref2 for separating the data “01” and the data “10” is an arithmetic average (Media) of the voltages V2 and V3 provided from the reference cells RMC <2> and RMC <3>, that is, (V2 + V3). Provided at / 2. The reference voltage Vref3 for separating the data “10” and the data “00” is provided as an arithmetic average (Median) of the voltages V3 and V4 provided from the reference cells RMC <3> and RMC <4>. Of course, each of the reference cells RMC <1>, RMC <2>, RMC <3>, RMC <4> must be programmed to correspond to each of the four resistance states. Illustratively, the reference cell RMC <2> has a resistance value corresponding to the data '00' (310, see FIG. 9), so that the reference cell RMC <2> corresponds to the data '01'. 320, the reference cell RMC <3> has a resistance value corresponding to the data '10' (330, see FIG. 9), and the reference cell RMC <4. > Is programmed to have a resistance value in a state (340, see FIG. 9) corresponding to data '11'. The programming of the reference cells RMC <1>, RMC <2>, RMC <3>, RMC <4> is the same as when the main cells MC <1> to MC <n> are programmed. That is, every time the main cells MC <1> to MC <n> connected to the same word line WL are programmed, the reference cells RMC <1>, RMC <2>, RMC <3>, RMC <4> Programmed as detailed. Accordingly, the magnitudes of changes in resistance values generated by the resistance elements of the memory cells due to time drift and thermal history are the main cells MC <1> to MC <n> and the reference cells RMC <1>, RMC <2>, RMC. The same applies to <3> and RMC <4>. Even if the resistance values of the main cells MC <1> to MC <n> change with the heat history and the passage of time, such resistance value changes are represented by data '00', '01', '10' and '11'. The same occurs in the reference cells RMC <1>, RMC <2>, RMC <3>, and RMC <4> programmed in the above. Therefore, reference voltages Vref1, Vref2, and Vref3 that can correct the change in resistance described in detail are provided. Here, since the reference voltages Vref1, Vref2, and Vref3 are variably generated with respect to thermal history, time drift, and other various factors, the reference voltages Vref1, Vref2, and Vref3 are provided as optimum reference voltages.

  FIG. 11 is a block diagram exemplarily illustrating an information processing system to which the multilevel phase change memory device of the present invention is attached. The multi-level phase change memory device of the present invention is a non-volatile memory device that can maintain stored data even when power is cut off. Phase change memory devices support random data access and provide fast data reading and processing. This means that the phase change memory device is ideal for code storage. With the increasing use of mobile devices such as cellular phones, PDA digital cameras, portable game consoles, and MP3 players, phase change memory devices are more widely used not only for code storage but also for data storage. . Phase change memory devices are also used for home applications such as HDTV, DVD, router, and GPS. An information processing system including a multi-level phase change memory device according to the present invention is schematically illustrated in FIG. An information processing system 400 according to the present invention, such as a computer system or a mobile device, includes an input / output device 420, a processing unit 430, a modem 440, a user interface 450, and the like electrically connected to a system bus 460. The information processing system includes the phase change memory device 410 according to the present invention in such a configuration. The phase change memory device 410 is implemented with the same multi-level phase change memory device as described in FIG. The multi-level phase change memory device 410 stores data provided from the processing unit 430. Alternatively, the multi-level phase change memory device 410 can provide data requested from other configurations of the information processing system 400. When the information processing system 400 according to the present invention is a mobile device, a battery (not shown) for supplying an operating voltage of the information processing system 400 is additionally provided. For example, although not shown in the drawings, the information processing system 410 according to the present invention includes an application chip set, a camera image processor (CIS), a mobile DRAM, a NAND flash memory device, and the like. What is further provided is obvious to those with ordinary knowledge in the field.

  It will be apparent to those skilled in the art that the structure of the present invention can be modified and changed in various ways without departing from the scope or the technical idea of the present invention. In view of the detailed description, if the modifications and changes of the present invention fall within the scope of the claims and the equivalents, it is considered that the present invention includes the changes and modifications of the present invention.

3 is a diagram illustrating a cell structure of a phase change memory device. 3 is a diagram illustrating a cell structure of a phase change memory device. 5 is a diagram illustrating temperature characteristics during programming of the phase change memory device. 6 is a diagram illustrating a multi-level state of an amorphous volume of a phase change memory device. 6 is a diagram illustrating resistance characteristics of a phase change memory cell over time. 5 is a diagram illustrating resistance characteristics according to thermal history of a phase change memory cell. 1 is a block diagram schematically showing a phase change memory device according to the present invention; FIG. It is a block diagram which shows the structure by 1st Embodiment of this invention. 7 is a diagram illustrating a program state of the reference cell of FIG. 6. It is a block diagram which shows the structure by 2nd Embodiment of this invention. FIG. 9 is a diagram illustrating a programming state of the reference cell of FIG. 8. 3 is a diagram illustrating a variable reference voltage according to the present invention. It is a block diagram which shows the information processing system by this invention.

Explanation of symbols

10, 20 PRAM cell 110 main cell area 120 reference cell area 130 sense amplifier circuit 140 reference voltage generation circuit 150 write driver 160 input / output buffer 170 control logic 180 address decoder 410 phase change memory device 420 input / output device 430 processing unit 440 modem 450 User interface 460 System bus

Claims (40)

A plurality of main cells programmed to have any one of a plurality of resistance states corresponding to each of the multi-bit data;
A plurality of reference cells programmed to have at least two different resistance states of the plurality of resistance states each time the plurality of main cells are programmed;
A variable resistance memory device, comprising: a reference voltage generating circuit that senses the plurality of reference cells and generates a reference voltage for identifying each of the plurality of resistance states.   The variable resistance memory device of claim 1, wherein the plurality of main cells and the plurality of reference cells are connected to the same word line.   The variable resistance memory device of claim 1, wherein the plurality of reference cells are programmed to have resistance values corresponding to two different states among the plurality of resistance states.   The plurality of reference cells are programmed in the second state every time the plurality of main cells are programmed in any one of the first to fourth states having different resistance magnitudes. The variable resistance memory device of claim 3, further comprising: a first reference cell that is programmed in a third state having a higher resistance value than the second state. The reference voltage generation circuit includes:
A first reference voltage for sensing the bit line of the first reference cell to identify the first state and the second state;
A third reference voltage for sensing the bit line of the second reference cell to identify the third state and the fourth state;
5. The variable according to claim 4, wherein a second reference voltage for discriminating between the second state and the third state is generated using levels of the first reference voltage and the third reference voltage. 6. Resistive memory device.   6. The variable resistance memory device of claim 5, wherein the second reference voltage is an arithmetic average of the first reference voltage and the third reference voltage.   The variable resistance memory device of claim 1, wherein the plurality of reference cells are programmed to have a resistance value corresponding to each of the plurality of resistance states.   8. The variable resistance memory device of claim 7, wherein the number of the plurality of reference cells corresponds to each of the plurality of resistance states. Each of the plurality of reference cells is programmed to have a resistance value corresponding to any one of the first to fourth states having different resistances.
A first reference cell programmed in the first state;
A second reference cell programmed in the second state having a higher resistance value than the first state;
A third reference cell programmed in the third state having a higher resistance value than the second state;
The variable resistance memory device of claim 8, further comprising a fourth reference cell programmed in the fourth state having a higher resistance value than the third state.   The reference voltage generation circuit generates first to third reference voltages for detecting the bit lines of the first to fourth reference cells and identifying the first to fourth states, respectively. The variable resistance memory device according to claim 9. Each of the plurality of main cells and the plurality of reference cells is
A variable resistor having any one of the plurality of resistance states;
The variable resistance memory device according to claim 1, further comprising: a selection element that switches to be selected in response to a selection signal provided to the word line.   The variable resistance memory device according to claim 11, wherein the variable resistor is formed of a chalcogenide alloy.   12. The variable resistance memory device according to claim 11, wherein the variable resistor has a crystal state and a plurality of amorphous states corresponding to the plurality of resistance states.   The sensing amplifier circuit according to claim 1, further comprising a sense amplifier circuit that compares the bit line voltage of each of the plurality of main cells with the reference voltage and reads multi-bit data stored in the plurality of main cells. Variable resistance memory device.   And a write driver for programming the plurality of reference cells to have at least two different states among the plurality of resistance states each time the plurality of main cells are programmed. Item 2. The variable resistance memory device according to Item 1. A method of reading a variable resistance memory device including memory cells each having one of a plurality of resistance states,
Generating a reference voltage using a bit line voltage sensed from a plurality of reference cells;
Reading the data programmed in the main cell with reference to the reference voltage.   The method of claim 16, further comprising programming the plurality of reference cells to have at least two of the plurality of resistance states.   The method of claim 17, wherein the plurality of reference cells and the main cell are connected to the same word line.   The method of claim 18, wherein the plurality of reference cells are programmed each time at least one of the main cells is programmed.   The read method according to claim 19, wherein the reference cell is programmed to have resistance values corresponding to two different states among the plurality of resistance states.   In the step of generating the reference voltage, a plurality of reference voltages for identifying each of the plurality of resistance states is generated using bit line voltages corresponding to two different states sensed from the reference cell. The reading method according to claim 20, wherein:   The reading method according to claim 21, wherein the plurality of reference cells include two reference cells programmed to have resistance values corresponding to the two different states.   The method of claim 19, wherein the plurality of reference cells are programmed to have a resistance value corresponding to each of the plurality of resistance states.   24. The reading method according to claim 23, wherein the number of the plurality of reference cells corresponds to the plurality of resistance states.   The step of generating the reference voltage includes generating a plurality of reference voltages for identifying each of the plurality of resistance states using a bit line voltage of each of the plurality of reference cells. 24. A reading method according to 24.   The read method according to claim 16, wherein the main cell and the plurality of reference cells comprise phase change memory cells. A method for generating a reference voltage of a multi-level phase change memory device, each having any one of a plurality of resistance states,
Programming a plurality of reference cells to have resistance values corresponding to at least two of the plurality of resistance states;
Generating a reference voltage using a bit line voltage sensed from the plurality of reference cells.   The method of claim 27, wherein the step of programming the plurality of reference cells is performed every time at least one of main cells connected to the same word line as the plurality of reference cells is programmed. Reference voltage generation method.   29. The method of claim 28, wherein the plurality of reference cells are programmed with resistance values corresponding to two different states among the plurality of resistance states.   The step of generating the reference voltage includes generating a reference voltage for identifying each of the plurality of resistance states using bit line voltages corresponding to the two different states. 29. A reference voltage generation method according to 29.   The reference voltage generation method of claim 30, wherein the plurality of reference cells include two phase change memory cells programmed to have resistance values corresponding to two different states.   32. The reference voltage according to claim 31, wherein in the step of generating the reference voltage, a plurality of reference voltages for identifying the plurality of resistance states are generated using bit line voltages of the two reference cells. Reference voltage generation method.   30. The method of claim 28, wherein the plurality of reference cells are programmed to have a resistance value corresponding to each of the plurality of resistance states.   The reference voltage generation method of claim 33, wherein the plurality of reference cells include a number of phase change memory cells corresponding to the plurality of resistance states.   35. The step of generating the reference voltage includes generating a plurality of reference voltages for identifying the plurality of resistance states using bit line voltages of the plurality of reference cells. The reference voltage generation method described. A variable resistance memory device;
A memory controller for controlling the variable resistance memory device, the variable resistance memory device comprising:
A plurality of main cells programmed to have any one of a plurality of resistance states corresponding to each of the multi-bit data;
A plurality of reference cells programmed to have at least two different resistance states of the plurality of resistance states each time the plurality of main cells are programmed;
And a reference voltage generating circuit that senses the plurality of reference cells and generates a reference voltage for identifying each of the plurality of resistance states.   37. The memory system of claim 36, wherein the plurality of reference cells are programmed to have resistance values corresponding to two different states of the plurality of resistance states.   The plurality of reference cells are programmed in the second state every time the plurality of main cells are programmed in any one of the first to fourth states having different resistance magnitudes. 38. The memory system of claim 37, further comprising: a first reference cell that is programmed and a second reference cell programmed in a third state having a higher resistance value than the second state. The reference voltage generation circuit includes:
A first reference voltage for sensing the bit line of the first reference cell to identify the first state and the second state;
A third reference voltage for sensing the bit line of the second reference cell to identify the third state and the fourth state;
The second reference voltage for identifying the second state and the third state is generated using levels of the first reference voltage and the third reference voltage. Memory system.   40. The memory system of claim 39, wherein the second reference voltage is an arithmetic average of the first reference voltage and the third reference voltage.

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