CN108665925A - A kind of reading/writing method and system based on multistage storage-type phase transition storage - Google Patents
A kind of reading/writing method and system based on multistage storage-type phase transition storage Download PDFInfo
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- CN108665925A CN108665925A CN201810378043.1A CN201810378043A CN108665925A CN 108665925 A CN108665925 A CN 108665925A CN 201810378043 A CN201810378043 A CN 201810378043A CN 108665925 A CN108665925 A CN 108665925A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/004—Reading or sensing circuits or methods
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/004—Reading or sensing circuits or methods
- G11C2013/0045—Read using current through the cell
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
- G11C2013/0076—Write operation performed depending on read result
Abstract
The invention discloses a kind of reading/writing methods and system based on multistage storage-type phase transition storage, belong to the Read-write Catrol technical field of phase transition storage.Reading/writing method includes reading method and write method, using two there is the phase-change memory cell of multistage storage capacity to constitute read-write base unit；2 bit datas of the opposite resistance value expression storage based on two phase-change memory cell；Reading method reads data for realizing from read-write base unit, and data are written for realizing to read-write base unit in write method.Read-write system includes gating circuit, reads driving circuit, read-write base unit, reading circuit, data output circuit, write operation decision circuitry, writes driving circuit.It is an object of the invention to, multistage storage capacity based on phase-change memory cell, data are expressed using the opposite resistance value of phase change cells in read-write base unit, to in the case where the density of data storage is constant, substantially reduce the execution number of write operation, read-write efficiency is improved, realizes the low power consumption read-write of phase transition storage.
Description
Technical field
The invention belongs to the Read-write Catrol technical fields of phase transition storage PCRAM, more particularly, to one kind based on multistage
The reading/writing method and system of storage-type phase transition storage.
Background technology
Ao Fuxinsiji (Stanford Ovshinsky) has delivered first opinion about noncrystal phase transformation in nineteen sixty-eight
Text, he describes the memory based on phase transformation theory for the first time：Material becomes crystal by non-crystal state, then becomes non-crystal mistake again
Cheng Zhong, different optical characteristics and resistance characteristic is presented in noncrystal and crystal state, therefore can utilize amorphous state and crystalline state
" 0 " and " 1 " is respectively represented to store information, this theory is known as Ao Fuxinsiji electronic effects.Phase transition storage (Phase
Change Random Access Memory, PCRAM) it is the element based on Ao Fuxinsiji electronic effects, therefore also referred to as Austria
Fu Xinsiji electrical effects Unified Memory (Ovonics Unified Memory, OUM).
For PCRAM usually by being made of chalcogenide compound material, common chalcogenide compound is Ge2Sb2Te5, referred to as
GST.It stores information using the reversible physical state variation of material, with non-volatile, process is small, storage density
It is high, have extended cycle life, the advantages that read or write speed is fast, low in energy consumption, resisting radiation interference.International Semiconductor Industry Association thinks PCRAM
Be likely to will to replace current flash memories and as the nonvolatile memory of the following mainstream.
According to the result of study of Liu Bo, Song Zhitang et al., (CN200410067987.5 can be used for phase transition storage multistage and deposit
The phase-change material of storage), PCRAM has the ability of multistage storage.Chalcogenide compound is during raised with temperature, square resistance
It is gradually reduced, and in temperature ramp de, two more apparent resistance steps occurs.The two steps are corresponding respectively
Transformation of the material from amorphous state to the transformation of FCC crystalline state and FCC crystalline structures to HCP crystalline structures.Therefore PCRAM has three
A relatively stable resistance state.
Operation is written and read to PCRAM generally by pulse current is applied to storage unit at present.Wherein, write operation
Electric current it is larger, will produce larger Joule heat in this process.If write operation frequently occurs, not only will produce larger
Power consumption, simultaneously because thermal accumlation is serious, it is also possible to the data stability of neighbouring storage unit can be adversely affected.
It is therefore desirable to study a kind of low power consumption read-write method and system of the phase transition storage based on multistage storage, to reduce PCRAM
Read-write power consumption, optimize its performance.
Invention content
For the disadvantages described above or Improvement requirement of the prior art, the present invention provides one kind to be deposited based on multistage storage-type phase transformation
The reading/writing method and system of reservoir, its object is to the multistage storage capacities based on phase-change memory cell, are had using two more
The phase-change memory cell of grade storage capacity constitutes read-write base unit, uses the opposite resistance value of phase change cells in read-write base unit
2 bit datas for expressing storage, in the case where the density of data storage is constant, substantially reduce the execution number of write operation,
Realize the low power consumption read-write of phase transition storage.
To achieve the above object, according to one aspect of the present invention, it provides a kind of based on multistage storage-type phase change memory
The reading/writing method of device, which is characterized in that including reading method and write method, reading/writing method, which is all made of two, has multistage storage capacity
Phase-change memory cell constitute read-write base unit；Opposite resistance of the read-write base unit based on two phase-change memory cell
2 bit datas of value expression storage, realize store function；The opposite resistance value of described two phase-change memory cells refers to two phase transformations
The difference of the stable state resistance value of storage unit；The stable state resistance measurement of one phase-change memory cell is three or three or more；
The reading method reads data for realizing from read-write base unit, and the write method is for realizing basic to read-write
Data are written in unit.
Preferably, the reading method includes the following steps：
D1. a phase-change memory cell in gating read-write base unit, reads its state value, i.e. first state value；
D2. another phase-change memory cell in gating read-write base unit, reads its state value, i.e. the second state value；
D3. by the first state value and the second state value input data output circuit；
D4. data output circuit is worth to combinations of states according to the first state value and second state, according to institute
It states combinations of states and exports corresponding data, wherein data output circuit defines combinations of states and data according to the opposite resistance value
Between relationship.
It is further preferred that step D1 is specially：
Gating circuit receives external address signal, a phase-change memory cell in gating read-write base unit；Read driving
Circuit receives external reading and enables, and generates pulse current, applies to the phase-change memory cell of gating and reads to encourage；The phase change memory of gating
The state value for the phase-change memory cell that exciter response is read to gate to reading circuit, reading circuit, i.e. first state value are read in unit output；
Step D2 is specially：
Another phase-change memory cell in gating circuit gating read-write base unit；Reading the external reading of driving circuit reception makes
Can, pulse current is generated, another phase-change memory cell of gating is applied and reads excitation；Another phase-change memory cell of gating
The state value for another phase-change memory cell that exciter response is read to gate to reading circuit, reading circuit, i.e. the second state are read in output
Value.
Preferably, the write method includes the following steps：
X1. a phase-change memory cell in gating read-write base unit, reads its state value, i.e. first state value；
X2. another phase-change memory cell in gating read-write base unit, reads its state value, i.e. the second state value；
X3. enabled while input is write in the first state value, second state value, data to be written, outside to write
Operation judges circuit；
X4. write operation decision circuitry judges the type of the phase-change memory cell for needing to carry out write operation and write operation, output
Control signal；
X5. control signal control gating circuit gating needs to carry out the phase-change memory cell of write operation, and controls and write driving
Circuit writes excitation to what the phase-change memory cell applied corresponding write operation type；
X6. excitation is write in phase-change memory cell response, carries out write operation, and data are written.
It is further preferred that step X1 is specially：
Gating circuit receives address signal, a phase-change memory cell in gating read-write base unit；Read driving circuit
It is enabled to receive external reading, generates pulse current, the phase-change memory cell of gating is applied and reads to encourage；The phase-change memory cell of gating
The state value for the phase-change memory cell that exciter response is read to gate to reading circuit, reading circuit, i.e. first state value are read in output；
Step X2 is specially：
Another phase-change memory cell in gating circuit gating read-write base unit；Reading the external reading of driving circuit reception makes
Can, pulse current is generated, another phase-change memory cell of gating is applied and reads excitation；Another phase-change memory cell of gating
The state value for another phase-change memory cell that exciter response is read to gate to reading circuit, reading circuit, i.e. the second state are read in output
Value.
State value expresses stabilization resistance state and stable state resistance value residing for phase-change memory cell；Opposite resistance value refers to that two phase transformations are deposited
The resistance value difference of the stabilization resistance state of the state value expression of storage unit.
It is another aspect of this invention to provide that a kind of read-write system based on multistage storage-type phase transition storage is provided,
It is characterized in that, including gating circuit, reading driving circuit, read-write base unit, reading circuit, data output circuit, write operation judge
Circuit writes driving circuit, wherein
The gating circuit is used to receive external address signal or receives the first control that the write operation decision circuitry is sent out
Signal processed gates corresponding phase transformation in the read-write base unit according to the external address signal or the first control signal
Storage unit；
The reading driving circuit is read to enable for receiving, and is provided to the read-write base unit required when executing read operation
Reading excitation；
The read-write base unit includes two phase-change memory cells, respectively the first phase-change memory cell and the second phase transformation
Storage unit, the phase-change memory cell have multistage storage capacity, for realizing store function, receive to read to encourage to provide and read to swash
It encourages response signal or receives and write excitation execution write operation；There are three the phase-change memory cell tools or three or more are stablized resistance
State, three or three corresponding or more state value；
The reading circuit reads exciter response signal for receiving, and amplifies the signal and described by relatively being obtained with reference value
Second state value of the first state value of the first phase-change memory cell and second phase-change memory cell, and output first,
Second state value；The reference value is the reference voltage level obtained according to the stable state resistance value of phase-change memory cell；First shape
State value expresses stabilization resistance state and stable state resistance value residing for first phase-change memory cell, the second state value expression described the
Stabilization resistance state residing for two phase-change memory cells and stable state resistance value；
The data output circuit defines data and state group according to the opposite resistance value between phase-change memory cell state value
Relationship between conjunction, the opposite resistance value wherein between state value refer to the resistance value difference between state value；The data output electricity
Road is worth to combinations of states, according to institute for inputting the first state value and second state value according to the two states
It states the relationship that state group merges between the data and combinations of states that foundation defines and exports corresponding data；
The write operation decision circuitry according to the data to be written of input, the first state value, second state value,
Outside is write enabled, judges the phase-change memory cell that need to carry out write operation, output first control signal to the gating circuit；It goes forward side by side
One step judges that the write operation type that the phase-change memory cell need to carry out, output second control signal write driving circuit described in；
The first control signal, which is used to control the gating circuit gating, need to carry out the phase-change memory cell of write operation, institute
Second control signal is stated described to write driving circuit generation for controlling and write excitation；
The driving circuit of writing inputs the second control signal, and output, which is write, is activated to the first control signal control choosing
Logical phase-change memory cell.
Preferably, the phase-change storage material that the phase-change memory cell uses is the material with three or more stable resistance state
Material.
Preferably, the excitation energy of writing for writing driving circuit generation makes the phase-change memory cell be turned between each state
It changes.
Preferably, the reading circuit includes sense amplifier and comparison circuit, and the sense amplifier is described for amplifying
Exciter response signal is read, the comparison circuit is used to the amplified signal and reference value relatively obtaining the phase change memory list
The state value of member.
Above-mentioned reading/writing method and system will have the read-write that the phase-change memory cell of multistage storage capacity is constituted using two
The least unit that base unit is implemented as reading/writing method, the opposite resistance based on two phase-change memory cells in read-write base unit
2 bit datas of value expression storage, realize store function.
In general, through the invention it is contemplated above technical scheme is compared with the prior art, can obtain down and show
Beneficial effect：
1, the multistage storage capacity based on phase-change memory cell, the phase change memory list that there is multistage storage capacity using two
Member constitutes read-write base unit, and 2 bit datas of storage are expressed using the opposite resistance value of phase change cells in read-write base unit, from
And in the case where the density of data storage is constant, the execution number of write operation is substantially reduced, read-write efficiency is improved, realizes that phase transformation is deposited
The low power consumption read-write of reservoir PCRAM；
2, the power consumption that the frequent write operations of PCRAM generate is reduced, and weakens the negative effect to storage unit thus brought.
Description of the drawings
Fig. 1 is the structural schematic diagram of read-write system in present pre-ferred embodiments；
Fig. 2 is the step schematic diagram for reading method in present pre-ferred embodiments in reading/writing method；
Fig. 3 is the module connection diagram that method is read in present pre-ferred embodiments；
Fig. 4 is reading circuit schematic diagram in present pre-ferred embodiments；
Fig. 5 is the step schematic diagram of write method in reading/writing method in present pre-ferred embodiments；
Fig. 6 is the module connection diagram of write method in present pre-ferred embodiments；
Fig. 7 is the execution block diagram of write operation decision circuitry in present pre-ferred embodiments.
Specific implementation mode
In order to make the purpose , technical scheme and advantage of the present invention be clearer, with reference to the accompanying drawings and embodiments, right
The present invention is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, and
It is not used in the restriction present invention.As long as in addition, technical characteristic involved in the various embodiments of the present invention described below
It does not constitute a conflict with each other and can be combined with each other.
The present invention has invented a kind of the low power consumption read-write method and its system of the phase transition storage based on multistage storage, purpose
It is to reduce the power consumption of phase transition storage, weakens the excessively high negative influence brought of its write operation power consumption.
Below by taking the phase-change memory cell with tertiary storage ability as an example, with two phase transformations with multistage storage capacity
Storage unit is the read-write base unit that this method is implemented, and elaborates the detailed content of the present invention.There to be tertiary storage energy
The stable resistance value of three kinds of the phase-change memory cell of power is referred to as state a, state b, state c, and wherein state a resistance values are minimum, shape
State b takes second place, hereafter state c resistance value highests repeat no more.
The present invention provides a kind of embodiment of the read-write system based on multistage storage-type phase transition storage.
Refering to fig. 1, it is the structural schematic diagram of read-write system.Including gating circuit 101, read driving circuit 102, read-write substantially
Unit 103, data output circuit 109, write operation decision circuitry 110, writes driving circuit 111 at reading circuit 108, wherein
Gating circuit 101 is used to receive external address signal or receives the control that the write operation decision circuitry 110 is sent out
Signal 1, according to corresponding phase-change memory cell A in external address signal or the control gating read-write base unit 103 of signal 1
(104) or B (105).
It is enabled for receiving external reading to read driving circuit 102, and is provided to read-write base unit 103 and executes read operation when institute
The reading excitation needed.
It includes two phase-change memory cells to read and write base unit 103, and respectively phase-change memory cell A (104) and phase transformation is deposited
Storage unit B (105), phase-change memory cell have multistage storage capacity, for realizing store function, receive to read to encourage to provide and read to swash
It encourages response signal or receives and write excitation execution write operation；There are three phase-change memory cell tools or three or more stable state resistance values, right
Answer three or three or more state values.
Reading circuit 108 reads exciter response signal for receiving, and amplifies the signal and by relatively obtaining phase transformation with reference value
The state value 1 of storage unit A (104) and the state value 2 of phase-change memory cell B (105), and export the two state values；Institute
It is the reference resistance value obtained according to the state value of phase-change memory cell to state reference value；State value 1 expresses phase-change memory cell A
(104) the stabilization resistance state residing for and stable state resistance value, state value 2 express stabilization resistance state residing for phase-change memory cell B (105) and steady
State resistance value.
Reading circuit 108 includes sense amplifier 106 and comparison circuit 107, and sense amplifier 106 is rung for amplifying to read to encourage
Induction signal, comparison circuit 107 are used to relatively obtain the amplified signal and reference value the state value of phase-change memory cell.
Data output circuit 109 defines data and state according to the opposite resistance value between phase-change memory cell A, B state value
Relationship between combination, the opposite resistance value wherein between state value refer to the resistance value difference between state value；Data output circuit
109 are used for input state value 1 and state value 2, and combinations of states is worth to according to the two states, merge foundation according to the state group
Relationship between the data defined and combinations of states exports corresponding data.
Write operation decision circuitry 110 writes enabled, judgement according to the data to be written of input, state value 1, state value 2, outside
The phase-change memory cell of write operation need to be carried out, output control signal 1 arrives gating circuit 101；And further judge the phase change memory
The write operation type that unit need to carry out, output control signal 2 is to writing driving circuit 111.
Control signal 1 is used to control gating circuit 101 and gates the phase-change memory cell that need to carry out write operation, controls signal 2
The generation of driving circuit 111, which is write, for control writes excitation.
111 input control signal 2 of driving circuit is write, the phase change memory list for being activated to the control control gating of signal 1 is write in output
Member.
The present invention also provides a kind of embodiments of the reading/writing method based on multistage storage-type phase transition storage, and combine read-write
The embodiment of the above read-write system is expanded on further in method.
It is the module for reading method and step schematic diagram and its realization of phase transition storage provided by the invention refering to Fig. 2 to Fig. 3
Connection diagram, reading method include the following steps：
201：After gating circuit receives external address signal, the phase-change memory cell A in gating read-write base unit 302
303, reading driving circuit 301 receives external reading and enables, and generates pulse current, applies to it and reads excitation, passes through reading circuit 305, reading
Obtain the state value of unit A；
202：After gating circuit receives address signal, the phase-change memory cell B304 in gating read-write base unit 302 is read
Driving circuit 301 receives external reading and enables, and generates pulse current, applies reading excitation to it, by reading circuit 305, reads to obtain unit B
State value；
203：By unit A, the state value input data output circuit 308 of unit B；
204：Data output circuit 308 is worth to combinations of states according to the state of unit A, unit B, defeated according to combinations of states
Go out corresponding data.Wherein data output circuit according to the opposite resistance value between phase-change memory cell state value define data with
Relationship between combinations of states.
Wherein reading circuit 305 includes 307 two parts of sense amplifier 306 and comparison circuit.
It is reading circuit schematic diagram refering to Fig. 4.After reading excitation is applied on phase-change memory cell, generates and read exciter response, it will
It reads exciter response and inputs reading circuit, the state value of output phase-change memory cell is compared by sense amplifier and comparison circuit.It reads
The key of circuit is the comparison for having used two reference values to carry out state output：Vref1, Vref2.Electricity is used in the present embodiment
Stream reads excitation, and reading exciter response is voltage value.Different voltage values is generated in the phase-change memory cell Jing Guo different resistance values, is led to
It crosses the higher phase-change memory cell of resistance value and generates higher voltage value, the reading exciter response voltage value of state a is most in the present embodiment
Low, state b takes second place, the reading exciter response voltage value highest of state c.It is formed in the reading exciter response voltage value of state a and state b
Section in the middle part of take Vref1, take Vref2 in the middle part of the section of the readings exciter response voltage value composition of state b and state c.
When phase-change memory cell is state a, it is by SA (401-1) amplifications and relatively rear more defeated with Vref1 to read exciter response
Go out low level, read exciter response by SA (401-2) amplify and with Vref2 relatively after same output low level, patrolled by combination
After volume, signal (402) exports high level and indicates that the state value for reading phase-change memory cell is state a；When phase-change memory cell is
When state b, read exciter response by SA (401-1) amplify and with export high level after Vref1, put by SA (401-2)
It is big and with export low level after Vref2, after combinational logic, signal (403) output high level indicates that reading phase transformation deposits
The state value of storage unit is state b；When phase-change memory cell be state c when, read exciter response by SA (401-1) amplify and with
High level is exported after Vref1, by SA (401-2) amplify and with Vref2 relatively after same output high level, by combination
After logic, signal (404) exports high level and indicates that the state value for reading phase-change memory cell is state c.
Key in the module connection figure that reading method is realized is data output circuit.Data output circuit is according to phase change memory
Opposite resistance value between cell-like state value defines the relationship between data and combinations of states, the opposite resistance value wherein between state value
It refer to the resistance value difference between state value.
The present invention is based on the multistage storage capacity of phase-change memory cell, the low power consumption read-write methods of the phase transition storage of proposition
Key be using it is described read-write base unit in phase change cells opposite resistance value express data.When expressing identical data,
The execution number of write operation can be reduced, power consumption is reduced.
The phase-change memory cell materials behavior a that is selected in the present embodiment and poor two orders of magnitude of state b resistance values, state b with
Poor four orders of magnitude of state c resistance values, it is data ' 00 ' to define ' phase-change memory cell A is close with phase-change memory cell B resistance values '；
' phase-change memory cell A resistance values are higher than bis- to four orders of magnitude of phase-change memory cell B ' is data ' 01 '；' phase-change memory cell B resistances
Value is higher than bis- to four orders of magnitude of phase-change memory cell A ' it is data ' 10 '；' phase-change memory cell A and phase-change memory cell B's
The difference of resistance value is in six number magnitudes ' it is data ' 11 '.
Relationship in the present embodiment in data output circuit between data and combinations of states is as follows：
Data ' 00 ' corresponding combinations of states aa, bb, cc；
Corresponding combinations of states cb, ba of data ' 01 '；
Corresponding combinations of states bc, ab of data ' 10 '；
Corresponding combinations of states ca, ac of data ' 11 '.
The state value input data output circuit of two phase-change memory cells in base unit, the data output will be read and write
Circuit is worth to combinations of states according to the state of two phase-change memory cells, according to combinations of states, exports corresponding data.Such as
The state value a and phase-change memory cell B state value b, data output circuit for inputting phase transformation storage unit A obtain combinations of states ab,
And output data ' 10 '.
It is the write method step schematic diagram of phase transition storage provided by the invention and its module of realization refering to Fig. 5 to Fig. 6
Connection diagram, write method include the following steps：
501：After gating circuit receives address signal, the phase-change memory cell A (603) in gating read-write base unit 602,
Reading driving circuit 601 receives external reading and enables, and generates pulse current, applies to it and reads excitation, by reading circuit 605, reads single
The state value of first A；
502：Phase-change memory cell B (604) in gating circuit gating read-write base unit 602, reads driving circuit 601 and receives
Read to outside enabled, generate pulse current, apply reading excitation to it, by reading circuit 605, read unit B state value；
503：Phase-change memory cell A, the state value of phase-change memory cell B, data to be written and outside are write enabled same
When input write operation decision circuitry 608；
504：Write operation decision circuitry 608 compares phase-change memory cell A, the state value of phase-change memory cell B and to be written
Data, judge need carry out write operation phase-change memory cell and write operation type, output control signal；
505：Control signal control gating needs to carry out the phase-change memory cell of write operation, and controls and write driving circuit 609
Excitation is write to what the phase-change memory cell applied corresponding write operation type；
506：Excitation is write in phase-change memory cell response, carries out write operation, and data are written.
The reading driving electricity read in driving circuit 601, read-write base unit 602 and reading circuit 605 and Fig. 3 in wherein Fig. 6
Road 301, read-write base unit 302 and reading circuit 305 are same structure, are understood refering to fig. 1.
Key in the module connection figure that write method is realized is write operation decision circuitry.Phase transformation in read-write base unit is deposited
After the state value of storage unit A and phase-change memory cell B and data to be written input write operation decision circuitry, write operation judges electricity
Road proceeds by write operation judgement.
It is the execution block diagram of write operation decision circuitry refering to Fig. 7.The execution step of write operation decision circuitry includes：
701：Input is read and write the state value of two phase-change memory cells, data to be written in base unit and is write enabled；
702：The possible state combined situation for comparing data to be written, according to two phase change memory lists in read-write base unit
The state value of member, judges the phase-change memory cell that need to carry out write operation；
703：It is compared with the state value that need to be written, according to the state value that need to carry out write operation phase-change memory cell, into
One step judges the write operation type that corresponding unit need to carry out；
704：Output control signal 1 and control signal 2, control signal 1 input gating circuit, and gating circuit gates 702 steps
The need judged in rapid carry out the phase-change memory cell of write operation, and the control input of signal 2 writes driving circuit, writes driving circuit output pair
The phase-change memory cell for being activated to gating should be write.
Table 1 to table 4 is write operation decision circuitry when writing ' 00 ' ' 01 ' ' 10 ' ' 11 ' four kind of situation of data in the present embodiment
Specific estimate of situation.
Write operation when table 1 writes 00 data judges
Write operation when table 2 writes 01 data judges
Write operation when table 3 writes 10 data judges
Write operation when table 4 writes 11 data judges
Wherein write operation type is divided into 6 classes：1 indicates storage unit being converted to state b from state a；2 indicate that list will be stored
Member is converted to state c from state a；3 indicate storage unit being converted to state a from state b；4 indicate storage unit from state b
Be converted to state c；5 indicate storage unit being converted to state a from state c；6 indicate storage unit being converted to shape from state c
State b.
Certain location modes are combined, when carrying out operation judges according to the write method, it is understood that there may be a variety of operation sides
A kind of operating method may be selected as fixed operation at this time in order to balance the loss of each phase-change memory cell in method.Example：Write 01 number
According to when, the case where ca is combined as location mode, two kinds of operating methods may be present, a kind of to be operated to A, another kind is to B
It is operated, it is fixed in the present embodiment that A is operated in that case；The case where bb is combined as location mode,
Two kinds of operating methods may be present, it is fixed in the present embodiment that B is operated in that case in order to balance.
Corresponding write operation is carried out according to the control signal of write operation decision circuitry output, can be seen that from table 1 to table 4
Need the probability all operated to two phase-change memory cells to significantly reduce, need not carry out in most cases operation or only
Write operation need to be carried out to one in two phase-change memory cells to be successfully written two to two phase-change memory cells
Data are stored, the average time of write operation is reduced, reduces power consumption.
The present invention intends to the multistage storage capacities based on phase-change memory cell, reduce the power consumption that frequent write operation generates,
Realize the low power consumption read-write method of phase transition storage PCRAM.The phase change memory list that the present invention has multistage storage capacity with two
The read-write base unit that member is constituted, the least unit implemented as this method.Based on two phase change memories in read-write base unit
2 bit datas of the opposite resistance value expression storage of unit, realize store function.Compared to legacy memory with two storage units
Absolute resistance value express 2 bit datas scheme, the present invention in the case where the density of data storage is constant, be based on phase change memory list
The multistage storage capacity of member reduces write operation, improves read-write efficiency, is effectively improved the larger problem of PCRAM power consumptions.
As it will be easily appreciated by one skilled in the art that the foregoing is merely illustrative of the preferred embodiments of the present invention, not to
The limitation present invention, all within the spirits and principles of the present invention made by all any modification, equivalent and improvement etc., should all include
Within protection scope of the present invention.
Claims (9)
1. a kind of reading/writing method based on multistage storage-type phase transition storage, which is characterized in that including reading method and write method, read
Write method is all made of two, and there is the phase-change memory cell of multistage storage capacity to constitute read-write base unit；The read-write is substantially single
2 bit datas of opposite resistance value expression storage of the position based on two phase-change memory cell, realize store function；Described two phases
The opposite resistance value for becoming storage unit refers to the difference of the stable state resistance value of two phase-change memory cells；One phase-change memory cell it is steady
State resistance measurement is three or three or more；
The reading method for realizing from read-write base unit read data, the write method for realizing to read-write base unit
Data are written.
2. a kind of reading/writing method based on multistage storage-type phase transition storage as described in claim 1, which is characterized in that described
Reading method includes the following steps：
D1. a phase-change memory cell in gating read-write base unit, reads its state value, i.e. first state value；
D2. another phase-change memory cell in gating read-write base unit, reads its state value, i.e. the second state value；
D3. by the first state value and the second state value input data output circuit；
D4. data output circuit is worth to combinations of states according to the first state value and second state, according to the shape
State combination exports corresponding data, and wherein data output circuit is defined according to the opposite resistance value between combinations of states and data
Relationship.
3. a kind of reading/writing method based on multistage storage-type phase transition storage as claimed in claim 2, which is characterized in that step
D1 is specially：
Gating circuit receives external address signal, a phase-change memory cell in gating read-write base unit；Read driving circuit
It is enabled to receive external reading, generates pulse current, the phase-change memory cell of gating is applied and reads to encourage；The phase-change memory cell of gating
The state value for the phase-change memory cell that exciter response is read to gate to reading circuit, reading circuit, i.e. first state value are read in output；
Step D2 is specially：
Another phase-change memory cell in gating circuit gating read-write base unit；It is enabled to read the external reading of driving circuit reception,
Pulse current is generated, another phase-change memory cell of gating is applied and reads excitation；Another phase-change memory cell of gating is defeated
Go out to read the state value for another phase-change memory cell that exciter response is read to gate to reading circuit, reading circuit, i.e. the second state value.
4. a kind of reading/writing method based on multistage storage-type phase transition storage as described in any one of claims 1-3, feature exist
In the write method includes the following steps：
X1. a phase-change memory cell in gating read-write base unit, reads its state value, i.e. first state value；
X2. another phase-change memory cell in gating read-write base unit, reads its state value, i.e. the second state value；
X3. the first state value, second state value, data to be written, outside are write enabled while inputs write operation
Decision circuitry；
X4. write operation decision circuitry judges the type of the phase-change memory cell for needing to carry out write operation and write operation, output control
Signal；
X5. control signal control gating circuit gating needs to carry out the phase-change memory cell of write operation, and controls and write driving circuit
Excitation is write to what the phase-change memory cell applied corresponding write operation type；
X6. excitation is write in phase-change memory cell response, carries out write operation, and data are written.
5. a kind of reading/writing method based on multistage storage-type phase transition storage as claimed in claim 4, which is characterized in that step
X1 is specially：
Gating circuit receives address signal, a phase-change memory cell in gating read-write base unit；Driving circuit is read to receive
Enabled, generation pulse current is read in outside, and excitation is read to the phase-change memory cell application of gating；The phase-change memory cell of gating exports
Read the state value for the phase-change memory cell that exciter response is read to gate to reading circuit, reading circuit, i.e. first state value；
Step X2 is specially：
Another phase-change memory cell in gating circuit gating read-write base unit；It is enabled to read the external reading of driving circuit reception,
Pulse current is generated, another phase-change memory cell of gating is applied and reads excitation；Another phase-change memory cell of gating is defeated
Go out to read the state value for another phase-change memory cell that exciter response is read to gate to reading circuit, reading circuit, i.e. the second state value.
6. a kind of read-write system based on multistage storage-type phase transition storage, which is characterized in that including gating circuit, read driving electricity
Read-write base unit, reading circuit, data output circuit, write operation decision circuitry, write driving circuit in road, wherein
The gating circuit is used to receive external address signal or receives the first control letter that the write operation decision circuitry is sent out
Number, corresponding phase change memory in the read-write base unit is gated according to the external address signal or the first control signal
Unit；
The reading driving circuit is read to enable for receiving, and reading required when executing read operation is provided to the read-write base unit
Excitation；
The read-write base unit includes two phase-change memory cells, respectively the first phase-change memory cell and the second phase change memory
Unit, the phase-change memory cell have multistage storage capacity, and for realizing store function, reception, which reads to encourage to provide to read to encourage, to ring
Induction signal or reception write excitation and execute write operation；There are three the phase-change memory cell tools or three or more stable resistance states, right
Answer three or three or more state values；
The reading circuit reads exciter response signal for receiving, and amplifies the signal and by relatively obtaining described first with reference value
Second state value of the first state value of phase-change memory cell and second phase-change memory cell, and export first, second
State value；The reference value is the reference voltage level obtained according to the stable state resistance value of phase-change memory cell；The first state value
The stabilization resistance state and stable state resistance value residing for first phase-change memory cell are expressed, second state value expresses second phase
Become the stabilization resistance state and stable state resistance value residing for storage unit；
The data output circuit according to the opposite resistance value between phase-change memory cell state value define data and combinations of states it
Between relationship, the opposite resistance value wherein between state value refers to the resistance value difference between state value；The data output circuit is used
In inputting the first state value and second state value, it is worth to combinations of states according to the two states, according to the shape
State group merges exports corresponding data according to the relationship between the data and combinations of states defined；
The write operation decision circuitry is according to the data to be written of input, the first state value, second state value, outside
It writes enabled, judges the phase-change memory cell that need to carry out write operation, output first control signal to the gating circuit；And further
Judge that the write operation type that the phase-change memory cell need to carry out, output second control signal write driving circuit described in；
The first control signal, which is used to control gating circuit gating, need to carry out the phase-change memory cell of write operation, and described the
Two control signals described write driving circuit generation and write excitation for controlling；
The driving circuit of writing inputs the second control signal, and output, which is write, is activated to the first control signal control gating
Phase-change memory cell.
7. a kind of read-write system based on multistage storage-type phase transition storage as claimed in claim 6, which is characterized in that described
The phase-change storage material that phase-change memory cell uses is the material with three or more stable resistance state.
8. a kind of read-write system based on multistage storage-type phase transition storage as claimed in claims 6 or 7, which is characterized in that
The excitation energy of writing for writing driving circuit generation makes the phase-change memory cell be converted between each state.
9. a kind of read-write system based on multistage storage-type phase transition storage as claimed in claim 6, which is characterized in that described
Reading circuit includes sense amplifier and comparison circuit, and the sense amplifier is described for amplifying the reading exciter response signal
Comparison circuit is used to relatively obtain the amplified signal and reference value the state value of the phase-change memory cell.
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| CN110189785A (en) * | 2019-04-09 | 2019-08-30 | 华中科技大学 | A kind of phase transition storage read/writing control method and system based on dual threshold gate tube |
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