CN110189785B - A phase-change memory read-write control method and system based on double-threshold strobe tube - Google Patents

Abstract

The invention discloses a read-write control method and system for a phase-change memory based on a double-threshold gate tube; the read-write control method includes: (1) after a memory cell to be operated is selected, applying different (2) Obtain the data stored in the current memory cell according to the current flowing through the memory cell; (3) If the current operation is a read operation, output the data; if the current operation is a write operation, write The read data is compared with the read data, and corresponding operations are performed on the storage unit according to the comparison result. In the present invention, the dual-threshold strobe requires voltage-type excitation to turn on and conduct, and the phase-change storage medium requires current-type excitation for stable reset and set operations. In view of these two properties, the present invention proposes a phase change memory with a 1S1R structure. The operation scheme of switching different excitation sources is carried out, so as to achieve the purpose of gating, reading, programming and other operation control of the phase change memory of 1S1R structure.

Description

A phase-change memory read-write control method and system based on double-threshold strobe tube

technical field

The invention belongs to the technical field of phase-change memory, and more particularly, relates to a read-write control method and system for a phase-change memory based on a double-threshold gate tube.

Background technique

Phase change memory is a non-volatile memory based on a certain chalcogenide film. The phase change material can achieve rapid and reversible changes in amorphous and crystalline states to achieve the function of storing data. When the material is amorphous, When the material is in a crystalline state, it is in a low resistance state, indicating a data '1'.

The traditional phase change memory mostly uses 1D1R, 1T1R memory cell structure, in which the 1T1R structure is a transistor connected to the phase change memory cell. This structure is beneficial to the peripheral circuit to control the memory array, but it limits the memory array to a certain extent in terms of implementation. The 1D1R structure is a diode connected to the phase-change memory unit, which also effectively realizes the control of the memory array by the peripheral circuit, and the array area is small, but the driving capability of the diode is small, and the diode can be manufactured with a small size and can pass a large current. The process is more complicated.

There is also a phase-change memory based on a double-threshold gating device. The memory cell adopts a phase-change material as the storage medium of the memory element, and at the same time uses the double-threshold gating device as a selector for controlling the current flowing through the storage medium. The selectors are coupled to form memory cells, which are called 1S1R structures. Due to the strong driving capability of the dual-threshold gate device and the small area of the memory cell formed by this structure, it is beneficial to the three-dimensional integration of the phase change memory, so it is an ideal memory cell structure.

When writing and erasing this type of storage unit, it is necessary to control the selector to open first, and then send the excitation into the storage medium to change the state of the storage medium to operate. The turn-on and turn-off of the selector is carried out by controlling the voltage at both ends of the selector. When the voltage divider across the selector is greater than its turn-on threshold voltage, the selector is turned on, allowing current to pass through the memory cell; when the voltage divider across the selector is less than its turn-on , the selector is turned off and the current that can flow through the memory cell is almost zero. After the selector is turned on, the excitation is sent to change the state of the storage medium. The changing direction of the storage medium state is determined by the heat received and the cooling method: when performing the Set operation, relatively low heat and a slower cooling process are required; In operation, relatively high heat and a rapid cooling process are required. Experiments in the field show that due to the existence of a threshold effect in phase change materials, current-type excitation is generally used to perform Set and Reset operations in the actual process.

Since the storage unit of the 1S1R structure is a device at both ends, the gating process and the reading and writing processes all need to be performed through two ports. This requires that the selector and the storage unit must and can only be controlled at the same time when operating the storage unit, whether it is the gating process or the reading and writing process. Therefore, for this new type of memory, it is necessary to propose a new read Write scheme and read-write system to realize its read-write function.

SUMMARY OF THE INVENTION

In view of the defects of the prior art, the purpose of the present invention is to provide a phase change memory read-write control method and system based on a dual threshold gate transistor, aiming to solve the problem of using a single excitation type to operate a 1S1R structure phase change memory strip in the prior art. Complicated control and poor stability problems.

The present invention provides a phase-change memory read-write control method based on a double-threshold gate tube, comprising the following steps:

(1) After the memory cell to be operated is selected, different bias voltages are applied to both ends of the memory cell;

(2) obtain the data Data_Read stored in the current storage unit according to the magnitude of the current flowing through the storage unit;

(3) If the current operation is a read operation, output data Data_Read; if the current operation is a write operation, compare the written data Data_In with the read data Data_Read, and perform corresponding operations on the storage unit according to the comparison result .

Further, the voltage difference Vread applied to both ends of the memory cell satisfies the following conditions: Vth0>Vread>Vth1; wherein, Vth0 is the threshold voltage required to turn on the phase-change memory cell when it is in an amorphous state, and Vth1 is the phase-change memory cell. The threshold voltage required to turn on when the cell is crystalline.

Further, in step (3), if the current operation is a write operation, and the written data Data_In is equal to the read data Data_Read, no write operation is required, and the operation cycle of the unit ends.

Further, in step (3), if the current operation is a write operation, and the written data Data_In is not equal to the read data Data_Read, a programming operation is performed on the memory cell.

Further, the programming operation on the storage unit is specifically:

A gate voltage is applied to the storage unit, the gate tube is turned on, and the resistance value of the gate tube is reduced;

After the gate voltage is removed, a programming current is applied to the storage cell, the storage medium undergoes a phase change, and the resistance value of the storage medium changes;

After the programming current is removed, a bias voltage in an unselected state is applied to the memory cell, the gate tube is turned off, and the resistance value of the gate tube increases.

Furthermore, voltage-type excitation is used when gating the memory cells, and current-type excitation is used when the memory cells are gated and programmed; and the switching time between different types of excitation or the switching time between excitations of the same type and different amplitudes is less than that of double excitation. Threshold gate delay time from on to off.

The invention also provides a phase-change memory read-write control system based on a double-threshold gate tube, comprising: an operation judgment module, a pulse width control module, an excitation switch selection module, an address decoding module, a sense amplifier module, and a programming current generation module. module and voltage bias module; the first input terminal of the operation judgment module is used for receiving the write enable signal, the second input terminal of the operation judgment module is used for receiving the read enable signal, and the third input terminal of the operation judgment module is used for receiving the read enable signal. to receive input data; the operation judgment module is used to judge the type of operation to be performed currently according to the write enable signal, the read enable signal and the input data; the input end of the pulse width control module is connected to the output end of the operation judgment module , the pulse width control module is used to generate a series of pulse signals of different widths according to the type of operation to be performed; the input end of the address decoding module is used to receive the address signal, and the address decoding module is used to decode the address signal according to the The selected storage unit is determined by code operation, and the decoding result is output; the first input end of the excitation switch selection module is connected to the output end of the pulse width control module, and the second input end is connected to the output end of the address decoding module , the excitation switch selection module is used to output the WL voltage control signal, the BL voltage control signal, the Set control signal, the Reset control signal and the Read control signal according to the pulse signal and the decoding result; the input end of the sense amplifier module is connected to to the first output end of the excitation switch selection module, the sense amplifier module is used to read the stored data of the selected memory cell according to the Read control signal, and output to the memory chip; the first input end of the programming current generation module is connected to To the second output terminal of the excitation switch selection module, the second input terminal of the programming current generation module is connected to the third output terminal of the excitation switch selection module, and the programming current generation module is used for the Set control signal and the Reset control signal to the selected memory cells. The current required for operation is provided to realize the transition of the phase change storage medium to a crystalline state or an amorphous state; the first input end of the voltage bias module is connected to the fourth output end of the excitation switch selection module, and the voltage bias module is connected to the fourth output end of the voltage bias module. The second input terminal is connected to the fifth output terminal of the excitation switch selection module, and the voltage bias module is used for respectively providing different voltage biases to the selected and unselected memory cells according to the WL voltage control signal and the BL voltage control signal. set.

Further, the pulse width control module includes: a synchronization state machine for controlling the sequence and width of the pulse signal; the synchronization state machine includes: an idle state, a read operation state, a gate operation state, a SET operation state, and a RESET operation state and end states; all idle states and end states output unselected voltage bias control signals; read operating states output read pulse control signals; selected operating states output gated voltage pulse control signals; all SET operating states output SET current pulses Control signal; output RESET current pulse control signal in all RESET operation state.

Further, the excitation switch selection module includes: a logic gate unit for obtaining a corresponding control signal after performing a logic gate operation on the decoding result and the pulse control signal output by the pulse width control module.

Further, the programming current generating module includes: an operational amplifier, a resistor and a current mirror,

The operational amplifier obtains the bandgap voltage after clamping the bandgap reference voltage;

The bandgap voltage is loaded on the resistor to obtain the programming current,

The current mirror is used to output the programming current.

Furthermore, the switching time between different types of excitations or the switching time between excitations of the same type and different amplitudes is less than the delay time from turning on to turning off of the double-threshold gate tube.

In the present invention, a gate voltage is applied first, and the voltage varies according to the state of the phase-change storage medium; when the phase-change storage medium is in a crystalline state, the gate voltage is smaller; when the phase-change storage medium is in an amorphous state When the gate voltage is large, the gate voltage is switched to current excitation after the gate voltage ends, and a current signal with a suitable amplitude and pulse width is selected to perform a programming operation on the memory cell.

According to the physical characteristics of the dual-threshold strobe and the phase-change storage medium, the present invention proposes a scheme of using synchronous state machine control to switch different excitation sources in an orderly manner to meet the needs of the read-write operation of the phase-change memory of the 1S1R structure, that is, the voltage is used first. The current-type excitation source turns on the double-threshold strobe, and then uses the current-type excitation source to program the phase-change storage medium. This scheme uses voltage-type excitation to operate dual-threshold gate transistors, which is in line with the voltage-triggered characteristics of dual-threshold gate transistors; this scheme uses current-type excitation to operate phase-change memory, avoiding the threshold effect of phase-change storage media in an amorphous state , the programming result is stable and reliable; the scheme switches different excitation sources to operate, which is simpler and faster in operation than the scheme of controlling the gate voltage of the switch tube to control the excitation size alone.

Description of drawings

Fig. 1 is the realization flow chart of the phase-change memory read-write control method based on double-threshold gate tube provided by the present invention;

2 is a specific implementation flow chart of programming operations based on a dual-threshold strobe-based phase-change memory read-write control method provided by an embodiment of the present invention;

Fig. 3 is the specific realization flow chart of the phase-change memory read-write control method based on the double-threshold gate tube provided by the embodiment of the present invention;

4 is a schematic diagram of an excitation switching circuit of a single memory cell provided by an embodiment of the present invention;

Fig. 5 (a) is the excitation switching control signal timing diagram when there is no need to perform the write operation of the present invention;

Fig. 5 (b) is the excitation switching control signal timing diagram during the Set operation of the present invention;

Fig. 5 (c) is the excitation switching control signal timing chart during the Reset operation of the present invention;

FIG. 6 is a schematic diagram of the connection of each module of the read-write control system provided by the embodiment of the present invention.

Detailed ways

In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention, but not to limit the present invention.

The storage unit of 1S1R structure is formed by coupling a dual-threshold gate tube and a phase-change storage medium, and is a two-terminal device. The research results in this field show that the double-threshold gate transistor needs to be operated by voltage-type excitation to be turned on; the phase-change storage medium is suitable for reset (Reset) and set (Set) operation by current-type excitation. In view of the different operation requirements of the two materials, the present invention proposes an operation method for the entire process from read operation to gating operation, and then to write operation, and a system composed of interconnected functional modules.

As shown in FIG. 1 , the implementation process of the method for reading and writing a phase change memory based on a dual-threshold strobe provided by an embodiment of the present invention includes:

First, after the memory cell to be operated is determined by the address decoding module, different bias voltages are applied to both ends of the cell, the voltage difference between the two ends is denoted as Vread, and the length of the applied voltage pulse width is denoted as T1. Since the resistance value of the phase change storage medium is in the amorphous state and the crystalline state, the difference in resistance value is large, and the voltage division of the double-threshold gate transistor is different. Therefore, when the phase change storage medium is in the amorphous state (high resistance value), The threshold voltage required to turn on the cell is Vth0; when the phase-change storage medium is in a crystalline state (low resistance value), the required threshold voltage of the cell to turn on is Vth1. The meaning that the unit is turned on is that the double-threshold gate transistor changes from a high resistance value (non-conduction state) to a low resistance value (conduction state) under voltage excitation. The magnitudes of the above three voltage amplitudes satisfy the following inequality: Vth0>Vread>Vth1;

After the Vread voltage is applied to both ends of the cell, the sense amplifier module can judge the data stored in the current cell according to the magnitude of the current flowing through the memory cell, which is recorded as Data_Read. This step can be implemented by technical solutions commonly used in the field. The Vread voltage pulse width length T1 needs to satisfy two conditions: to enable the sense amplifier module to output data; to ensure that the storage medium does not undergo a phase change.

Then, the next operation judgment is made according to the external control signal. If the current operation is a read operation, the stored data obtained in the previous step is output, and the operation cycle of the unit ends.

If the current operation is a write operation, the next operation is controlled according to the written data Data_In. If the written data Data_In is equal to the previously read data Data_Read, no write operation is required, and the operation cycle of the unit ends. If Data_In is not equal to Data_Read, the unit is to be programmed with the following description:

After the pulse of Vread ends, another voltage pulse will be triggered to be applied to both ends of the memory cell. The voltage amplitude is recorded as Vots and the pulse width is recorded as T2. This voltage pulse is used to turn on the cell. If Data_Read=0, then Vots=Vth0; if Data_Read=1, then Vots=Vth1. The length of T2 needs to satisfy two conditions: ensuring that the storage medium does not undergo a phase change; and enabling the storage unit to be turned on.

After the Vots pulse ends, a current pulse is triggered to be applied to the memory cell, and this current pulse is used to cause a phase change in the phase-change storage medium. If Data_In=1, the current pulse amplitude is Iset, and the pulse width is marked as T3. The current pulse can make the phase-change storage medium change to a crystalline state, corresponding to data "1". If Data_In=0, the current pulse amplitude is Ireset and the pulse width is T4, and the current pulse can make the phase change storage medium into an amorphous state, corresponding to data "0".

It is worth noting that in the process of switching Vots to Iset or Ireset, the voltage difference across the device may decrease to a level smaller than the minimum sustain voltage difference Vhold that keeps the OTS turned on, which may cause the OTS to turn off. However, research in this field shows that OTS has a certain delay time from the on state to the off state. During this time, if Iset or Ireset is applied to the memory cell, the voltage across the OTS can be greater than or equal to Vhold, so that the current The pulse can smoothly pass through the storage unit to perform programming operation on the storage medium.

As shown in Figure 2, the programming operation is as follows: applying a gate voltage across the device, the resistance value of the gate tube is reduced, and the overall resistance value of the device is reduced to a level equivalent to the resistance value of the phase change storage medium; switching the excitation source , remove the strobe voltage and apply the programming current. The magnitude and pulse width of the current are determined by the type of operation. After the applied programming current ends, the phase change storage medium undergoes a phase change, and the resistance value changes. At this time, the unselected bias voltage is applied again, the resistance value of the strobe tube increases, and the overall resistance value of the device increases to a level equivalent to the resistance value of the strobe tube resistance.

The phase change memory read/write control system based on the dual threshold gate tube provided by the embodiment of the present invention includes: a voltage bias module, a programming current generation module, a sense amplifier module, an address decoding module, an operation judgment module, a pulse width control module and Activate switch selection module. The address decoding module receives the external address signal for decoding operation, and transmits the decoding result to the excitation switch selection module; the operation judgment module receives the external read and write enable signal and input data, and generates an operation type signal and transmits it to the excitation switch selection module The Read control signal generated by the excitation switch selection module is passed to the sense amplifier module, the generated Set control and Reset control signals are passed to the programming current generation module, and the generated BL voltage control and WL voltage control are passed to the voltage bias module.

The voltage bias module is used to provide voltage excitation with various amplitudes; the programming current generation module is used to provide current excitation with various amplitudes; the sense amplifier module is used to read the stored data in the memory cells; the address decoding module It is used to select the storage unit corresponding to the input address signal; the operation judgment module is used to determine the type of operation to be performed in the current operation cycle; the pulse width control module is used to generate the pulse width signal required for the corresponding operation; the excitation switch selection module is used to select Different kinds of incentives.

According to the physical characteristics of the double-threshold strobe tube and the phase-change storage medium, the invention proposes a scheme of orderly switching different excitation sources to meet the needs of the read-write operation of the phase-change memory of the 1S1R structure, and has the advantages of simplicity, speed and high stability. .

As an embodiment of the present invention, the phase-change storage medium material in the memory cell may be a chalcogenide compound with two or more stable resistance states, such as GST

As an embodiment of the present invention, the material of the dual-threshold gate transistor in the memory cell should have a larger switching ratio, such as SiTe, ZnTe.

The implementation of the technical method is further described below in conjunction with the accompanying drawings:

The present invention provides a read-write control method and system for a phase change memory based on a double-threshold strobe tube, and aims to provide a control method for strobe, reading, programming and other operations for a phase change memory device with a 1S1R structure.

The English names in the detailed description and in the drawings are common terms in the art, and have the same meanings as the English names in the previous content of the invention, with the additions that: WL is a word line; BL is a bit line.

In the embodiment of the present invention, a phase change storage medium having two stable resistance states is taken as an example.

Fig. 3 shows the realization flow chart of the read-write control method in a kind of embodiment, and the steps are as follows:

101: The memory cell is in an unselected state, and an appropriate bias voltage needs to be applied across WL and BL to ensure that the cell will not be mistakenly gated. In one embodiment, both WL and BL are connected to a bias voltage of 1.5V.

102: The storage unit is selected, and a read operation is to be performed at this time. BL is terminated with a voltage of 2.5V and WL is terminated with 0V (ground) for a duration of 100ns. In this step, the read data Data_Read can be obtained.

103: Determine whether the write enable of the current operation cycle is valid. If yes, go to step 105, if not, go to step 104.

104: Determine whether the read enable of the current operation cycle is valid. If yes, go to step 111, if no, end the current cycle.

105 : Determine whether the current input data Data_In is equal to the data Data_Read read in step 102 . If it is equal, end the current operation cycle; if not, enter step 106 .

106: Determine whether the current input data is equal to "1". If it is not equal, go to step 107, and if it is equal, go to step 108. In this embodiment, data "1" corresponds to the crystalline state of the phase change storage medium; data "0" corresponds to the amorphous state of the phase change storage medium.

107: The BL terminal is connected to 2V, and the WL terminal is connected to 0V (ground) for 10ns. This step can turn on the OTS without changing the state of the phase change storage medium.

108: The BL terminal is connected to 3V, and the WL terminal is connected to 0V (ground) for 10ns. This step can turn on the OTS without changing the state of the phase change storage medium.

109: Perform the Reset operation, input a current of 80uA to the BL terminal, and ground the WL terminal for 50ns, and then end the operation cycle. This step can make the phase change storage medium amorphous.

110: Perform the Set operation, input a current of 15uA to the BL terminal, and ground the WL terminal for 200ns, and then end the operation cycle. This step can make the phase change storage medium crystalline.

111: Output the read data Data_Read, and end this operation cycle.

The above-mentioned specific data such as voltage value, current value, duration, etc. can be adjusted accordingly according to different parameters such as material type and size.

FIG. 4 depicts a schematic diagram of the excitation switching circuit of a single memory cell in one embodiment (the excitation in the unselected state is omitted). 201 to 205 are excitation source generating modules capable of providing current-type or voltage-type excitation required for operating the memory cells. 206 is a switching device, which is in a conducting state when the control signal is valid, and can transmit excitation to the BL terminal of the storage unit 213, and five such devices are shown in FIG. 4 . 207 is a selection device that selects different excitations according to the value of the read data Data_Read, and the specific method has been described above. 208 to 212 are control signals of the switching device, which play the role of controlling excitation switching, and are usually a series of pulse signals, which are active high in this embodiment.

FIG. 5(a)(b)(c) depicts the timing relationship of the control signals 208-212 in performing different types of operations in one embodiment. The input signals in FIG. 5(a)(b)(c) can be various signals received from the outside by the memory chip, such as address signals, read and write enable signals, chip select enable signals, and data input signals.

Fig. 5(a) depicts the case where no write operation is performed during the read operation cycle, or during the write operation cycle. When the input signal changes, a pulse signal 210 is triggered to be generated for a duration of T1 , and this pulse is used to control the excitation source 203 to be applied to the BL terminal of the storage unit 213 .

Figure 5(b) describes the situation in which the Set operation needs to be performed during the write operation cycle. When the input signal changes, a read pulse signal 210 is triggered to be generated for a duration of T1 , and this pulse is used to control the excitation source 203 to be applied to the BL terminal of the memory cell 213 . After the read pulse signal 210 ends, its falling edge triggers the generation of an OTS pulse signal 211 for a duration of T2. The OTS pulse signal 211 is used to control the excitation source 204 or 205 to be applied to the BL terminal of the memory cell 213 . After the OTS pulse signal 211 ends, the falling edge of the OTS pulse signal 211 triggers the set pulse signal 208 for a duration of T3. The set pulse signal 208 is used to control the excitation source 201 to be applied to the BL terminal of the memory cell 213 .

Figure 5(c) depicts the situation in which a Reset operation needs to be performed during the write operation cycle. When the input signal changes, a read pulse signal 210 is triggered to be generated for a duration of T1 , and this pulse is used to control the excitation source 203 to be applied to the BL terminal of the memory cell 213 . After the read pulse signal 210 ends, its falling edge triggers the generation of an OTS pulse signal 211 for a duration of T2. The OTS pulse signal 211 is used to control the excitation source 204 or 205 to be applied to the BL terminal of the memory cell 213 . After the OTS pulse signal 211 ends, the falling edge of the OTS pulse signal 211 triggers the reset pulse signal 209 for a duration of T4. The reset pulse signal 209 is used to control the excitation source 202 to be applied to the BL terminal of the memory cell 213 .

FIG. 6 depicts a system block diagram for implementing the read/write control method of the present invention and lists some important signals. 409 is a memory peripheral circuit part, 408 is a memory array part, and the two are generally interconnected and coupled through WL and BL. The external input signal provides address signal, clock signal, read enable, write enable and input data. After processing in 409, it provides appropriate stimulus to 408, and finally completes data writing or obtains output data.

The operation judgment module 401 judges which of the three operations of Read, Set or Reset is currently to be executed according to the external read enable, write enable and input data, and sends the result to the pulse width control module 402 .

The pulse width control module 402 generates a series of pulse signals with different widths to the excitation switch selection module 403 according to the operation type to be performed.

At the same time, the address decoding module 404 performs a decoding operation according to the externally input address signal to determine the selected storage unit, and sends the decoding result to the excitation switch selection module 403 .

The excitation switch selection module 403 processes the input signals from 404 and 402, outputs the generated WL voltage control signal and BL voltage control signal to the voltage bias module 407, and outputs the Set control signal and the Reset control signal to the programming current generation module 406 , input the Read control signal to the sense amplifier module 405 .

The voltage bias module 407 may provide different voltage biases for the selected and unselected memory cells, respectively.

The programming current generating module 406 can provide the current required for operation to the selected memory cells, so as to realize the transition of the phase-change storage medium to a crystalline state or an amorphous state.

The sense amplifier module 405 can read the stored data of the selected memory cell and output it to the outside of the memory chip.

When working, the address decoding module and the operation judgment module first receive the external input signal of the memory chip, including address, write enable, read enable, input data, etc., and obtain the operation type signal and decoding result signal after processing. The pulse width control module controls the sequence of the entire read and write pulse signal according to the operation type signal, and outputs the pulse signal. The excitation switch selection module outputs the corresponding operation control signals on WL and BL to the voltage bias module, programming current generation module, and sense amplifier module according to the decoding result and the pulse signal, and finally obtains the corresponding voltage or current signal to the storage unit.

As an embodiment of the present invention, the operation judging module 401 is implemented by a 3-8 decoder, and decodes the input write enable, read enable and input data to obtain the operation type control signal to be executed.

The pulse width control module 402 controls the sequence and width of the pulse signals by a synchronization state machine. The state machine has six states, idle state, read operation state, gate operation state, SET operation state, RESET operation state, and end state, and each state outputs a corresponding control signal. Idle state and end state output unselected voltage bias; read operation state output read pulse control signal; gate operation state output gate voltage pulse control signal; SET operation state output SET current pulse control signal; RESET operation state output RESET current pulse control signal. The switching sequence between the states is the same as that of the flowchart in FIG. 3 .

The address decoding module 404 is implemented by a decoder, the number of input signals of the decoder is determined by the bit width of the address signal, and the output of the decoder is the WL and BL selection signals corresponding to the address signal.

The excitation switch selection module 403 is implemented by an AND or OR logic gate, and performs logical operations on the decoding result from the address decoding module 404 and the pulse signal from the pulse width control module to obtain a corresponding control signal.

The voltage bias module 407 obtains the bandgap voltage by using the clamping function of the operational amplifier, and then divides the voltage by the resistor to obtain the required voltage, and then connects to the buffer to drive the load.

The programming current generation module 406 obtains the bandgap voltage by using the clamping function of the operational amplifier, and loads it on a resistor of a certain size to obtain the required current. The current output structure is a current mirror, and the required current is obtained through the current mirror.

The core circuit of the sense amplifier module 405 is a comparator, which outputs 0 or 1 by comparing the current of the reference circuit and the storage circuit. Its essence is to judge the current resistance value of the memory. When it is less than a set resistance value, the sense amplifier Output 1, when it is greater than the same set resistance value, the sense amplifier outputs 0.

The above-mentioned embodiment only expresses an embodiment of the present invention, and its description is more specific and detailed, but it should not be construed as a limitation on the scope of the present invention. It should be pointed out that for those skilled in the art, without departing from the concept of the present invention, several adaptive deformations and improvements can be made, which all belong to the protection scope of the present invention. Therefore, the scope of protection of the present invention should be determined by the appended claims. Those skilled in the art can easily understand that the above are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present invention, etc., All should be included within the protection scope of the present invention.

Claims (8)

1. a phase-change memory read-write control method based on a double-threshold gate tube, is characterized in that, comprises the following steps: (1) After the memory cell to be operated is selected, different bias voltages are applied to both ends of the memory cell; (2) obtain the data Data_Read stored in the current storage unit according to the magnitude of the current flowing through the storage unit; (3) If the current operation is a read operation, output data Data_Read; if the current operation is a write operation, compare the written data Data_In with the read data Data_Read, and perform corresponding operations on the storage unit according to the comparison result , if the current operation is a write operation, and the written data Data_In is not equal to the read data Data_Read, then a programming operation is performed on the storage unit, and the programming operation on the storage unit is specifically: applying to the storage unit When the gate voltage is turned on, the gate tube is turned on, and the resistance value of the gate tube is reduced; after the gate voltage is removed, a programming current is applied to the storage cell, the storage medium undergoes a phase change, and the resistance value of the storage medium changes; The bias voltage in the unselected state is applied to the memory cell, the gate tube is turned off, and the resistance value of the gate tube is increased. 2. The read-write control method of a phase change memory according to claim 1, wherein the voltage difference Vread applied to both ends of the storage cell satisfies the following conditions: Vth0>Vread>Vth1; Wherein, Vth0 is a threshold voltage required to turn on the memory cell when the memory cell is in an amorphous state, and Vth1 is a threshold voltage required to turn on the memory cell when the memory cell is in a crystalline state. 3. phase change memory read-write control method as claimed in claim 1 or 2, is characterized in that, in step (3), if current operation is write operation, and when the data Data_In of writing is equal to the data Data_Read of readout , the write operation is not required, and the operation cycle of the storage unit ends. 4. The phase-change memory read-write control method as claimed in claim 1 or 2, characterized in that, voltage-type excitation is used when gating memory cells, and current-type excitation is used when gating programming memory cells; and the difference between different types of excitation The switching time between the two or the switching time between excitations of the same type and different amplitudes is less than the delay time of the double-threshold gate tube from turning on to turning off. 5. A phase-change memory read-write control system based on a double-threshold gate tube, characterized in that, comprising: an operation judgment module (401), a pulse width control module (402), an excitation switch selection module (403), an address translation module a code module (404), a sense amplifier module (405), a programming current generation module (406) and a voltage bias module (407); The first input terminal of the operation judgment module (401) is used for receiving the write enable signal, the second input terminal of the operation judgment module (401) is used for receiving the read enable signal, and the third input terminal of the operation judgment module (401) The terminal is used to receive input data; the operation judgment module (401) is used to judge the current operation type to be performed according to the write enable signal, the read enable signal and the input data; The input end of the pulse width control module (402) is connected to the output end of the operation judgment module (401), and the pulse width control module (402) is used to generate a series of pulse signals of different widths according to the type of operation to be performed; The input end of the address decoding module (404) is used to receive an address signal, and the address decoding module (404) is used to perform a decoding operation according to the address signal to determine the selected storage unit, and output the decoding result; The first input end of the excitation switch selection module (403) is connected to the output end of the pulse width control module (402), the second input end is connected to the output end of the address decoding module (404), and the excitation switch selection module (403) ) for outputting the WL voltage control signal, the BL voltage control signal, the Set control signal, the Reset control signal and the Read control signal according to the pulse signal and the decoding result; The input end of the sense amplifier module (405) is connected to the first output end of the excitation switch selection module (403), and the sense amplifier module (405) is used for reading the stored data of the selected storage unit according to the Read control signal, And output to the memory chip; The first input terminal of the programming current generation module (406) is connected to the second output terminal of the excitation switch selection module (403), and the second input terminal of the programming current generation module (406) is connected to the excitation switch selection module (403) The third output terminal of the programming current generation module (406) is used for the Set control signal and the Reset control signal to provide the current required for the operation to the selected memory cell, so as to realize the transition of the phase-change storage medium to a crystalline state or an amorphous state; The first input terminal of the voltage bias module (407) is connected to the fourth output terminal of the excitation switch selection module (403), and the second input terminal of the voltage bias module (407) is connected to the excitation switch selection module (403) The fifth output terminal of , the voltage bias module (407) is used for respectively providing different voltage biases to the selected and unselected memory cells according to the WL voltage control signal and the BL voltage control signal. 6. The phase change memory read-write control system according to claim 5, wherein the pulse width control module (402) comprises: a synchronization state machine for controlling the sequence and width of the pulse signal; The synchronization state machine includes: an idle state, a read operation state, a gate operation state, a SET operation state, a RESET operation state and an end state; The idle state and the end state output an unselected voltage bias control signal; The read operation state outputs a read pulse control signal; The gate operation state outputs a gate voltage pulse control signal; The SET operating state outputs a SET current pulse control signal; The RESET operating state outputs a RESET current pulse control signal. 7. The phase change memory read-write control system according to claim 5, wherein the excitation switch selection module (403) comprises: a logic gate unit for controlling the decoding result and the pulse width The pulse control signal output by the module is subjected to logic gate operation to obtain the corresponding control signal. 8. The phase change memory read-write control system according to any one of claims 5-7, wherein the switching time between different types of excitations or the switching time between excitations of the same type and different amplitudes is less than two Threshold gate delay time from on to off.

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