CN110189785B - Phase change memory read-write control method and system based on dual-threshold gate tube - Google Patents
Phase change memory read-write control method and system based on dual-threshold gate tube Download PDFInfo
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- CN110189785B CN110189785B CN201910282767.0A CN201910282767A CN110189785B CN 110189785 B CN110189785 B CN 110189785B CN 201910282767 A CN201910282767 A CN 201910282767A CN 110189785 B CN110189785 B CN 110189785B
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- G11C16/00—Erasable programmable read-only memories
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- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/12—Programming voltage switching circuits
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- G—PHYSICS
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- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
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- G11C16/06—Auxiliary circuits, e.g. for writing into memory
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Abstract
The invention discloses a phase change memory read-write control method and system based on a dual-threshold gate tube; the read-write control method comprises the following steps: (1) after the operated memory cell is selected, applying different bias voltages to two ends of the memory cell; (2) acquiring data stored in the current storage unit according to the current flowing through the storage unit; (3) if the current operation is a read operation, outputting data; and if the current operation is a write operation, comparing the written data with the read data, and performing corresponding operation on the storage unit according to the comparison result. According to the invention, the dual-threshold gate tube needs voltage-type excitation to be turned on, and the phase change storage medium needs current-type excitation to perform stable reset and set operations, and the invention provides an operation scheme for switching different excitation sources for the phase change memory with the 1S1R structure aiming at the two properties so as to achieve the purpose of performing operation control such as gating, reading, programming and the like on the phase change memory with the 1S1R structure.
Description
Technical Field
The invention belongs to the technical field of phase change memories, and particularly relates to a phase change memory read-write control method and system based on a dual-threshold gate tube.
Background
The phase change memory is a nonvolatile memory based on a certain chalcogenide compound film, can realize rapid and reversible change in an amorphous state and a crystalline state through a phase change material to achieve the function of storing data, and shows a high resistance state representing data '0' when the material is in the amorphous state, and shows a low resistance state representing data '1' when the material is in the crystalline state.
The traditional phase change memory mostly uses a memory cell structure of 1D1R and 1T1R, wherein the 1T1R structure is that a transistor is connected with a phase change memory cell, the structure is favorable for a peripheral circuit to control a memory array, but the scale of the memory array is limited to a certain extent in implementation; the 1D1R structure is that a diode is connected with a phase change memory cell, the control of a peripheral circuit on a memory array is effectively realized, the array area is small, the driving capability of the diode is small, and the process for manufacturing the small-size diode capable of passing large current is complex.
There is also a phase change memory based on a dual threshold gating device, in which the memory cell uses a phase change material as a storage medium of a memory element, and the dual threshold gating device is used as a selector for controlling the current flowing through the storage medium, and the storage medium is coupled with the selector to form a memory cell, which is called a 1S1R structure. The driving capability of the double-threshold gating device is strong, and meanwhile, the area of a storage unit formed by the structure is small, so that the three-dimensional integration of the phase change memory is facilitated, and the double-threshold gating device is an ideal storage unit structure.
When writing and erasing the memory unit, the selector is controlled to be started, and then excitation is sent to the storage medium to change the state of the storage medium for operation. The on and off of the selector are carried out by controlling the voltage at two ends of the selector, and when the divided voltage at two ends of the selector is greater than the threshold voltage for the on of the selector, the selector is turned on to allow the current to pass through the storage unit; when the divided voltage at the two ends of the selector is smaller than the threshold voltage for starting the selector, the selector is switched off, and the current which can flow through the storage unit is almost zero. After the selector is started, the state of the storage medium is changed by sending excitation, and the change direction of the state of the storage medium is determined by the received heat and the cooling mode: when the Set operation is carried out, relatively low heat and a slow cooling process are needed to realize; when performing Reset operation, relatively high heat and rapid cooling process are required. Experiments in the field show that, because of the threshold effect of the phase change material, current mode excitation is generally used for Set and Reset operations in practical processes.
Since the memory cell of the 1S1R structure is a two-terminal device, the gating process and the reading and writing processes are performed through two ports. This requires that the selector and the memory cell must be controlled simultaneously during the operation of the memory cell, regardless of the gating process or the read/write process, so that a new read/write scheme and a new read/write system are required to be provided for the new type of memory to achieve the read/write function.
Disclosure of Invention
Aiming at the defects of the prior art, the invention aims to provide a phase change memory read-write control method and system based on a dual-threshold gate tube, and aims to solve the problems of complex control and poor stability caused by the use of a single excitation type operation 1S1R structure phase change memory in the prior art.
The invention provides a phase change memory read-write control method based on a dual-threshold gate tube, which comprises the following steps:
(1) applying different bias voltages to two ends of the memory cell after the operated memory cell is selected;
(2) acquiring Data _ Read stored in the current storage unit according to the current flowing through the storage unit;
(3) if the current operation is a Read operation, outputting Data _ Read; and if the current operation is a write operation, comparing the written Data _ In with the Read Data _ Read, and performing corresponding operation on the storage unit according to the comparison result.
Further, a voltage difference Vread applied across the memory cell satisfies the following condition: vth0> Vread > Vth 1; wherein, Vth0 is the threshold voltage required for turning on the phase change memory cell in the amorphous state, and Vth1 is the threshold voltage required for turning on the phase change memory cell in the crystalline state.
Further, In step (3), if the current operation is a write operation and the written Data _ In is equal to the Read Data _ Read, then the write operation is not required and the operation cycle for the cell ends.
Further, In step (3), if the current operation is a write operation and the written Data _ In is not equal to the Read Data _ Read, the memory cell is programmed.
Further, the programming operation performed on the memory cell specifically includes:
applying gating voltage to the storage unit, starting a gate tube, and reducing the resistance value of the gate tube;
applying programming current to the storage unit after the gating voltage is removed, so that the storage medium is subjected to phase change, and the resistance value of the storage medium is changed;
and after the programming current is removed, applying bias voltage in an unselected state to the memory unit, closing the gate tube and increasing the resistance of the gate tube.
Furthermore, voltage-type excitation is adopted when the storage unit is gated, and current-type excitation is adopted when the storage unit is gated and programmed; and the switching time between different types of excitation or the switching time between same type of excitation with different amplitudes is less than the delay time of the dual-threshold gate tube from opening to closing.
The invention also provides a phase change memory read-write control system based on the dual-threshold gate tube, which comprises the following steps: the device comprises an operation judgment module, a pulse width control module, an excitation switch selection module, an address decoding module, a sensitive amplifier module, a programming current generation module and a voltage bias module; the first input end of the operation judgment module is used for receiving a write enable signal, the second input end of the operation judgment module is used for receiving a read enable signal, and the third input end of the operation judgment module is used for receiving input data; the operation judging module is used for judging the type of the operation to be executed currently according to the write enabling signal, the read enabling signal and the input data; the input end of the pulse width control module is connected to the output end of the operation judgment module, and the pulse width control module is used for generating a series of pulse signals with different widths according to the type of operation to be executed; the input end of the address decoding module is used for receiving an address signal, and the address decoding module is used for performing decoding operation according to the address signal to determine a selected storage unit and outputting a decoding result; the first input end of the excitation switch selection module is connected to the output end of the pulse width control module, the second input end of the excitation switch selection module is connected to the output end of the address decoding module, and the excitation switch selection module is used for outputting a WL voltage control signal, a BL voltage control signal, a Set control signal, a Reset control signal and a Read control signal according to the pulse signal and the decoding result; the input end of the sense amplifier module is connected to the first output end of the excitation switch selection module, and the sense amplifier module is used for reading the storage data of the selected storage unit according to the Read control signal and outputting the storage data to the storage chip; the first input end of the programming current generation module is connected to the second output end of the excitation switch selection module, the second input end of the programming current generation module is connected to the third output end of the excitation switch selection module, and the programming current generation module is used for providing current required by operation for a selected storage unit through a Set control signal and a Reset control signal to realize the conversion of the phase-change storage medium to a crystalline state or an amorphous state; the first input end of the voltage bias module is connected to the fourth output end of the excitation switch selection module, the second input end of the voltage bias module is connected to the fifth output end of the excitation switch selection module, and the voltage bias module is used for providing different voltage biases for selected and unselected memory cells respectively according to the WL voltage control signal and the BL voltage control signal.
Further, the pulse width control module includes: a synchronous state machine for controlling the sequence and width of the pulse signals; the synchronization state machine includes: an idle state, a read operation state, a strobe operation state, a SET operation state, a RESET operation state, and an end state; outputting unselected voltage bias control signals in the idle state and the ending state; outputting a read pulse control signal in the read operation state; the gated operation state outputs a gating voltage pulse control signal; the SET operation state outputs an SET current pulse control signal; the RESET operation state outputs a RESET current pulse control signal.
Still further, the activation switch selection module includes: and the logic gate unit is used for carrying out logic gate operation on the decoding result and the pulse control signal output by the pulse width control module to obtain a corresponding control signal.
Still further, the programming current generation module includes: an operational amplifier, a resistor and a current mirror,
the operational amplifier clamps the band gap reference voltage to obtain a band gap voltage;
the bandgap voltage loading on the resistor results in a programming current,
the current mirror is used for outputting the programming current.
Further, the switching time between different types of stimuli or between stimuli of the same type and different magnitudes is less than the delay time from on to off of the dual threshold gate tube.
In the invention, a gating voltage is applied firstly, and the voltage is different according to different states of the phase change storage medium; when the phase change storage medium is in a crystalline state, the gating voltage is smaller; when the phase-change storage medium is in an amorphous state, the gating voltage is larger; after the gating voltage is ended, the current excitation is switched, and a current signal with proper amplitude and pulse width is selected to carry out programming operation on the memory cell.
According to the physical characteristics of the dual-threshold gate tube and the phase-change storage medium, the invention provides a scheme of using a synchronous state machine to control and sequentially switch different excitation sources to adapt to the read-write operation requirement of the phase-change memory with the 1S1R structure, namely, firstly opening the dual-threshold gate tube by using a voltage type excitation source and then programming the phase-change storage medium by using a current type excitation source. The scheme uses voltage type excitation to operate the dual-threshold gate tube, and conforms to the voltage triggering characteristics of the dual-threshold gate tube; the scheme uses current-mode excitation to operate the phase change memory, so that the threshold effect of the phase change memory medium in an amorphous state is avoided, and the programming result is stable and reliable; the scheme switches different excitation sources to operate, and is simpler and quicker in operation than the scheme of independently controlling the grid voltage of the switching tube to control the excitation size.
Drawings
FIG. 1 is a flowchart illustrating a method for controlling read/write operations of a phase change memory based on a dual-threshold gate tube according to an embodiment of the present invention;
fig. 2 is a flowchart illustrating a specific implementation of programming operations in a phase change memory read/write control method based on a dual-threshold gate transistor according to an embodiment of the present invention;
fig. 3 is a flowchart illustrating a specific implementation of a phase change memory read/write control method based on a dual-threshold gate tube according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a stimulus switching circuit for a single memory cell provided by an embodiment of the present invention;
FIG. 5(a) is a timing diagram of the control signals for switching the activation when the write operation is not required according to the present invention;
FIG. 5(b) is a timing diagram of the activation switching control signal during the Set operation of the present invention;
FIG. 5(c) is a timing diagram of the activation switching control signal during Reset operation according to the present invention;
fig. 6 is a schematic diagram illustrating connection of modules of the read/write control system according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
The storage unit with the structure of 1S1R is formed by coupling a dual-threshold gate tube and a phase change storage medium, and is a two-terminal device. Research results in the field indicate that the double-threshold gate tube needs to be energized by voltage to operate conduction; the phase-change storage medium is suitable for Reset (Reset) and Set (Set) operations by current mode excitation. Aiming at different operation requirements of two materials, the invention provides an operation method of the whole process from reading operation to gating operation and then writing operation and a system formed by connecting all functional modules.
As shown in fig. 1, an implementation flow of a phase change memory read-write control method based on a dual-threshold gate tube according to an embodiment of the present invention includes:
first, after the address decoding module determines the operated memory cell, different bias voltages are applied to two ends of the cell, the voltage difference between the two ends is denoted as Vread, and the pulse width length of the applied voltage is denoted as T1. Since the phase change memory medium has a large difference between the resistance values in the amorphous state and the crystalline state, and the voltage division conditions for the dual-threshold gate tubes are different, it is noted that when the phase change memory medium is in the amorphous state (high resistance value), the threshold voltage required for cell turn-on is Vth 0; when the phase change memory medium is crystalline (low resistance), the required threshold voltage for the cell to turn on is Vth 1. The unit is turned on, meaning that the dual threshold gate changes from a high resistance (non-conducting state) to a low resistance (conducting state) under voltage excitation. The magnitudes of the three voltage amplitudes satisfy the following inequalities: vth0> Vread > Vth 1;
after Vread voltage is applied to the two ends of the cell, the sense amplifier module can judge the Data stored in the current cell according to the value of the current flowing through the memory cell, and the Data is recorded as Data _ Read. This step can be carried out with the technical solutions commonly used in the art. The Vread voltage pulse width length T1 needs to satisfy two conditions: enabling the sense amplifier module to output data; the storage medium is guaranteed not to undergo phase change.
Then, the next operation judgment is made according to the external control signal. If the current operation is a read operation, the memory data obtained in the previous step is output and the operation cycle for the cell ends.
If the current operation is a write operation, the next operation is controlled according to the written Data _ In. If the written Data _ In is equal to the previously Read Data _ Read, the writing operation is not necessary, and the operation cycle for the cell ends. If Data _ In is not equal to Data _ Read, then the cell is to be programmed, as described below:
after the Vread pulse ends, another voltage pulse is triggered to be applied across the memory cell, with the voltage amplitude denoted as Vots and the pulse width denoted as T2, and the voltage pulse is used to turn on the cell. If Data _ Read is 0, Vots is Vth 0; if Data _ Read is 1, Vots is Vth 1. The length of T2 needs to satisfy two conditions: ensuring that the storage medium does not generate phase change; the memory cell can be turned on.
After the Vots pulse is completed, a current pulse is triggered and applied to the memory cell, and the current pulse is used for causing the phase change of the phase change memory medium. If Data _ In is equal to 1, the current pulse has an amplitude Iset and a pulse width T3, and the current pulse can make the phase-change storage medium become crystalline, corresponding to Data "1". If Data _ In is equal to 0, the current pulse has an amplitude of Ireset and a pulse width of T4, and the current pulse can change the phase-change storage medium into an amorphous state corresponding to Data "0".
It is worth noting that during the Vots switching to Iset or Ireset, the voltage difference across the device may drop to a level less than the minimum hold voltage difference Vhold that keeps the OTS on, possibly causing the OTS to turn off. However, research in the art indicates that there is a certain delay time from the on state to the off state of the OTS, and during this time, if Iset or Ireset is applied to the memory cell, the voltage across the OTS can be greater than or equal to Vhold, so that the current pulse can smoothly pass through the memory cell to perform a programming operation on the memory medium.
As shown in fig. 2, the programming operation specifically includes: applying gating voltage at two ends of the device, reducing the resistance value of the gate tube resistor, and reducing the overall resistance value of the device to a level equivalent to that of the phase change storage medium resistor; and switching the excitation source, removing the gating voltage and applying a programming current. The magnitude and pulse width of the current is determined by the type of operation. After the applied programming current is finished, the phase change storage medium is subjected to phase change, and the resistance value of the resistor is changed. At this time, unselected bias voltage is applied, the resistance value of the gate tube resistor is increased, and the resistance value of the whole device resistor is increased to a level equivalent to that of the gate tube resistor.
The phase change memory read-write control system based on the dual-threshold gate tube provided by the embodiment of the invention comprises: the device comprises a voltage bias module, a programming current generation module, a sensitive amplifier module, an address decoding module, an operation judgment module, a pulse width control module and an excitation switch selection module. The address decoding module receives an external address signal to perform decoding operation and transmits a decoding result to the excitation switch selection module; the operation judgment module receives external read-write enabling signals and input data, generates operation type signals and transmits the operation type signals to the excitation switch selection module; the Read control signal generated by the excitation switch selection module is transmitted to the sensitive amplifier module, the generated Set control and Reset control signals are transmitted to the programming current generation module, and the generated BL voltage control and WL voltage control are transmitted to the voltage bias module.
The voltage bias module is used for providing voltage excitation with various amplitudes; the programming current generation module is used for providing current excitation with various amplitudes; the sensitive amplifier module is used for reading the storage data in the storage unit; the address decoding module is used for selecting a storage unit corresponding to the input address signal; the operation judging module is used for determining which operation type is to be executed in the current operation period; the pulse width control module is used for generating a pulse width signal required by corresponding operation; the excitation switch selection module is used for selecting different types of excitation sources.
The invention provides a scheme for orderly switching different excitation sources according to the physical characteristics of the dual-threshold gate tube and the phase change storage medium to meet the requirement of read-write operation of the phase change memory with the 1S1R structure, and has the advantages of simplicity, rapidness and higher stability.
As one embodiment of the present invention, the phase change memory medium material in the memory cell may be a chalcogenide compound with two or more stable resistance states, such as GST
As an embodiment of the present invention, the material of the dual-threshold gate tube in the memory cell should have a large on-off ratio, such as SiTe, ZnTe.
The implementation of the technical method is further explained below with reference to the accompanying drawings:
the invention provides a phase change memory read-write control method and system based on a dual-threshold gate tube, and aims to provide control methods for operations such as gating, reading, programming and the like for a phase change memory device with a 1S1R structure.
The english designations appearing in the detailed description and in the drawings are common terms in the art, and have the same meaning as the english designations appearing in the preceding summary of the invention, supplemented by: WL is the word line; BL is a bit line.
In the embodiment of the present invention, a phase change memory medium having two stable resistance states is taken as an example.
Fig. 3 is a flowchart showing an implementation of the read/write control method in an embodiment, and includes the following steps:
101: the memory cell is in an unselected state, and appropriate bias voltage needs to be applied to the two ends of WL and BL to ensure that the cell cannot be mistakenly gated. In one embodiment, WL and BL are both biased at 1.5V.
102: the memory cell is selected, at which time a read operation is to be performed. BL is terminated by 2.5V and WL is terminated by 0V (ground) for 100 ns. This step can get the Read Data _ Read.
103: it is determined whether the write enable for the current operation cycle is valid. If yes, go to step 105, if not, go to step 104.
104: and judging whether the read enable of the current operation cycle is effective or not. If yes, go to step 111, otherwise, end the cycle.
105: it is determined whether the current input Data _ In is equal to the Data _ Read In step 102. If yes, ending the operation period; if not, step 106 is entered.
106: it is determined whether the current input data is equal to "1". If not, step 107 is entered, and if so, step 108 is entered. In this embodiment, data "1" corresponds to a crystalline state of the phase change storage medium; data "0" corresponds to the amorphous state of the phase-change storage medium.
107: BL is terminated with 2V voltage and WL is terminated with 0V (ground) for 10 ns. This step can turn the OTS on without changing the state of the phase change storage medium.
108: BL is terminated with 3V voltage and WL is terminated with 0V (ground) for 10 ns. This step can turn the OTS on without changing the state of the phase change storage medium.
109: reset operation is performed, the BL terminal inputs 80uA of current, the WL terminal is grounded for 50ns, and then the operation cycle is ended. This step may cause the phase-change storage medium to become amorphous.
110: and (4) performing Set operation, inputting 15uA current into the BL end, grounding the WL end for 200ns, and ending the operation period. This step may cause the phase change storage medium to become crystalline.
111: the Read Data _ Read is output, and the present operation cycle is ended.
The specific data of the voltage value, the current value, the duration and the like can be adjusted according to different parameters of the material type, the size and the like.
FIG. 4 depicts a schematic of a stimulus switching circuit for a single memory cell in one embodiment (stimulus in the unselected state is omitted). 201-205 are stimulus source generating modules capable of providing current mode or voltage mode stimuli required to operate the memory cells. 206 is a switching device that is turned on when the control signal is asserted and can deliver a stimulus to the BL terminal of memory cell 213, 5 such devices being shown in fig. 4. 207 is a selection device for selecting different stimuli according to the value of the Read Data _ Read, as described above. 208 to 212 are control signals for the switching devices, which function to control the switching of the excitation, typically a series of pulse signals, which are active high in this embodiment.
FIGS. 5(a) (b) (c) illustrate the timing relationships of control signals 208-212 in performing different types of operations, in one embodiment. The input signals in fig. 5(a), (b), and (c) may be various signals received from the outside of the memory chip, such as an address signal, a read/write enable signal, a chip select enable signal, and a data input signal.
Fig. 5(a) describes a case where a write operation is not performed in a read operation period, or a write operation period. When the input signal changes, it triggers generation of a pulse signal 210, of duration T1, which is used to control the application of the excitation source 203 to the BL terminal of the memory cell 213.
Fig. 5(b) describes a case where a Set operation needs to be performed in a write operation cycle. When the input signal changes, it triggers the generation of a read pulse signal 210, of duration T1, which is used to control the application of the stimulus source 203 to the BL terminal of the memory cell 213. After the read pulse signal 210 is ended, its falling edge triggers the generation of the OTS pulse signal 211, lasting T2. The OTS pulse signal 211 is used to control the application of the stimulus source 204 or 205 to the BL terminal of the memory cell 213. After the OTS pulse signal 211 ends, its falling edge triggers the set pulse signal 208 for a time duration T3. The set pulse signal 208 is used to control the stimulus source 201 applied to the BL terminal of the memory cell 213.
Fig. 5(c) describes a case where a Reset operation needs to be performed in a write operation cycle. When the input signal changes, it triggers the generation of a read pulse signal 210, of duration T1, which is used to control the application of the stimulus source 203 to the BL terminal of the memory cell 213. After the read pulse signal 210 is ended, its falling edge triggers the generation of the OTS pulse signal 211, lasting T2. The OTS pulse signal 211 is used to control the application of the stimulus source 204 or 205 to the BL terminal of the memory cell 213. After the OTS pulse signal 211 ends, its falling edge triggers the reset pulse signal 209 for a time duration T4. The reset pulse signal 209 is used to control the stimulus source 202 to be applied to the BL terminal of the memory cell 213.
FIG. 6 depicts a system block diagram of a read-write control method embodying the present invention and lists some of the important signals. 409 is a memory peripheral circuit portion and 408 is a memory array portion, both of which are typically interconnected coupled by WL, BL. The external input signal provides an address signal, a clock signal, read enable, write enable and input data, and the processing is performed in 409 to provide 408 with appropriate excitation, and finally data writing is completed or output data is obtained.
The operation determining module 401 determines which of Read, Set, or Reset operation is to be executed currently according to external Read enable, write enable, and input data, and sends the result to the pulse width control module 402.
The pulse width control module 402 generates a series of pulse signals of different widths to the actuation switch selection module 403, depending on the type of operation to be performed.
Meanwhile, the address decoding module 404 performs decoding operation according to an externally input address signal to determine a selected memory cell, and sends a decoding result to the excitation switch selection module 403.
The excitation switch selection module 403 processes the input signals from 404 and 402, and outputs the generated WL voltage control signal and BL voltage control signal to the voltage bias module 407, the Set control signal and Reset control signal to the programming current generation module 406, and the Read control signal to the sense amplifier module 405.
The voltage bias module 407 may provide different voltage biases for selected and unselected memory cells, respectively.
Program current generation module 406 may provide the current required for operation to the selected memory cell to effect the transition of the phase change memory medium to the crystalline or amorphous state.
The sense amplifier module 405 may read the memory data of the selected memory cell and output the read memory data to the outside of the memory chip.
When the memory chip works, the address decoding module and the operation judging module receive signals input from the outside of the memory chip, including address, write enable, read enable, input data and the like, and the signals are processed to obtain operation type signals and decoding result signals. The pulse width control module controls the time sequence of the whole read-write pulse signal according to the operation type signal and outputs the pulse signal. And the excitation switch selection module outputs operation control signals corresponding to WL and BL to the voltage bias module, the programming current generation module and the sensitive amplifier module according to the decoding result and the pulse signal, and finally obtains a corresponding voltage or current signal to the storage unit.
As an embodiment of the present invention, the operation determining module 401 is implemented by a 3-8 decoder, and decodes the input write enable, read enable, and input data to obtain the executed operation type control signal.
The pulse width control module 402 controls the order and width of the pulse signals by a synchronous state machine. The state machine has six states, namely an idle state, a read operation state, a strobe operation state, a SET operation state, a RESET operation state and an end state, wherein each state outputs a corresponding control signal. Outputting unselected voltage bias in an idle state and an end state; reading operation state output read pulse control signal; the gating operation state outputs a gating voltage pulse control signal; the SET operation state outputs an SET current pulse control signal; the RESET operation state outputs a RESET current pulse control signal. The switching sequence between states is consistent with the flow of fig. 3.
The address decoding module 404 is implemented by a decoder, the number of input signals of the decoder is determined by the bit width of the address signal, and the output of the decoder is the WL and BL selection signals corresponding to the address signal.
The excitation switch selection module 403 is implemented by an and/or logic gate, and performs logic operation on the decoding result from the address decoding module 404 and the pulse signal of the pulse width control module to obtain a corresponding control signal.
The voltage bias module 407 obtains a band gap voltage by using the clamping action of the operational amplifier, divides the voltage by a resistor to obtain a required voltage, and then connects to a buffer to drive a load.
The programming current generation module 406 obtains a bandgap voltage by using the clamping effect of the operational amplifier, loads the bandgap voltage on a resistor with a specific size, and obtains a required current, and the current output structure is a current mirror, and obtains the required current through the current mirror.
The sense amplifier module 405 has a core circuit of a comparator, which outputs 0 or 1 by comparing the current magnitudes of the reference circuit and the memory circuit, and is essentially to determine the current resistance of the memory, and when the current resistance is smaller than a set resistance, the sense amplifier outputs 1, and when the current resistance is larger than the set resistance, the sense amplifier outputs 0.
The above-mentioned embodiments only express one embodiment of the present invention, and the description thereof is more specific, but not to be construed as limiting the scope of the present invention. It should be noted that several adaptations and modifications may be made by those skilled in the art without departing from the spirit of the present invention, and these are within the scope of the present invention. Therefore, the protection scope of the present invention should be subject to the appended claims. It will be understood by those skilled in the art that the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the invention, and that any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (8)
1. A phase change memory read-write control method based on a dual-threshold gate tube is characterized by comprising the following steps:
(1) applying different bias voltages to two ends of the memory cell after the operated memory cell is selected;
(2) acquiring Data _ Read stored in the current storage unit according to the current flowing through the storage unit;
(3) if the current operation is a Read operation, outputting Data _ Read; if the current operation is a write operation, comparing the written Data _ In with the Read Data _ Read, and performing corresponding operation on the storage unit according to the comparison result, if the current operation is a write operation and the written Data _ In is not equal to the Read Data _ Read, performing programming operation on the storage unit, wherein the programming operation on the storage unit specifically comprises the following steps: applying gating voltage to the storage unit, starting a gate tube, and reducing the resistance value of the gate tube; applying programming current to the storage unit after the gating voltage is removed, so that the storage medium is subjected to phase change, and the resistance value of the storage medium is changed; and after the programming current is removed, applying bias voltage in an unselected state to the memory unit, closing the gate tube and increasing the resistance of the gate tube.
2. The phase-change memory read-write control method according to claim 1, wherein the voltage difference Vread applied across the memory cell satisfies the following condition: vth0> Vread > Vth 1;
where Vth0 is the threshold voltage required for the memory cell to turn on in the amorphous state, and Vth1 is the threshold voltage required for the memory cell to turn on in the crystalline state.
3. The phase-change memory Read-write control method according to claim 1 or 2, characterized In that In step (3), if the current operation is a write operation and the written Data _ In is equal to the Read Data _ Read, then the operation cycle for the memory cell is ended without performing the write operation.
4. The phase change memory read-write control method according to claim 1 or 2, characterized in that voltage-mode excitation is used when the memory cell is gated, and current-mode excitation is used when the memory cell is gated and programmed; and the switching time between different types of excitation or the switching time between same type of excitation with different amplitudes is less than the delay time of the dual-threshold gate tube from opening to closing.
5. A phase change memory read-write control system based on a dual-threshold gate tube is characterized by comprising: the device comprises an operation judgment module (401), a pulse width control module (402), an excitation switch selection module (403), an address decoding module (404), a sensitive amplifier module (405), a programming current generation module (406) and a voltage bias module (407);
a first input end of the operation judgment module (401) is used for receiving a write enable signal, a second input end of the operation judgment module (401) is used for receiving a read enable signal, and a third input end of the operation judgment module (401) is used for receiving input data; the operation judging module (401) is used for judging the type of the operation to be executed currently according to the write enabling signal, the read enabling signal and the input data;
the input end of the pulse width control module (402) is connected to the output end of the operation judgment module (401), and the pulse width control module (402) is used for generating a series of pulse signals with different widths according to the type of operation to be executed;
the input end of the address decoding module (404) is used for receiving an address signal, and the address decoding module (404) is used for performing decoding operation according to the address signal to determine a selected storage unit and outputting a decoding result;
a first input end of the excitation switch selection module (403) is connected to an output end of the pulse width control module (402), a second input end of the excitation switch selection module is connected to an output end of the address decoding module (404), and the excitation switch selection module (403) is used for outputting a WL voltage control signal, a BL voltage control signal, a Set control signal, a Reset control signal and a Read control signal according to the pulse signal and the decoding result;
the input end of the sense amplifier module (405) is connected to the first output end of the excitation switch selection module (403), and the sense amplifier module (405) is used for reading the storage data of the selected storage unit according to the Read control signal and outputting the storage data to the storage chip;
a first input end of the programming current generation module (406) is connected to a second output end of the excitation switch selection module (403), a second input end of the programming current generation module (406) is connected to a third output end of the excitation switch selection module (403), and the programming current generation module (406) is used for providing currents required by operation for the selected memory cell by a Set control signal and a Reset control signal to realize the transformation of the phase-change storage medium to a crystalline state or an amorphous state;
the first input end of the voltage bias module (407) is connected to the fourth output end of the excitation switch selection module (403), the second input end of the voltage bias module (407) is connected to the fifth output end of the excitation switch selection module (403), and the voltage bias module (407) is used for providing different voltage biases for the selected and unselected memory cells respectively according to the WL voltage control signal and the BL voltage control signal.
6. The phase change memory read-write control system of claim 5, wherein the pulse width control module (402) comprises: a synchronous state machine for controlling the sequence and width of the pulse signals;
the synchronization state machine includes: an idle state, a read operation state, a strobe operation state, a SET operation state, a RESET operation state, and an end state;
the idle state and the ending state output unselected voltage bias control signals;
the read operation state outputs a read pulse control signal;
the gating operation state outputs a gating voltage pulse control signal;
the SET operating state outputs a SET current pulse control signal;
the RESET operating state outputs a RESET current pulse control signal.
7. The phase change memory read-write control system of claim 5, wherein the activation switch selection module (403) comprises: and the logic gate unit is used for carrying out logic gate operation on the decoding result and the pulse control signal output by the pulse width control module to obtain a corresponding control signal.
8. The phase change memory read-write control system of any one of claims 5-7, wherein the switching time between different types of stimuli or different magnitudes of stimuli of the same type is less than the delay time from turn-on to turn-off of the dual threshold gate tube.
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