CN101118784A - Reset operation method of resistor stochastic memory - Google Patents
Reset operation method of resistor stochastic memory Download PDFInfo
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Abstract
The present invention belongs to the art field of microelectronics, in particular to a method for the reposition operating of a non-volatile resistive random access memory. The present invention designs a reposition programming model for the pulse margin in a stepping growth, which can greatly improve and prolong the erasing times and the service life of a resistive storage unit.
Description
Technical field
The invention belongs to microelectronics technology, be specifically related to the reset operation method of a kind of resistance random access memory (Resistive Random AccessMemory) nonvolatile memory.
Background technology
Storer occupies an important position in semi-conductor market.Because constantly popularizing of portable electric appts, the share of nonvolatile memory in whole storage market is also increasing, and wherein the share more than 90% is occupied by FLASH.But owing to crosstalk (CROSS TALK) and tunnel layer can not with technology generation develop unrestricted attenuate, with the bottleneck problem of FLASH such as embedded system is integrated development, force people to seek the more superior novel non-volatilization storer of performance.Recently resistance random access memory (Resistive Random Access Memory abbreviates resistance random access memory as) is because its high density, low cost, have very strong causing with characteristics such as technology generation developing abilities to show great attention to, and employed material has phase-change material
[1], the SrZrO that mixes
3 [2], ferroelectric material PbZrTiO
3 [3], ferromagnetic material Pr
1-xCa
xMnO
3 [4], the binary metal oxide material
[5], organic material
[6]Deng.The some of them binary metal oxide is (as the oxide of copper
[7], tungsten oxide, titanyl compound, the oxide of nickel, the oxide of aluminium etc.) because accurately control at component, and ic process compatibility and cost aspect potential advantages especially paid close attention to.
Fig. 1 is the characteristic synoptic diagram of the I-V of resistive memory cell
[7], curve 101 has represented that primary state is the IV curve of high resistant, the voltage scanning direction increases to V when voltage since 0 to forward as shown by arrows gradually
T1The time, electric current can increase rapidly suddenly, shows that memory resistor is mutated into low resistive state from high resistant, and curve 100 has represented that primary state is the state of low-resistance, gradually increases to V by 0 to negative sense when voltage
T2The time, electric current reaches maximal value, and this after-current can reduce rapidly suddenly, shows that memory resistor is mutated into high-impedance state from low-resistance.Under the electric signal effect, but device can be between high resistant and low-resistance inverse conversion, thereby reach the effect of signal storage.Usually claim from what high resistant was converted to low-resistance to be operating as set (set) operation, be converted to operating of high resistant for reset (reset) from low-resistance.
Fig. 2 is the characteristic synoptic diagram of I-V that resistive memory cell repeatedly scans programming, has described the process of three set of storage unit and reset operation among Fig. 2 typically.101a, 101b, 101c are three set operation of resistance unit, and its corresponding SET operating voltage is respectively V
T3, V
T4, V
T5100a, 100b, 100c are three reset operations of resistance unit, and its corresponding RESET operating voltage is respectively V
T6, V
T7, V
T8Wherein 101a, 101b, 101c set operation are corresponding with 100a, 100b, 100c reset operation respectively.Find in the experiment that there are drift phenomenon in SET and RESET operating voltage, promptly from Fig. 2, can find, SET operating voltage V
T3, V
T4, V
T5With RESET operating voltage V
T6, V
T7, V
T8Be distributed in a regional extent (0.1V-1V) rather than a fixing numerical point.Therefore Memister is in the process of single pulse program, be generally to adopt and apply one and be higher than the potential pulse of maximum SET operating voltage or apply a potential pulse method that is higher than maximum RESET operating voltage, Figure 2 shows that example, added SET potential pulse amplitude is greater than V
T5, RESET potential pulse amplitude is greater than V
T8, could guarantee the success of the each programming of storage unit.For the different storage unit of same storage array, owing to the factors such as deviation of technology, there is the unequal phenomenon of different units SET and RESET operating voltage equally, its solution generally also is a method of taking to maximize the programming pulse amplitude.Present resistance random memory unit mainly adopts the mode of single pulse to programme, as shown in Figure 3 [1].
In the programming process of Memister, its high-impedance state and low resistance state back and forth program cycles number of times we be defined as fatigue properties, good fatigue properties will help the serviceable life of resistance random access memory.Adopt single potential pulse reset operation, will make most reset operations of storage unit all have programming excessive (over-programming) phenomenon, the existence of this phenomenon will reduce the fatigue properties of resistive memory cell.
Summary of the invention
The invention provides a kind of reset operation method of the resistance random access memory that can improve the erasable repeatedly number of times of resistive memory cell, increase the service life.
Memister reset operation method provided by the invention specifically is to realize programming with a kind of way of a plurality of pulses that pulse height increases with step-by-step movement that provides in the reset operation process, and concrete steps are:
According to the initial storage data mode of resistance random access memory, carry out read operation, selection need be carried out the unit of reset operation;
Needs are carried out the storage unit of reset operation, apply voltage or current impulse, the elemental height of pulse is by minimal reset operating current in resistance random access memory storage unit or the array or voltage decision; The size of generally getting initial voltage is 0V～1.5V;
Described storage unit is carried out read operation, if storage unit changes high-impedance state into by original low resistive state, then reset operation success if the resistive memory cell state does not take place to change or do not reach high-impedance state, then continues to apply the reset operation pulse;
Increase certain pulse height and apply this pulse, described storage unit is carried out read operation, if storage unit changes high-impedance state into by original low resistive state, then reset operation success, if the resistive memory cell state does not take place to change or do not reach high-impedance state, then continue to apply the reset operation pulse; The amplitude of generally getting increase is 0.1V～1V;
Whether the certain pulse height of continuation increase under the reset operation case of successful, and detection pulse height exceeds the maximum impulse amplitude, if less than the maximum impulse amplitude, applies this pulse in storage unit, if greater than the maximum impulse amplitude, and then reset operation failure; The maximum impulse range value is generally got 1V～3V by maximum reset operating current in resistance random access memory storage unit or the array or voltage decision; Further described storage unit is carried out read operation, if storage unit changes high-impedance state into by original low resistive state, then reset operation success is not if high-impedance state takes place to change or do not reach in the resistive memory cell state, then repeat this step, up to the reset operation success.
Certain pulse amplitude values that described step-by-step movement increases is decided by the drift distribution situation of the resetting voltage or the electric current of resistance random access memory, and the pulse amplitude values that general each step-by-step movement increases equates, but also not and be limited to this kind situation.
Adopt described step-by-step movement increase programming pulse to resistance immediately storer carry out reset operation, can improve the erasable repeatedly number of times of resistive memory cell greatly, prolong its serviceable life.
Described Memister is to be storage medium with the metal-oxide film, and metal-oxide film can be Cu
xO (1＜x≤2) resistive memory, perhaps WO
x(1≤x≤3) resistive memory film, or NiO
x(0.66＜x≤1) resistive memory film, or TiO
2The resistive memory film.
The present invention also provides a kind of system, and the pulse producer and the resistive memory array that can provide pulse height to increase with step-by-step movement are provided, and the controller that is coupled to storage array, and the input and output of communicating by letter with described controller, and power supply; Said storer is that metal-oxide film is the resistance random access memory of storage medium.
The system that is provided can also comprise the wave point that is coupled to this processor.
Description of drawings
Fig. 1 is the characteristic synoptic diagram of the I-V of resistive memory cell.
Fig. 2 repeatedly scans the characteristic synoptic diagram of I-V of programming for resistive memory cell.
Fig. 3 is the synoptic diagram of the monopulse programmed method of resistive memory cell employing.
Fig. 4 is the embodiment of a conventional resistance random access memory.
Fig. 5 is the embodiment based on a current feedback circuit of the present invention.
The electric impulse signal characteristic of Fig. 6 for applying in the reset operation method proposed by the invention.
Fig. 7 is the embodiment of reset operation method proposed by the invention.
Fig. 8 is the part based on the system of one embodiment of the present of invention.
Embodiment
In the following detailed description that provides, provided the embodiment of a kind of resistor random-access storage array and peripheral circuit thereof.Reset operation method disclosed herein and interlock circuit can be applicable to this storage array.In addition, provide many detailed details so that thorough understanding of embodiments of the invention to be provided.Yet those skilled in the relevant art will recognize that, the present invention is under the situation of neither one or a plurality of details, and method, element, material that perhaps adopts other etc. also can be implemented.
" embodiment " that whole instructions is mentioned or " embodiment " expression combine special characteristic, structure or the characteristic described and comprise at least one embodiment of the present invention with this embodiment.Therefore, " in one embodiment " or the wording such as " in an embodiment " of each place appearance in whole instructions not necessarily refer to same embodiment entirely.And concrete characteristics, structure or characteristic can combine in an embodiment or a plurality of embodiment in any suitable manner.
Fig. 3 signal has provided the embodiment of a conventional resistance random access memory.A resistance random access memory 300 has comprised a resistive memory cell array, and in the present embodiment, these resistive memory cells are positioned at the crossover position place of word line WL and bit line BL.Though only provided a smaller array among the figure, institute of the present invention applicable scope is not limited only to the memory array of specific size.Term used herein " word line " and " bit line " also only are schematically, are not limited to the storage array of particular type.
Resistance random access memory in the present embodiment has comprised a typical resistive memory cell array 305, and the resistive memory cell in this array is arranged in the row that row that word line WL constituted and bit line BL constituted.
Resistive memory cell in the resistive memory cell array 305 visits by selecting corresponding row (or word line) and row (or bit line).Row selector 310 and column selector 315 have been realized the selection function to row and column respectively.
Under idle condition, perhaps before each read operation, row selector 310 keeps all word lines at low level state, and gating device 35b is ended, and column selector 315 cuts off all bit lines and writes being connected of driving circuit 320 and sensing circuit 325 by the logical transistor 36 of column selection simultaneously.In this manner, all resistive memory cells all can't be accessed, because all bit lines all are in floating dummy status, the voltage on the resistance memory reduces to zero.
In the process of read operation or write operation, row selector 310 can improve the voltage on the selected word line, and keeping the voltage on the selected word line not simultaneously still is zero, makes the gating device conducting on the selected row.Similarly, column selector selected bit line with write driving circuit 320 or sensing circuit 325 is communicated with,, and do not choose bit line still to remain on floating dummy status.In this manner, write driving circuit 320 or sensing circuit 325 imposes certain pulse signal to selected cell, to finish specific read/write operation.After read operation was finished, the state of selected resistive memory cell was cached to output buffer 345; Before write operation took place, logical value to be written was cached to input buffer 340.
In one embodiment, if the material of resistance memory is nonvolatile resistive material, resistance memory just can be programmed at least two kinds of store statuss by it being applied the electric signal pulse so, and the electric signal pulse can make the resistance of resistance memory change between high resistant and low-resistance two states.Should be pointed out that in another embodiment resistance memory may be programmed to two or more resistance states, should regard as among the scope of application of the present invention equally.
Can be to the programming of resistance memory by bit line, the word line of choosing being applied certain voltage or current signal is realized.In this case, the two ends of resistance memory can produce certain pressure drop, thereby form program current, change the resistance characteristic of memory device.In one embodiment, apply the voltage of 1.5V on the selected bit line, apply the voltage of 1.5V on the selected word line, will form the voltage of a 1V at the two ends of resistive memory cell, thereby, be programmed for low resistive state the resistance value set of resistance memory; Apply the voltage of 3V on the selected bit line, apply the voltage of 1.5V on the selected word line, will form the voltage of a 2V at the two ends of resistive memory cell, thereby the resistance value of resistance memory is resetted, be programmed for high-impedance state.Here " set " and " resetting " together the relation of " low-resistance " and " high resistant " be a kind of agreement of customary, those skilled in the relevant art should be appreciated that other agreement can be used equally.
Institute's canned data can obtain by the resistance value of measuring resistance memory device in the resistive memory cell.In one embodiment, can on selected bit line, apply a current signal, thereby obtain a voltage, this voltage is compared with reference source, just can obtain the resistance states of resistive memory cell at the two ends of resistive memory cell.
In one embodiment, above-mentioned read/write operation may be planned as a whole by a controller 350, and controller 350 is accepted outside read/write operation order, produces the required various signals of internal control, various piece to Memister is successively sent action command, finishes the operation of appointment.
Fig. 4 signal has provided the embodiment of a current feedback circuit 400.Current feedback circuit 400 has comprised a state machine 410 and a current source circuit 420, and state machine 410 passes through VIREF, EN1, EN2, EN3, EN4 with current source circuit 420 ... signals such as ENn communicate.
State machine 410 obtains read current configuration information and resetting current configuration information from the outside.The read current configuration information has comprised the current signal content that offers read operation; The resetting current configuration information has comprised the current signal content that offers reset operation.Because factors such as process deviation, these information may be all different on different silicon chips, that is to say, by regulating these configuration informations, current feedback circuit 400 provides special compensation can for read operation and reset operation, and then optimizes the various characteristics of Memister.In addition, state machine 410 also obtains whether will start the signal of a read operation or reset operation from the outside, and a clock signal.
The a series of EN1-ENn signal of state machine 410 outputs comes Control current source circuit 420 to produce the current signal of specific size.The value of n equals 32 in an embodiment of the present invention, and in a further embodiment, the value of n also can be different, so that different currents combination mode to be provided.
State machine 410 also can produce or export the voltage control signal VIREF of an outside, and this signal is used to control MOS transistor 40.In one embodiment, the size of voltage control signal VIREF depends on read current configuration information and resetting current configuration information, and these information are relevant with the process conditions of particular batch silicon chip.The driving force of MOS transistor 40 has determined the size of PBIAS point voltage, thus the size of the current reference source that control cascode structure 42 produces.
In one embodiment of the invention, cascode structure 42 and MOS transistor 40 constitute a reference current source, and the electric current of reference current source is mirrored onto among the cascode structure 421-42n, and wherein the value of n is 32, and is equal with the quantity of EN signal.State machine 410 can pass through or subclass in these cascode structure of EN signal activation, thereby obtains different currents combination.MOS transistor 45 and MOS transistor 46 constitute a pair of current mirror, and the total current that flows through among the cascode structure 421-42n is mirrored in the branch road at metal-oxide-semiconductor 46 places once more by VC1.In the present embodiment, the node capacitor of VC1 is C1, is mainly contributed by the drain electrode of cascode structure 421-42n, and the node capacitor of VC2 is C2, is mainly contributed by the input end capacitor of I/O module 450 and sense amplifier.Isolate C1 and C2 by current mirror, can reduce the impulse electricity time of branch road separately, produce rising edge and the more precipitous current pulse signal of negative edge.
VC2 has absorbed the current of equal that all cascode structure produce, and goes out to form a voltage at node, and this voltage is made up of resistance memory 35a and gating device 35b two parts, and its size is determined by the state of resistance memory 35a.When resistance memory 35a was in high-impedance state, the VC2 node formed a high voltage; When resistance memory 35a was in low resistance state, the VC2 node formed a low-voltage.In the present embodiment, the VC2 node is coupled to the input end of an I/O module 450 simultaneously, in order to the direct access path of outer bound pair resistive memory cell to be provided.
In one embodiment, the VC2 node is coupled to the input end of a sense amplifier 430, compares with reference source 440, and the voltage of reference source 440 is set between high-impedance state voltage and low resistive state voltage.The output of sense amplifier 430 is connected to I/O module 470, to indicate the resistance states of accessed resistive memory cell.
Fig. 5 signal has provided the electric impulse signal characteristic that applies in the reset operation method proposed by the invention.Carry out the resistive memory cell of reset operation for needs, at first apply an electric pulse 501 that amplitude is less relatively, be generally 0V～1.5V.In this case, some resistive memory cell possibly can't complete successfully reset operation, at this moment needs the state of resistive memory cell is verified, if not success of operation just need apply an electric pulse 502 that amplitude is bigger.In the process of whole reset operation, may need to apply the continuous electric pulse sequence that an amplitude ladder increases progressively, successfully resetted up to selected resistive memory cell, perhaps reach a maximum electrical pulse amplitudes 509 that may cause the unit to quicken and damage.Change the electrical pulse amplitudes that applies, only need to reduce or increase the cascode structure that activates.
The concrete operations step of above-mentioned reset algorithm is as follows:
A. according to the initial storage data mode of resistance random access memory, carry out read operation, selection need be carried out the unit of reset operation;
B. needs are carried out the storage unit of reset operation, apply the voltage or the current impulse of an elemental height, the elemental height of pulse is by minimal reset operating current in resistance random access memory storage unit or the array or voltage decision, and generally getting the initial voltage amplitude is 0V～1.5V;
C. described storage unit is carried out read operation, if storage unit changes high-impedance state into by original low resistive state, then reset operation success if the resistive memory cell state changes or do not reach high-impedance state for taking place, then continues to apply the reset operation pulse;
D. increase certain pulse height and apply this pulse, described storage unit is carried out read operation, if storage unit changes high-impedance state into by original low resistive state, then reset operation success, if the resistive memory cell state changes or do not reach high-impedance state for taking place, then continue to apply the reset operation pulse; Generally getting the pulse increasing degree is 0.1V～1V;
E. do not continue to increase certain pulse height under the reset operation case of successful, and detect pulse height and whether exceed the maximum impulse amplitude, if less than the maximum impulse amplitude, apply this pulse in storage unit, if greater than the maximum impulse amplitude, then reset operation failure; The maximum impulse range value is generally got 1V～3V by maximum reset operating current in resistance random access memory storage unit or the array or voltage decision; Further described storage unit is carried out read operation, if storage unit changes high-impedance state into by original low resistive state, then reset operation success is if high-impedance state for taking place to change or do not reach in the resistive memory cell state, then repeat this step, up to the reset operation success.
The electric impulse signal that the employing amplitude increases progressively one by one comes resistance memory is carried out reset operation, can improve the erasable repeatedly number of times of resistance memory significantly, prolongs the serviceable life of Memister.
Fig. 6 signal has provided the embodiment of reset operation method proposed by the invention.In code 605, state machine is at first obtained the primary data state, and in one embodiment, the primary data state has comprised read current configuration information and resetting current configuration information, and code 605 can be software, firmware, hardware or their combination.The primary data state can be the information that obtains from external source, also can be the appropriate value that calculates according to information specific.
610 resistance states that read selected resistive memory cell, and and then in 615 rhombuses, judge whether to impose reset pulse.
If the resistance states of resistive memory cell is consistent with expectation value, do not need to carry out any reset operation so; If the resistance states of resistive memory cell and expectation value are inconsistent, be starting point with 620 primary data so, 625 just may need to apply the reseting pulse signal that a series of amplitudes shown in Figure 5 increase progressively one by one.The required reset pulse amplitude of resistive memory cell of part may be higher than other resistive memory cells, yet they can not surpass a default maximal value.
635 rhombuses judge according to the result of 630 checkings whether the result of a preceding reset operation is successful, if operation success, then safety withdraws from, if success, then 640 continuation increase the reset pulse amplitude.
645 rhombuses judge whether the reset pulse amplitude has surpassed default maximal value, and in the present embodiment, this maximal value is defined as and may makes resistance memory damage the minimal reset pulse height of failing with follow-up set in advance.
With reference to figure 7 is an embodiment of system provided by the invention, and system 700 can comprise a controller 701, wave point 702, storer 703, input and output (I/O) device 704, power supply 705.。Should be noted that the embodiment that scope of the present invention is not limited to have any of these parts or has all these parts.
List of references
[1]Baek?I.G.，Lee?M.S.，Seo?S.，Lee?M.J.，Seo?D.H.，Suh?D.-S.，Park?J.C.，Park?S.O.，KimH.S.，Yoo?I.K.，Chung?U.-In.，Moon?J.，“Highly?scalable?nonvolatile?resistive?memoryusing?simple?binary?oxide?driven?by?asymmetric?unipolar?voltage?pulses”，IEEEInternational?Electron?Devices?Meeting，p587-590，2004
Claims (2)
1. the method for the reset operation of a resistance random access memory is characterized in that concrete steps are as follows:
(1) according to the initial storage data mode of resistance random access memory, carry out read operation, selection need be carried out the unit of reset operation;
(2) needs are carried out the storage unit of reset operation, apply voltage or current impulse, the elemental height of pulse is by minimal reset operating current in resistance random access memory storage unit or the array or voltage decision, and the initial voltage amplitude is 0V～1.5V;
(3) described storage unit is carried out read operation, if storage unit changes high-impedance state into by original low resistive state, then reset operation success if the resistive memory cell state does not take place to change or do not reach high-impedance state, then continues to apply the reset operation pulse;
(4) increase certain pulse height and apply this pulse, described storage unit is carried out read operation, if storage unit changes high-impedance state into by original low resistive state, then reset operation success, if the resistive memory cell state does not take place to change or do not reach high-impedance state, then continue to apply the reset operation pulse; Getting the pulse increasing degree is 0.1V～1V;
(5) do not continue to increase certain pulse height under the reset operation case of successful, and detect pulse height and whether exceed the maximum impulse amplitude, if less than the maximum impulse amplitude, apply this pulse in storage unit, if greater than the maximum impulse amplitude, then reset operation failure; The maximum impulse range value is got 1V～3V by maximum reset operating current in resistance random access memory storage unit or the array or voltage decision; Further described storage unit is carried out read operation, if storage unit changes high-impedance state into by original low resistive state, then reset operation success is not if high-impedance state takes place to change or do not reach in the resistive memory cell state, then repeat this step, up to the reset operation success.
2. a system comprises: the pulse producer and the resistive memory array that can provide pulse height to increase with step-by-step movement, and the controller that is coupled to storage array, and the input and output of communicating by letter with described controller, and power supply; Said storer is that metal-oxide film is the resistance random access memory of storage medium.
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