CN101923901B - Programming driving system and driving method for phase change memory - Google Patents
Programming driving system and driving method for phase change memory Download PDFInfo
- Publication number
- CN101923901B CN101923901B CN 201010172859 CN201010172859A CN101923901B CN 101923901 B CN101923901 B CN 101923901B CN 201010172859 CN201010172859 CN 201010172859 CN 201010172859 A CN201010172859 A CN 201010172859A CN 101923901 B CN101923901 B CN 101923901B
- Authority
- CN
- China
- Prior art keywords
- programming pulse
- programming
- controller
- rising edge
- mux
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Electronic Switches (AREA)
Abstract
The invention discloses a programming driving system and a driving method for a phase change memory, and the system comprises a logic control circuit and a programming pulse rising edge controller, a programming pulse hold time controller, a programming pulse falling edge controller and a programming pulse generating circuit which are respectively connected with the logic control circuit, wherein the logic control circuit is used for controlling the switching of programming pulse current among the rising edge stage, the hold stage and the falling edge stage during the programming process; the programming pulse rising edge controller is used for controlling the rising edge series and the time of the programming pulse current; the programming pulse hold time controller is used for controlling the time length of keeping the programming pulse current at the stable value; the programming pulse falling edge controller is used for controlling the falling edge series and the time of the programming pulse current; and the programming pulse generating circuit is used for generating the programming pulse current. The system and the method can carry out independent adjustment on the rising time, the hold time and the falling time of the programming pulse current.
Description
Technical field
The invention belongs to the communications electronics field, relate to a kind of phase transition storage programming drive system and driving method.
Background technology
The phase transition storage technology is to set up in the conception that the phase-change thin film that propose beginning of the seventies late 1960s can be applied to the phase change memory medium, is the memory device of a kind of low price, stable performance.
Phase transition storage is to utilize to make it become the nonvolatile memory of the character of non-crystalline state (high impedance) or crystalline state (Low ESR) by the material such as chalcogenide series is heated, generally be Joule heat and the application time that produces by by electric current, it is changed between high impedance (RESET) state and Low ESR (SET) state.
Repeatedly the writing indegree and can reach 10 of phase transition storage
12Inferior even higher, the write time needs several nanoseconds to several microseconds.As a rule, owing to being subject to manufacturing process, the impact of the different factors such as environment temperature and phase change resistor unit initial impedance, phase change resistor unit in the phase transition storage is set high resistance (RESET) operation, the current flow heats time that needs 10ns～500ns, and the phase change resistor unit in the phase transition storage is set low resistance (SET) operation, need the current flow heats time of 200ns～3000ns even wider time range.Repeatedly repeatedly read at phase transition storage, after the write operation, having element characteristic changes, the current flow heats time that needs also can change, so if use changeless programming operation time and operating current, can cause the phase transition storage can't accurately writing data.
And, because there is the OTS effect in phase change resistor, that is, voltage is added in two ends, phase change resistor unit, after voltage is higher than certain threshold value, the impedance meeting of phase change resistor unit suddenly descends, but this moment, phase change resistor did not have by actual program, if remove the voltage that is added in the phase change resistor unit, phase change resistor can come back to original resistance, when the phase change resistor unit was high-impedance state, this phenomenon was more obvious.The phase change resistor unit is carried out SET when operation, because the OTS effect, in the moment that the phase change resistor impedance reduces suddenly, have electric current and overcharge and manifest, may cause the SET operation failure.
Summary of the invention
Technical matters to be solved by this invention is: a kind of phase transition storage programming drive system is provided;
The present invention also provides a kind of phase transition storage programming driving method in addition.
For solving the problems of the technologies described above, the present invention adopts following technical scheme.
A kind of phase transition storage programming drive system comprises logic control circuit, programming pulse rising edge controller, programming pulse hold time controller, programming pulse falling edge controller, programming pulse generating circuit; Described logic control circuit week is with rising edge stage, the maintenance stage of programming pulse current in the control programming process, the switching in negative edge stage; Described programming pulse rising edge controller links to each other with described logic control circuit, in order to rising edge series and the time of controlling programming pulse current; Described programming pulse hold time controller links to each other with described logic control circuit, the time span that remains stable in order to control programming pulse current; Described programming pulse falling edge controller links to each other with described logic control circuit, in order to control programming pulse current falling edge series and time; Described programming pulse generating circuit links to each other with described logic control circuit, in order to generate programming pulse current.
As a preferred embodiment of the present invention, described programming pulse rising edge controller comprises the d type flip flop of several series connection and the MUX that links to each other with each d type flip flop respectively, and described MUX is in order to control the output of described programming pulse rising edge controller.
As another kind of preferred version of the present invention, described programming pulse hold time controller comprises frequency divider, delay control circuit; Described frequency divider comprises the d type flip flop that several link to each other; Described delay control circuit links to each other with described frequency divider, comprises the d type flip flop and several MUX that link to each other with the d type flip flop output terminal of several series connection, and described MUX is in order to control the output of described programming pulse hold time controller.
As another preferred version of the present invention, described programming pulse falling edge controller comprises the d type flip flop of several series connection and the MUX that links to each other with each d type flip flop respectively, and described MUX is in order to control the output of described programming pulse falling edge controller.
As another preferred version of the present invention, described logic control circuit comprises several MUX by the unified control of same signal, in order to control the programming pulse current rising edge stage in the programming process, maintenance stage, the switching in negative edge stage.
As another preferred version of the present invention, described programming pulse generating circuit comprises the transmission gate that several are in parallel, the control end of described transmission gate links to each other with described logic control circuit, and described logic control circuit is in order to control opening and closing order, opening time of transmission gate.
A kind of phase transition storage programming driving method may further comprise the steps:
As a preferred embodiment of the present invention, described programming pulse rising edge controller comprises the d type flip flop of several series connection and the MUX that links to each other with each d type flip flop respectively, described MUX is in order to control the output of described programming pulse rising edge controller, and described programming pulse rising edge controller increases the rising edge series of programming pulse current by the number of adjusting d type flip flop.
As another kind of preferred version of the present invention, described programming pulse falling edge controller comprises the d type flip flop of several series connection and the MUX that links to each other with each d type flip flop respectively, described MUX is in order to control the output of described programming pulse falling edge controller, and described programming pulse falling edge controller increases the falling edge series of programming pulse current by the number of adjusting d type flip flop.
As another preferred version of the present invention, described programming pulse generating circuit comprises the transmission gate that several are in parallel, the control end of described transmission gate links to each other with described logic control circuit, and described logic control circuit is in order to control opening and closing order, opening time of transmission gate.
Beneficial effect of the present invention is: the present invention can be to the rise time of programming pulse current, retention time, and fall time independently adjust, and the present invention can increase by the number of revising d type flip flop in the drive system rising edge and the falling edge series of Iprog, and the length of retention time; Can also adjust by the size of adjusting program current the size of pulse current.
Description of drawings
Fig. 1 is the first programming signal figure of the embodiment of the invention one;
Fig. 2 is the structural representation of the embodiment of the invention one described phase transition storage programming drive system;
Fig. 3 is the second programming signal figure of the embodiment of the invention one;
Fig. 4 is the third programming signal figure of the embodiment of the invention one;
Fig. 5 is the 4th kind of programming signal figure of the embodiment of the invention one;
Fig. 6 is the 5th kind of programming signal figure of the embodiment of the invention one;
Fig. 7 is the 6th kind of programming signal figure of the embodiment of the invention one;
Fig. 8 is the 7th kind of programming signal figure of the embodiment of the invention one;
Fig. 9 is the inner structure schematic diagram of programming pulse rising edge controller;
Figure 10 is the inner structure schematic diagram of programming pulse hold time controller;
Figure 11 is the inner structure schematic diagram of programming pulse falling edge controller;
Figure 12 is the inner structure schematic diagram of logic control circuit;
Figure 13 is the inner structure schematic diagram of programming pulse generating circuit;
Figure 14 is the signal timing diagram of programming pulse rising edge controller;
Figure 15 is the signal timing diagram of programming pulse hold time controller;
Figure 16 is the signal timing diagram of programming pulse falling edge controller.
The primary clustering symbol description:
200, phase transition storage programming drive system; 201, logic control circuit;
202, programming pulse rising edge controller; 203, programming pulse hold time controller;
204, programming pulse falling edge controller.
Embodiment
The invention provides a kind of phase transition storage programming drive system that the programming pulse shape is set, this system comprises logic control circuit, programming pulse rising edge controller, programming pulse hold time controller, programming pulse falling edge controller, programming pulse generating circuit.
[logic control circuit]
Described logic control circuit comprises several MUX by the unified control of same signal, in order to the switching in rising edge stage of controlling programming pulse current in the programming process, maintenance stage, negative edge stage.
[programming pulse rising edge controller]
Described programming pulse rising edge controller links to each other with described logic control circuit, in order to rising edge series and the time of controlling programming pulse current; Described programming pulse rising edge controller comprises the d type flip flop of several series connection and the MUX that links to each other with each d type flip flop respectively, and described MUX is in order to control the output of described programming pulse rising edge controller.
[programming pulse hold time controller]
Described programming pulse hold time controller links to each other with described logic control circuit, the time span that remains stable in order to control programming pulse current; Described programming pulse hold time controller comprises frequency divider, delay control circuit; Described frequency divider comprises 2 continuous d type flip flops; Described delay control circuit links to each other with described frequency divider, comprises d type flip flop and 2 MUX of 6 series connection, and 2 MUX link to each other with the output terminal of 3 d type flip flops respectively, in order to control the output of described programming pulse hold time controller.
[programming pulse falling edge controller]
Described programming pulse falling edge controller links to each other with described logic control circuit, in order to control programming pulse current falling edge series and time; Described programming pulse falling edge controller comprises the d type flip flop of several series connection and the MUX that links to each other with each d type flip flop respectively, and described MUX is in order to control the output of described programming pulse falling edge controller.
[programming pulse generating circuit]
Described programming pulse generating circuit links to each other with described logic control circuit, in order to generate programming pulse current.Described programming pulse generating circuit comprises the transmission gate of 4 parallel connections, the control end of described 4 transmission gates links to each other with the output terminal of described logic control circuit, programming pulse rising edge controller, programming pulse hold time controller, programming pulse falling edge controller respectively, in order to control opening and closing order, opening time of transmission gate.
The present invention can be to the rise time of programming pulse current, the retention time, and independently adjust fall time.Below in conjunction with accompanying drawing the specific embodiment of the present invention is described in further detail.
Embodiment one
The present embodiment provides a kind of phase transition storage programming drive system, as shown in Figure 2, this phase transition storage programming drive system 200 comprises: logic control circuit 201, programming pulse rising edge controller 202, programming pulse hold time controller 203, programming pulse falling edge controller 204, programming pulse generating circuit 205; Logic control circuit 201 is in order to the switching in rising edge stage of controlling programming pulse current in the programming process, maintenance stage, negative edge stage; Programming pulse rising edge controller 202 is used for setting and controlling the rising edge of programming pulse; Programming pulse hold time controller 203 is used for the time span (value after the programming pulse current rising edge finishes is defined as stationary value) that the control programming pulse remains stable; Programming pulse falling edge controller 204 is used for control programming pulse falling edge progression and time; Programming pulse generating circuit 205 produces programming pulse current.
Fig. 1 is a kind of programming signal figure of the present embodiment, and wherein WE is the program enable signal of phase transition storage, and high level represents program enable; In the programming cycle of a data, program current Iprog is by rising edge, and the retention time, negative edge forms, and rising time, and the retention time, the negative edge time is independent controlled, and the rising edge of Iprog and negative edge are formed by the electric current ladder; The PROG signal is an output signal of programmed circuit, and when the PROG signal was high level, the expression programmed circuit was in the programming state; When the PROG signal was low level, the expression programmed circuit was in idle state; Iprog is the program current of phase transition storage;
Fig. 9 is the inner structure schematic diagram of programming pulse rising edge controller 202, and wherein DFF is d type flip flop, and the clock signal clk rising edge triggers, and RES_ is the d type flip flop reset terminal, carries out asynchronous reset during low level; MUX is MUX, the output of REN, R2_4 control MUX MUX.
Figure 14 is the signal timing diagram of programming pulse rising edge controller 202.Originally WE is low level, and d type flip flop DFF is reset, QR1, and QR2, QR 3, and QR4 all is low level, and after WE was high level, clock CLK rising edge triggered d type flip flop DFF, QR1, QR2, QR3, the QR4 waveform is as shown in figure 14.When REN=" 1 ", during R2_4=" 1 ", QR1 is connected to RS1 through MUX, QR2 is connected to RS2 through MUX, QR3 is connected to RS3 through MUX, and QR4 is connected to RS4 through MUX, under this pattern, the rising edge of program current Iprog is made of the level Four staircase waveform, and every grade of staircase waveform time is a clock period; When REN=" 1 ", during R2_4=" 0 ", QR1 is connected to RS1 through MUX, QR2 is connected to RS1 through MUX, QR3 is connected to RS2 through MUX, and QR4 is connected to RS2 through MUX, under this pattern, the rising edge of program current Iprog is made of the two-stage staircase waveform, and every grade of staircase waveform time is a clock period; When REN=" 0 ", QR1 is connected to RS1 through MUX, and QR2 is connected to RS1 through MUX, and QR3 is connected to RS1 through MUX, and QR4 is connected to RS1 through MUX, and under this pattern, program current Iprog rising edge is steep.The concrete signal waveform as shown in figure 14.
Figure 10 is the inner structure schematic diagram of programming pulse hold time controller 203.Wherein, DFF1 to DFF8 is d type flip flop, and the clock signal clk rising edge triggers, and SET_ is the set end of d type flip flop DFF1 to DFF2, and low level is carried out asynchronous set, and RES_ is the reset terminal of d type flip flop DFF3 to DFF8, and low level is carried out asynchronous reset; MUX is MUX; AND is and door.DFF1 and DFF2 form frequency divider, and d type flip flop DFF3 to DFF8 and MUX MUX form delay control circuit.
Figure 15 is the signal timing diagram of programming pulse hold time controller 203.When the WE low level, or RS4 is when being low level, and DFF1 to DFF2 is in SM set mode, and DFF3 to DFF8 is in reset mode, and FS is low level; As WE and after being high level, the programming beginning, when programming pulse rising edge finishes, RS4 can rise to high level by low level, start the frequency divider of DFF1 to DFF2 composition and the delay circuit that DFF3 to DFF8 forms this moment, through all after dates of N clock, FS rises to high level (N=8xP3+4xP2+2xP1+P0), delay between RS4 and the FS rising edge is through the logical circuit computing of back, as the retention time of programming pulse.
Figure 11 is the inner structure schematic diagram of programming pulse falling edge controller 204, and wherein DFF is d type flip flop, and the clock signal clk rising edge triggers, and SET_ is d type flip flop set end, carries out asynchronous set during low level; MUX is MUX, FEN, the output of F2_4 control MUX MUX.
Figure 16 is the signal timing diagram of programming pulse falling edge controller 204.Originally FS is low level, and d type flip flop DFF is set, and QF1, QF2, QF3, QF4 all are high level, and after the pulse retention time finished, FS became high level, and clock CLK rising edge triggers d type flip flop DFF, QF1, and QF2, QF3, the QF4 waveform is as shown in figure 16.When FEN=" 1 ", during F2_4=" 1 ", QF1 is connected to FS1 through MUX, QF2 is connected to FS2 through MUX, QF3 is connected to FS3 through MUX, and QF4 is connected to FS4 through MUX, under this pattern, the negative edge of program current Iprog is made of the level Four staircase waveform, and every grade of staircase waveform time is a clock period; When FEN=" 1 ", during F2_4=" 0 ", QF1 is connected to FS1 through MUX, QF2 is connected to FS1 through MUX, QF3 is connected to FS2 through MUX, and QF4 is connected to FS2 through MUX, under this pattern, the negative edge of program current Iprog is made of the two-stage staircase waveform, and every grade of staircase waveform time is a clock period; When FEN=" 0 ", QF1 is connected to FS1 through MUX, and QF2 is connected to FS1 through MUX, and QF3 is connected to FS1 through MUX, and QF4 is connected to FS1 through MUX, and under this pattern, the negative edge of program current Iprog is steep.The concrete signal waveform as shown in figure 16.
Figure 12 is the inner structure schematic diagram of logic control circuit 201, and AND is and door that MUX is MUX, works as WE, S1 output FS1 when FS is high level, S2 exports FS2, and S3 exports FS3, and S4 exports FS4, otherwise S1 exports RS1, and S2 exports RS2, and S3 exports RS3, and S4 exports RS4.When FS4 is high level, and WE is when being high level, and PROG is high level, in the expression programming.
Figure 13 is the inner structure schematic diagram of programming pulse generating circuit 205.Wherein TG is transmission gate, and S1 to S4 is the control end of transmission gate TG, transmission gate conducting during high level, and Iprog1 to Iprog4 is current source, and program current is provided.Logic control circuit 201, programming pulse rising edge controller 202, programming pulse hold time controller 203 and programming pulse falling edge controller 204 are opened and are closed order by S1 to S4 signal controlling transmission gate TG's, opening time, thereby produce the rising edge of programming pulse current Iprog, retention time, and negative edge.
The present embodiment also provides a kind of phase transition storage programming driving method, and the method may further comprise the steps:
The present invention can reach by the number of revising the d type flip flop among Fig. 9 to Figure 13 rising edge and the falling edge series that increases Iprog, and the purpose of the length of retention time.Can play the effect of adjusting the pulse current size by the size of adjusting Iprog1 to Iprog4.And d type flip flop can use to descend and set out, or other triggering modes serve the same role.
Embodiment two
Pulse current rising edge part, the pulse current retaining part, the pulse current negative edge partly forms a complete program current to single phase transition storage, programmed circuit than traditional phase transition storage, the rising edge control that has added programming pulse current, and the rising time of programming pulse current, the retention time of pulse current and the negative edge of programming pulse current all can independently be controlled.Fig. 3 is the second programming signal figure of embodiment one, and under this kind programming mode, program current Iprog rising edge is staircase waveform, and negative edge is steep.
Embodiment three
Fig. 4 is the third programming signal figure of embodiment one, and under this kind programming mode, program current Iprog rising edge is steep, and negative edge is staircase waveform.
Embodiment four
Fig. 5, fourth, fifth kind of programming signal figure of the 6th, embodiment one, the rising edge of program current Iprog, negative edge can be arranged to different ladder progression and time span.
Embodiment five
Fig. 7 is the 6th kind of programming signal figure of embodiment one, under this kind programming mode, and the pulse current that programmed circuit output is traditional, rising edge and negative edge are all steep.
Embodiment six
Fig. 8 is the 7th kind of programming signal figure of embodiment two, and under this kind programming mode, the pulse retention time can be regulated length.
Here description of the invention and application is illustrative, is not to want with scope restriction of the present invention in the above-described embodiments.Here the distortion of disclosed embodiment and change is possible, and the various parts of the replacement of embodiment and equivalence are known for those those of ordinary skill in the art.Those skilled in the art are noted that in the situation that do not break away from spirit of the present invention or essential characteristic, and the present invention can be with other forms, structure, layout, ratio, and realize with other elements, material and parts.
Claims (2)
1. a phase transition storage programming drive system is characterized in that, described drive system comprises:
Logic control circuit is in order to the switching in rising edge stage of controlling programming pulse current in the programming process, maintenance stage, negative edge stage;
Programming pulse rising edge controller links to each other with described logic control circuit, in order to rising edge series and the time of controlling programming pulse current;
Programming pulse hold time controller links to each other the time span that remains stable in order to control programming pulse current with described logic control circuit;
Programming pulse falling edge controller links to each other with described logic control circuit, in order to control programming pulse current falling edge series and time;
Programming pulse generating circuit links to each other with described logic control circuit, in order to generate programming pulse current;
Described programming pulse rising edge controller comprises the d type flip flop of several series connection and the first group of MUX that links to each other with each d type flip flop respectively, and described first group of MUX is in order to control the output of described programming pulse rising edge controller;
Described programming pulse hold time controller comprises: frequency divider and delay control circuit; Described frequency divider comprises the d type flip flop that several link to each other; Described delay control circuit links to each other with described frequency divider, comprises the d type flip flop of several series connection and the second group of MUX that links to each other with the d type flip flop output terminal, and described second group of MUX is in order to control the output of described programming pulse hold time controller;
Described programming pulse falling edge controller comprises the d type flip flop of several series connection and the 3rd group of MUX that links to each other with each d type flip flop respectively, and described the 3rd group of MUX is in order to control the output of described programming pulse falling edge controller;
Described logic control circuit comprises the 4th group of MUX by the unified control of same signal, in order to control the programming pulse current rising edge stage in the programming process, maintenance stage, the switching in negative edge stage;
Described programming pulse generating circuit comprises the transmission gate that several are in parallel, and the control end of described transmission gate links to each other with described logic control circuit, and described logic control circuit is in order to control opening and closing order, opening time of transmission gate.
2. a phase transition storage programming driving method is characterized in that, said method comprising the steps of:
Step 1, rising edge series and the time of programming pulse rising edge controller control programming pulse current, the time span that programming pulse hold time controller control programming pulse current remains stable, programming pulse falling edge controller control programming pulse current falling edge series and time; Described programming pulse rising edge controller comprises the d type flip flop of several series connection and the first group of MUX that links to each other with each d type flip flop respectively, described first group of MUX is in order to control the output of described programming pulse rising edge controller, and described programming pulse rising edge controller increases the rising edge series of programming pulse current by the number of adjusting d type flip flop; Described programming pulse falling edge controller comprises the d type flip flop of several series connection and the second group of MUX that links to each other with each d type flip flop respectively, described second group of MUX is in order to control the output of described programming pulse falling edge controller, and described programming pulse falling edge controller increases the falling edge series of programming pulse current by the number of adjusting d type flip flop;
Step 2, logic control circuit receives the output signal of described programming pulse rising edge controller, programming pulse hold time controller, programming pulse falling edge controller, simultaneously according to the programming pulse current rising edge stage in the setup control programming process, the maintenance stage, the switching in negative edge stage;
Step 3, programming pulse generating circuit generates programming pulse current according to the signal of described logic control circuit output; Described programming pulse generating circuit comprises the transmission gate that several are in parallel, and the control end of described transmission gate links to each other with described logic control circuit, and described logic control circuit is in order to control opening and closing order, opening time of transmission gate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010172859 CN101923901B (en) | 2010-05-13 | 2010-05-13 | Programming driving system and driving method for phase change memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010172859 CN101923901B (en) | 2010-05-13 | 2010-05-13 | Programming driving system and driving method for phase change memory |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101923901A CN101923901A (en) | 2010-12-22 |
| CN101923901B true CN101923901B (en) | 2013-01-09 |
Family
ID=43338757
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201010172859 Active CN101923901B (en) | 2010-05-13 | 2010-05-13 | Programming driving system and driving method for phase change memory |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101923901B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102426856B (en) * | 2011-12-08 | 2016-04-13 | 上海新储集成电路有限公司 | Based on non-volatile d type flip flop circuit and the implementation method of phase-change memory cell |
| WO2015165055A1 (en) * | 2014-04-30 | 2015-11-05 | 华为技术有限公司 | Data storage method, memory controller and central processing unit |
| JP6741811B1 (en) * | 2019-03-07 | 2020-08-19 | 力晶積成電子製造股▲ふん▼有限公司Ｐｏｗｅｒｃｈｉｐ Ｓｅｍｉｃｏｎｄｕｃｔｏｒ Ｍａｎｕｆａｃｔｕｒｉｎｇ Ｃｏｒｐｏｒａｔｉｏｎ | Erase control circuit and method for nonvolatile semiconductor memory device, and nonvolatile semiconductor memory device |
| US10825373B1 (en) * | 2019-06-11 | 2020-11-03 | Synaptics Incorporated | Gate select signal with reduced interference |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101118784A (en) * | 2007-09-06 | 2008-02-06 | 复旦大学 | Reset operation method of resistor stochastic memory |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE60323202D1 (en) * | 2003-02-21 | 2008-10-09 | St Microelectronics Srl | Phase change memory device |
| KR100764738B1 (en) * | 2006-04-06 | 2007-10-09 | 삼성전자주식회사 | Phase change memory device with improved reliability, write method thereof, and system including the same |
| US8027186B2 (en) * | 2007-09-26 | 2011-09-27 | Intel Corporation | Programming a phase change memory |
-
2010
- 2010-05-13 CN CN 201010172859 patent/CN101923901B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101118784A (en) * | 2007-09-06 | 2008-02-06 | 复旦大学 | Reset operation method of resistor stochastic memory |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101923901A (en) | 2010-12-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101923901B (en) | Programming driving system and driving method for phase change memory | |
| CN102741935A (en) | Phase change memory programming method and phase change memory | |
| CN104821179B (en) | Memory body drive circuit | |
| CN105427793A (en) | Voltage control circuit and method, grid driving circuit, and display apparatus | |
| CN101340755B (en) | High-speed driving circuit of LED capable of overshooting prevention | |
| CN108832915A (en) | A kind of duty-ratio calibrating circuit | |
| CN105915210A (en) | Input/output circuit | |
| CN106416070A (en) | Wide-band duty cycle correction circuit | |
| CN102170279B (en) | The method of delay circuit and inhibit signal | |
| CN108736875A (en) | One kind trimming code value generation circuit | |
| CN1139810A (en) | Quick voltage equalizing for complementary data line after writing cycle in storage circuit | |
| CN103199864B (en) | A kind of gradual approaching A/D converter | |
| CN100547925C (en) | Reduce propagation delay and flow-route and temperature method to the buffer influence | |
| US7030663B2 (en) | Method and apparatus for generating narrow pulse width monocycles | |
| KR20160085976A (en) | Method and System for Writing of Multi level Phase Change Memory | |
| KR20120033899A (en) | Semiconductor memory apparatus | |
| CN102426856B (en) | Based on non-volatile d type flip flop circuit and the implementation method of phase-change memory cell | |
| CN101414480B (en) | Control device for phase-change memory cell and method for adding phase-change memory cell reliability | |
| CN101335045A (en) | Write circuit of phase-change memory | |
| CN103971727B (en) | Divider controls circuit | |
| CN102945683B (en) | A kind of flash operational approach of phase change memory | |
| CN107908878B (en) | Circuit model for simulating phase change memory computing unit | |
| CN102769458A (en) | Low-power-consumption drive circuit | |
| CN208723865U (en) | A kind of duty-ratio calibrating circuit | |
| CN102592671A (en) | Write circuit for phase change memories and write method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |