CN102520338B - Delay time measurement circuit, delay time determining method - Google Patents
Delay time measurement circuit, delay time determining method Download PDFInfo
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- CN102520338B CN102520338B CN201110436601.3A CN201110436601A CN102520338B CN 102520338 B CN102520338 B CN 102520338B CN 201110436601 A CN201110436601 A CN 201110436601A CN 102520338 B CN102520338 B CN 102520338B
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Abstract
A kind of delay time measurement circuit, delay time determining method.Described delay time measurement circuit is connected with circuit under test, for measuring the time delay of circuit under test, comprise: signal produces source, d type flip flop and AND circuit, wherein, signal produces the first input end of the first output terminal connection AND circuit in source, signal produces the input end of the second output terminal connection circuit under test in source, the output terminal of circuit under test connects the first input end of d type flip flop, signal produces the 3rd output terminal in source and the second input end of d type flip flop couples, and the output terminal of d type flip flop connects the second input end of AND circuit; When the output terminal of described AND circuit jumps to low level from high level, described signal generation second output terminal in source and the signal time difference of the 3rd output terminal are exactly the time delay of described circuit under test.The present invention can measure the time delay of circuit under test simply exactly.
Description
Technical field
The present invention relates to technical field of integrated circuits, particularly relate to a kind of delay time measurement circuit, delay time determining method.
Background technology
Time delay is the physical characteristics of electron device itself or wiring, and its implication is signal from electron device or wiring through the required time.Such as: in a logical circuit, its output terminal and input end are not synchronous excitation and response, start there is voltage, and output terminal may be that 100 milliseconds just had voltage to occur when input end was at zero second.Now, the time delay of this logical circuit is exactly 100 milliseconds.Therefore, in integrated circuit design, need to measure the time delay drawing each electron device, circuit or wiring etc.
Shown in figure 1, it illustrates the structural representation of a kind of delay time measurement circuit of prior art.This delay time measurement circuit comprises: the first d type flip flop 10, second d type flip flop 20, phase inverter 30 and signal produce source 40.Wherein, the first input end D connection signal of the first d type flip flop 10 produces first output terminal in source 40, to receive the first signal S1; Second input end CK connection signal of the first d type flip flop 10 produces second output terminal in source 40, to receive secondary signal S2; The output terminal Q of the first d type flip flop 10 exports the 3rd signal S3, and connects the input end of circuit under test 100.The input end connection signal of phase inverter 30 produces second output terminal in source 40, to receive secondary signal S2; The output terminal of phase inverter 30 exports the 5th signal S5, and connects the second input end CK of the second d type flip flop 20.The first input end D of the second d type flip flop 20 connects the output terminal of circuit under test 100, and the output end signal of described circuit under test 100 is the 4th signal S4, and the output signal of the output terminal Q of the second d type flip flop 20 is the 6th signal S6.Above-mentioned first trigger 10 and the second trigger 20 are all rising edge flip-flops.
In conjunction with reference to shown in figure 2, Fig. 3 and Fig. 4, to it illustrates in Fig. 1 the clock signal figure of six signals three moment.Mistiming Δ t between described 4th signal S4 and described 3rd signal S3 is exactly the time delay of circuit under test 100.
First, shown in figure 2, the first signal S1 is a first low rear high level signal; Secondary signal S2 has a wider high level after a bit of low level, and then is duration adjustable high level after experiencing one section of low level, is again finally low level; 3rd signal S3 is determined by the first signal S1 and secondary signal S2, and it is under the first signal S1 is the prerequisite of high level state, and the time trigger being upgraded to high level by low level as secondary signal S2 is high level; 4th signal S4 is the signal obtained after the 3rd signal S3 postpones the Δ t time; 5th signal S5 is contrary with the level state of secondary signal S2; 6th signal S6 is determined by the 4th signal S4 and the 5th signal S5, and it is under the 4th signal S4 is the prerequisite of high level state, and the time trigger being upgraded to high level by low level as the 5th signal S5 is high level.
Constantly reduce the duration of second high level of secondary signal S2 in Fig. 2, and the time of at every turn reducing is all very short, therefore after reducing several times, the negative edge moment of second high level of secondary signal S2 is identical with the rising edge time of the 4th signal S4.Now, shown in figure 3, first signal S1, the 3rd signal S3, the 4th signal S4 do not change, and second rising edge time of the negative edge moment of second high level of secondary signal S2, the rising edge time of the 4th signal S4, the 5th signal S5 is all identical with the rising edge time of the 6th signal S6.
If continue to reduce the duration of second high level of secondary signal S2 in Fig. 3, shown in figure 4, now, first signal S1, the 3rd signal S3, the 4th signal S4 still do not change, moment of second negative edge of secondary signal S2 is prior to the moment of the 4th signal S4 rising edge, then the moment of second rising edge of the 5th signal S5 is prior to moment of the 4th signal S4 rising edge, and therefore the 6th signal S6 is always low level.
Mistiming between the rising edge of the 3rd signal S3 and the rising edge of the 4th signal S4 is exactly the mistiming Δ t between the 3rd signal S3 and the 4th signal S4.In order to obtain mistiming Δ t, can become the moment of Fig. 4 at Fig. 3, namely the 6th signal S6 is the low level moment from high level saltus step, duration of second high level of scanning secondary signal S2, and this duration just equals time delay of circuit under test 100.
But, the circuit more complicated of transfer delay time in prior art, and the Area comparison taken is large, as: need a signal to produce source, two d type flip flops and a phase inverter.
Therefore, the time delay of how to measure electron device or wiring etc. simply just becomes those skilled in the art's problem demanding prompt solution.
Summary of the invention
The problem that the present invention solves is to provide a kind of delay time measurement circuit, delay time determining method, can measure the time delay of electron device or wiring etc. simply.
For solving the problem, the invention provides a kind of delay time measurement circuit, be connected with circuit under test, for measuring the time delay of circuit under test, comprise: signal produces source, d type flip flop and AND circuit, wherein, signal produces source and comprises three output terminals, signal produces the first input end of the first output terminal connection AND circuit in source, signal produces the input end of the second output terminal connection circuit under test in source, the output terminal of circuit under test connects the first input end of d type flip flop, signal produces the 3rd output terminal in source and the second input end of d type flip flop couples, the output terminal of d type flip flop connects the second input end of AND circuit, when the output terminal of described AND circuit jumps to low level from high level, described signal generation second output terminal in source and the signal time difference of the 3rd output terminal are exactly the time delay of described circuit under test.
Alternatively, described d type flip flop is rising edge flip-flops.
Alternatively, described delay time measurement circuit also comprises: impact damper, its input end connection signal produces the 3rd output terminal in source, and its output terminal connects the second input end of d type flip flop, and the signal that the 3rd output terminal for producing source to signal produces carries out buffered.
Alternatively, described signal is produced between second output terminal in source and the input end of circuit under test and is connected by first line, described signal produces by the second connection between first output terminal in source and the first input end of AND circuit, and resistance value or the capacitance of described first line and described second circuit are equal.
Alternatively, the material of described first line and described second circuit, length, diameter are all identical.
Alternatively, described AND circuit comprises: the first nmos pass transistor, second nmos pass transistor, 3rd nmos pass transistor, first PMOS transistor, second PMOS transistor and the 3rd PMOS transistor, wherein, the source electrode of the first PMOS transistor, the source electrode of the second PMOS transistor is connected supply voltage with the source electrode of the 3rd PMOS transistor, the grid of the first PMOS transistor and the grid connection signal of the first nmos pass transistor produce first output terminal in source, the grid of the second PMOS transistor is connected the output terminal of d type flip flop with the grid of the second nmos pass transistor, the source electrode of the second nmos pass transistor and the source ground of the 3rd nmos pass transistor, the drain electrode of the first PMOS transistor, the drain electrode of the second PMOS transistor, the drain electrode of the first nmos pass transistor, the grid of the 3rd PMOS transistor is connected with the grid of the 3rd nmos pass transistor, the source electrode of the first nmos pass transistor connects the drain electrode of the second nmos pass transistor, the drain electrode of the 3rd PMOS transistor connects the drain electrode of the 3rd nmos pass transistor, and as the output terminal of AND circuit.
Alternatively, described first PMOS transistor is identical with the second PMOS transistor, and described first nmos pass transistor is identical with the second nmos pass transistor.
For solving the problem, present invention also offers a kind of delay time determining method applying above-mentioned delay time measurement circuit, comprising:
The first input end that the first output terminal that described signal produces source is always described AND circuit provides high level signal, the input end that second output terminal in described signal generation source is circuit under test provides the first low rear high level signal comprising the first rising edge, the second input end that 3rd output terminal in described signal generation source is d type flip flop provides the first low rear high level signal comprising the second rising edge, and the moment of described second rising edge is later than the moment of described first rising edge;
Described signal produces the moment that source repeatedly adjusts described second rising edge, to shorten the mistiming between described second rising edge and described first rising edge;
When the output terminal of AND circuit jumps to low level from high level, record the mistiming between the first rising edge and the second rising edge, the described mistiming is the time delay of circuit under test.
Alternatively, described signal produces the moment that source adjusts described second rising edge equably.
Alternatively, the described signal source that produces adjusts the adjustment amount in the moment of described second rising edge at every turn and comprises: 1ns ~ 100ns.
Compared with prior art, the present invention has the following advantages:
1) the invention provides the simple delay time measurement circuit of a kind of structure, it only comprises a signal and produces source, d type flip flop and AND circuit, thus area occupied is little.
2) in possibility, signal is produced between second output terminal in source and the input end of circuit under test and is connected by first line, signal produces between first output terminal in source and the first input end of AND circuit by the second connection, equal by the resistance value or capacitance that make first line and described second circuit, thus the accuracy of measurement can be improved.
Accompanying drawing explanation
Fig. 1 is the structural representation of Time delay measurement circuit in prior art;
Fig. 2 to Fig. 4 is the clock signal figure of circuit shown in Fig. 1 three moment;
Fig. 5 is the structural representation of delay time measurement circuit in one embodiment of the invention;
Fig. 6 is the structural representation of AND circuit in Fig. 5;
Fig. 7 is the structural representation of delay time measurement circuit in another embodiment of the present invention;
Fig. 8 to Figure 10 is the clock signal figure of circuit shown in Fig. 5 three moment.
Embodiment
For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.
Set forth a lot of detail in the following description so that fully understand the present invention, but the present invention can also adopt other to be different from alternate manner described here to implement, therefore the present invention is not by the restriction of following public specific embodiment.
Just as described in the background section, the circuit more complicated of transfer delay time in prior art, area occupied are large.In addition, shown in figure 1, two d type flip flops wherein and a phase inverter all can make the signal passed through produce certain time delay, thus reduce the accuracy of delay time measurement.
For above-mentioned defect, the invention provides and a kind ofly only comprise the delay time measurement circuit that signal produces source, a d type flip flop and an AND circuit, it is compared with prior art simple, area occupied is little, and accuracy is high.
Be described in detail below in conjunction with accompanying drawing.
Shown in figure 5, one embodiment of the invention provides a kind of delay time measurement circuit, and it is connected with circuit under test 100, for measuring the time delay of circuit under test 100, comprising: signal produces source 200, d type flip flop 300 and AND circuit 400.Wherein, signal produces the first input end in1 of the first output terminal connection AND circuit 400 in source 200, signal produces the input end of the second output terminal connection circuit under test 100 in source 200, the output terminal of circuit under test 100 connects the first input end D of d type flip flop 300, signal produces the 3rd output terminal in source 200 and the second input end CK of d type flip flop 300 couples, and the output terminal Q of d type flip flop 300 connects the second input end in2 of AND circuit 400.When the output terminal of described AND circuit 400 jumps to low level from high level, described signal generation second output terminal in source 200 and the signal time difference of the 3rd output terminal are exactly the time delay of described circuit under test 100.
Wherein, described circuit under test 100 can be the device of the times that possible be delayed such as any electron device, wiring, integrated circuit.
Particularly, the first input end in1 that first output terminal in signal generation source 200 is AND circuit 400 provides the first signal A1, the second output terminal that signal produces source 200 provides secondary signal A2 for circuit under test 100, the first input end D that the output terminal of circuit under test 100 is d type flip flop 300 provides the 3rd signal A3, it is that the second input end (i.e. clock signal input terminal) CK of d type flip flop 300 provides the 4th signal A4 that signal produces the 3rd output terminal in source 200, the second input end in2 that the output terminal Q of d type flip flop 300 is AND circuit 400 provides the 5th signal A5, the output terminal of AND circuit 400 exports the 6th signal A6.
Wherein, described d type flip flop 300 is rising edge flip-flops, namely only has when the 3rd signal A3 is high level signal, and when the 4th signal A4 is in rising edge, it is high level signal that described d type flip flop 300 exports just saltus step; Otherwise d type flip flop 300 can only output low level signal.
Preferably, the second output terminal that described signal produces source 200 is connected by first line with between the input end of circuit under test 100, described signal produces between first output terminal in source 200 and the first input end in1 of AND circuit 400 by the second connection, resistance value or the capacitance of described first line and described second circuit are equal, thus can ensure that the time delay that first line produces secondary signal A2 is identical with the time delay that the second circuit produces the first signal A1, finally can improve the accuracy of measurement.Particularly, when the material of described first line and described second circuit, length, diameter homogeneous phase simultaneously, can ensure the resistance value of first line and described second circuit or capacitance equal.
Wherein, shown in figure 6, described AND circuit 400 can be CMOS and door, comprise: the first nmos pass transistor NM1, second nmos pass transistor NM2, 3rd nmos pass transistor NM3, first PMOS transistor PM1, second PMOS transistor PM2 and the 3rd PMOS transistor PM3, wherein, the source electrode of the first PMOS transistor PM1, the source electrode of the second PMOS transistor PM2 is connected supply voltage VDD with the source electrode of the 3rd PMOS transistor PM3, the grid of the first PMOS transistor PM1 and the grid connection signal of the first nmos pass transistor NM1 produce first output terminal in source 200, the grid of the second PMOS transistor PM2 is connected the output terminal of d type flip flop with the grid of the second nmos pass transistor NM2, the source electrode of the second nmos pass transistor NM2 and the source ground of the 3rd nmos pass transistor NM3, the drain electrode of the first PMOS transistor PM1, the drain electrode of the second PMOS transistor PM2, the drain electrode of the first nmos pass transistor NM1, the grid of the 3rd PMOS transistor PM3 is connected with the grid of the 3rd nmos pass transistor NM3, the source electrode of the first nmos pass transistor NM1 connects the drain electrode of the second nmos pass transistor NM2, the drain electrode of the 3rd PMOS transistor PM3 connects the drain electrode of the 3rd nmos pass transistor NM3, and as the output terminal of AND circuit 400.
In order to the accuracy measured, the turnover voltage of AND circuit 400 two input ends can be made identical, preferably, described first PMOS transistor PM1 is identical with the second PMOS transistor PM2, and described first nmos pass transistor NM1 is identical with the second nmos pass transistor NM2.Now, described first PMOS transistor PM1 is all identical with width with the length of the second PMOS transistor PM2, and described first nmos pass transistor NM1 is all identical with width with the length of the second nmos pass transistor NM2.
It should be noted that, in other embodiments of the invention, described AND circuit 400 can also adopt other structures, and it does not limit the scope of the invention.
In another embodiment of the present invention, shown in figure 7, described delay time measurement circuit can also comprise: impact damper 500, its input end connection signal produces the 3rd output terminal in source 200, its output terminal connects the second input end CK of d type flip flop 300, the 4th signal A4 produced for the 3rd output terminal producing source 200 to signal carries out buffered, thus the 4th signal A4 signal rises to high level signal time from low level signal can be shortened, and increase the pulse height of the 4th signal A4 high level signal.
In order to the time delay adopting the circuit shown in Fig. 5 or Fig. 7 to obtain circuit under test 100, in conjunction with reference to figure 8 to Figure 10, comprise the following steps:
During original state, shown in figure 8, the first input end that first output terminal in described signal generation source 200 is described AND circuit 400 provides high level signal (i.e. the first signal A1), the input end that second output terminal in described signal generation source 200 is circuit under test 100 provides the first low rear high level signal (i.e. secondary signal A2) comprising the first rising edge, the second input end CK that 3rd output terminal in described signal generation source 200 is d type flip flop 300 provides the first low rear high level signal comprising the second rising edge (i.e. the 4th signal A4), and the moment of described second rising edge is later than the moment of described first rising edge.
Particularly, the signal that the first input end of AND circuit 400 receives is high level signal, when the signal only having the second input end when AND circuit 400 to receive is also for high level, the output terminal of AND circuit 400 could export high level signal, otherwise the output terminal of AND circuit 400 can only output low level signal.Secondary signal A2 is low level signal within the time period of 0 to T1, from the T1 moment, become high level signal.3rd signal A3 is then the signal of secondary signal A2 after circuit under test 100, and life period difference Δ t between the 3rd signal A3 and secondary signal A2, described mistiming Δ t is exactly the time delay of circuit under test 100.4th signal A4 is low level signal from 0 to the time period of (T1+ Δ t+T2), from the T1+ Δ t+T2 moment, become high level signal.5th signal A5 is determined by the 3rd signal A3 and the 4th signal A4, because d type flip flop 300 is rising edge flip-flops, therefore the 5th signal A5 is low level signal from 0 to the time period of (T1+ Δ t+T2), from the T1+ Δ t+T2 moment, become high level signal.6th signal A6 is the signal after the 5th signal A5 and the first signal A1 carry out logical and process, therefore the 6th signal A6 is also be low level signal from 0 to the time period of (T1+ Δ t+T2), and from the T1+ Δ t+T2 moment, the 6th signal A6 becomes high level signal.It is larger that described time period T2 can be arranged, as: 10ms.
Then, described signal produces the moment of more than 200 described second rising edge of adjustment in source, to shorten the mistiming between described second rising edge and described first rising edge.In order to the mistiming that can obtain the first rising edge and the second rising edge equals this moment of Δ t, described signal produces the adjustment amount in the moment of described second rising edge of each adjustment in source 200 should be smaller.Due to time delay Δ t value multidigit in ms rank, the time that therefore can arrange each movement is ns rank, thus the mistiming of the first rising edge and the second rising edge can be found to equal the moment of Δ t.Particularly, the time of described second rising edge movement at every turn can be identical, and namely described signal produces source 200 and adjusts the second rising edge equably at every turn; Also can be different, namely described signal produces source 200 is not adjust the second rising edge equably, as: the amount of movement of the second rising edge is from big to small, thus more close to the position of the first rising edge, its amount of movement is less, the mistiming of the first rising edge and the second rising edge so just must be found to equal the moment of Δ t, the moment that namely the 4th signal A4 is identical with the 3rd signal A3.
As an object lesson, the adjustment amount that described signal produces the moment of described second rising edge of each adjustment in source 200 can comprise: 1ns ~ 100ns, as: 1ns, 5ns, 50ns or 100ns etc.
When the mistiming of the first rising edge and the second rising edge equals Δ t, i.e. time period T2=0, shown in figure 9, first signal A1, secondary signal A2, the 3rd signal A3 all do not change, and the signal of the signal of the 4th signal A4, the signal of the 5th signal A5, the 6th signal A6 is identical with the 3rd signal A3.Now, when (T1+ Δ t), the 6th signal A6 is high level signal.
Then, the moment that adjustment signal produces second rising edge of the 4th level signal A4 that source 200 the 3rd output terminal provides is continued, to shorten the mistiming between described second rising edge and described first rising edge.With reference to shown in Figure 10, when rising edge early than the 3rd signal A3 of the rising edge of the 4th signal A4 signal, first signal A1, secondary signal A2, the 3rd signal A3 still remain unchanged, 4th signal A4 is low level from 0 to the time period of (T1+T3), wherein, T3 < Δ t, the 5th signal A5 is identical with the 4th signal A4, and the 6th signal A6 then remains low level signal.
Above-mentioned input signal (i.e. the first signal A1, secondary signal A2 and the 4th signal A4) can learn its concrete level state at any time, and output signal (i.e. the 6th signal A6) is also can be learn its concrete level state at any time.The amount of movement each due to the 4th signal A4 is smaller, therefore can think that the 6th signal A6 be low level from high level saltus step is in a flash.
Comparison diagram 9 and Figure 10 known, low level moment is jumped to from high level at the output terminal (i.e. the 6th signal A6) of AND circuit 400, record the mistiming between the first rising edge and the second rising edge, the described mistiming is time delay of circuit under test 100.
So far, the time delay having drawn circuit under test 100 is measured.
Because the first signal A1 in AND circuit 400 is constant in the present embodiment, change, therefore can not be delayed by the signal of AND circuit 400; In addition, in the present embodiment, only comprise a d type flip flop 300, thus compared with prior art, additionally reduce the time delay that a d type flip flop causes, finally ensure that the accuracy of delay time measurement.
In order to increase the accuracy of measurement further, technical scheme of the present invention can be adopted to take multiple measurements, finally getting the time delay of arithmetic mean as circuit under test 100 of multiple measurement result.
Although the present invention discloses as above with preferred embodiment, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (10)
1. a delay time measurement circuit, be connected with circuit under test, for measuring the time delay of circuit under test, it is characterized in that, comprise: signal produces source, d type flip flop and AND circuit, wherein, signal produces source and comprises three output terminals, signal produces the first input end of the first output terminal connection AND circuit in source, signal produces the input end of the second output terminal connection circuit under test in source, the output terminal of circuit under test connects the first input end of d type flip flop, signal produces the 3rd output terminal in source and the second input end of d type flip flop couples, the output terminal of d type flip flop connects the second input end of AND circuit, when the output terminal of described AND circuit jumps to low level from high level, described signal generation second output terminal in source and the signal time difference of the 3rd output terminal are exactly the time delay of described circuit under test,
The first input end that the first output terminal that described signal produces source is always described AND circuit provides high level signal, the input end that second output terminal in described signal generation source is circuit under test provides the first low rear high level signal comprising the first rising edge, the second input end that 3rd output terminal in described signal generation source is d type flip flop provides the first low rear high level signal comprising the second rising edge, and the moment of described second rising edge is later than the moment of described first rising edge.
2. delay time measurement circuit as claimed in claim 1, it is characterized in that, described d type flip flop is rising edge flip-flops.
3. delay time measurement circuit as claimed in claim 1, it is characterized in that, described delay time measurement circuit also comprises: impact damper, its input end connection signal produces the 3rd output terminal in source, its output terminal connects the second input end of d type flip flop, and the signal that the 3rd output terminal for producing source to signal produces carries out buffered.
4. delay time measurement circuit as claimed in claim 1, it is characterized in that, described signal is produced between second output terminal in source and the input end of circuit under test and is connected by first line, described signal produces by the second connection between first output terminal in source and the first input end of AND circuit, and resistance value or the capacitance of described first line and described second circuit are equal.
5. delay time measurement circuit as claimed in claim 4, is characterized in that, the material of described first line and described second circuit, length, diameter are all identical.
6. delay time measurement circuit as claimed in claim 1, it is characterized in that, described AND circuit comprises: the first nmos pass transistor, second nmos pass transistor, 3rd nmos pass transistor, first PMOS transistor, second PMOS transistor and the 3rd PMOS transistor, wherein, the source electrode of the first PMOS transistor, the source electrode of the second PMOS transistor is connected supply voltage with the source electrode of the 3rd PMOS transistor, the grid of the first PMOS transistor and the grid connection signal of the first nmos pass transistor produce first output terminal in source, the grid of the second PMOS transistor is connected the output terminal of d type flip flop with the grid of the second nmos pass transistor, the source electrode of the second nmos pass transistor and the source ground of the 3rd nmos pass transistor, the drain electrode of the first PMOS transistor, the drain electrode of the second PMOS transistor, the drain electrode of the first nmos pass transistor, the grid of the 3rd PMOS transistor is connected with the grid of the 3rd nmos pass transistor, the source electrode of the first nmos pass transistor connects the drain electrode of the second nmos pass transistor, the drain electrode of the 3rd PMOS transistor connects the drain electrode of the 3rd nmos pass transistor, and as the output terminal of AND circuit.
7. delay time measurement circuit as claimed in claim 6, it is characterized in that, described first PMOS transistor is identical with the second PMOS transistor, and described first nmos pass transistor is identical with the second nmos pass transistor.
8. application rights requires a delay time determining method for the delay time measurement circuit according to any one of 1 to 7, it is characterized in that, comprising:
The first input end that the first output terminal that described signal produces source is always described AND circuit provides high level signal, the input end that second output terminal in described signal generation source is circuit under test provides the first low rear high level signal comprising the first rising edge, the second input end that 3rd output terminal in described signal generation source is d type flip flop provides the first low rear high level signal comprising the second rising edge, and the moment of described second rising edge is later than the moment of described first rising edge;
Described signal produces the moment that source repeatedly adjusts described second rising edge, to shorten the mistiming between described second rising edge and described first rising edge;
When the output terminal of AND circuit jumps to low level from high level, record the mistiming between the first rising edge and the second rising edge, the described mistiming is the time delay of circuit under test.
9. delay time determining method as claimed in claim 8, is characterized in that, described signal produces the moment that source adjusts described second rising edge equably.
10. delay time determining method as claimed in claim 8 or 9, is characterized in that, the described signal source that produces adjusts the adjustment amount in the moment of described second rising edge at every turn and comprises: 1ns ~ 100ns.
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| CN105699734A (en) * | 2014-11-26 | 2016-06-22 | 环旭电子股份有限公司 | Device and method for detecting delay time of signal |
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| CN106531655B (en) * | 2016-11-14 | 2019-02-19 | 河海大学常州校区 | Single particle effect modulates lower trap circuit for measuring potential in CMOS technology |
| CN108009112A (en) * | 2017-09-27 | 2018-05-08 | 上海玮舟微电子科技有限公司 | A kind of high-frequency clock IQ phase calibration circuit |
| JP2020009240A (en) * | 2018-07-10 | 2020-01-16 | ソニー株式会社 | Circuit, device, and method for signal processing |
| CN111077438B (en) * | 2018-10-22 | 2021-11-12 | 中芯国际集成电路制造(北京)有限公司 | I/O interface delay time test circuit |
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| JP2622845B2 (en) * | 1987-11-30 | 1997-06-25 | 株式会社アドバンテスト | Delay time measurement circuit |
| JP3334762B2 (en) * | 1993-06-22 | 2002-10-15 | 川崎マイクロエレクトロニクス株式会社 | Circuit for measuring delay time of logic circuit on semiconductor chip |
| JPH11101851A (en) * | 1997-09-26 | 1999-04-13 | Toshiba Corp | Delay time measuring circuit and delay time measuring method |
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| CN1912643A (en) * | 2005-08-08 | 2007-02-14 | 联华电子股份有限公司 | Delay time measuring device and method |
| CN101627538A (en) * | 2007-03-30 | 2010-01-13 | 富士通株式会社 | Delay time determining method, delay time adjusting method and variable delay circuit |
| CN101680920A (en) * | 2007-06-18 | 2010-03-24 | 艾勒博科技股份有限公司 | Delay time measurement circuit and method |
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