CN108009112A - A kind of high-frequency clock IQ phase calibration circuit - Google Patents
A kind of high-frequency clock IQ phase calibration circuit Download PDFInfo
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- CN108009112A CN108009112A CN201710890352.2A CN201710890352A CN108009112A CN 108009112 A CN108009112 A CN 108009112A CN 201710890352 A CN201710890352 A CN 201710890352A CN 108009112 A CN108009112 A CN 108009112A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0002—Serial port, e.g. RS232C
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Abstract
The embodiment of the invention discloses a kind of high-frequency clock IQ phase calibration circuit, including：First time delay module, the second time delay module and Orthogonal phase detection module；The input terminal of first time delay module is electrically connected with the first signal end, and output terminal is electrically connected with the first input end of Orthogonal phase detection module, for the first signal to be carried out delay process；The input terminal of second time delay module is electrically connected with secondary signal end, and output terminal is electrically connected with the second input terminal of Orthogonal phase detection module, for secondary signal to be carried out delay process；Orthogonal phase detection module is respectively according to the first signal and the second signal after delay process, the phase difference of the first signal and the second signal is converted into timing_delay estimation voltage, and export timing_delay estimation voltage to the second time delay module by output terminal, to adjust the time delay of the second time delay module.Technical solution provided in an embodiment of the present invention, can solve the generation susceptible of existing quadrature clock signal, cause a deviation the problem of larger.
Description
Technical field
The present embodiments relate to clock and data recovery technical field, more particularly to a kind of high-frequency clock IQ phase calibration
Circuit.
Background technology
In high-speed serial data communication, in order to save expense, general only transmission data-signal is believed without transmitting with data
The clock signal of number synchronization.In this way, in receiving terminal in order to ensure that the timing informations such as the synchronization of data processing, clock must be from data
In extract, then data are carried out using the clock to eliminate the shake accumulated in transmitting procedure " when resetting ", this when
Process when clock extracts and data are reset is commonly referred to as clock and data recovery (Clock and Data Recovery, CDR).
1 is used for high-frequency clock data recovery more：4 (demux/mux) or 1：2 (demux/mux) multiplexers drop
Low sampling rate, reduces design difficulty and reduces power consumption.But the problem of bringing is to need multiphase clock, with 1：4demux
, it is necessary to which phase difference is followed successively by 90 degree of 4 clock signals exemplified by baudrate CDR designs.
Usually, a simple phase inverter is only needed when phase difference is 180 degree, postpones the amount at several picoseconds
Level, for existing maximum transmission rate 25Gbps, this delay almost can be ignored.But 90 degree of difference, produce process compared with
Complexity, and precision is subject to circuit design and laying out pattern etc. to influence, and easy deflection difference is larger.
The content of the invention
The present invention provides a kind of high-frequency clock IQ phase calibration circuit, to solve the generation of existing quadrature clock signal
Susceptible, causes a deviation the problem of larger.
In a first aspect, an embodiment of the present invention provides a kind of high-frequency clock IQ phase calibration circuit, including：First delay
Module, the second time delay module and Orthogonal phase detection module；
The input terminal of first time delay module is electrically connected with the first signal end, output terminal and the Orthogonal phase detection mould
The first input end of block is electrically connected, for the first signal to be carried out delay process；The input terminal of second time delay module and
Binary signal end is electrically connected, and output terminal is electrically connected with the second input terminal of the Orthogonal phase detection module, for by secondary signal
Carry out delay process；
The Orthogonal phase detection module is respectively according to the first signal and the second signal after delay process, by described in
The phase difference of the first signal and the second signal is converted to timing_delay estimation voltage, and the timing_delay estimation voltage is passed through described orthogonal
The output terminal of phase detecting module is exported to second time delay module, to adjust the time delay of second time delay module.
High-frequency clock IQ phase calibration circuit provided in an embodiment of the present invention, the first orthogonal letter that latch is produced
Number and secondary signal be separately input into the first time delay module and the second time delay module, the first time delay module and the second time delay module point
The first signal and the second signal Yong Yu not be carried out with delay process, and the first signal and the second signal after delay process are transmitted
To Orthogonal phase detection module, Orthogonal phase detection module is used for the phase of the first signal and the second signal after delay process
Difference is converted to timing_delay estimation voltage, and by timing_delay estimation voltage output to the second time delay module, to adjust the second time delay module
Time delay so that when the phase of the first signal and the second signal is not accurate orthogonality relation, adjust the second time delay module when
Prolong, be more accurate orthogonality relation by the phase adjusted of the first signal and the second signal.This programme by negative feedback control just
The timing_delay estimation voltage of clock generation circuit is handed over, so as to control the phase difference of high-frequency clock, can be obtained more accurately orthogonal
The high-frequency clock of phase, the precision for solving existing quadrature clock signal are easily subject to the shadow of circuit design and laying out pattern
The problem of ringing, causing quadrature clock signal phase deviation larger.
Brief description of the drawings
Fig. 1 is a kind of high-frequency clock IQ phase calibration electrical block diagram provided in an embodiment of the present invention；
Fig. 2 is another high-frequency clock IQ phase calibration electrical block diagram provided in an embodiment of the present invention；
Fig. 3 is the structure chart of Orthogonal phase detection module provided in an embodiment of the present invention；
Fig. 4 is the structure chart for another Orthogonal phase detection module that the present invention implements offer；
Fig. 5 is the structure chart of another Orthogonal phase detection module provided in an embodiment of the present invention；
Four orthogonal clock sequence diagrams when Fig. 6 a are no phase mismatch provided in an embodiment of the present invention；
Fig. 6 b are that four orthogonal clocks that Fig. 6 a are provided pass through high speed and the duty cycle schematic diagram after door；
Fig. 7 a are four orthogonal clock sequence diagrams when CK90 phases are advanced；
Fig. 7 b are that four orthogonal clocks that Fig. 7 a are provided pass through high speed and the duty cycle schematic diagram after door；
Four orthogonal clock sequence diagrams when Fig. 8 a are CK90 delayed phases；
Fig. 8 b are that four orthogonal clocks that Fig. 8 a are provided pass through high speed and the duty cycle schematic diagram after door；
Fig. 9 is the structure diagram of high speed AND gate circuit provided in an embodiment of the present invention；
Figure 10 is low speed AND gate circuit structure schematic diagram of the prior art.
Embodiment
The present invention is described in further detail with reference to the accompanying drawings and examples.It is understood that this place is retouched
The specific embodiment stated is used only for explaining the present invention, rather than limitation of the invention.It also should be noted that in order to just
It illustrate only part related to the present invention rather than entire infrastructure in description, attached drawing.
The embodiment of the present invention provides a kind of high-frequency clock IQ phase calibration circuit, and with reference to figure 1, Fig. 1 is implementation of the present invention
A kind of high-frequency clock IQ phase calibration electrical block diagram that example provides, the high-frequency clock IQ phase calibration circuit bag
Include：
First time delay module 11, the second time delay module 12 and Orthogonal phase detection module 13；
The input terminal of first time delay module 11 is electrically connected with the first signal end CKI, output terminal OUT1 and Orthogonal phase detection
The first input end of module 13 is electrically connected, for the first signal to be carried out delay process；The input terminal of second time delay module 12 with
Secondary signal end CKQ is electrically connected, and output terminal OUT2 is electrically connected with the second input terminal of Orthogonal phase detection module 13, for by the
Binary signal carries out delay process；
Orthogonal phase detection module 13 respectively according to the first signal and the second signal after delay process, by the first signal and
The phase difference of secondary signal is converted to timing_delay estimation voltage, and the output by timing_delay estimation voltage by Orthogonal phase detection module
End output is to the second time delay module 12, to adjust the time delay of the second time delay module 12.
In high-frequency clock data recovery, the clock signal that phase differs 90 degree successively may be used, then needs to produce
The high-speed clock signal of two-way quadrature in phase, then respectively obtains phase phase by above-mentioned two-way high-speed clock signal using phase inverter
The high-speed clock signal of poor 180 degree, so that obtained phase differs 90 Du, tetra- road high-speed clock signals successively.Ordinary circumstance
Under, the clock signal that phase difference is 90 degree can be produced by latch, but the orthogonal high-frequency clock produced by latch is believed
Number phase difference may not be accurate 90 degree, its precision is easily by circuit design affect, it is possible to more than 90 degree, it is also possible to small
In 90 degree, then in the present embodiment, by respectively by two-way high-speed clock signal input the first time delay module 11 and the second delay
Module 12, carries out the adjustment of phase.With reference to figure 1, the first signal that the first signal end CKI and secondary signal end CKQ are exported respectively
Orthogonal signalling of the phase difference at 90 degree or so produced with secondary signal for phase locking unit, the first signal and the second signal are passed through respectively
The delay process of first time delay module 11 and the second time delay module 12, exports as accurate orthogonal signalling, the first delay mould
The output terminal OUT2 of the output terminal OUT1 of block 11 and the second time delay module 12 exports orthogonal high-speed clock signal for clock number
Used according to recovery.
In the present embodiment, the time delay of the second time delay module 12 is adjustable, for adjusting the phase of secondary signal so that second
The phase of signal and the first signal accurately differ 90 degree, the time delay of the second time delay module 12 by Orthogonal phase detection module 13 into
Row is adjusted, the first input end of Orthogonal phase detection module 13 and the second input terminal output terminal with the first time delay module 11 respectively
The output terminal OUT2 of OUT1 and the second time delay module 12 be electrically connected, for judge the first signal and the second signal phase difference whether
Switch to timing_delay estimation voltage more than or less than 90 degree, and by the phase difference of the first signal and the second signal, and timing_delay estimation is electric
Pressure output is adjusted the time delay of the second time delay module 12 to the second time delay module 12.It is exemplary, if secondary signal and the
The phase difference of one signal is more than 90 degree, then timing_delay estimation voltage controls the time delay of the second time delay module 12 to reduce, then the second delay
The phase of the secondary signal of 12 output terminal OUT2 of module outputs shifts to an earlier date so that the phase of secondary signal and the first time delay module 11 are defeated
The phase difference of outlet OUT1 is 90 degree；If secondary signal and the phase difference of the first signal are less than 90 degree, timing_delay estimation voltage control
Make the phase steric retardation of the time delay increase, the then secondary signal of 12 output terminal OUT2 of the second time delay module outputs of the second time delay module 12
Afterwards so that the phase difference of the phase of secondary signal and the first signal of 11 output terminal OUT1 of the first time delay module outputs is 90 degree.
Similarly, Orthogonal phase detection module 13 can also select that the first time delay module 11 is adjusted so that first prolongs
When the first signal that exports of module 11 go the secondary signal of matching the second time delay module 12 output, equally can by the first signal and
The phase difference of secondary signal is adjusted to accurately 90 degree.
High-frequency clock IQ phase calibration circuit provided in an embodiment of the present invention, the first orthogonal letter that latch is produced
Number and secondary signal be separately input into the first time delay module and the second time delay module, the first time delay module and the second time delay module point
The first signal and the second signal Yong Yu not be carried out with delay process, and the first signal and the second signal after delay process are transmitted
To Orthogonal phase detection module, Orthogonal phase detection module is used for the phase of the first signal and the second signal after delay process
Difference is converted to timing_delay estimation voltage, and by timing_delay estimation voltage output to the second time delay module, to adjust the second time delay module
Time delay so that when the phase of the first signal and the second signal is not accurate orthogonality relation, adjust the second time delay module when
Prolong, be more accurate orthogonality relation by the phase adjusted of the first signal and the second signal.This programme by negative feedback control just
The timing_delay estimation voltage of clock generation circuit is handed over, so as to control the phase difference of high-frequency clock, can be obtained more accurately orthogonal
The high-frequency clock of phase, the precision for solving existing quadrature clock signal are easily subject to the shadow of circuit design and laying out pattern
The problem of ringing, causing quadrature clock signal phase deviation larger.
On the basis of above-described embodiment, with reference to figure 2, Fig. 2 be another high-frequency clock provided in an embodiment of the present invention just
Phase calibration circuitry structure diagram is handed over, optionally, the first time delay module 11 includes multiple phase inverters being sequentially connected in series, the first anti-
The input terminal of phase device is electrically connected by the input terminal of the first time delay module with the first signal end CKI, the output terminal of last bit Inverting device
It is electrically connected by the output terminal OUT1 of the first time delay module 11 with the first input end CK0 of Orthogonal phase detection module 13；Wherein,
The cold end of each phase inverter is electrically connected with ground terminal；
Second time delay module 12 includes the phase inverter that is sequentially connected in series identical with 11 numbers of the first time delay module, the first anti-phase
The input terminal of device is electrically connected by the input terminal of the second time delay module 12 with secondary signal end CKQ, the output terminal of last bit Inverting device
It is electrically connected by the output terminal OUT2 of the second time delay module 12 with the second input terminal CK90 of Orthogonal phase detection module 13；Its
In, the cold end of each phase inverter is electrically connected by the first gain transistor M1 with ground terminal.
First time delay module 11 includes the phase inverter of multiple series connection so that the first signal has certain delay, each anti-phase
Device all includes an input terminal, an output terminal, a hot end and a cold end, the input of first phase inverter
End connects the first signal end CKI by the input terminal of the first time delay module 11, and for obtaining the first signal, output terminal is with connecting
The input terminal of next phase inverter is electrically connected, and so on, the output terminal of last phase inverter passes through the first time delay module 11
Output terminal OUT1 be electrically connected with the first input end CK0 of Orthogonal phase detection module 13.The hot end of phase inverter and low electricity
Position end is used to power for the work of phase inverter, and the hot end of each phase inverter connects identical high level, cold end company
Connect identical ground terminal.
Second time delay module 12 includes the phase inverter identical with 11 numbers of the first time delay module, the input terminal of phase inverter and defeated
The opposite connection relation of outlet is identical with the phase inverter in the first time delay module 11, is equally the input terminal and of the first phase inverter
Binary signal end CKQ is electrically connected, and the output terminal of last bit Inverting device is electrically connected with the second input terminal CK90 of Orthogonal phase detection module 13
Connect.The hot end of each phase inverter connects the high level identical with phase inverter in the first time delay module 11, still, each anti-phase
The cold end of device is all electrically connected by the first gain transistor with ground terminal, then the first gain transistor M1 can be according to control terminal
Control signal adjusts the current value of the first gain transistor, and it is by varying the first gain to be reflected in the second time delay module 12
Transistor M1 bias voltages (the timing_delay estimation voltage in this implementation) adjust bias current and resistance, so as to adjust the second delay
The delay duration of module 12, so as to adjust the phase relation of the secondary signal after delay process and the first signal.
Difference lies in cold end to be connected to the first gain transistor for second time delay module 12 and the first time delay module 11
M1, the bias current and resistance of the first gain transistor are adjusted by adjusting timing_delay estimation voltage, so that adjustable phase inverter
Delay duration.
Optionally, with reference to figure 2, the control terminal VB of the output terminal of Orthogonal phase detection module 13 and the first gain transistor M1
It is electrically connected, for exporting timing_delay estimation voltage to the first gain transistor M1 to control the time delay of the second time delay module 12.
Phase difference is converted to bias voltage, i.e. timing_delay estimation voltage by Orthogonal phase detection module 13, and by timing_delay estimation
Voltage is exported to the control terminal VB of the first gain transistor M1 by output terminal, so as to adjust the biasing of the first gain transistor M1
Electric current and resistance, control the delay duration of each phase inverter, and then adjust secondary signal and the potential difference of the first signal.
Optionally, further included with reference to figure 2, high-frequency clock IQ phase calibration circuit：First reverse module 14 and second is anti-
To module 15；
The input terminal of first reverse module 14 is electrically connected with the output terminal OUT1 of the first time delay module 11, output terminal OUT3 with
3rd input terminal CK180 of Orthogonal phase detection module 13 is electrically connected, for the first signal after delay process to be converted to the
Three signals；
The input terminal of second reverse module 15 is electrically connected with the output terminal OUT2 of the second time delay module 12, output terminal OUT4 with
4th input terminal CK270 of Orthogonal phase detection module 13 is electrically connected, for the secondary signal after delay process to be converted to the
Four signals.
When high-frequency clock data recovery needs 4 clock signals of 90 degree of phase difference successively, the first signal and the second letter
The 3rd signal and the 4th that phase difference is 180 degree is each produced by the first reverse 14 and second reverse module 15 of module number respectively
Signal, then phase difference is 90 degree successively for the first signal, secondary signal, the 3rd signal and the 4th signal.
With reference to figure 2, optionally, the first reverse module 14 includes a phase inverter, and the input terminal of phase inverter is anti-by first
It is electrically connected to the input terminal of module 14 with the output terminal OUT1 of the first time delay module 11, output terminal passes through the first reverse module 14
Output terminal OUT3 is electrically connected with the 3rd input terminal CK180 of Orthogonal phase detection module 13；Second reverse module 15 includes one
Phase inverter, the input terminal of phase inverter pass through the input terminal of the second reverse module 15 and the output terminal OUT2 electricity of the second time delay module 12
Connection, output terminal pass through the output terminal OUT4 of the second reverse module 15 and the 4th input terminal of Orthogonal phase detection module 13
CK270 is electrically connected.
First reverse 14 and second reverse module 15 of module includes a phase inverter respectively, and a phase inverter can be by signal
Phase delay 180 degree, obtain the 3rd signal and the 4th signal.Generally, the output terminal OUT1 of the first time delay module 11, second
The output terminal OUT2 of time delay module 12, the first reverse module 14 the reverse modules 15 of output terminal OUT3 and second output terminal OUT4
First input end CK0 with Orthogonal phase detection module 13, the second output terminal CK90, the 3rd output terminal CK180 and respectively
Four output terminal CK270 are electrically connected, for the phase difference after delay process to be followed successively by 90 Du, tetra- road signal input quadrature phases
Detection module 13, makes Orthogonal phase detection module 13 be compared the phase of four road signals, so as to pass through timing_delay estimation voltage
Delays time to control is carried out to the second time delay module 12, so as to adjust the phase difference of four road signals, obtains accurate orthogonal signalling, it is described
Four road signals are the first signal, secondary signal, the 3rd signal and the 4th signal.
Optionally, with reference to figure 3, Fig. 3 is the structure chart of Orthogonal phase detection module provided in an embodiment of the present invention, orthorhombic phase
Position detection module 13 includes：First converting unit 131, the second converting unit 132, operational amplifier OPA and the second gain are brilliant
Body pipe M2；
The input terminal of first converting unit 131 respectively four input terminal CK0, CK90 with Orthogonal phase detection module 13,
CK180 and CK270 are electrically connected, for the first signal and the second signal to be carried out logic and operation, and by the 3rd signal and the 4th
Signal carries out logic and operation；And the signal for obtaining two-way logic and operation is filtered and is handled with adduction, and it is straight to obtain first
Flow signal；
The input terminal of second converting unit 132 respectively four input terminal CK0, CK90 with Orthogonal phase detection module 13,
CK180 and CK270 are electrically connected, for the first signal and the 4th signal to be carried out logic and operation, and by secondary signal and the 3rd
Signal carries out logic and operation；And the signal for obtaining two-way logic and operation is filtered and is handled with adduction, and it is straight to obtain second
Flow signal；
The positive input terminal and negative input end of operational amplifier OPA respectively with the first converting unit 131 and the second converting unit
132 output terminal is electrically connected, for the difference of the first direct current signal and the second direct current signal to be amplified processing and is exported extremely
The control terminal of second gain transistor M2；
The first connecting pin of second gain transistor M2 connects the first high level end V1, second connection end by pull-up resistor Rs
Ground connection, the first connecting pin are additionally operable to be electrically connected with the second time delay module 12 by the output terminal of Orthogonal phase detection module 13, join
Fig. 1 or Fig. 2 is examined, for by the timing_delay estimation voltage output that the first connecting pin exports to the second time delay module 12.
The first signal and the second signal are carried out logic and operation respectively and carry out filtering process by the first converting unit 131,
Direct current signal is obtained, the 3rd signal and the 4th signal are subjected to logic and operation and carry out filtering process, obtains direct current signal, because
It is to be postponed by the first signal phase obtained by 180 degree for the 3rd signal, the 4th signal is by secondary signal phase delay 180 degree institute
, the 3rd signal and the 4th signal are subjected to direct current signal that logic and operation and carrying out obtains after filtering process and by the first letter
Number and secondary signal obtain it is identical, so the two-way direct-flow signal voltage value after filtering process is identical, then by two paths of signals phase
Add to obtain the first direct current signal.
Similarly, the first signal and the 4th signal are carried out logic and operation and carry out filtering process by the second converting unit 132,
Direct current signal is obtained, secondary signal and the 3rd signal are subjected to logic and operation and carry out filtering process, obtains direct current signal, two
Road direct current signal is added to obtain the second direct current signal.
The positive input terminal and negative input end of operational amplifier OPA connects the first converting unit 131 respectively and the second conversion is single
The output terminal of member 132, for the difference of the first direct current signal and the second direct current signal to be amplified processing, if positive-negative input end
Difference be zero, then operational amplifier OPA output terminal output bias voltage remain unchanged.Operational amplifier OPA is by difference
Signal is amplified and is delivered to the control terminal of the second gain transistor M2, for controlling the biased electrical of the second gain transistor M2
Stream, so that the magnitude of voltage of pull-up resistor Rs is controlled, so as to control the output terminal electricity of the first connecting pin of the second gain transistor M2
Pressure, the first connecting pin are electrically connected by the output terminal of Orthogonal phase detection module 13 with the input terminal of the second time delay module 12, are used
The second time delay module 12 is delivered in the timing_delay estimation voltage for producing the first connecting pin, in the present embodiment, the second delay mould
The structure of block 12 can be as shown in Fig. 2, then the first connecting pin of the second gain transistor M2 passes through Orthogonal phase detection module 13
Control terminal VB of the output terminal directly with the first gain transistor M1 is electrically connected.
It is worth noting that：When the phase difference of secondary signal and the first signal is just equal to 90 degree, the 4th signal and first
The phase difference of signal is similarly 90 degree, then the first direct current signal and the second direct current signal are equal, illustrates at this time for more accurately
The first signal and the second signal orthogonal signalling, then timing_delay estimation voltage is constant, and the first signal and the second signal can be kept at this time
Phase difference；When the phase difference of secondary signal and the first signal is more than 90 degree, then the phase difference of the 4th signal and the first signal is less than
90 degree, then the first direct current signal that the first converting unit 131 produces is less than the second direct current letter that the second converting unit 132 produces
Number, then operational amplifier OPA output voltages reduce, the timing_delay estimation voltage of the first connecting pin output of the second gain transistor M2
Increase so that the time delay of the second time delay module 12 reduces, and the phase difference of secondary signal and the first signal reduces；When secondary signal and
The phase difference of first signal is less than 90 degree, then the phase difference of the 4th signal and the first signal is more than 90 degree, then the first direct current signal
More than the second direct current signal, then operational amplifier OPA output voltages increase, the first connecting pin output of the second gain transistor M2
Timing_delay estimation voltage reduce so that the phase difference of the increase of the time delay of the second time delay module 12, secondary signal and the first signal increases
Greatly.By the above process, the delay duration of the second time delay module 12 is adjusted in Orthogonal phase detection module 13, so as to control
Phase difference between four road signals.
Optionally, with reference to figure 4, Fig. 4 is the structure chart for another Orthogonal phase detection module that the present invention implements offer, the
One converting unit 131 includes：First high speed and 1312 and first filter circuit 1313 of door 1311, the second high speed and door；
The input terminal of first high speed and door 1311 respectively with the first input end CK0 of Orthogonal phase detection module 13 and second
Input terminal CK90 is electrically connected, and output terminal is electrically connected with the first input end of the first filter circuit 1313, for by the first signal with
Secondary signal carries out logic and operation and exports to the first filter circuit 1313；
The input terminal of second high speed and door 1312 respectively with the 3rd input terminal CK180 of Orthogonal phase detection module 13 and
Four input terminal CK270 are electrically connected, and output terminal is electrically connected with the second input terminal of the first filter circuit 1313, for by the 3rd signal
Logic and operation is carried out with the 4th signal and is exported to the first filter circuit 1313；
The output terminal of first filter circuit 1313 is electrically connected with the positive input terminal of operational amplifier OPA, for high by first
The output signal of speed and 1311 and second high speed of door and door 1312 is filtered to be handled to obtain the first direct current signal with adduction.
With reference to figure 4, optionally, the second converting unit 132 includes：3rd high speed and door 1321, the 4th high speed and door 1322
With the second filter circuit 1323；
The input terminal of 3rd high speed and door 1321 respectively with the first input end CK0 of Orthogonal phase detection module 13 and the 4th
Input terminal CK270 is electrically connected, and output terminal is electrically connected with the first input end of the second filter circuit 1323, for by the first signal with
4th signal carries out logic and operation and exports to the second filter circuit 1323；
The input terminal of 4th high speed and door 1322 respectively with the second input terminal CK90 of Orthogonal phase detection module 13 and
Three input terminal CK180 are electrically connected, and output terminal is electrically connected with the second input terminal of the second filter circuit 1323, for by secondary signal
Logic and operation is carried out with the 3rd signal and is exported to the second filter circuit 1323；
The output terminal of second filter circuit 1323 is electrically connected with the negative input end of operational amplifier OPA, for high by the 3rd
The output signal of speed and 1321 and the 4th high speed of door and door 1322 is filtered to be handled to obtain the second direct current signal with adduction.
Optionally, with reference to figure 5, Fig. 5 is the structure chart of another Orthogonal phase detection module provided in an embodiment of the present invention,
As shown in Figure 5, the first filter circuit 1313 includes：First resistor R1, second resistance R2 and the first capacitance C1；
The first connecting pin of first resistor R1 is electrically connected with the first input end of the first filter circuit 1313, second connection end
It is electrically connected with the second connection end of second resistance R2, the first connecting pin of second resistance R2 and the second of the first filter circuit 1313
Input terminal is electrically connected；The second connection end of first resistor R1 is grounded by the first capacitance C1, and with the first filter circuit 1313
Output terminal is electrically connected；
Second filter circuit 1323 includes：3rd resistor R3, the 4th resistance R4 and the second capacitance C2；
The first connecting pin of 3rd resistor R3 is electrically connected with the first input end of the second filter circuit 1323, second connection end
It is electrically connected with the second connection end of the 4th resistance R4, the first connecting pin of the 4th resistance R4 and the second of the second filter circuit 1323
Input terminal is electrically connected；The second connection end of 3rd resistor R3 is grounded by the second capacitance C2, and with the second filter circuit 1323
Output terminal is electrically connected.
With reference to figure 5, the first high speed is electrically connected with door 1311 by first resistor R1 and the positive input terminal of operational amplifier OPA
Connect, the second high speed is electrically connected with door 1312 by second resistance R2 with the positive input terminal of operational amplifier OPA, and second resistance
R2 or first resistor R1 is grounded, then first close to one end, that is, second connection end of operational amplifier OPA by the first capacitance C1
High speed passes through the filtering of first resistor R1 and the first capacitance C1 with clock signal caused by door 1311, generates direct current signal, the
Two high speeds then generate direct current signal with door 1312 by the filtering of second resistance R2 and the first capacitance C1, and because two-way direct current is believed
Number all positive input terminals of input operational amplifier OPA, then actually enter operational amplifier OPA positive input terminal for two-way direct current
The adduction of signal, i.e. the first direct current signal.
3rd high speed is electrically connected with door 1321 by 3rd resistor R3 with the negative input end of operational amplifier OPA, and the 4th is high
Speed is electrically connected with door 1322 by the 4th resistance R4 with the negative input end of operational amplifier OPA, and the 4th resistance R4 or the
Three resistance R3 are grounded close to one end, that is, second connection end of operational amplifier OPA by the second capacitance C4.Similarly, the 3rd at a high speed
With door 1321 caused by clock signal and the 4th high speed with clock signal caused by door 1322 by 3rd resistor R3, the 4th
The filtering of resistance R4 and the second capacitance C2 obtain two-way direct current, and by the negative of two-way direct current input operational amplifier OPA at the same time
Input terminal, i.e., input the second direct current signal to the negative input end of operational amplifier OPA.
On the basis of above-described embodiment, the present embodiment is to include the high-frequency clock of Orthogonal phase detection module shown in Fig. 5
Exemplified by IQ phase calibration circuit, description high-frequency clock IQ phase calibration circuit calibrates orthogonal high-speed clock signal
Process.
Referring to figs. 2 and 5 latch produces the high-speed clock signal of nearly orthogonal：The first signal and the second signal, first
Signal and secondary signal are exported to the first time delay module 11 and second by the first signal end CKI and secondary signal end CKQ respectively
Time delay module 12, carries out delay process, obtains the first signal and the second signal after delay process, and obtain the by phase inverter
Three signals and the 4th signal.First signal, secondary signal, the 3rd signal and the 4th signal pass through Orthogonal phase detection module respectively
13 input terminal CK0, CK90, CK180 and CK270 is inputted to Orthogonal phase detection module 13, the first signal, secondary signal,
3rd signal and the 4th signal differ 90 degree of high-speed clock signal for phase difference successively.
The first signal and the second signal are filtered by the first high speed with door 1311 and by first resistor R1 and the first capacitance C1
After ripple, produce a DC voltage V3 at the first capacitance C1, the 3rd signal and the 4th signal by the second high speed with door 1312 simultaneously
After second resistance R2 and the first capacitance C1 filtering, a DC voltage V4, such first capacitance are produced at the first capacitance C1
The upper DC voltage U1=V3+V4 of C1；
First signal and the 4th signal are filtered by the 3rd high speed with door 1321 and by 3rd resistor R3 and the second capacitance C2
After ripple, produce a DC voltage V5 at the second capacitance C2, secondary signal and the 3rd signal by the 4th high speed with door 1332 simultaneously
After the 4th resistance R4 and the second capacitance C2 filtering, a DC voltage V6, such second capacitance are produced at the second capacitance C2
The upper DC voltage U2=V5+V6 of C2.
The voltage difference of voltage U1 and voltage U2 is amplified by operational amplifier OPA, and the voltage difference of amplification controls the second gain
Transistor M2 produces electric current, and electric current flows through the timing_delay estimation voltage of generation delay of control after pull-up resistor Rs.
It is possible that three kinds of situations, the first situation is that secondary signal and the phase difference of the first signal are proper for 90 degree, then
Four road signals do not have phase mismatch.With reference to figure 6a, when Fig. 6 a are no phase mismatch provided in an embodiment of the present invention four it is orthogonal when
Clock sequence diagram.For the ease of being recognized to four road signals, respectively by the first signal, secondary signal, the 3rd signal and the 4th letter
Number it is respectively labeled as title CK0, CK90, CK180 and CK270 of Orthogonal phase detection module input mouth.In no phase mismatch
When, CK0 and CK90 by the first high speed with behind the door, duty cycle 1/4, as shown in Figure 6 b, Fig. 6 b be that Fig. 6 a are provided four are just
Clock is handed over by a high speed and the duty cycle schematic diagram after door, i.e., each cycle for a quarter high level, 3/4ths
Low level.If high level is Vh, low level 0, CK0 and CK90 are by high speed with after door and filtering, producing DC voltage V3
=Vh/4.
Without phase mismatch, CK180 and CK270 are by a high speed and behind the door, duty cycle is 1/4 as shown in Figure 6 b, i.e., each all
Phase be a quarter high level, 3/4ths low level.If high level is Vh, low level 0, CK180 and CK270 warps
Cross at a high speed with after door and filtering, producing DC voltage V4=Vh/4.
On capacitance C1, the DC voltage U1=Vh/4+Vh/4=Vh/2 of generation.Similarly, under the conditions of no phase mismatch,
On capacitance C2, the DC voltage U2=Vh/4+Vh/4=Vh/2 of generation, then operational amplifier OPA input voltages difference is zero, fortune
Calculate that the voltage that amplifier OPA is exported to the second gain transistor M2 is constant, input the time delay of the first gain transistor M1 control terminals
Control voltage remains unchanged, and the time delay of the second time delay module 12 is constant.
The second situation is phase mismatch, and CK90 phases are advanced, with reference to figure 7a and Fig. 7 b, Fig. 7 a for CK90 phases it is advanced when
Four orthogonal clock sequence diagrams, Fig. 7 b are that four orthogonal clocks that Fig. 7 a are provided are illustrated by high speed and the duty cycle after door
Figure.
CK90 phases are advanced, then CK0 and CK90 by the first high speed with behind the door, duty cycle as shown in Figure 7b, more than 1/4.
If high level is Vh, low level 0, CK0 and CK90 by the first high speed with after door and filtering, it is big that it produces DC voltage V3
In Vh/4.For CK180 and CK270 after the second high speed AND gate circuit, duty cycle is more than 1/4.CK180 and CK270 passes through second
At a high speed with after door and filtering, its produce DC voltage V4 be more than Vh/4.In this way, the DC voltage U1 produced on capacitance C1 is more than
Vh/2。
CK90 phases are advanced, CK0 and CK270 by the 3rd high speed with behind the door, duty cycle as shown in Figure 7b, less than 1/4.Such as
Fruit high level be Vh, low level 0, CK0 and CK270 by the 3rd high speed with after door and filtering, it is small that it produces DC voltage V5
In Vh/4.For CK90 and CK180 after high speed AND gate circuit, duty cycle is less than 1/4.CK90 and CK180 by the 4th high speed with
After door and filtering, it produces DC voltage V6 and is less than Vh/4.In this way, the DC voltage U2 produced on capacitance C2 is less than Vh/2.
Then operational amplifier positive input terminal voltage is more than negative input end voltage, then input dc power pressure difference is on the occasion of passing through
Operational amplifier amplifies this voltage difference, and output control the second gain transistor M2, and the control electricity of pull-up resistor Rs is flowed through in increase
Stream, timing_delay estimation voltage reduce, and the time delay increase of the second time delay module 12, adjusts CK90 branch time delays so that CK90 (CK270)
Increase with CK0 (CK180) phase difference.
The third situation is phase mismatch, CK90 delayed phases, when with reference to figure 8a and Fig. 8 b, Fig. 8 a being CK90 delayed phases
Four orthogonal clock sequence diagrams, Fig. 8 b are that four orthogonal clocks that Fig. 8 a are provided are illustrated by high speed and the duty cycle after door
Figure.
CK90 delayed phases, then CK0 and CK90 by the first high speed with behind the door, duty cycle as shown in Figure 8 b, less than 1/4.
If high level is Vh, low level 0, CK0 and CK90 by the first high speed with after door and filtering, it is small that it produces DC voltage V3
In Vh/4.For CK180 and CK270 after the second high speed AND gate circuit, duty cycle is less than 1/4.CK180 and CK270 passes through second
At a high speed with after door and filtering, its produce DC voltage V4 be less than Vh/4.In this way, the DC voltage U1 produced on capacitance C1 is less than
Vh/2。
CK90 delayed phases, CK0 and CK270 by the 3rd high speed with behind the door, duty cycle as shown in Figure 7b, more than 1/4.Such as
Fruit high level be Vh, low level 0, CK0 and CK270 by the 3rd high speed with after door and filtering, it is big that it produces DC voltage V5
In Vh/4.For CK90 and CK180 after high speed AND gate circuit, duty cycle is more than 1/4.CK90 and CK180 by the 4th high speed with
After door and filtering, it produces DC voltage V6 and is more than Vh/4.In this way, the DC voltage U2 produced on capacitance C2 is more than Vh/2.
Then operational amplifier positive input terminal voltage is less than negative input end voltage, then input dc power pressure difference is negative value, is passed through
Operational amplifier amplifies this voltage difference, and output control the second gain transistor M2, reduces the control electricity for flowing through pull-up resistor Rs
Stream, the increase of timing_delay estimation voltage, the time delay of the second time delay module 12 reduce, and adjust CK90 branch time delays so that CK90 (CK270)
Reduce with CK0 (CK180) phase difference.
In short, if the time delay of CK90 paths is less than normal, i.e., CK0 and CK90 phase differences are less than 90 degree, then CK0＆CK90+
The duty cycle of CK180＆CK270 is more than the duty cycle of CK0＆CK270+CK90＆CK180, amplifier output voltage rise, time delay control
Voltage processed reduces, phase difference increase.
If the time delay of CK90 paths is bigger than normal, i.e., CK0 and CK90 phase differences are more than 90 degree, then CK0＆CK90+CK180＆
The duty cycle of CK270 is less than the duty cycle of CK0＆CK270+CK90＆CK180, and amplifier output voltage reduces, timing_delay estimation voltage
Rise, phase difference reduce.
That is, phase feedback circuit can give CK90 paths appropriate time delay, so that the phase difference for ensureing CK0 and CK90 is 90
Degree, and then ensure to export four road ideal quadrature signals.
With reference to figure 9, Fig. 9 is the structure diagram of high speed AND gate circuit provided in an embodiment of the present invention.In the present embodiment, it is
Ensure the accuracy of phase, the first high speed used and door, the second high speed and door, the 3rd high speed and door and the 4th high speed
The circuit structure identical with Men Douwei, optionally, each high speed AND gate circuit include respectively：
First PMOS tube M3, the first NMOS tube M4 and the second NMOS tube M5, the first connecting pin of the first PMOS tube M3 and the
Two high level end V2 are electrically connected, and second connection end is electrically connected with the first connecting pin of the first NMOS tube M4；First NMOS tube M4's
Second connection end is electrically connected with the first connecting pin of the second NMOS tube M5；The second connection end ground connection of second NMOS tube M5；
Second PMOS tube M6, the 3rd NMOS tube M7 and the 4th NMOS tube M8, the first connecting pin of the second PMOS tube M6 and the
Two high level end V2 are electrically connected, and second connection end is electrically connected with the first connecting pin of the 3rd NMOS tube M7；3rd NMOS tube M7's
Second connection end is electrically connected with the first connecting pin of the 4th NMOS tube M8；The second connection end ground connection of 4th NMOS tube；
3rd PMOS tube M9 and the 5th NMOS tube M10, the first connecting pin of the 3rd PMOS tube M9 and the second high level end V2
It is electrically connected, second connection end is electrically connected with the first connecting pin of the 5th NMOS tube M10；The second connection end of 5th NMOS tube M10
Ground connection；
Wherein, the first connecting pin of the first NMOS tube M4, the first connecting pin of the 3rd NMOS tube M7, the 3rd PMOS tube M9
Control terminal and the control terminal of the 5th NMOS tube M10 are electrically connected two-by-two；
The first input end A of high speed AND gate circuit respectively with the first PMOS tube M3, the first NMOS tube M4 and the 4th NMOS tube
The control terminal of M8 is electrically connected, the second input terminal B controls with the second PMOS tube M6, the second NMOS tube M5 and the 3rd NMOS tube M7 respectively
End processed is electrically connected；
The output terminal F of high speed AND gate circuit is electrically connected with the first connecting pin of the 5th NMOS tube M10.
The first input end A of high speed AND gate circuit and the second input terminal B are respectively used to by Orthogonal phase detection module 13
Input terminal access high-speed clock signal after delay process, high speed AND gate circuit is used for first input end A and second
The high-speed clock signal of input terminal B inputs carries out logic and operation, and is exported to filter circuit and be filtered by output terminal F.
Exemplary, with reference to figure 5, if high speed AND gate circuit is the first high speed AND gate circuit 1311, first input end A and quadrature phase
The first input end CK0 of detection module 13 is electrically connected, the second input terminal B and the second input terminal of Orthogonal phase detection module 13
CK90 is electrically connected, and output terminal F is electrically connected with the first filter circuit 1313.Understand that high speed AND gate circuit is holohedral symmetry knot with reference to figure 9
Structure, when first input end A and the second input terminal B the input phases with signal when, first input end A and the second input terminal B are complete
Equivalent, signal response is just the same.Then the high speed AND gate circuit in the present embodiment realizes electricity by good physical Design
It is of good performance symmetrical, the logic and operation of high speed signal can be carried out, and improve phase-detection accuracy rate.
And now common AND gate circuit is as shown in Figure 10, Figure 10 is that low speed AND gate circuit structure of the prior art is illustrated
Figure, the structure of the AND gate circuit shown in Figure 10 is asymmetric, unobvious when low speed is run, but during input high speed signal,
Low speed AND gate circuit introduces phase error in itself.As shown in Figure 10, the control terminal of input terminal A and PMOS tube M11 and NMOS tube M13
It is electrically connected, input terminal B is electrically connected with the control terminal of PMOS tube M12 and NMOS tube M14, although PMOS tube M11 and M12 are and are coupled
Structure, can realize equivalent, but NMOS tube M13 and M14 are series relationship, and M13 and M14 respectively hold operating point and loading condition complete
Difference, output signal response is not exclusively the same, error just occurs when inputting high speed signal, so described in the present embodiment
High speed AND gate circuit does not introduce detection error, is conducive to obtain accurately orthogonal high-speed clock signal.
High-frequency clock IQ phase calibration circuit described in the embodiment of the present invention, is produced by negative feedback control orthogonal clock
The timing_delay estimation voltage (belonging to low frequency signal) of circuit, so as to control high-frequency clock phase (ultra high speed signal), is believed by low frequency
Number control high-frequency signal；Whole calibration circuit, in addition to four simple high speed AND gate circuits, without other high speed circuits, reduces
Power consumption；It is not required big component and the outer high-quality-factor device of piece in piece, it is fully integrated in suitable sheets, and cost is low, is adapted to
Volume production.
Note that it above are only presently preferred embodiments of the present invention and institute's application technology principle.It will be appreciated by those skilled in the art that
The invention is not restricted to specific embodiment described here, can carry out for a person skilled in the art various obvious changes,
Readjust, be combined with each other and substitute without departing from protection scope of the present invention.Therefore, although by above example to this
Invention is described in further detail, but the present invention is not limited only to above example, is not departing from present inventive concept
In the case of, other more equivalent embodiments can also be included, and the scope of the present invention is determined by scope of the appended claims.
Claims (10)
- A kind of 1. high-frequency clock IQ phase calibration circuit, it is characterised in that including：First time delay module, the second time delay module And Orthogonal phase detection module；The input terminal of first time delay module is electrically connected with the first signal end, output terminal and the Orthogonal phase detection module First input end is electrically connected, for the first signal to be carried out delay process；The input terminal of second time delay module and the second letter Number end be electrically connected, output terminal is electrically connected with the second input terminal of the Orthogonal phase detection module, for secondary signal to be carried out Delay process；The Orthogonal phase detection module is respectively according to the first signal and the second signal after delay process, by described first Signal and the phase difference of secondary signal are converted to timing_delay estimation voltage, and the timing_delay estimation voltage is passed through the quadrature phase The output terminal of detection module is exported to second time delay module, to adjust the time delay of second time delay module.
- 2. high-frequency clock IQ phase calibration circuit according to claim 1, it is characterised in that：First time delay module includes multiple phase inverters being sequentially connected in series, and the input terminal of the first phase inverter prolongs by described first When module input terminal be electrically connected with first signal end, the output terminal of last bit Inverting device passes through first time delay module Output terminal is electrically connected with the first input end of the Orthogonal phase detection module；Wherein, the cold end of each phase inverter with Ground terminal is electrically connected；Second time delay module includes the phase inverter that is sequentially connected in series identical with the first time delay module number, the first anti-phase The input terminal of device is electrically connected by the input terminal of second time delay module with the secondary signal end, the output of last bit Inverting device End is electrically connected by the output terminal of second time delay module with the second input terminal of the Orthogonal phase detection module；Wherein, The cold end of each phase inverter is electrically connected by the first gain transistor with ground terminal.
- 3. high-frequency clock IQ phase calibration circuit according to claim 2, it is characterised in that：The output terminal of the Orthogonal phase detection module is electrically connected with the control terminal of first gain transistor, for exporting Timing_delay estimation voltage is stated to first gain transistor to control the time delay of second time delay module.
- 4. high-frequency clock IQ phase calibration circuit according to claim 1, it is characterised in that further include：First is reverse Module and the second reverse module；The input terminal of the first reverse module is electrically connected with the output terminal of first time delay module, output terminal with it is described orthogonal 3rd input terminal of phase detecting module is electrically connected, for first signal after delay process to be converted to the 3rd signal；The input terminal of the second reverse module is electrically connected with the output terminal of second time delay module, output terminal with it is described orthogonal 4th input terminal of phase detecting module is electrically connected, for the secondary signal after delay process to be converted to the 4th signal.
- 5. high-frequency clock IQ phase calibration circuit according to claim 4, it is characterised in that：The first reverse module includes a phase inverter, and the input terminal of the phase inverter passes through the defeated of the described first reverse module Enter end to be electrically connected with the output terminal of first time delay module, output terminal by the output terminal of the described first reverse module with it is described 3rd input terminal of Orthogonal phase detection module is electrically connected；The second reverse module includes a phase inverter, and the input terminal of the phase inverter passes through the defeated of the described second reverse module Enter end to be electrically connected with the output terminal of second time delay module, output terminal by the output terminal of the described second reverse module with it is described 4th input terminal of Orthogonal phase detection module is electrically connected.
- 6. high-frequency clock IQ phase calibration circuit according to claim 4, it is characterised in that the Orthogonal phase detection Module includes：First converting unit, the second converting unit, operational amplifier and the second gain transistor；The input terminal of first converting unit is electrically connected with four input terminals of Orthogonal phase detection module respectively, for by One signal and secondary signal carry out logic and operation, and the 3rd signal and the 4th signal are carried out logic and operation；And by two-way The signal that logic and operation obtains is filtered to be handled with adduction, obtains the first direct current signal；The input terminal of second converting unit is electrically connected with four input terminals of Orthogonal phase detection module respectively, for by One signal and the 4th signal carry out logic and operation, and secondary signal and the 3rd signal are carried out logic and operation；And by two-way The signal that logic and operation obtains is filtered to be handled with adduction, obtains the second direct current signal；The positive input terminal and negative input end of the operational amplifier are single with first converting unit and second conversion respectively The output terminal of member is electrically connected, for the difference of first direct current signal and second direct current signal to be amplified processing simultaneously Export to the control terminal of second gain transistor；First connecting pin of second gain transistor connects the first high level end by pull-up resistor, and second connection end is grounded, First connecting pin is additionally operable to be electrically connected with second time delay module by the output terminal of the Orthogonal phase detection module, For by the timing_delay estimation voltage output that the first connecting pin exports to second time delay module.
- 7. high-frequency clock IQ phase calibration circuit according to claim 6, it is characterised in that first converting unit Including：First high speed and door, the second high speed and door and the first filter circuit；First high speed and the input terminal of door are electric with the first input end of the Orthogonal phase detection module and the second input terminal respectively Connection, output terminal is electrically connected with the first input end of first filter circuit, for by the first signal and the second signal Carry out logic and operation and export to the first filter circuit；Second high speed and the input terminal of door are electric with the 3rd input terminal of the Orthogonal phase detection module and the 4th input terminal respectively Connection, output terminal is electrically connected with the second input terminal of first filter circuit, for by the 3rd signal and the 4th signal Carry out logic and operation and export to the first filter circuit；The output terminal of first filter circuit is electrically connected with the positive input terminal of the operational amplifier, for by the first high speed with Door and the output signal of the second high speed and door are filtered and handle to obtain first direct current signal with adduction.
- 8. high-frequency clock IQ phase calibration circuit according to claim 7, it is characterised in that second converting unit Including：3rd high speed and door, the 4th high speed and door and the second filter circuit；3rd high speed and the input terminal of door are electric with the first input end of the Orthogonal phase detection module and the 4th input terminal respectively Connection, output terminal is electrically connected with the first input end of second filter circuit, for by first signal and the 4th signal Carry out logic and operation and export to the second filter circuit；4th high speed and the input terminal of door are electric with the second input terminal of the Orthogonal phase detection module and the 3rd input terminal respectively Connection, output terminal is electrically connected with the second input terminal of second filter circuit, for by the secondary signal and the 3rd signal Carry out logic and operation and export to the second filter circuit；The output terminal of second filter circuit is electrically connected with the negative input end of the operational amplifier, for by the 3rd high speed with Door and the output signal of the 4th high speed and door are filtered and handle to obtain second direct current signal with adduction.
- 9. high-frequency clock IQ phase calibration circuit according to claim 8, it is characterised in that：First filter circuit includes：First resistor, second resistance and the first capacitance；First connecting pin of the first resistor is electrically connected with the first input end of first filter circuit, second connection end with The second connection end of the second resistance is electrically connected, and the of the first connecting pin of the second resistance and first filter circuit Two input terminals are electrically connected；The second connection end of the first resistor by the first capacity earth, and with first filter circuit Output terminal be electrically connected；Second filter circuit includes：3rd resistor, the 4th resistance and the second capacitance；First connecting pin of the 3rd resistor is electrically connected with the first input end of second filter circuit, second connection end with The second connection end of 4th resistance is electrically connected, and the of the first connecting pin of the 4th resistance and second filter circuit Two input terminals are electrically connected；The second connection end of the 3rd resistor by the second capacity earth, and with second filter circuit Output terminal be electrically connected.
- 10. the high-frequency clock IQ phase calibration circuit according to claim 7 or 8, it is characterised in that each electric with door at a high speed Road includes respectively：First PMOS tube, the first NMOS tube and the second NMOS tube, the first connecting pin of first PMOS tube and described second high Level terminal is electrically connected, and second connection end is electrically connected with the first connecting pin of first NMOS tube；The of first NMOS tube Two connecting pins are electrically connected with the first connecting pin of second NMOS tube；The second connection end ground connection of second NMOS tube；Second PMOS tube, the 3rd NMOS tube and the 4th NMOS tube, the first connecting pin of second PMOS tube and described second high Level terminal is electrically connected, and second connection end is electrically connected with the first connecting pin of the 3rd NMOS tube；The of 3rd NMOS tube Two connecting pins are electrically connected with the first connecting pin of the 4th NMOS tube；The second connection end ground connection of 4th NMOS tube；3rd PMOS tube and the 5th NMOS tube, the first connecting pin and the second high level end of the 3rd PMOS tube are electrically connected Connect, second connection end is electrically connected with the first connecting pin of the 5th NMOS tube；The second connection end of 5th NMOS tube connects Ground；Wherein, the first connecting pin of first NMOS tube, the first connecting pin of the 3rd NMOS tube, the control terminal of the 3rd PMOS tube It is electrically connected two-by-two with the control terminal of the 5th NMOS tube；The first input end of the high speed AND gate circuit respectively with first PMOS tube, the first NMOS tube and the 4th NMOS tube Control terminal is electrically connected, and the second input terminal is electric with the control terminal of second PMOS tube, the second NMOS tube and the 3rd NMOS tube respectively Connection；The output terminal of the high speed AND gate circuit is electrically connected with the first connecting pin of the 5th NMOS tube.
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| US11979149B2 (en) | 2020-06-24 | 2024-05-07 | Inspur Suzhou Intelligent Technology Co., Ltd. | Phase self-correction circuit |
| CN114003542A (en) * | 2021-11-09 | 2022-02-01 | 合肥联宝信息技术有限公司 | Signal conditioner, signal conditioning method, electronic device, and storage medium |
| CN114003542B (en) * | 2021-11-09 | 2024-05-31 | 合肥联宝信息技术有限公司 | Signal conditioner, signal conditioning method, electronic device, and storage medium |
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