CN114003542B - Signal conditioner, signal conditioning method, electronic device, and storage medium - Google Patents
Signal conditioner, signal conditioning method, electronic device, and storage medium Download PDFInfo
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Abstract
The present disclosure provides a signal conditioner, a signal conditioning method, an electronic device, and a storage medium, wherein the signal conditioner includes: the power conversion module is used for receiving a first input detection signal and a second input detection signal, respectively performing power conversion on the first input detection signal and the second input detection signal, and correspondingly obtaining a first output detection signal and a second output detection signal; the signal enhancement module is used for executing signal enhancement operation according to the received enabling signal; the control module is used for determining detection time according to the first input detection signal, the first output detection signal, the second input detection signal and the second output detection signal; and the signal loss detector is used for detecting the voltage of the first output detection signal and the second output detection signal at the detection time and outputting the enabling signal according to the voltage so as to enable the signal enhancement module. The present disclosure can improve the accuracy of device monitoring.
Description
Technical Field
The present disclosure relates to the field of signal processing technologies, and in particular, to a signal conditioner, a signal conditioning method, an electronic device, and a storage medium.
Background
At present, the USB3.2 has the characteristics of high speed and multiple supporting devices, and is widely applied to various electronic devices. However, the requirements of the USB3.2 on the frame of the electronic device are very strict, the wiring length is required to be short, and if the wiring length is too long, a USB3.2 signal conditioner (Re-Driver or Re-timer) is required to be added to enhance the driving capability of the signal. Compared with Re-timer, the USB3.2 Re-Driver has simple design and low price, and is the first choice for many design and development. However, in the process of using a signal conditioner (such as USB3.2 Re-Driver), a problem that the device is not connected or the device system is pulled out is often encountered, resulting in misoperation of the device.
Disclosure of Invention
The disclosure provides a signal regulator, a signal regulating method, electronic equipment and a storage medium, which can correct the detection time of a signal and can realize accurate judgment of the connection or disconnection of external equipment.
The present disclosure provides a signal conditioner comprising:
The power conversion module is used for receiving a first input detection signal and a second input detection signal, respectively performing power conversion on the first input detection signal and the second input detection signal, and correspondingly obtaining a first output detection signal and a second output detection signal;
The signal enhancement module is used for executing signal enhancement operation according to the received enabling signal;
The control module is used for determining detection time according to the first input detection signal, the first output detection signal, the second input detection signal and the second output detection signal;
And the signal loss detector is used for detecting the voltage of the first output detection signal and the second output detection signal at the detection time and outputting the enabling signal according to the voltage so as to enable the signal enhancement module.
In some possible embodiments, the signal loss detector is further configured to output a first signal controlling the signal enhancement module to turn off a signal enhancement operation if the voltage of the first output detection signal and the second output detection signal at the detection time are the same;
And/or outputting a second signal controlling the signal enhancing module to enable a signal enhancing operation in case that the voltages of the first output detecting signal and the second output detecting signal at the detecting time are different.
In some possible embodiments, the control module includes:
A timer unit for obtaining a first time difference according to the first input detection signal and the first output detection signal, and obtaining a second time difference according to the second input detection signal and the second output detection signal;
A comparison unit for obtaining a third time difference between the first time difference and the second time difference;
And the determining unit is used for determining bias time according to the first time difference, the second time difference and the third time difference and determining the detection time based on the bias time.
In some possible embodiments, the determining unit is further configured to obtain a binary code using a bias time corresponding to the third time difference, and determine the detection time using the binary code.
In some possible embodiments, the determining unit is further configured to:
Determining that the offset time is zero and a binary code sequence corresponding to the zero offset time is a reference binary code when the first time difference, the second time difference and the third time difference meet a first condition;
And under the condition that the first time difference, the second time difference and the third time difference do not meet the first condition, determining the corresponding binary code in the preset relation between the offset time and the binary code by utilizing the third time difference.
In some possible embodiments, the first condition includes: the first time difference, the second time difference, and the third time difference are all less than a time threshold.
In some possible implementations, the determining unit is further configured to perform digital-to-analog conversion on the binary code to convert the binary code into the detection time.
According to another aspect of the present disclosure, there is provided a signal conditioning method, including:
Receiving a first input detection signal and a second input detection signal, and respectively performing power conversion on the first input detection signal and the second input detection signal to correspondingly obtain a first output detection signal and a second output detection signal;
Determining a detection time according to a time difference between the first input detection signal and the first output detection signal and a time difference between the second input detection signal and the second output detection signal;
Detecting the voltage of the first output detection signal and the second output detection signal at the detection time, and outputting an enabling signal according to the voltage;
And performing signal enhancement operation of the first output detection signal and the second output detection signal according to the enabling.
According to another aspect of the present disclosure, there is provided an electronic device, including:
A processor;
a memory for storing processor-executable instructions;
Wherein the processor is configured to invoke the instructions stored by the memory to perform the signal conditioning method.
According to another aspect of the present disclosure, a computer-readable storage medium is provided, on which computer program instructions are stored, which, when executed by a processor, implement the signal conditioning method.
In the embodiment of the disclosure, two paths of input detection signals can be received, two paths of output detection signals are correspondingly generated, the detection time is determined based on the time difference between the input detection signals and the output detection signals, whether external equipment is accessed currently or not is determined by utilizing the voltage values corresponding to the detection time of the two paths of output signals, a signal enhancement module is enabled, and signal enhancement processing is executed. The method and the device can correct the detection time through the time difference between the detection signals, and improve the monitoring accuracy of the external equipment.
Drawings
FIG. 1 is a schematic diagram of a prior art misjudgment;
FIG. 2 is a block diagram of a signal conditioner according to an embodiment of the present disclosure;
FIG. 3 is a circuit schematic of a signal conditioner according to an embodiment of the present disclosure;
FIG. 4 is a flow chart of a signal conditioning method according to an embodiment of the present disclosure;
FIG. 5 is a block diagram of an electronic device according to an embodiment of the present disclosure;
fig. 6 is a block diagram of a storage medium according to an embodiment of the present disclosure.
Detailed Description
Various exemplary embodiments, features and aspects of the disclosure will be described in detail below with reference to the drawings. In the drawings, like reference numbers indicate identical or functionally similar elements. Although various aspects of the embodiments are illustrated in the accompanying drawings, the drawings are not necessarily drawn to scale unless specifically indicated.
The word "exemplary" is used herein to mean "serving as an example, embodiment, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.
The term "and/or" is herein merely an association relationship describing an associated object, meaning that there may be three relationships, e.g., a and/or B, may represent: a exists alone, A and B exist together, and B exists alone. In addition, the term "at least one" herein means any one of a plurality or any combination of at least two of a plurality, for example, including at least one of A, B, C, may mean including any one or more elements selected from the group consisting of A, B and C.
Furthermore, numerous specific details are set forth in the following detailed description in order to provide a better understanding of the present disclosure. It will be understood by those skilled in the art that the present disclosure may be practiced without some of these specific details. In some instances, methods, means, elements, and circuits well known to those skilled in the art have not been described in detail in order not to obscure the present disclosure.
The signal conditioner provided by the embodiment of the disclosure can be applied to any electronic device, such as an electronic device with a USB3.2 port, and is used for performing signal conditioning processing, such as signal enhancement or signal attenuation, when external device access exists in the USB3.2 port. The electronic device may be a User Equipment (UE), a mobile device, a User terminal, a cellular phone, a cordless phone, a Personal digital assistant (Personal DIGITAL ASSISTANT, PDA), a handheld device, a computing device, an in-vehicle device, a wearable device, or the like. In some possible implementations, the corresponding signal conditioning method may be implemented by way of a processor invoking computer readable instructions stored in a memory.
It will be appreciated that the above-mentioned method embodiments of the present disclosure may be combined with each other to form a combined embodiment without departing from the principle logic, and are limited to the description of the present disclosure.
Fig. 2 shows a block diagram of a signal conditioner according to an embodiment of the present disclosure, fig. 3 shows a circuit schematic of the signal conditioner according to an embodiment of the present disclosure, as shown in fig. 2 and 3, including:
The power conversion module 10 is configured to receive a first input detection signal and a second input detection signal, and perform power conversion on the first input detection signal and the second input detection signal, respectively, to obtain a first output detection signal and a second output detection signal, respectively;
a signal enhancement module 20 for performing a signal enhancement operation according to the received enable signal;
A control module 30 for determining a detection time based on a first time difference between the first input detection signal and the first output detection signal and a time difference between the second input detection signal and the second output detection signal;
and a signal loss detector 40 for detecting voltages of the first and second output detection signals at the detection time and outputting the enable signal according to the voltages to enable the signal enhancement module.
In the prior art, the first output detection signal and the second output detection signal are directly compared, and when the voltages are different, it is determined that the external device is connected or disconnected. Fig. 1 is a schematic diagram showing a case where misjudgment occurs in the prior art. Wherein, CRU1, CRU2, KGU represent three sets of conditions of judging the detection signals respectively, and the middle vertical dashed line is the detection time. It can be seen that, in the detection signals of the CRU1 and the CRU2 sets, when the voltages between the two output detection signals RX1 and RX2 are different, it is determined that there is a device on or a device off, and only when the voltages of the two output detection signals of the KGU are the same, it is not determined that the device is in an on or off state, and this case ignores the difference of the detection signals in the transmission process, which is easy to cause misjudgment.
In the embodiment of the disclosure, the control module is utilized to correct the detection time, so as to obtain accurate voltage detection time and reduce misjudgment. The specific procedure is as described in the examples below.
The power conversion module 10 of the embodiment of the present disclosure can receive a detection signal sent by a motherboard, where the detection signal is a periodic digital or analog signal, rises rapidly at an initial stage of the signal, and is maintained for a period of time after reaching a preset voltage, and an interval of the periodic signal and a voltage value of the preset voltage can be set according to requirements, and fig. 1 shows waveforms of the embodiment of the present disclosure, but is not limited to this embodiment.
The two input ends RXP, RXN of the signal regulator receive two paths of transmitted detection signals respectively, namely a first input detection signal and a second input detection signal. The detection signal has signal loss in the transmission process, so that signal recovery needs to be performed on the received first input detection signal and the received second input detection signal, and the power conversion module receives the two paths of detection signals (the first input detection signal and the second input detection signal) respectively and recovers the voltage values of the first input detection signal and the second input detection signal to initial voltages to obtain a first output detection signal and a second output detection signal. Wherein the initial voltage may be any voltage value in the interval of 0.4V-0.6V, the present disclosure is set to 0.6V, but is not particularly limited thereto. The power conversion module may include a signal amplifier such as a power amplifier.
Since the signal is not only lost but also may generate a delay in the transmission process, the control module 20 of the present disclosure may determine the detection time according to the first input detection signal, the first output detection signal, and the second input detection signal and the second output detection signal.
The control module 20 may determine the detection time for detecting whether the device is connected by using the time delay (first time difference) between the first output detection signal and the first input detection signal, the time delay (second time difference) between the second output detection signal and the second input detection signal, and the time difference (third time difference) between the first time difference and the second time difference.
Specifically, the control module 20 of the present disclosure includes: a timer unit, a comparing unit and a determining unit. The timer unit is used for obtaining a first time difference according to the first input detection signal and the first output detection signal, and obtaining a second time difference according to the second input detection signal and the second output detection signal. The determining of the first time difference and the second time difference may be performed by using the feature point of the detection signal, for example, a first time of the signal trip point in the first input detection signal and a second time of the signal trip point in the first output detection signal may be stored, and a difference between the second time and the first time is used as the first time difference. The selection of the feature point is not particularly limited, and any point in the signal may be used as the feature point. Correspondingly, the difference between the third time of the signal jump point in the second output detection signal and the fourth time of the signal jump point in the second input detection signal can be used as the second time difference. The comparison unit may be adapted to obtain a third time difference between said first time difference and said second time difference. The determining unit may determine a bias time according to the first time difference, the second time difference, and the third time difference, and determine the detection time based on the bias time.
Specifically, the determining unit may obtain a binary code using the offset time corresponding to the third time difference, and determine the detection time using the binary code. In an embodiment of the present disclosure, the determining unit is further configured to configure a preset relationship between the bias time and the binary code, and includes:
setting positive and negative bias time points at a first interval by taking zero time deviation as a center;
and setting positive and negative binary coding points at a second interval by taking a reference binary code corresponding to zero time deviation as a center, wherein the bias time points correspond to the binary coding points one by one.
Table 1 shows a partial preset relationship, the first column being a binary coded column and the second column being a bias time column, wherein the first interval between bias times is 3ns and the second interval of binary coding is 00000001. According to the I2C standard specification, the Data length Data Byte is 8 bits, the offset can be set to be 3nS first order, 256 steps are taken, 10000000 is defined as 0 offset bit, other bytes are subjected to phase offset, the left offset and the right offset reach more than 380nS, and the specific definition can refer to the following table. The first interval, the second interval, and the maximum value of the encoding length, the bias time, and the like in the table are not particularly limited to the present disclosure, and may be set as required by those skilled in the art.
Table 1 binary coding and offset time correspondence.
| Encoding | Bias time |
| 00000000 | -384ns |
| …… | …… |
| 01111110 | -6ns |
| 01111111 | -3ns |
| 10000000 | 0 |
| 10000001 | +3ns |
| 10000010 | +6ns |
| …… | …… |
| 11111111 | +381ns |
In some embodiments, the determining unit is further configured to determine that the offset time is zero and the binary code sequence corresponding to the zero offset time is the reference binary code, if the first time difference, the second time difference, and the third time difference satisfy a first condition; and under the condition that the first time difference, the second time difference and the third time difference do not meet the first condition, determining the corresponding binary code in the preset relation between the offset time and the binary code by utilizing the third time difference.
Wherein the first condition includes: the first time difference, the second time difference, and the third time difference are all less than a time threshold. In the embodiment of the present disclosure, the time threshold may be a value less than or equal to the first interval, for example, the time threshold of the embodiment of the present disclosure is 3ns. And when the first time difference, the second time difference and the third time difference are smaller than 3ns, determining that the offset time is zero, and the corresponding binary code is the reference binary code 10000000. In the case where the first time difference, the second time difference, and the third time difference do not satisfy the first condition, the binary code corresponding to the third time may be determined using a preset relationship. In the embodiment of the present disclosure, when the third time difference is an integer multiple of the first interval, the third time difference is directly searched in a preset relationship, and the binary code corresponding to the third time difference is directly determined; and under the condition that the ratio of the third time difference to the first interval is a non-integer, adding 1 to the integer part of the ratio and multiplying the first interval to obtain offset time, and further obtaining binary codes by using the offset time.
Further, the determining unit may further perform digital-to-analog conversion on the obtained binary code, and convert the binary code into the detection time. In an embodiment of the present disclosure, the midpoint of the detection signal may be determined as an initial point in time, and the determining unit may include an analog-to-digital conversion module to convert the binary code into a time node, which is a detection time with respect to the initial time.
The signal loss detector 30 may receive information of the detection time, detect voltages of the first output detection signal and the second output detection signal at the detection time, and output the enable signal according to the voltages to enable the signal enhancement module. Under the condition that the voltage of the first output detection signal and the voltage of the second output detection signal at the detection time are the same, the signal loss detector determines that the external equipment is not connected at the moment, and outputs a first signal for controlling the signal enhancement module to execute signal enhancement operation; and/or under the condition that the voltages of the first output detection signal and the second output detection signal at the detection time are different, judging that equipment connection exists at the moment, and outputting a second signal for controlling the signal enhancement module to enable signal enhancement operation. In the disclosed embodiment, the signal loss detector 30 may be connected to the analog/digital conversion module for enhancing the first signal or the second signal transmission value signal by the signal enhancement module 40. If the first signal can be 0, the second signal can be 1.
The signal enhancing module 40 receives the enable signal and selects to perform a signal enhancing operation using the enable signal. The signal enhancing module includes a signal receiving/enhancing unit RX EQ and a signal transmitting unit TX. The signal enhancement module maintains transmission of the line but does not perform signal enhancement processing when the first signal is received, and performs signal enhancement operation and performs transmission of the signal when the second signal is received, so as to complete the signal enhancement processing.
Based on the above configuration, the embodiments of the present disclosure may receive two paths of input detection signals, generate two paths of output detection signals correspondingly, determine a detection time based on a time difference between the input detection signals and the output detection signals, determine whether an external device is currently connected by using voltage values corresponding to the two paths of output signals at the detection time, enable the signal enhancement module, and perform signal enhancement processing. The method and the device can correct the detection time through the time difference between the detection signals, and improve the monitoring accuracy of the external equipment.
In addition, the embodiment of the disclosure also provides a signal conditioning method which can be applied to the signal conditioner. It will be appreciated by those skilled in the art that in the implementation of the above-described apparatus of the specific embodiments, the written order of steps is not meant to imply a strict order of execution but rather should be construed according to the function and possibly inherent logic of the steps.
Fig. 4 shows a flowchart of a signal conditioning method according to an embodiment of the present disclosure. The signal conditioning method comprises the following steps:
S10: receiving a first input detection signal and a second input detection signal, and respectively performing power conversion on the first input detection signal and the second input detection signal to correspondingly obtain a first output detection signal and a second output detection signal;
S20: determining a detection time according to a time difference between the first input detection signal and the first output detection signal and a time difference between the second input detection signal and the second output detection signal;
s30: detecting the voltage of the first output detection signal and the second output detection signal at the detection time, and outputting an enabling signal according to the voltage;
s40: and performing signal enhancement operation of the first output detection signal and the second output detection signal according to the enabling.
In some embodiments, functions or modules included in an apparatus provided by the embodiments of the present disclosure may be used to perform a method described in the foregoing method embodiments, and specific implementations thereof may refer to descriptions of the foregoing method embodiments, which are not repeated herein for brevity.
The disclosed embodiments also provide a computer readable storage medium having stored thereon computer program instructions which, when executed by a processor, implement the above-described method. The computer readable storage medium may be a non-volatile computer readable storage medium.
The embodiment of the disclosure also provides an electronic device, which comprises: a processor; a memory for storing processor-executable instructions; wherein the processor is configured as the method described above.
The electronic device may be provided as a terminal, server or other form of device.
Fig. 5 illustrates a block diagram of an electronic device 800, according to an example embodiment. For example, electronic device 800 may be a mobile phone, computer, digital broadcast terminal, messaging device, game console, tablet device, medical device, exercise device, personal digital assistant, or the like.
Referring to fig. 5, an electronic device 800 may include one or more of the following components: a processing component 802, a memory 804, a power component 806, a multimedia component 808, an audio component 810, an input/output (I/O) interface 812, a sensor component 814, and a communication component 816.
The processing component 802 generally controls overall operation of the electronic device 800, such as operations associated with display, telephone calls, data communications, camera operations, and recording operations. The processing component 802 may include one or more processors 820 to execute instructions to perform all or part of the steps of the methods described above. Further, the processing component 802 can include one or more modules that facilitate interactions between the processing component 802 and other components. For example, the processing component 802 can include a multimedia module to facilitate interaction between the multimedia component 808 and the processing component 802.
The memory 804 is configured to store various types of data to support operations at the electronic device 800. Examples of such data include instructions for any application or method operating on the electronic device 800, contact data, phonebook data, messages, pictures, videos, and so forth. The memory 804 may be implemented by any type or combination of volatile or nonvolatile memory devices such as Static Random Access Memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic or optical disk.
The power supply component 806 provides power to the various components of the electronic device 800. The power components 806 may include a power management system, one or more power sources, and other components associated with generating, managing, and distributing power for the electronic device 800.
The multimedia component 808 includes a screen between the electronic device 800 and the user that provides an output interface. In some embodiments, the screen may include a Liquid Crystal Display (LCD) and a Touch Panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive input signals from a user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensor may sense not only the boundary of a touch or slide action, but also the duration and pressure associated with the touch or slide operation. In some embodiments, the multimedia component 808 includes a front camera and/or a rear camera. When the electronic device 800 is in an operational mode, such as a shooting mode or a video mode, the front camera and/or the rear camera may receive external multimedia data. Each front camera and rear camera may be a fixed optical lens system or have focal length and optical zoom capabilities.
The audio component 810 is configured to output and/or input audio signals. For example, the audio component 810 includes a Microphone (MIC) configured to receive external audio signals when the electronic device 800 is in an operational mode, such as a call mode, a recording mode, and a voice recognition mode. The received audio signals may be further stored in the memory 804 or transmitted via the communication component 816. In some embodiments, audio component 810 further includes a speaker for outputting audio signals.
The I/O interface 812 provides an interface between the processing component 802 and peripheral interface modules, which may be a keyboard, click wheel, buttons, etc. These buttons may include, but are not limited to: homepage button, volume button, start button, and lock button.
The sensor assembly 814 includes one or more sensors for providing status assessment of various aspects of the electronic device 800. For example, the sensor assembly 814 may detect an on/off state of the electronic device 800, a relative positioning of the components, such as a display and keypad of the electronic device 800, the sensor assembly 814 may also detect a change in position of the electronic device 800 or a component of the electronic device 800, the presence or absence of a user's contact with the electronic device 800, an orientation or acceleration/deceleration of the electronic device 800, and a change in temperature of the electronic device 800. The sensor assembly 814 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. The sensor assembly 814 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 814 may also include an acceleration sensor, a gyroscopic sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.
The communication component 816 is configured to facilitate communication between the electronic device 800 and other devices, either wired or wireless. The electronic device 800 may access a wireless network based on a communication standard, such as WiFi,2G, or 3G, or a combination thereof. In one exemplary embodiment, the communication component 816 receives broadcast signals or broadcast related information from an external broadcast management system via a broadcast channel. In one exemplary embodiment, the communication component 816 further includes a Near Field Communication (NFC) module to facilitate short range communications. For example, the NFC module may be implemented based on Radio Frequency Identification (RFID) technology, infrared data association (IrDA) technology, ultra Wideband (UWB) technology, bluetooth (BT) technology, and other technologies.
In an exemplary embodiment, the electronic device 800 may be implemented by one or more Application Specific Integrated Circuits (ASICs), digital Signal Processors (DSPs), digital Signal Processing Devices (DSPDs), programmable Logic Devices (PLDs), field Programmable Gate Arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic elements for executing the methods described above.
In an exemplary embodiment, a non-transitory computer readable storage medium is also provided, such as memory 804 including computer program instructions executable by processor 820 of electronic device 800 to perform the above-described methods.
Fig. 6 illustrates a block diagram of an electronic device 1900, according to an example embodiment. For example, electronic device 1900 may be provided as a server. Referring to FIG. 6, electronic device 1900 includes a processing component 1922 that further includes one or more processors and memory resources represented by memory 1932 for storing instructions, such as application programs, that can be executed by processing component 1922. The application programs stored in memory 1932 may include one or more modules each corresponding to a set of instructions. Further, processing component 1922 is configured to execute instructions to perform the methods described above.
The electronic device 1900 may also include a power component 1926 configured to perform power management of the electronic device 1900, a wired or wireless network interface 1950 configured to connect the electronic device 1900 to a network, and an input/output (I/O) interface 1958. The electronic device 1900 may operate based on an operating system stored in memory 1932, such as Windows Server, mac OS XTM, unixTM, linuxTM, freeBSDTM, or the like.
In an exemplary embodiment, a non-transitory computer readable storage medium is also provided, such as memory 1932, including computer program instructions executable by processing component 1922 of electronic device 1900 to perform the methods described above.
The present disclosure may be a system, method, and/or computer program product. The computer program product may include a computer readable storage medium having computer readable program instructions embodied thereon for causing a processor to implement aspects of the present disclosure.
The computer readable storage medium may be a tangible device that can hold and store instructions for use by an instruction execution device. The computer readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer-readable storage medium would include the following: portable computer disks, hard disks, random Access Memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static Random Access Memory (SRAM), portable compact disk read-only memory (CD-ROM), digital Versatile Disks (DVD), memory sticks, floppy disks, mechanical coding devices, punch cards or in-groove structures such as punch cards or grooves having instructions stored thereon, and any suitable combination of the foregoing. Computer-readable storage media, as used herein, are not to be construed as transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., optical pulses through fiber optic cables), or electrical signals transmitted through wires.
The computer readable program instructions described herein may be downloaded from a computer readable storage medium to a respective computing/processing device or to an external computer or external storage device over a network, such as the internet, a local area network, a wide area network, and/or a wireless network. The network may include copper transmission cables, fiber optic transmissions, wireless transmissions, routers, firewalls, switches, gateway computers and/or edge servers. The network interface card or network interface in each computing/processing device receives computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium in the respective computing/processing device.
The computer program instructions for performing the operations of the present disclosure may be assembly instructions, instruction Set Architecture (ISA) instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source or object code written in any combination of one or more programming languages, including an object oriented programming language such as SMALLTALK, C ++ or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The computer readable program instructions may be executed entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computer (for example, through the Internet using an Internet service provider). In some embodiments, aspects of the present disclosure are implemented by personalizing electronic circuitry, such as programmable logic circuitry, field Programmable Gate Arrays (FPGAs), or Programmable Logic Arrays (PLAs), with state information of computer readable program instructions, which can execute the computer readable program instructions.
Various aspects of the present disclosure are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the disclosure. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer-readable program instructions.
These computer readable program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. These computer readable program instructions may also be stored in a computer readable storage medium that can direct a computer, programmable data processing apparatus, and/or other devices to function in a particular manner, such that the computer readable medium having the instructions stored therein includes an article of manufacture including instructions which implement the function/act specified in the flowchart and/or block diagram block or blocks.
The computer readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the instructions which execute on the computer, other programmable apparatus or other devices implement the functions/acts specified in the flowchart and/or block diagram block or blocks.
The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
The foregoing description of the embodiments of the present disclosure has been presented for purposes of illustration and description, and is not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the various embodiments described. The terminology used herein was chosen in order to best explain the principles of the embodiments, the practical application, or the technical improvement of the technology in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
Claims (6)
1. A signal conditioner comprising:
The power conversion module is used for receiving a first input detection signal and a second input detection signal, respectively performing power conversion on the first input detection signal and the second input detection signal, and correspondingly obtaining a first output detection signal and a second output detection signal;
The signal enhancement module is used for executing signal enhancement operation according to the received enabling signal;
The control module is used for determining detection time according to the first input detection signal, the first output detection signal, the second input detection signal and the second output detection signal;
A signal loss detector for detecting voltages of the first output detection signal and the second output detection signal at the detection time, and outputting the enable signal according to the voltages to enable the signal enhancement module;
The control module includes:
A timer unit for obtaining a first time difference according to the first input detection signal and the first output detection signal, and obtaining a second time difference according to the second input detection signal and the second output detection signal;
A comparison unit for obtaining a third time difference between the first time difference and the second time difference;
a determining unit configured to determine a bias time according to the first time difference, the second time difference, and the third time difference, and determine the detection time based on the bias time;
the determining unit is further configured to obtain a binary code using the offset time corresponding to the third time difference, and determine the detection time using the binary code;
the determining unit is further configured to:
Determining that the offset time is zero and a binary code sequence corresponding to the zero offset time is a reference binary code when the first time difference, the second time difference and the third time difference meet a first condition;
Determining a binary code corresponding to a preset relation between offset time and binary code by utilizing the third time difference under the condition that the first time difference, the second time difference and the third time difference do not meet the first condition;
the first condition includes: the first time difference, the second time difference, and the third time difference are all less than a time threshold.
2. The signal conditioner of claim 1, wherein the signal loss detector is further configured to output a first signal that controls the signal enhancement module to turn off a signal enhancement operation if the first output detection signal and the second output detection signal have the same voltage at the detection time;
And/or outputting a second signal controlling the signal enhancing module to enable a signal enhancing operation in case that the voltages of the first output detecting signal and the second output detecting signal at the detecting time are different.
3. The signal conditioner of any one of claims 1-2, wherein the determining unit is further configured to digital-to-analog convert the binary code to the detection time.
4. A method of signal conditioning comprising:
Receiving a first input detection signal and a second input detection signal, and respectively performing power conversion on the first input detection signal and the second input detection signal to correspondingly obtain a first output detection signal and a second output detection signal;
Determining a bias time from a first time difference between the first input detection signal and the first output detection signal, a second time difference between the second input detection signal and the second output detection signal, and a third time difference between the first time difference and the second time difference, and determining a detection time based on the bias time:
Obtaining a binary code according to the offset time corresponding to the third time difference, and determining the detection time according to the binary code:
Determining that the offset time is zero and a binary code sequence corresponding to the zero offset time is a reference binary code when the first time difference, the second time difference and the third time difference meet a first condition;
Determining a binary code corresponding to a preset relation between offset time and binary code by utilizing the third time difference under the condition that the first time difference, the second time difference and the third time difference do not meet the first condition;
the first condition includes: the first time difference, the second time difference and the third time difference are all smaller than a time threshold;
Performing digital-to-analog conversion on the binary code, and converting the binary code into the detection time;
Detecting the voltage of the first output detection signal and the second output detection signal at the detection time, and outputting an enabling signal according to the voltage;
And performing signal enhancement operation of the first output detection signal and the second output detection signal according to the enabling.
5. An electronic device, comprising:
A processor;
a memory for storing processor-executable instructions;
Wherein the processor is configured to invoke the memory-stored instructions to perform the method of claim 4.
6. A computer readable storage medium having stored thereon computer program instructions, which when executed by a processor, implement the method of claim 4.
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