CN110543481B

CN110543481B - Data processing method and device, computer equipment and storage medium

Info

Publication number: CN110543481B
Application number: CN201910785363.3A
Authority: CN
Inventors: 唐平; 葛维; 胡均浩; 李振中; 石玲宁
Original assignee: Unisoc Chongqing Technology Co Ltd
Current assignee: Unisoc Chongqing Technology Co Ltd
Priority date: 2019-08-23
Filing date: 2019-08-23
Publication date: 2022-12-06
Anticipated expiration: 2039-08-23
Also published as: CN110543481A

Abstract

The present disclosure relates to the field of computer technologies, and in particular, to a data processing method, an apparatus, a computer device, and a storage medium, where the method includes: acquiring data to be processed; and according to the data to be processed, carrying out multiple iterative operations by adopting a Hash algorithm to obtain a Hash value, caching corresponding intermediate data after the first n-level logical operation in at least one iterative operation of the multiple iterative operations by one level, wherein n is a positive integer greater than 1. According to the embodiment of the invention, the corresponding intermediate data is cached in one level after the first n levels of logical operation in at least one iterative operation of multiple iterative operations of the hash algorithm, so that the flow level of data caching in the process of realizing the hash algorithm is simplified, the data processing efficiency is improved, and the power consumption of computer equipment is reduced.

Description

Data processing method and device, computer equipment and storage medium

Technical Field

The present disclosure relates to the field of computer technologies, and in particular, to a data processing method and apparatus, a computer device, and a storage medium.

Background

The data processing method comprises the step that the computer equipment calculates the data to be processed by adopting a specified algorithm to obtain the hash value.

In the related art, taking a designated algorithm as an example of hash operation, the data processing method includes: the computer equipment adopts a Hash algorithm to the data to be processed, and iterates and circulates through the multi-stage iteration units to obtain a Hash value.

In the data processing process, a plurality of iteration units are involved, so that the number of pipeline stages of an iteration loop is very large, the data processing speed is slow, and the power consumption of a computer is large.

Disclosure of Invention

In view of this, the present disclosure provides a data processing method, an apparatus, a computer device and a storage medium. The technical scheme is as follows:

according to an aspect of the present disclosure, there is provided a data processing method for use in a computer device, the method including:

acquiring data to be processed;

and according to the data to be processed, carrying out multiple iterative operations by adopting a Hash algorithm to obtain a Hash value, caching corresponding intermediate data after the first n-level logical operation in at least one iterative operation of the multiple iterative operations by one level, wherein n is a positive integer greater than 1.

In a possible implementation manner, the performing, according to the data to be processed, a plurality of iterations by using a hash algorithm to obtain a hash value includes:

in the ith iterative operation of the iterative operations, according to the data to be processed, the hash algorithm is adopted to perform the n-level logical operation of the 1 st-level iterative unit to obtain the intermediate data, the intermediate data is cached, and i is a designated numerical value;

according to the cached intermediate data, performing logic operation and caching corresponding to each lower-level iteration unit to obtain output data of the ith iteration operation;

the output data of the current iterative operation is the input data of the next iterative operation, and the output data of the last iterative operation in the multiple iterative operations is the hash value.

In another possible implementation manner, the method further includes:

and in each iteration operation except the ith iteration operation in the multiple iteration operations, performing logic operation and cache corresponding to each of the multiple stages of iteration units by adopting the Hash algorithm according to the data to be processed to obtain output data of the current iteration operation.

In another possible implementation, the hash Algorithm is Secure Hash Algorithm (SHA) 256.

In another possible implementation manner, an ith iteration operation of the multiple iteration operations involves x levels of iteration units, wherein i is a designated sub-value, and x is a positive integer;

the 1 st stage of the iteration unit of the x stage of iteration unit comprises an n stage of logic operation unit and a first stage of register unit;

the first register unit is used for caching corresponding intermediate data after the operation of the n levels of the logic operation units.

In another possible implementation manner, each of the iteration units in the lower level of the iteration unit of the level 1 includes a level one of the logical operation units and a level one of the second register units;

the lower iteration unit comprises an x-1 level iteration unit positioned at the lower level of the 1 st level iteration unit in the x level iteration unit, and the second register unit is used for caching corresponding intermediate data after the operation of the logic operation unit at the current level.

According to another aspect of the present disclosure, a data processing apparatus for use in a computer device, the apparatus comprising:

the acquisition module is used for acquiring data to be processed;

and the operation module is used for carrying out multiple iterative operations by adopting a Hash algorithm according to the data to be processed to obtain a Hash value, caching corresponding intermediate data after the first n-level logical operation in at least one iterative operation of the multiple iterative operations by one level, wherein n is a positive integer greater than 1.

In a possible implementation manner, the operation module is further configured to perform, in an ith iterative operation of the multiple iterative operations, the n-level logical operation of the 1 st-level iteration unit by using the hash algorithm according to the data to be processed to obtain the intermediate data, and cache the intermediate data, where i is a specified-order value; according to the cached intermediate data, performing logic operation and caching corresponding to each lower iteration unit to obtain output data of the ith iteration operation;

In another possible implementation manner, the operation module is further configured to perform, according to the data to be processed, logic operation and cache corresponding to each of the multiple stages of iteration units by using the hash algorithm in each iteration operation except the ith iteration operation among the multiple iteration operations, so as to obtain output data of the current iteration operation.

In another possible implementation, the hash algorithm is the SHA256 algorithm.

In another possible implementation manner, the ith iterative operation of the multiple iterative operations involves x stages of iterative units, wherein i is a specified numerical value, and x is a positive integer;

the 1 st stage of the iteration unit of the x stage comprises an n stage logic operation unit and a first register unit;

the first register unit is used for caching corresponding intermediate data after the operation of the logic operation unit of the n levels.

In another possible implementation manner, each of the iteration units in the lower level of the iteration unit of the level 1 includes a level of the logical operation unit and a level of a second register unit;

the lower-level iteration unit comprises an x-1-level iteration unit positioned at the lower level of the 1 st-level iteration unit in the x-level iteration unit, and the second register unit is used for caching corresponding intermediate data after the intermediate data is operated by the logic operation unit at the current level.

According to another aspect of the present disclosure, there is provided a computer device including:

a processor;

a memory for storing processor-executable instructions;

wherein the processor is configured to:

acquiring data to be processed;

According to another aspect of the present disclosure, there is provided a non-transitory computer readable storage medium having stored thereon computer program instructions which, when executed by a processor, implement the above-described method.

According to the data processing method and device, the computer device performs multiple iterative operations according to the data to be processed by adopting the Hash algorithm to obtain the Hash value, the corresponding intermediate data after the first n-level logical operations in at least one iterative operation of the multiple iterative operations are cached in a first level, n is a positive integer greater than 1, the flow series of data caching in the implementation process of the Hash algorithm is simplified, the data processing efficiency is improved, and the power consumption of the computer device is reduced.

Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate exemplary embodiments, features, and aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

Fig. 1 shows a schematic structural diagram of a computer device to which an embodiment of the present disclosure relates;

FIG. 2 illustrates a flow chart of a data processing method provided by an exemplary embodiment of the present disclosure;

FIG. 3 shows a schematic structural diagram of a computer device provided by another exemplary embodiment of the present disclosure;

FIG. 4 shows a flow chart of a data processing method provided by another example embodiment of the present disclosure;

FIG. 5 shows a flow chart of a data processing method provided by another exemplary embodiment of the present disclosure;

fig. 6 is a schematic diagram illustrating a data processing method according to another exemplary embodiment of the present disclosure;

fig. 7 shows a schematic structural diagram of an iteration unit provided in another exemplary embodiment of the present disclosure;

fig. 8 is a schematic diagram illustrating a data processing method according to another exemplary embodiment of the present disclosure;

fig. 9 is a schematic diagram illustrating a mapping relationship involved in a data processing method according to another exemplary embodiment of the present disclosure;

fig. 10 is a schematic structural diagram of a data processing apparatus according to an embodiment of the present disclosure;

FIG. 11 is a block diagram illustrating a terminal in accordance with an exemplary embodiment;

FIG. 12 is a block diagram illustrating a server in accordance with an exemplary embodiment.

Detailed Description

Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. In the drawings, like reference numbers can indicate functionally identical or similar elements. While the various aspects of the embodiments are presented in drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

The word "exemplary" is used exclusively herein to mean "serving as an example, embodiment, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

Furthermore, in the following detailed description, numerous specific details are set forth in order to provide a better understanding of the present disclosure. It will be understood by those skilled in the art that the present disclosure may be practiced without some of these specific details. In some instances, methods, means, elements and circuits that are well known to those skilled in the art have not been described in detail so as not to obscure the present disclosure.

In the related art, the hash operation process includes: and the computer equipment adopts a Hash algorithm according to the data to be processed and obtains a Hash value through multi-stage iteration unit iteration circulation for multiple times. Each stage of iteration unit comprises a logic operation unit and a register unit. In a chip with large computational power, the chip is composed of a plurality of iteration units, and the number of flow stages in the iteration cycle process is large, so that the computing speed of computer equipment is low, the data processing efficiency is low, and the power consumption of the computer equipment is large.

The embodiment of the disclosure provides a data processing method, a data processing device, computer equipment and a storage medium, wherein the computer equipment performs multiple iterative operations according to data to be processed by adopting a Hash algorithm to obtain a Hash value, corresponding intermediate data after first n levels of logic operations in at least one iterative operation of the multiple iterative operations are cached for one level, n is a positive integer greater than 1, the pipeline level of data caching in the implementation process of the Hash algorithm is simplified, the data processing efficiency is improved, and the power consumption of the computer equipment is reduced.

Before explaining the embodiments of the present disclosure, an application scenario of the embodiments of the present disclosure is explained. Referring to fig. 1, a schematic structural diagram of a computer device according to an embodiment of the present disclosure is shown.

The computer device comprises a terminal or a server. The terminal is for example a mobile phone or a tablet computer or a laptop portable computer or a desktop computer. The embodiments of the present disclosure do not limit this.

The computer device includes: a processor 11, a receiver 12, a transmitter 13, a memory 14 and a bus 15. The receiver 12, the transmitter 13, and the memory 14 are connected to the processor 11 via buses, respectively.

The processor 11 includes one or more processing cores, and the processor 11 executes software programs and modules to execute the method performed by the access network device in the transmission configuration method provided by the embodiment of the present disclosure.

The receiver 12 and the transmitter 13 may be implemented as a communication component, which may be a communication chip, and the communication chip may include a receiving module, a transmitting module, a modulation and demodulation module, and the like, for modulating and/or demodulating information and receiving or transmitting the information through a wireless signal.

The memory 14 may be used to store software programs and modules.

Memory 14 may store at least one functionally described application module 16.

The receiver 12 is used to perform the functions related to the receiving step in the embodiments of the present disclosure; the processor 11 is used to perform functions related to processing steps in the embodiments of the present disclosure; the transmitter 13 is used to perform the functions related to the transmission step in the embodiments of the present disclosure.

Further, the memory 14 may be implemented by any type or combination of volatile or non-volatile memory devices, such as Static Random Access Memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic or optical disks.

In the following, the data processing method provided by the present disclosure is described by using only an exemplary embodiment.

Referring to fig. 2, a flowchart of a data processing method according to an exemplary embodiment of the disclosure is shown. The present embodiment is exemplified by applying the data processing method to the computer apparatus shown in fig. 1. The data processing method comprises the following steps:

step 201, data to be processed is acquired.

The computer device obtains data to be processed. The data to be processed is data with any length.

Optionally, the type of the data to be processed includes at least one of video data, audio data, picture data, and text data. The present embodiment does not impose any limitation on the type of data to be processed.

Step 202, according to the data to be processed, a hash algorithm is adopted to perform multiple iterative operations to obtain a hash value, the corresponding intermediate data after the first n levels of logical operations in at least one iterative operation of the multiple iterative operations is cached in one level, and n is a positive integer greater than 1.

Optionally, N iterative operations exist in the multiple iterative operations, and the corresponding intermediate data after the first N-level logical operation in each iterative operation of the N iterative operations is cached in one level. Wherein N is a positive integer. According to actual needs, the N iterative operations may be any N continuous or discontinuous iterative operations among multiple iterative operations.

For example, N takes the value of 1 or 2. For example, n is a positive integer greater than 1 and less than 4. The specific values of N and N are not limited in this embodiment.

Illustratively, the multiple iterative operations are 64 iterative operations, N is 2, N is 3, the computer device performs 64 iterative operations by using a hash algorithm according to the data to be processed to obtain a hash value, the 64 iterative operations include 2 iterative operations, and the corresponding intermediate data after the first 3-level logical operation in each iterative operation of the 2 iterative operations is cached in one level.

Alternatively, the above-mentioned logical operation is also referred to as an encryption round operation.

And the intermediate data comprises output data after the first n-stage logic operation in one iteration operation. Illustratively, intermediate data corresponding to the first n-level logical operation in one iterative operation is cached in the 1 st level and used in the logical operation of the next level. I.e. the intermediate data of the level 1 buffer as input data of the lower level. The lower-level logic operation may include a logic operation following the first n-level logic operation, which is concatenated with the first n-level logic operation.

Optionally, the intermediate data further includes n input fields used in the n-level logical operation process. The input field is a word corresponding to the data to be processed, and one word is 32 bits.

The hash value obtained by carrying out multiple iterative operations is a binary value with a fixed length, and the length of the hash value is smaller than that of the data to be processed. The hash value is also called a Message Digest (English) or a hash string.

Optionally, the hash algorithm includes one of an SHA1 algorithm, an SHA224 algorithm, an SHA256 algorithm, an SHA 384 algorithm, and an SHA512 algorithm.

For example, when the hash algorithm is the SHA256 algorithm, according to the data to be processed, the computer device performs multiple iterative operations using the SHA256 algorithm to obtain the hash value, wherein the intermediate data corresponding to the previous n-level logical operations in at least one of the multiple iterative operations is cached in one level.

To sum up, in this embodiment, the computer device performs multiple iterative operations according to the data to be processed by using a hash algorithm to obtain a hash value, the corresponding intermediate data after the first n-level logical operations in at least one iterative operation of the multiple iterative operations is cached in one level, n is a positive integer greater than 1, the pipeline number of data caching in the implementation process of the hash algorithm is simplified, the data processing efficiency is improved, and the power consumption of the computer device is reduced.

Referring to fig. 3, a schematic structural diagram of a computer device provided in another exemplary embodiment of the present disclosure is shown.

The computer device includes a hash input unit 31, a hash calculation unit 32, a hash output unit 33, a variable input unit 34, and a constant input unit 35.

The hash input unit 31 is configured to obtain data to be processed, and send the data to be processed to the hash calculation unit 32.

The hash calculation unit 32 is configured to receive the data input by the hash input unit 31, and perform multiple iterative operations according to the data to be processed by using a hash algorithm to obtain a hash value. And caching the corresponding intermediate data one level after the first n-level logic operation in at least one iterative operation of the iterative operations for a plurality of times.

The hash calculation unit 32 is further configured to perform multiple iterative operations by using a hash algorithm according to the variable input by the variable input unit 34 and the constant input by the constant input unit 35 and according to the data to be processed, so as to obtain a hash value.

Optionally, the hash calculation unit 32 includes a multi-stage iteration unit. The hash calculation unit 32 is further configured to perform, in each iteration operation of the multiple iteration units, a logical operation corresponding to each of the multiple iteration units by using a hash algorithm according to the data to be processed, so as to obtain output data. The output data of each iterative operation is input data of the next iterative operation, and the output data of the last iterative operation in the iterative operations is a hash value.

Optionally, the ith iterative operation of the multiple iterative operations involves x-level iterative units, that is, the ith iterative operation is executed through the x-level iterative units, i is a designated numerical value, and x is a positive integer. Illustratively, i includes at least one specified sub-value. For example, i has a value of 2. The value of i is not limited in this embodiment.

The 1 st level iteration unit of the x level iteration unit comprises an n level logic operation unit and a first level first register unit; the first register unit is used for caching corresponding intermediate data after the operation of the n-level logic operation unit.

Each iteration unit in the lower iteration units of the 1 st level iteration unit comprises a first level logic operation unit and a first level second register unit; the lower iteration unit comprises an x-1 level iteration unit positioned at the lower level of the 1 st level iteration unit in the x level iteration unit, and the second register unit is used for caching corresponding intermediate data after the operation of the logic operation unit at the current level. Under the condition that all levels of iteration units sequentially work in series, the intermediate data cached by the level-1 iteration unit can be provided for the level-2 iteration unit and used as the input of the level-2 iteration unit, the intermediate data cached by the level-2 iteration unit can be provided for the level-3 iteration unit and used as the input of the level-3 iteration unit, and the like.

Referring to fig. 4, a flowchart of a data processing method according to another exemplary embodiment of the disclosure is shown. The present embodiment is exemplified by applying the data processing method to the computer apparatus shown in fig. 1 or fig. 3. The data processing method comprises the following steps:

step 401, the computer device obtains data to be processed.

The computer equipment acquires the data to be processed through the Hash input unit.

It should be noted that, for the process of acquiring the data to be processed by the computer device, reference may be made to relevant details in the foregoing embodiments, and details are not described herein again.

Step 402, the computer device preprocesses data to be processed.

Optionally, the computer device preprocesses the data to be processed through the hash input unit to obtain the preprocessed data. Wherein the preprocessing comprises at least one of binary conversion, bit complement operation, message extension and packet processing.

Optionally, after performing message extension on the data to be processed, the computer device groups the data to be processed into m data blocks with fixed lengths, where m is a positive integer, so that the subsequent computer device performs multiple iterative operations on the m data blocks with fixed lengths by using a hash algorithm with multiple hash values and multiple hash constants.

For example, when the hash algorithm is the SHA256 algorithm, the fixed length is 512 bits (English: bit).

And 403, according to the preprocessed data, in each iterative operation of multiple iterative operations, performing respective corresponding logical operations of multiple stages of iterative units by using a hash algorithm to obtain output data, and caching corresponding intermediate data after the first n-stage logical operations in at least one iterative operation of the multiple iterative operations one stage.

Wherein n is a positive integer greater than 1. The output data of the current iteration operation is the input data of the next iteration operation, and the output data of the last iteration operation in the multiple iteration operations is a hash value.

And caching the corresponding intermediate data one level after the first n-level logic operation in at least one iterative operation of the iterative operations for a plurality of times.

Optionally, the pipeline data cached by the first register unit in the level 1 iteration unit of the x-level iteration unit is used in the logic operation of the lower-level iteration unit. Namely, the output data in the pipeline data of the level 1 buffer serves as the input data of the lower iteration unit.

Optionally, the computer device receives, through the hash calculation unit, the multiple hash values H of the variable input unit and the multiple hash constants K of the constant input unit, and performs multiple iterative operations on the m data blocks with fixed lengths by using the multiple hash values H and the multiple hash constants K through the hash calculation unit.

For convenience of description, the data processing method provided in this embodiment is described below only by taking the hash algorithm including the SHA256 algorithm as an example.

The computer equipment groups the data to be processed into m data blocks with fixed length, for each data block, the computer equipment adopts 8 hash values H with 32 bits and 64 hash constants K with 32 bits to carry out operation of an x-level iteration unit on the data block, wherein x is a positive integer less than 64, namely 64-level logic operation and x-level data cache, and one-time iteration operation can be completed.

In one illustrative example, a computer device divides data M into M512-bit data blocks, which are data block M1, data block M2, data block M3 \8230, and data block Mm, in that order.

The hash value H0 is operated through a first data block M1 to obtain a hash value H1, namely, the first iterative operation is completed, the hash value H1 is operated through a second data block M2 to obtain a hash value H2, namely, the 2 nd iterative operation is completed, the processing is carried out in sequence, and finally, the hash value H is obtained _m+1 The hash value H _m+1 The 8 32 bits of (a) are concatenated into a 256-bit hash value.

Optionally, in the ith iterative operation of the multiple iterative operations, according to the data to be processed, a hash algorithm is used for performing n-level logical operation of the 1 st-level iterative unit to obtain intermediate data, the intermediate data is cached, and i is a designated numerical value; according to the cached intermediate data, performing logic operation and caching corresponding to each lower iteration unit to obtain output data of the ith iteration operation; the output data of the current iteration operation is input data of the next iteration operation, and the output data of the last iteration operation in the multiple iteration operations is a hash value.

Illustratively, i above includes at least one specified sub-value.

Optionally, in each iteration operation except the ith iteration operation in the multiple iteration operations, the computer device performs logic operation and cache corresponding to each of the multiple iteration units by using a hash algorithm according to the data to be processed, so as to obtain output data of the current iteration operation.

For example, the multiple iteration operation is 3 iteration operations, i is 2, n is 3, and the hash algorithm is SHA256 algorithm. In the 1 st iteration operation of the 3 iterations, the computer device performs logic operation and cache corresponding to each of 64 levels of iteration units by using a hash algorithm according to data to be processed, so as to obtain output data of the 1 st iteration operation. And taking the output data of the 1 st iterative operation as the input data of the 2 nd iterative operation, and caching the output data obtained by calculation after the previous 3-level logic operation unit as intermediate data through a first-level first register unit of the 1 st-level iterative unit by the computer equipment according to the data to be processed and the input data in the 2 nd iterative operation. Then, the computer device takes the intermediate data buffered by the level-1 iteration unit as input data of the remaining 61-level iteration units, and performs iteration loop through the logic operation units and the second register units corresponding to the remaining 61-level iteration units, so as to obtain output data of the 2 nd iteration operation. And taking the output data of the 2 nd iterative operation as the input data of the 3 rd iterative operation, and in the 3 rd iterative operation, performing logic operation and cache corresponding to 64 levels of iterative units by using a hash algorithm by the computer equipment according to the input data and the data to be processed to obtain the output data of the 3 rd iterative operation, namely the hash value corresponding to the data to be processed.

Optionally, the computer device performs multiple iterative operations according to the data to be processed by using an SHA256 algorithm to obtain a hash value, and then outputs the hash value meeting the preset condition through the hash output unit.

The preset condition is set by default of the computer equipment or set by user self-definition. For example, the preset condition is that the value of the hash value is greater than a preset threshold. This embodiment is not limited thereto.

In summary, in the embodiment, in the iterative operation corresponding to the specified times of numerical values of the multiple iterative operations, the computer device performs n-level logical operations of the 1 st-level iterative unit by using the hash algorithm according to the data to be processed to obtain intermediate data, caches the intermediate data, and uses the cached intermediate data in lower-level logical operations, thereby simplifying the pipeline levels of data caching in the implementation process of the hash algorithm, improving the data processing efficiency, and reducing the power consumption of the computer device.

In the embodiment, the first iteration unit stages in the iterative operation corresponding to the specified times are merged in the hash operation process, that is, the 1 st iteration unit includes an n-stage logical operation unit and a first register unit, the first register unit is used for caching corresponding intermediate data after the operation of the n-stage logical operation unit, the optimized logical operation unit meets the time sequence requirement, the cost of the storage register unit is saved, the power consumption and the area of computer equipment are further reduced, and the computing power of the computer equipment is improved.

The present embodiment does not impose limitations on the types of data to be processed, hash values, and hash algorithms. In an illustrative example, taking the hash algorithm as the SHA256 algorithm as an example, the data processing method provided by the embodiment of the present disclosure is described, please refer to fig. 5, and the data processing method includes the following steps:

step 501, the computer device performs multiple iterative operations on the block header by using the SHA256 algorithm to obtain a message digest, and caches corresponding intermediate data after the first n-level logical operations in the 2 nd iterative operation of the multiple iterative operations by one level.

In one illustrative example, as shown in FIG. 6, 2 512bit data blocks, a first data block and a second data block, wherein the second data block includes a padding 384bit. The computer equipment carries out three times of iterative operation on the block header to obtain a message abstract of 256 bits. In the 1 st iterative operation, namely an SHA256 stage (english: stage) _0, the computer device performs logic operation and cache corresponding to each of 64-stage iterative units by using an SHA256 algorithm according to the first data block to obtain 256-bit output data of the 1 st iterative operation. Taking the output data of the 1 st iterative operation as the input data of the 2 nd iterative operation, in the preparation stage of the 2 nd iterative operation, namely SHA256 stage _ preparation, according to 256-bit input data and a second data block, the computer equipment obtains 256-bit intermediate data through the calculation of the previous 3-stage logic operation unit of the 1 st-stage iteration unit, and caches the intermediate data through the first-stage first register unit of the 1 st-stage iteration unit. Then, the computer device takes the intermediate data buffered by the level 1 iteration unit as input data of the remaining level 61 iteration units. In SHA256 stage _1 of the 2 nd iterative operation, the computer device performs iterative loop through the respective corresponding logic operation units and second register units of the remaining 61 stages of iteration units to obtain 512-bit output data of the 2 nd iterative operation. The computer device takes the output data of the 2 nd iterative operation as the input data of the 3 rd iterative operation, and in the 3 rd iterative operation, namely SHA256 stage _2, the computer device performs logic operation and cache corresponding to each of 64 levels of iterative units by adopting an SHA256 algorithm according to the input data and a second data block to obtain 256-bit output data of the 3 rd iterative operation, namely a 256-bit message abstract.

Based on the example provided in fig. 6, in the 2 nd iteration operation of the multiple iteration operations, the 1 st iteration unit includes a three-level logic operation unit and a one-level storage register unit, as shown in fig. 7. In fig. 7, the adders, CH, SIGMA0, SIGMA1, and MAJ are all logic units. A. The 8 hash values of B, C, D, E, F, G and H are 8 words of 32 bits, namely H _i-1 (0) To H _i-1 (7) And i is a positive integer with an initial value of 1. These 8 hash values are updated according to a certain rule.

For example, the initial values of the 8 hash values in the first iteration of the plurality of iterations include H0 (0): 6a09e667; h0 (1): bb67ae85; h0 (2): 3c6ef372; h0 (3): a54ff53a; h0 (4): 510e527f; h0 (5): 9b05688c; h0 (6): 1f83d9ab; h0 (7): 5be0cd19.

K _ i is the ith key, i is a positive integer, and is the ith of 64 32-bit hash constants K.

W _ i is the ith word corresponding to the data to be processed, and is the ith word in 64 32-bit words, namely W [0] to W [63]. For each 512bit data block, the computer device constructs the corresponding 64 words of the data block.

Optionally, for each 512-bit data block, the computer device constructs 64 32-bit words corresponding to the data block, including: the computer device breaks the block into 16 32bit words, denoted w [0] to w [15]. That is, the first 16 words of the 64 32-bit words are obtained by decomposing the data block, and the last 48 words are obtained by the preset iterative formula, and are marked as w [16] to w [63].

Based on the structural schematic diagram provided in fig. 7, in the 2 nd iteration operation, the first-stage iteration unit processes the first three-stage logic operation in the 64-stage logic operation through the mapping function round, and a corresponding schematic diagram is shown in fig. 8.

The first-stage iteration unit directly maps and outputs a path without logic operation according to three-stage shift according to a shift mapping relation, maps and outputs a path after only one-stage logic operation or two-stage logic operation according to three-stage shift, and maps and outputs a path after three-stage logic operation, wherein the mapping relation is shown in fig. 9. In fig. 9, the 8 hash values are a, B, C, D, E, F, G, and H in this order. In the 1 st-stage logical operation, the A, B, C, E, F and G do not have logical operation and are mapped according to one-stage shift, the D and H respectively obtain E _ tmp1 and A _ tmp1 through the logical operation, and the E _ tmp1 and the A _ tmp1 are mapped according to one-stage shift. During the second-level logic operation, the A _ tmp1, the A, the B, the E _ tmp1, the E and the F do not have logic operation and are mapped according to one-level shift, the C and the G respectively obtain the E _ tmp2 and the A _ tmp2 through the logic operation, the E _ tmp2 and the A _ tmp2 are mapped according to the one-level shift, and at the moment, 8 hash values are output to be the A _ tmp2, the A _ tmp1, the A, the B, the E _ tmp2, the E _ tmp1, the E and the F in sequence. In the third-level logic operation, the A _ tmp2, the A _ tmp1, the A, the E _ tmp2, the E _ tmp1 and the E have no logic operation and are mapped according to one-level shift, the B and the F respectively obtain E _ tmp3 and A _ tmp3 through the logic operation, the E _ tmp3 and the A _ tmp3 are mapped according to the one-level shift, and at the moment, 8 hash values are output to be the A _ tmp3, the A _ tmp2, the A _ tmp1, the A, the E _ tmp3, the E _ tmp2, the E _ tmp1 and the E in sequence.

The following are embodiments of the apparatus of the present application that may be used to perform embodiments of the method of the present application. For details which are not disclosed in the embodiments of the apparatus of the present application, reference is made to the embodiments of the method of the present application.

Referring to fig. 10, a schematic structural diagram of a data processing apparatus according to an embodiment of the disclosure is shown. The data processing apparatus can be implemented as all or a part of the computer device in fig. 1 by a dedicated hardware circuit, or a combination of hardware and software, and includes: an acquisition module 1010 and an operation module 1020.

An obtaining module 1010, configured to obtain data to be processed;

the operation module 1020 is configured to perform multiple iterative operations by using a hash algorithm according to the data to be processed to obtain a hash value, cache corresponding intermediate data after a first n-level logical operation in at least one iterative operation of the multiple iterative operations by one level, where n is a positive integer greater than 1.

In a possible implementation manner, the operation module 1020 is further configured to, in an ith iterative operation of multiple iterative operations, perform n-level logical operations of a level 1 iterative unit by using a hash algorithm according to data to be processed to obtain intermediate data, and cache the intermediate data, where i is a designated-order value; according to the cached intermediate data, performing logic operation and caching corresponding to each lower iteration unit to obtain output data of the ith iteration operation;

the output data of the current iteration operation is input data of the next iteration operation, and the output data of the last iteration operation in the multiple iteration operations is a hash value.

In another possible implementation manner, the operation module 1020 is further configured to perform, according to the data to be processed, respective corresponding logical operations and cache of the multiple stages of iteration units by using a hash algorithm in each iteration operation except for the ith iteration operation in multiple iteration operations, so as to obtain output data of the current iteration operation.

In another possible implementation, the hash algorithm is the SHA256 algorithm.

In another possible implementation manner, the ith iterative operation of the multiple iterative operations relates to x stages of iterative units, i is a designated numerical value, and x is a positive integer;

the 1 st level iteration unit of the x level iteration unit comprises an n level logic operation unit and a first level first register unit;

the first register unit is used for caching corresponding intermediate data after the operation of the n-level logic operation unit.

In another possible implementation manner, each iteration unit in the lower iteration units of the 1 st level iteration unit comprises a first level logical operation unit and a first level second register unit;

the lower-level iteration unit comprises an x-1-level iteration unit positioned at the lower level of the 1 st-level iteration unit in the x-level iteration unit, and the second register unit is used for caching corresponding intermediate data after the intermediate data are operated by the logic operation unit at the current level.

It should be noted that, when the apparatus provided in the foregoing embodiment implements the functions thereof, the division of each functional module is merely used as an example, and in practical applications, the above function distribution may be completed by different functional modules according to needs, that is, the internal structure of the device is divided into different functional modules, so as to complete all or part of the functions described above. In addition, the apparatus and method embodiments provided in the above embodiments belong to the same concept, and specific implementation processes thereof are described in detail in the method embodiments, which are not described herein again.

Fig. 11 is a block diagram illustrating a terminal 1100 in accordance with an example embodiment. For example, the terminal 1100 can be a mobile phone, a computer, a digital broadcast terminal, a messaging device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, and the like.

Referring to fig. 11, terminal 1100 can include one or more of the following components: processing component 1102, memory 1104, power component 1106, multimedia component 1108, audio component 1110, input/output (I/O) interface 1112, sensor component 1114, and communications component 1116.

The processing component 1102 generally controls overall operation of the terminal 1100, such as operations associated with display, telephone calls, data communications, camera operations, and recording operations. The processing component 1102 may include one or more processors 1120 to execute instructions to perform all or a portion of the steps of the methods described above. Further, the processing component 1102 may include one or more modules that facilitate interaction between the processing component 1102 and other components. For example, the processing component 1102 may include a multimedia module to facilitate interaction between the multimedia component 1108 and the processing component 1102.

Memory 1104 is configured to store various types of data to support operation at terminal 1100. Examples of such data include instructions for any application or method operating on terminal 1100, contact data, phonebook data, messages, pictures, videos, and so forth. The memory 1104 may be implemented by any type or combination of volatile or non-volatile memory devices such as Static Random Access Memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic or optical disks.

Power components 1106 provide power to the various components of terminal 1100. Power components 1106 can include a power management system, one or more power sources, and other components associated with generating, managing, and distributing power for terminal 1100.

The multimedia component 1108 includes a screen between the terminal 1100 and the user that provides an output interface. In some embodiments, the screen may include a Liquid Crystal Display (LCD) and a Touch Panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive an input signal from a user. The touch panel includes one or more touch sensors to sense touch, slide, and gestures on the touch panel. The touch sensor may not only sense the boundary of a touch or slide action, but also detect the duration and pressure associated with the touch or slide operation. In some embodiments, the multimedia component 1108 includes a front facing camera and/or a rear facing camera. The front camera and/or the rear camera may receive external multimedia data when the terminal 1100 is in an operation mode, such as a photographing mode or a video mode. Each front camera and rear camera may be a fixed optical lens system or have a focal length and optical zoom capability.

The audio component 1110 is configured to output and/or input audio signals. For example, the audio component 1110 includes a Microphone (MIC) that is configured to receive external audio signals when the terminal 1100 is in an operational mode, such as a call mode, a recording mode, and a voice recognition mode. The received audio signals may further be stored in the memory 1104 or transmitted via the communication component 1116. In some embodiments, audio assembly 1110 further includes a speaker for outputting audio signals.

The I/O interface 1112 provides an interface between the processing component 1102 and peripheral interface modules, which may be keyboards, click wheels, buttons, etc. These buttons may include, but are not limited to: a home button, a volume button, a start button, and a lock button.

Sensor assembly 1114 includes one or more sensors for providing various aspects of state estimation for terminal 1100. For example, sensor assembly 1114 can detect an open/closed state of terminal 1100, a relative positioning of components such as a display and a keypad of terminal 1100, sensor assembly 1114 can also detect a change in position of terminal 1100 or a component of terminal 1100, the presence or absence of user contact with terminal 1100, an orientation or acceleration/deceleration of terminal 1100, and a change in temperature of terminal 1100. Sensor assembly 1114 may include a proximity sensor configured to detect the presence of nearby objects in the absence of any physical contact. The sensor assembly 1114 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 1114 may also include an acceleration sensor, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

The communication component 1116 is configured to facilitate communication between the terminal 1100 and other devices in a wired or wireless manner. The terminal 1100 may access a wireless network based on a communication standard, such as WiFi,2G or 3G, or a combination thereof. In an exemplary embodiment, the communication component 1116 receives broadcast signals or broadcast related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 1116 also includes a Near Field Communication (NFC) module to facilitate short-range communications. For example, the NFC module may be implemented based on Radio Frequency Identification (RFID) technology, infrared data association (IrDA) technology, ultra Wideband (UWB) technology, bluetooth (BT) technology, and other technologies.

In an exemplary embodiment, the terminal 1100 may be implemented by one or more Application Specific Integrated Circuits (ASICs), digital Signal Processors (DSPs), digital Signal Processing Devices (DSPDs), programmable Logic Devices (PLDs), field Programmable Gate Arrays (FPGAs), controllers, micro-controllers, microprocessors or other electronic components for performing the above-described methods.

In an exemplary embodiment, a non-transitory computer readable storage medium, such as the memory 1104 including computer program instructions executable by the processor 1120 of the terminal 1100 to perform the above-described method, is also provided.

Fig. 12 is a block diagram illustrating a server 1200 in accordance with an example embodiment. The server 1200 includes a processing component 1222 that further includes one or more processors, and memory resources, represented by memory 1232, for storing instructions, such as application programs, that are executable by the processing component 1222. The application programs stored in memory 1232 may include one or more modules that each correspond to a set of instructions. Further, the processing component 1222 is configured to execute instructions to perform the above-described methods.

The server 1200 may also include a power component 1226 configured to perform power management of the server 1200, a wired or wireless network interface 1250 configured to connect the server 1200 to a network, and an input output (I/O) interface 1258. The server 1200 may operate based on an operating system stored in memory 1232, such as Windows Server, mac OS XTM, unixTM, linuxTM, freeBSDTM, or the like.

In an exemplary embodiment, a non-transitory computer readable storage medium, such as the memory 1232, is also provided that includes computer program instructions executable by the processing component 1222 of the server 1200 to perform the above-described methods.

The present disclosure may be systems, methods, and/or computer program products. The computer program product may include a computer-readable storage medium having computer-readable program instructions embodied thereon for causing a processor to implement various aspects of the present disclosure.

The computer readable storage medium may be a tangible device that can hold and store the instructions for use by the instruction execution device. The computer readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, semiconductor memory device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer readable storage medium would include the following: a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a Static Random Access Memory (SRAM), a portable compact disc read-only memory (CD-ROM), a Digital Versatile Disc (DVD), a memory stick, a floppy disk, a mechanical coding device, such as punch cards or in-groove projection structures having instructions stored thereon, and any suitable combination of the foregoing. Computer-readable storage media as used herein is not to be construed as transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission medium (e.g., optical pulses through a fiber optic cable), or electrical signals transmitted through electrical wires.

The computer-readable program instructions described herein may be downloaded from a computer-readable storage medium to a respective computing/processing device, or to an external computer or external storage device via a network, such as the internet, a local area network, a wide area network, and/or a wireless network. The network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers and/or edge servers. The network adapter card or network interface in each computing/processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in a computer-readable storage medium in the respective computing/processing device.

The computer program instructions for carrying out operations of the present disclosure may be assembler instructions, instruction Set Architecture (ISA) instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, C + + or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet service provider). In some embodiments, the electronic circuitry that can execute the computer-readable program instructions implements aspects of the present disclosure by utilizing the state information of the computer-readable program instructions to personalize the electronic circuitry, such as a programmable logic circuit, a Field Programmable Gate Array (FPGA), or a Programmable Logic Array (PLA).

Various aspects of the present disclosure are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the disclosure. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer-readable program instructions.

These computer-readable program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. These computer-readable program instructions may also be stored in a computer-readable storage medium that can direct a computer, programmable data processing apparatus, and/or other devices to function in a particular manner, such that the computer-readable medium storing the instructions comprises an article of manufacture including instructions which implement the function/act specified in the flowchart and/or block diagram block or blocks.

The computer readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the instructions which execute on the computer, other programmable apparatus or other devices implement the functions/acts specified in the flowchart and/or block diagram block or blocks.

The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

Having described embodiments of the present disclosure, the foregoing description is intended to be exemplary, not exhaustive, and not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen in order to best explain the principles of the embodiments, the practical application, or technical improvements to the technology in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A data processing method, for use in a computer device, the method comprising:

acquiring data to be processed;

according to the data to be processed, a hash algorithm is adopted to carry out multiple iterative operations to obtain a hash value, corresponding intermediate data after the first n-level logical operation in at least one iterative operation of the multiple iterative operations are cached in one level, and n is a positive integer greater than 1;

the ith iteration operation of the multiple iteration operations relates to x-level iteration units, wherein i is a designated numerical value, and x is a positive integer; for the lower-level iteration units of the 1 st-level iteration units of the x-level iteration units, each iteration unit in the lower-level iteration units comprises a first-level logic operation unit and a first-level second register unit;

2. The method according to claim 1, wherein the performing, according to the data to be processed, multiple iterative operations by using a hash algorithm to obtain a hash value comprises:

in the ith iterative operation of the multiple iterative operations, according to the data to be processed, the hash algorithm is adopted to perform the n-level logical operation of the 1 st-level iterative unit to obtain the intermediate data, the intermediate data is cached, and i is a designated numerical value;

according to the cached intermediate data, performing logic operation and caching corresponding to each lower iteration unit to obtain output data of the ith iteration operation;

3. The method of claim 2, further comprising:

4. The method according to any one of claims 1 to 3, wherein the hash algorithm is the secure hash algorithm SHA256.

5. The method according to any one of claims 1 to 3, wherein the 1 st stage of the x-stage iteration unit comprises an n-stage logical operation unit and a first register unit;

6. A data processing apparatus for use in a computer device, the apparatus comprising:

the acquisition module is used for acquiring data to be processed;

the operation module is used for carrying out multiple iterative operations by adopting a Hash algorithm according to the data to be processed to obtain a Hash value, the corresponding intermediate data after the first n-level logical operation in at least one iterative operation of the multiple iterative operations is cached in one level, and n is a positive integer greater than 1;

7. A computer device, characterized in that the computer device comprises:

a processor;

a memory for storing processor-executable instructions;

wherein the processor is configured to:

acquiring data to be processed;

8. A non-transitory computer readable storage medium having computer program instructions stored thereon, wherein the computer program instructions, when executed by a processor, implement the method of any of claims 1 to 5.