CN109905228A - A kind of dedicated computing circuit for realizing Hash operation - Google Patents
A kind of dedicated computing circuit for realizing Hash operation Download PDFInfo
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Abstract
A kind of dedicated computing circuit for realizing Hash operation, including at least one Hash calculation module；Specifically include variable, constant input unit, Hash input, output unit and Hash calculation unit；The interative computation number of the Hash operation is N, and each computing module is respectively completed n times interative computation using N number of Hash calculation unit；It is connected between N number of Hash calculation unit by hard wires, one group of new input data is inputted to Hash calculation unit initially through Hash input unit in the clock cycle A calculated each time, the Hash input value of the latter Hash calculation unit is the Hash output valve of previous Hash calculation unit；The number of N number of variable input unit and constant input unit is corresponding with N number of Hash calculation unit respectively to be connected, for inputting corresponding variate-value and constant value；Result is exported by Hash output unit after Hash operation.Using above-mentioned dedicated computing circuit of the invention, the power consumption and cost of counting circuit can reduce in Hash operation.
Description
Technical field
The present invention relates to Hash operation fields, and in particular to a kind of dedicated computing circuit for realizing Hash operation.
Background technique
Hash (Hash) operation is a kind of common operation, can be by the message compression of random length to a certain regular length
Eap-message digest.Common hash algorithm has SHA256, SHA3, SM3 etc., and the output of these hash algorithms is all 256, and
And safety is relatively high, is the hash algorithm of current mainstream.The purposes of Hash operation has file verification, digital signature, authentication
Agreement, proof of work etc..
Hash algorithm has a specific purposes, is the cryptographic Hash for the input message for calculating certain length and examines cryptographic Hash
Specific output position whether be equal to value of some fixation, for example whether first 32 of cryptographic Hash be equal to full 0 or complete 1, either
It is no to be equal to 0x12345678 etc..The characteristics of hash function, which determines, reversely to extrapolate input by exporting, therefore is directed to this
Class purposes, only way are exactly to continuously attempt to different input combinations, calculate its cryptographic Hash and compare whether its output meets
Condition.
In response to the above problems, it can be solved using universal cpu.When performance requirement is relatively high, can also using GPU or
Person FPGA is solved.CPU, GPU, FPGA are universal computing platforms, therefore for such specific computational problem, efficiency one
As it is less high, calculate consumed by power consumption it is bigger.
In order to reduce the power consumption of Hash calculation, ASIC (Application Specific Integrated is generally used
Circuit), i.e. specific integrated circuit realizes hash algorithm.By taking SHA256 as an example, the circuit structure and calculating process of ASIC is such as
Shown in Fig. 1, including Hash input unit, Hash calculation unit, variable input unit, constant input unit and Hash output are single
Member.
The input of SHA256 algorithm has two groups, and one group is input data datain0 ... datain15, is 16 32bit numbers；
Another group is input cryptographic Hash hashin0 ... hashin7, is 8 32bit numbers.In calculating process, with the shape of 8 32bit
State register state0 ... state7, to indicate current calculating state.The initial value of state0 ... state7 is exactly
Hashin0 ... hashin7, is entered into Hash input unit, and output enters Hash calculation unit.SHA256's is calculated as 64
Wheel, the input of each round are state0 ... state7, variable wvalue, constant kvalue, and the output of each round is one group new
State0 ... state7 value.It is preceding 16 wheel wvalue be exactly input data datain0 ... datain15, it is rear 48 wheel wvalue by
Datain0 ... datain15 is calculated, and inputs to Hash calculation unit by variable input unit.The kvalue's of each round
Value is all that constant and datain0 ... datain15, hashin0 ... hashin7, state0 ... state7 are unrelated, passes through constant
Input unit inputs to Hash calculation unit.At the end of 64 wheels calculate, the state0 ... state7 being finally calculated distinguishes
It is added with initial value hashin0 ... hashin7, the hash output hashout0 ... hashout7 of 8 32bit is obtained, by Hash
Output unit output.
Fig. 1 represents existing SHA256 circuit structure.The advantages of circuit is that occupancy computing resource is few, and 64 wheels calculate weight
Same group of computing module state0 ... state7 has been used again.But the shortcomings that circuit structure is that power consumption is still relatively high.It is former
Because being in its circuit structure based on circulation, some additional control circuits and data selector are needed, these are additional
Required for circuit is not algorithm itself, but brought by this circuit structure based on circulation.
Summary of the invention
In view of the above-mentioned problems, the object of the present invention is to provide it is a kind of operation power consumption and cost is relatively low realize Hash operation it is complete
Flowing water circuit structure.
The present invention is achieved through the following technical solutions:
A kind of dedicated computing circuit for realizing Hash operation, including at least one Hash calculation module；
The Hash calculation module includes variable input unit, constant input unit, Hash input unit, Hash calculation list
Member and Hash output unit；
The interative computation number of the Hash operation is N, and each Hash calculation module is distinguished using N number of Hash calculation unit
N times interative computation is completed, calculates need fixed clock periodicity A each time, needs A × N number of clock cycle to complete altogether primary
Hash operation, N and A are natural number；
Data transmitting is carried out by hard wires between N number of Hash calculation unit, at the beginning of the clock cycle A calculated each time
Begin to input one group of new input data, the Hash of the latter Hash calculation unit to Hash calculation unit by Hash input unit
Input value is the Hash output valve of previous Hash calculation unit；
The number of variable input unit and constant input unit difference is N number of, and phase corresponding with N number of Hash calculation unit respectively
Even, for inputting corresponding variate-value and constant value；
Result is exported by Hash output unit after Hash operation.
Further, when needing to do multiple Hash operation, using multiple Hash calculation modules, each Hash calculation module it
Between be sequentially connected, the output data of previous computing module is sent into the latter computing module as input data.
Further, in the input data twice in succession of Hash calculation unit, some data are remained unchanged, then dynamic is closed
Close a part of the constant circuit of input data or circuit.
Further, the Hash calculation unit is with additive based on device, in the adders input of certain iterative calculation
There are multiple constants, multiple constants are added up to obtain a constant and then carry out by the constant and with other variables again in advance
It is added.
Further, when only needing to examine the specific output of cryptographic Hash, not needing to obtain all cryptographic Hash can be complete
When at verifying work, the output valve for needing to examine is contained in the calculated result that certain is once iterated to calculate, then at once
It is verified, the verification without just carrying out output valve after completing whole Hash calculations.
Further, when the cryptographic Hash more than one for needing to verify, then each cryptographic Hash is proved to be successful, final
Verification result can just succeed；If there is any one cryptographic Hash authentication failed, then final verification result also fails；Therefore, when
When some cryptographic Hash authentication failed, no matter subsequent verification result success or not, final verification result is all failure, so
Subsequent iterative calculation and checking circuit is all closed.
Further, for gate circuit, the gate cell for selecting area small, low in energy consumption, and/or select without reset reset,
The output valve of Hash calculation units at different levels is stored without the trigger of scanning scan.
Further, the gate cell is multidigit gate cell.
Further, the operating voltage of gate circuit is reduced, to reduce the power consumption of each Hash operation.
Further, the Hash operation includes SHA256, SHA3 or SM3.
Above-mentioned technical proposal of the invention has following beneficial technical effect:
1, compared to the existing circuit structure based on cycle calculations, the present invention uses N identical with iterative calculation times N
A Hash calculation unit calculates separately each interative computation, and each Hash calculation unit passes through hard wires and carry out data biography
It passs, reduces additional control circuit and data selector, reduce the power consumption and cost of circuit.
2, according to Hash operation the characteristics of closes a part of circuit or saves the counting circuit of certain rounds；Or selection is low
The circuit components of power consumption further decrease the power consumption of circuit.
Detailed description of the invention
Fig. 1 is the counting circuit of SHA256 and calculating process schematic diagram in the prior art；
Fig. 2 is full flowing water circuit structure diagram of the present invention by taking SHA256 as an example；
Fig. 3 is the full flowing water circuit working state figure by taking SHA256 as an example.
Specific embodiment
In order to make the objectives, technical solutions and advantages of the present invention clearer, With reference to embodiment and join
According to attached drawing, the present invention is described in more detail.It should be understood that these descriptions are merely illustrative, and it is not intended to limit this hair
Bright range.In addition, in the following description, descriptions of well-known structures and technologies are omitted, to avoid this is unnecessarily obscured
The concept of invention.
A kind of dedicated computing circuit for realizing Hash operation of the present invention, including at least one Hash calculation module；The Kazakhstan
Uncommon computing module includes variable input unit, constant input unit, and Hash input unit, Hash calculation unit and Hash output are single
Member；The interative computation number of the Hash operation is N, and each Hash calculation module is respectively completed N using N number of Hash calculation unit
Secondary interative computation calculates need fixed clock periodicity A each time, and A × N number of clock cycle is needed to complete a Hash fortune altogether
It calculates, N and A are natural number；Data transmitting is carried out by hard wires between N number of Hash calculation unit, what is calculated each time
Clock cycle A inputs one group of new input data, the latter Hash meter to Hash calculation unit initially through Hash input unit
The Hash input value for calculating unit is the Hash output valve of previous Hash calculation unit；Variable input unit and constant input unit
Number difference it is N number of and corresponding with N number of Hash calculation unit connected respectively, for inputting corresponding variate-value and constant value；One
Result is exported by Hash output unit after secondary Hash operation.
It is further illustrated below with SHA256 operation is specific implementation benefit.
Each SHA256 operation needs 64 wheels, and the calculating process of every wheel is identical, if carrying out Hash meter with CPU software
It calculates, it is general to be calculated by the way of circulation.SHA256 operation is realized with special hardware circuit, can also use cycling circuit
Structure is calculated, and each round circulation inputs different input datas to identical counting circuit, available different output
Data.The adjunct circuits such as corresponding control circuit and input/output selector are needed using cycling circuit structure, these are attached
Required for power-up road is not algorithm itself, but required by cycling circuit structure, as shown in Figure 1, additional function can be brought
Consumption and additional circuit cost.The present invention is in order to reduce the power consumption of circuit and reduce the cost of circuit, using another function
Consumption and all lower full flowing water circuit structure of cost.The SHA256 computing unit of full flowing water circuit structure uses 64 dedicated computings
Circuit goes to be respectively completed the calculating of 64 wheels, and each round, which calculates, needs a clock cycle, and 64 clock cycle is needed to go completion one altogether
Secondary SHA256 is calculated.Data transmitting is carried out by hard wires between 64 dedicated computing circuits, eliminates cycling circuit structure
In additional control circuit and inputoutput data selector, to reduce the power consumption and cost of circuit.As shown in Figure 2 one
A Hash calculation module, including a Hash input unit and a Hash output unit, 64 Hash calculation units, 64 changes
Measure input unit and 64 constant input units.Each clock cycle inputs one group of new input data, the latter Hash calculation
The Hash input value of unit is the Hash output valve of previous Hash calculation unit.Primary complete Hash calculation are as follows: pass through 64
The initial value of Hash input and the Hash calculation results added after 64 wheels calculate are obtained into final result after wheel iterative calculation,
The final result is exported by Hash output unit.
As premise, each clock cycle gives SHA256 computing unit one group of new input data, this group input number
According to after 64 clock cycle, corresponding calculated result will be provided.After full flowing water circuit works together, calculating at different levels
The state of circuit is as shown in Figure 3.First clock cycle is initial, inputs Hash initial value H1S0, breathes out by a clock cycle
The calculating of the circuit 1 of uncommon computing unit 1, obtains output valve H1S1, and output valve H1S1 is as second clock cycle Hash
The input value of the circuit 2 of computing unit 2, is computed and obtains output valve H1S2 ... ... and so on, ties in the 64th clock cycle
Shu Shi, the output valve of the circuit 64 of Hash calculation unit 64 are H1S64；While second clock cycle starts, Hash is given
The circuit 1 of computing unit 1 inputs one group of new Hash initial value H2S0 again, until at the end of the 65th clock cycle, Hash meter
The output valve for calculating the circuit 64 of unit 64 is H2S64.The calculating of each round can all have a variable and a constant to be input to Kazakhstan
Computing unit is wished, is not shown in Fig. 3.After the completion of 64 wheels calculate, it is added to obtain once completely with calculated result by initial input value
Hash operation as a result, being the final result after Hash operation such as the result of H1S0+H1S64.
Needing to do multiple SHA256 operation in certain applications just can access final Hash calculation as a result, applying herein
Under scene, multiple SHA256 computing modules can be used, be sequentially connected between each SHA256 computing module, previous calculating mould
The output data of block is sent into next computing module as input data.
In the input data twice in succession of SHA256 computing unit, some data can be remained unchanged.According to data variation
This feature, can dynamically close a part of circuit or circuit that those input datas will not change.This part in this way
Circuit would not invert, just not additional dynamic power consumption, to reduce whole power consumption.
SHA256 computing unit has more based on 32 adders in the adder input of the computing unit of certain rounds
A constant, in circuit design, multiple constants can be added up in advance to obtain a constant and, then the constant and again and its
Its variable is added.The adder of constant addition can be thus saved, to further save the power consumption and cost of circuit.
The output data of SHA256 shares 8 32 digits, uses state0, state1, state2, state3 respectively,
State4, state5, state6, state7 are represented.Wherein state1, state2, state3, state5, state6,
This 6 output data of state7, is state0, state1, state2, state4, the state5 of last round of calculated result respectively,
The value of state6, it may be assumed that
State1_out=state0_in；
State2_out=state1_in；
State3_out=state2_in；
State5_out=state4_in；
State6_out=state5_in；
State7_out=state6_in.
In the application scenarios of the art of this patent, it is only necessary to examine the specific output of cryptographic Hash, that is, not need to obtain institute
Verifying work can be completed in some cryptographic Hash, it is contemplated that the calculation features of SHA256, in the calculated result of a certain round,
When the included output valve for needing to examine, can be verified at once, without until complete whole Hash calculations it
The verification of output valve is just carried out afterwards.The counting circuit of certain rounds can be saved in this way, or saves the part meter of certain rounds
Calculate circuit (because not needing its calculated result).To save the power consumption and cost of circuit.
When cryptographic Hash 32 digit of more than one for needing to verify, when each 32 digit is proved to be successful, final is tested
Card result can just succeed；If there is any one 32 digit authentication failed, then final verification result is also failure.Work as front
Some 32 digit authentication failed when, no matter subsequent verification result success or not, final verification result is all failure, institute
It can be closed with the calculating of subsequent round and checking circuit.To save the power consumption of calculating and checking circuit.
In gate circuit rank, in order to reduce the dynamic power consumption of circuit, the gate cell that area is small, low in energy consumption is selected, with drop
The power consumption that low each SHA256 is calculated.It selects without reset, without the trigger (flip flop) of scan and stores meters at different levels
The output valve of circuit is calculated, to reduce the power consumption of trigger itself.
It, further, can be using (such as multidigit triggering of multidigit gate cell due to being all 32 calculating in SHA256 algorithm
Device, multidigit selector etc.) multiple one gate cell are replaced, to further decrease the area and power consumption of gate circuit.Multi-position door
The data bit width of unit can be 4,8,16, i.e., and 2nPosition, be also possible to it is other be greater than 1 natural number.
Due to the power consumption AND gate circuit of gate circuit operating voltage it is square directly proportional, further, door electricity can be reduced
The operating voltage on road, the power consumption of each SHA256 operation is greatly reduced.
Explanation about term: Hash calculation unit: refer to the counting circuit of N wheel Hash calculation is for SHA256
64 wheels, so there is 64 Hash calculation units.Hash calculation module: N number of Hash calculation unit, with corresponding N number of variable cell,
N number of constant unit and Hash input, output unit together constitute a complete Hash calculation module.Hash calculation electricity
Road: if necessary to multiple Hash calculation modules, then multiple modules can be sequentially connected in series.
Low power technology used in the present invention, although can be used for other Hash by taking SHA256 as an example
The design of computing circuit, and have in the circuit design of similar characteristics.In conclusion a kind of realization provided by the invention is breathed out
The uncommon dedicated computing circuit calculated, the effect that can be reached and reduce power consumption, reduce cost.
It should be understood that above-mentioned specific embodiment of the invention is used only for exemplary illustration or explains of the invention
Principle, but not to limit the present invention.Therefore, that is done without departing from the spirit and scope of the present invention is any
Modification, equivalent replacement, improvement etc., should all be included in the protection scope of the present invention.In addition, appended claims purport of the present invention
Covering the whole variations fallen into attached claim scope and boundary or this range and the equivalent form on boundary and is repairing
Change example.
Claims (10)
1. a kind of dedicated computing circuit for realizing Hash operation, it is characterised in that: including at least one Hash calculation module；
The Hash calculation module includes variable input unit, constant input unit, Hash input unit, Hash calculation unit and
Hash output unit；
The interative computation number of the Hash operation is N, and each Hash calculation module is respectively completed using N number of Hash calculation unit
N times interative computation calculates need fixed clock periodicity A each time, and A × N number of clock cycle is needed to complete a Hash altogether
Operation, N and A are natural number；
Data transmitting is carried out by hard wires between N number of Hash calculation unit, is initially led in the clock cycle A calculated each time
It crosses Hash input unit and inputs one group of new input data, the Hash input of the latter Hash calculation unit to Hash calculation unit
Value is the Hash output valve of previous Hash calculation unit；
The number of variable input unit and constant input unit difference is N number of, and corresponding with N number of Hash calculation unit connected respectively,
For inputting corresponding variate-value and constant value；
Result is exported by Hash output unit after Hash operation.
2. dedicated computing circuit according to claim 1, it is characterised in that: when needing to do multiple Hash operation, using more
A Hash calculation module is sequentially connected between each Hash calculation module, and the output data of previous computing module is sent into latter
A computing module is as input data.
3. dedicated computing circuit according to claim 1, it is characterised in that: the input number twice in succession of Hash calculation unit
According in the middle, some data are remained unchanged, then dynamic closes a part of the constant circuit or circuit of input data.
4. dedicated computing circuit according to claim 1, it is characterised in that: device is the Hash calculation unit with additive
It is main, there are multiple constants in the adder input of certain iterative calculation, multiple constants are added up in advance to obtain a constant
Be then added again by the constant and with other variables.
5. dedicated computing circuit according to claim 1, it is characterised in that: when the specific output for only needing to examine cryptographic Hash
When, when not needing to obtain all cryptographic Hash verifying work can be completed, in the calculated result that certain is once iterated to calculate
The included output valve for needing to examine, then verified at once, without just carrying out after completing whole Hash calculations
The verification of output valve.
6. dedicated computing circuit according to claim 1, it is characterised in that: when the cryptographic Hash more than one that needs verify
When, then each cryptographic Hash is proved to be successful, and final verification result can just succeed；It verifies and loses if there is any one cryptographic Hash
It loses, then final verification result also fails；Therefore, when some cryptographic Hash authentication failed, no matter subsequent verification result is successful
Whether, final verification result is all failure, so subsequent iterative calculation and checking circuit is all closed.
7. dedicated computing circuit according to claim 1, it is characterised in that: for gate circuit, select area small, low in energy consumption
Gate cell, and/or select without resetting reset, store Hash calculation units at different levels without the trigger of scanning scan
Output valve.
8. dedicated computing circuit according to claim 7, it is characterised in that: the gate cell is multidigit gate cell.
9. dedicated computing circuit according to claim 7, it is characterised in that: the operating voltage of gate circuit is reduced, to reduce
The power consumption of each Hash operation.
10. dedicated computing circuit according to claim 1, it is characterised in that: the Hash operation includes SHA256, SHA3
Or SM3.
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| CN113794567A (en) * | 2021-09-13 | 2021-12-14 | 上海致居信息科技有限公司 | Synthesis acceleration method and device of SHA256 Hash algorithm zero-knowledge proof circuit |
| CN113794567B (en) * | 2021-09-13 | 2024-04-05 | 上海致居信息科技有限公司 | Synthetic acceleration method and device for SHA256 hash algorithm zero knowledge proof circuit |
| CN113946313A (en) * | 2021-10-12 | 2022-01-18 | 哲库科技(北京)有限公司 | Processing circuit, chip and terminal of LOOKUP3 hash algorithm |
| CN116094691A (en) * | 2022-12-26 | 2023-05-09 | 声龙(新加坡)私人有限公司 | Data processing method, device and chip based on workload certification |
| CN116094691B (en) * | 2022-12-26 | 2023-11-03 | 声龙(新加坡)私人有限公司 | Data processing method, device and chip based on workload certification |
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