CN117093267B

CN117093267B - Storage method, device, equipment and storage medium for branch instruction jump address

Info

Publication number: CN117093267B
Application number: CN202311344689.5A
Authority: CN
Inventors: 傅腾蛟; 勾凌睿; 王凯帆; 陈键; 唐丹; 包云岗
Original assignee: Beijing Open Source Chip Research Institute
Current assignee: Beijing Open Source Chip Research Institute
Priority date: 2023-10-17
Filing date: 2023-10-17
Publication date: 2023-12-22
Anticipated expiration: 2043-10-17
Also published as: CN117093267A

Abstract

The application provides a storage method, a device, equipment and a storage medium for a branch instruction jump address, which relate to the technical field of branch target buffers and comprise the following steps: acquiring a jump address of a branch instruction, and acquiring a used table entry pair from a branch target buffer under the condition that the number of bits of the jump address is greater than that of the address bits of the table entry; under the condition that the used table entry pair has an idle tag bit, acquiring a table entry corresponding to the idle tag bit and an idle table entry; the jump address is split into a first subsection and a second subsection, the first subsection is stored in the idle tag bit, and the second subsection is stored in the address bit of the idle table entry, so that the first subsection for storing the jump address by using the idle tag bit in the used table entry pair is realized, the waste of the idle tag bit in the used table entry pair is reduced, and the problem of waste of storage resources caused in the prior art is solved.

Description

Storage method, device, equipment and storage medium for branch instruction jump address

Technical Field

The present disclosure relates to the field of branch target buffers, and in particular, to a method, an apparatus, a device, and a storage medium for storing a jump address of a branch instruction.

Background

The branch target buffer (BTB, branch Target Buffer) is used for storing branch instruction information, including a jump address corresponding to the branch instruction, i.e. a branch target address (BTA, branch target address). In order to store a jump address using a branch target buffer, a method of storing a jump address of a branch instruction is required.

It should be noted that the branch target buffer includes a plurality of entries, each including a tag bit and an address bit. The address bits are used to store addresses and the tag bits are used to store tag information used to index addresses in entries.

In the prior art, in the case where the number of bits of the jump address is greater than the number of bits of the address bits of one entry, two entries are formed into an entry pair, the high order bits of the jump address are stored in the address bits of one entry of the entry pair, and the low order bits of the jump address are stored in the address bits of the other entry of the entry pair, and tag information is stored using one tag bit of the entry pair.

In implementing the present application, the inventors found that at least the following problems exist in the prior art: since one tag bit in the entry pair is used to store tag information and the other tag bit in the entry pair is redundant, waste of storage resources results.

Disclosure of Invention

The embodiment of the application provides a storage method, a device, equipment and a storage medium for a branch instruction jump address, which are used for solving the problem of waste of storage resources caused by using one tag bit in an entry pair to store tag information and the other tag bit in the entry pair to be redundant in the prior art.

In a first aspect, an embodiment of the present application provides a method for storing a jump address of a branch instruction, where the jump address is applied to a branch target buffer, where the branch target buffer includes a plurality of entries, and each of the entries includes a tag bit and an address bit, and the method includes:

acquiring a jump address of a branch instruction, and acquiring a used table entry pair from the branch target buffer under the condition that the number of bits of the jump address is greater than that of the address bits of the table entry;

under the condition that an idle tag bit exists in the used table entry pair, acquiring a table entry corresponding to the idle tag bit and an idle table entry;

splitting the jump address into a first part and a second part, storing the first part in the idle tag bit, and storing the second part in the address bit of the idle table item.

In a second aspect, an embodiment of the present application provides a storage device for a branch instruction jump address, applied to a branch target buffer, where the branch target buffer includes a plurality of entries, each of the entries includes a tag bit and an address bit, and the device includes:

a first obtaining module, configured to obtain a jump address of a branch instruction, and obtain a used table entry pair from the branch target buffer when a bit number of the jump address is greater than a bit number of an address bit of the table entry;

the second acquisition module is used for acquiring an entry corresponding to the idle tag bit and an idle entry under the condition that the idle tag bit exists in the used entry pair;

the storage module is used for splitting the jump address into a first subsection and a second subsection, storing the first subsection in the idle tag bit, and storing the second subsection in the address bit of the idle table item.

In a third aspect, embodiments of the present application further provide an electronic device, including a processor;

a memory for storing the processor-executable instructions;

wherein the processor is configured to execute the instructions to implement the method of the first aspect.

In a fourth aspect, embodiments of the present application also provide a computer-readable storage medium, which when executed by a processor of an electronic device, causes the electronic device to perform the method of the first aspect.

In the embodiment of the application, the used table entry pair is acquired from the branch target buffer by acquiring the jump address of the branch instruction and under the condition that the number of bits of the jump address is larger than that of the address bits of the table entry; under the condition that the used table entry pair has an idle tag bit, acquiring a table entry corresponding to the idle tag bit and an idle table entry; the jump address is split into a first subsection and a second subsection, the first subsection is stored in the idle tag bit, and the second subsection is stored in the address bit of the idle table item, so that the first subsection of storing the jump address by using the idle tag bit in the used table item pair is realized, the waste of the idle tag bit in the used table item pair is reduced, and the problem of waste of storage resources caused by using one tag bit in the table item pair to store tag information and the other tag bit in the table item pair to be redundant in the prior art is solved.

The foregoing description is only an overview of the technical solutions of the present application, and may be implemented according to the content of the specification in order to make the technical means of the present application more clearly understood, and in order to make the above-mentioned and other objects, features and advantages of the present application more clearly understood, the following detailed description of the present application will be given.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort to a person skilled in the art.

FIG. 1 is a flowchart illustrating steps of a method for storing a jump address of a branch instruction according to an embodiment of the present invention;

FIG. 2 is a flowchart illustrating steps of another method for storing a branch instruction jump address according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of entries in a prior art packet;

FIG. 4 is a schematic diagram of entries in a packet provided by an embodiment of the present application;

FIG. 5 is a block diagram of a memory device for a branch instruction jump address according to an embodiment of the present invention;

FIG. 6 is a block diagram of an electronic device provided by an embodiment of the invention;

fig. 7 is a block diagram of another electronic device in accordance with another embodiment of the present invention.

Detailed Description

The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.

The terms first, second and the like in the description and in the claims, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged, as appropriate, such that embodiments of the present application may be implemented in sequences other than those illustrated or described herein, and that the objects identified by "first," "second," etc. are generally of a type and not limited to the number of objects, e.g., the first object may be one or more. Furthermore, the term "and/or" as used in the specification and claims to describe an association of associated objects means that there may be three relationships, e.g., a and/or B, may mean: a exists alone, A and B exist together, and B exists alone. The character "/" generally indicates that the context-dependent object is an "or" relationship. The term "plurality" in the embodiments of the present application means two or more, and other adjectives are similar thereto.

Term interpretation:

a new branch target buffer (FTB, fetch Target buffer) for storing branch instruction addresses and corresponding jump addresses, i.e. branch target addresses, in instruction blocks.

The branch target buffer is an important component for storing branch instruction information, and can record a jump address corresponding to a branch instruction, namely, a branch target address, so that a processor can prefetch the instruction of the jump address, and each table entry of the branch target buffer comprises a tag bit and an address bit, wherein the tag bit is used for storing tag information, and the address bit is used for storing the branch target address.

FTB is a new type of branch target buffer, where only one entry of a conventional BTB can store information of one branch instruction, and one entry of FTB can store information of one instruction block. Wherein one instruction block includes two branch instructions.

An entry of the FTB includes two slots and a tag bit, one slot containing an address bit for storing a jump address of a branch instruction in the instruction block, the tag bit storing tag information.

Tag information: for comparing tag information of an indexed entry with the upper bits of a Program Counter (PC) after indexing the branch target buffer using the lower bits of the PC to determine that the entry contains a desired branch target address.

Branch target address: for taking the branch target address as the next target address for instruction prefetching when the direction predictor predicts a branch jump.

It should be noted that, the method for storing the jump address of the branch instruction provided in the embodiment of the present application is applied to the branch target buffer.

The following describes in detail, with reference to the attached drawings, a specific embodiment and an application scenario thereof, a method for storing a branch instruction jump address provided in the embodiment of the present application.

Fig. 1 is a flowchart of a method for storing a jump address of a branch instruction according to an embodiment of the present application, where, as shown in fig. 1, the method may include:

step 101, obtaining the jump address of the branch instruction, and obtaining the used table entry pair from the branch target buffer under the condition that the number of bits of the jump address is greater than the number of bits of the address bits of the table entry.

In the embodiment of the application, the used table entry pair is obtained from the branch target buffer by obtaining the jump address of the branch instruction and under the condition that the number of bits of the jump address is greater than that of the address bits of the table entry, and then under the condition that the idle tag bit exists in the used table entry pair, the table entry corresponding to the idle tag bit and an idle table entry are obtained.

It should be noted that an entry pair includes two entries, and a used entry pair refers to an address bit of each entry in the entry pair being used. Unused pairs of entries refer to two free entries, or one of the entries is a free entry and the other entry stores a jump address or a portion of a jump address. Free entries, i.e. entries for which address bits are not used.

For a BTB entry pair, one entry pair includes two address bits and two tag bits, where one address bit of a used entry stores the upper bits of the jump address of a branch instruction stored previously, the other address bit stores the lower bits of the jump address, one tag bit stores tag information, and the other tag bit is free if unoccupied.

For example, a table entry pair of a used BTB stores a jump address 1, the table entry of the used BTB includes a table entry 1 and a table entry 2, the table entry 1 includes an address bit 1, a tag bit 1, the table entry 2 includes an address bit 2, and a tag bit 2, wherein the address bit 1 stores a high order bit of the jump address 1, the address bit 2 stores a low order bit of the jump address 1, the tag bit 1 stores tag information, and the tag bit 2 is a free tag bit when not occupied.

For an entry of the FTB, one entry pair includes 4 slots and two tag bits, wherein two slots of one used entry store the upper bits of the jump address of one instruction block previously stored, the other two slots store the lower bits of the jump address of one instruction block previously stored, one tag bit stores tag information, and the other tag bit is free tag bit if unoccupied.

For example, an entry pair of a used FTB includes a jump address of a memory block 1, including a jump address 2 and a jump address 3, the entry of the used FTB includes an entry 3 and an entry 4, the entry 3 includes a slot 1, a slot 2, and a tag bit 1, the entry 4 includes a slot 3, a slot 4, and a tag bit 2, where the slot 1 stores the high order of the jump address 2, the slot 2 stores the low order of the jump address 2, the slot 3 stores the high order of the jump address 3, the slot 4 stores the low order of the jump address 3, the tag bit 1 stores tag information, and the tag bit 2 is free when unoccupied.

Step 102, under the condition that the used table entry pair has an idle tag bit, acquiring a table entry corresponding to the idle tag bit and an idle table entry.

In the embodiment of the application, under the condition that the idle tag bit exists in the used table entry pair, the table entry corresponding to the idle tag bit and an idle table entry are acquired, so that the jump address is split into a first part and a second part, the first part is stored in the idle tag bit, and the second part is stored in the address bit of the idle table entry.

It should be noted that, the free entry is an entry whose address bit is unoccupied and which is not paired with other entries. The table entry corresponding to the idle tag bit is one table entry in the used table entry pair, and the tag bit of the table entry is the idle tag bit.

In the case where the tag bit stores tag information or the tag bit stores all or a part of the jump address, the tag bit is an occupied tag bit and does not belong to an idle tag bit.

Step 103, splitting the jump address into a first subsection and a second subsection, storing the first subsection in the idle tag bit, and storing the second subsection in the address bit of the idle table entry.

In the embodiment of the application, the jump address is split into the first subsection and the second subsection, the first subsection is stored in the idle tag bit, and the second subsection is stored in the address bit of the idle table entry, so that the first subsection for storing the jump address by using the redundant idle tag bit in the used table entry pair is realized, and the utilization rate of the storage space is improved.

Specifically, in some embodiments, where the first subsection is the upper bits of the jump address, the second subsection is the lower bits of the jump address; in other embodiments, where the first subsection is the lower order bits of the jump address, the second subsection is the upper order bits of the jump address.

In summary, in the embodiment of the present application, by acquiring the jump address of the branch instruction, and in the case that the number of bits of the jump address is greater than the number of bits of the address bits of the entry, the used entry pair is acquired from the branch target buffer; under the condition that the used table entry pair has an idle tag bit, acquiring a table entry corresponding to the idle tag bit and an idle table entry; the jump address is split into a first subsection and a second subsection, the first subsection is stored in the idle tag bit, and the second subsection is stored in the address bit of the idle table item, so that the first subsection of storing the jump address by using the idle tag bit in the used table item pair is realized, the waste of the idle tag bit in the used table item pair is reduced, and the problem of waste of storage resources caused by using one tag bit in the table item pair to store tag information and the other tag bit in the table item pair to be redundant in the prior art is solved.

Fig. 2 is a flowchart of specific steps of a method for storing a branch instruction jump address according to an embodiment of the present application, as shown in fig. 2, the method may include:

step 201, obtaining a jump address of a branch instruction, and obtaining a used table entry pair from the branch target buffer in a case that the number of bits of the jump address is greater than the number of bits of the address bits of the table entry.

The implementation of this step is similar to the implementation of step 101, and will not be described here again.

Step 202, obtaining label matching information of the packet according to preset label matching bits of the packet.

Wherein said branch target buffer comprises a plurality of packets, each of said packets comprising a plurality of entry pairs, each of said entry pairs comprising two of said entries; and the bits in the label matching bits are in one-to-one correspondence with the corresponding table entry pairs in the packet.

In the embodiment of the application, the tag bit pairing information of the packet is obtained according to the preset tag bit pairing corresponding to the packet, whether the used table entry pair contains the idle tag bit is further judged according to the tag bit pairing information, and the table entry corresponding to the idle tag bit and an idle table entry are obtained under the condition that the tag bit pairing information comprises the idle tag bit in the used table entry pair.

It should be noted that, each packet has a corresponding tag matching bit, specifically, the tag matching bit may be in the form of multiple binary bits, for example, one packet includes 8 entries, which are respectively an entry a, an entry B, an entry C, an entry D, an entry E, an entry F, an entry G, and an entry H, where the entry a and the entry B are used entry pairs, and contain one free tag bit; the table items C and D are unused table item pairs; the table item E and the table item F are used table items, but do not contain idle tag bits, namely one tag bit in a table item pair formed by pairing the table item E and the table item F stores tag information A, and the other tag bit stores a first subsection of a jump address A; the table item G and the table item H are unused table item pairs, the table item G is a used table item, the address bit of the table item G stores a second subsection of the jump address A, the tag bit stores tag information B, and the table item H is an idle table item. The tag pair bit of the packet includes "0010", wherein a first bit "0" indicates that the table entry a and the table entry B contain idle tag bits; the second bit "0" indicates that the table entry C and the table entry D contain idle tag bits; the third bit "1" indicates that the table entry E, table entry F, does not contain an idle tag bit; the fourth bit "0" indicates that the table entry G and the table entry H contain idle tag bits. Therefore, according to "0010" in the tag matching bit of the packet, the tag matching information of the packet may be obtained, where the tag matching information is that the table entry a and the table entry B contain idle tag bits, the table entry C and the table entry D contain idle tag bits, the table entry E and the table entry F do not contain idle tag bits, and the table entry G and the table entry H contain idle tag bits.

Step 203, obtaining an entry corresponding to the idle tag bit and an idle entry when the tag bit pairing information includes that the idle tag bit exists in the used entry pair.

In the embodiment of the application, under the condition that the tag bit pairing information includes that the used table entry pair has the idle tag bit, the table entry corresponding to the idle tag bit and an idle table entry are acquired, and then the jump address is split into a first part and a second part, and then the first part is stored in the idle tag bit, and the second part is stored in the address bit of the idle table entry.

Step 204, splitting the jump address into a first branch and a second branch, storing the first branch in the idle tag bit, and storing the second branch in the address bit of the idle table entry.

The implementation of this step is similar to the implementation of step 103, and will not be described here again.

Optionally, in some embodiments, the method further comprises the following steps (step 205 to step 206):

step 205, setting a value of a bit corresponding to the first entry pair in the corresponding tag pairing bit to a first value in the case that the first entry pair exists in the packet.

Wherein the idle tag bit is present in the tag bits of the entries of the first entry pair.

In the embodiment of the present application, when the first entry pair exists in the packet, the value of the bit corresponding to the first entry pair in the corresponding tag matching pair is set to the first value, so that the idle tag bit exists in the tag bits of the entries of the first entry pair through the tag matching pair.

Specifically, in some embodiments, the first value is a binary "0".

Step 206, setting the value of the bit corresponding to the first entry pair in the corresponding tag pairing bit to be a second value in the case that the second entry pair exists in the packet.

Wherein the idle tag bit does not exist in the tag bits of the entries of the second entry pair.

In this embodiment of the present application, when the second entry pair exists in the packet, the value of the bit corresponding to the first entry pair in the corresponding tag matching pair is set to the second value, so that the tag bit of the entry of the second entry pair may be represented by the tag matching pair, where the idle tag bit does not exist.

Specifically, in some embodiments, the second value is a binary "1".

By executing steps 205 to 206, it may be achieved that the tag bit pair indicates whether the entry pair in the packet contains a free tag bit, so that tag bit pair information may be obtained.

Optionally, in some embodiments, step 202 may include the following sub-steps:

in the case that the value of the bit corresponding to the used entry pair is the first value, the sub-step 2021 determines that the tag bit pair information includes that the used entry pair has the idle tag bit.

In the embodiment of the present application, in the tag matching bits, when the value of the bit corresponding to the used table entry pair is the first value, it is determined that the tag matching information includes that the used table entry pair has an idle tag bit, and then when the used table entry pair has the idle tag bit, the table entry corresponding to the idle tag bit and an idle table entry are obtained.

Optionally, in some embodiments, the acquiring the used table entry pair from the branch target buffer includes the following sub-steps:

and a substep 2011, obtaining item pairing information of the group according to preset item pairing bits of the group.

Wherein, the bit in the table item matching bit corresponds to the table item pair in the corresponding grouping one by one.

In the embodiment of the application, the item pairing information of the group is obtained according to the preset item pairing bit of the group, and then the used item pair is obtained from the corresponding group when the item pairing information comprises the used item pair in the group.

It should be noted that, each group has a corresponding table entry matching bit, specifically, the table entry matching bit may be in the form of multiple binary bits, for example, one group includes 4 table entries, which are respectively table entry a, table entry B, table entry C, and table entry D, where table entry a and table entry B are used table entry pairs, table entry C and table entry D are unused table entry pairs, and the table entry matching bit of the group includes "10", where "1" indicates that table entry a and table entry B are paired, and "0" indicates that table entry C and table entry D are unused table entry pairs. Therefore, from "10" in the table item pairing bit of the group, the table item pairing information of the group can be obtained, the table item pairing information is the table item A and the table item B, the table item A and the table item B are paired, the table item C and the table item D are unused table item pairs.

Substep 2012, in a case where the entry pairing information includes that the used entry pair exists in the packet, obtaining the used entry pair from the corresponding packet.

In the embodiment of the application, when the table item pairing information includes that the used table item pair exists in the packet, the used table item pair is obtained from the corresponding packet, and then when the idle tag bit exists in the used table item pair, the table item corresponding to the idle tag bit and an idle table item are obtained.

By executing sub-steps 2011 to 2012, it is possible to determine whether there is a used table entry pair in the packet according to the table entry matching bit of the packet, obtain the used table entry pair when there is a used table entry pair in the packet, further determine whether the used table entry pair contains an idle tag bit, and obtain a table entry corresponding to the idle tag bit and an idle table entry when there is an idle tag bit in the used table entry pair.

Optionally, in some embodiments, the method further comprises the following steps (step 207 to step 208):

step 207, setting the value of the bit corresponding to the third table entry pair in the corresponding table entry pair to a third value when the used third table entry pair exists in the packet.

In the embodiment of the present application, in the case that the used third table entry pair exists in the packet, the value of the bit corresponding to the third table entry pair in the corresponding table entry pair bit is set to the third value, so that the used third table entry existing in the packet may be represented by the table entry pair bit.

Step 208, setting the value of the bit corresponding to the fourth table entry pair in the corresponding table entry pair to a fourth value in the case that the fourth table entry pair which is not used exists in the packet.

In the embodiment of the present application, when an unused fourth entry pair exists in the packet, the value of the bit corresponding to the fourth entry pair in the corresponding entry pair is set to the fourth value, so that the unused fourth entry pair existing in the packet may be represented by the entry pair bit.

The implementation of steps 207 to 208 may be achieved by using the table entry pairing bit to represent the use condition of the table entry pairs in the group, and further, the table entry pairing information of the group may be obtained through the table entry pairing bit of the group.

Optionally, in some embodiments, sub-step 2011 may include the following sub-steps:

in step 2011a, if there is a bit having the third value in the table entry pairing bits, determining that the table entry pairing information includes that the used table entry pair exists in the packet.

In the embodiment of the present application, by determining that the table entry pairing information includes that the used table entry pair exists in the packet when the bit having the third value exists in the table entry pairing bits, the table entry corresponding to the idle tag bit and an idle table entry are further obtained when the idle tag bit exists in the used table entry pair.

Optionally, in some embodiments, after step 204, the method further comprises the following steps (step 209 to step 212):

step 209, obtaining a first tag bit corresponding to the target branch instruction, and determining a target table entry to which the first tag bit belongs.

In the embodiment of the application, the first tag bit corresponding to the target branch instruction is obtained, the target table item to which the first tag bit belongs is determined, and then the target table item pairing information of the target group is obtained according to the target table item pairing bit of the target group to which the target table item belongs.

Step 210, obtaining target table item pairing information of the target group according to target table item pairing bits of the target group to which the target table item belongs.

In the embodiment of the application, the target item pairing information of the target packet is obtained according to the target item pairing bit of the target packet to which the target item belongs, and further, the target tag bit pairing information of the target packet is obtained according to the tag pairing bit of the target packet when the target item pairing information includes that the target item is not paired with other items in the target packet.

Step 211, obtaining target tag bit pairing information of the target packet according to the tag pairing bit of the target packet when the target entry pairing information includes that the target entry is not paired with other entries in the target packet.

In this embodiment, when the target tag bit pairing information includes that the target address bit of the target entry is paired with the second tag bit of the used entry pair, the target first part of the target jump address of the target branch instruction is obtained from the second tag bit, the target second part of the target jump address is obtained from the target address bit, and then the target first part and the target second part are formed into the target jump address.

It should be noted that, each packet has a corresponding tag matching bit, specifically, the tag matching bit may be in the form of a plurality of binary bits, for example, the target packet includes 4 table entries, which are respectively a table entry a, a table entry B, a table entry C, and a table entry D, where the table entry a and the table entry B are used table entry pairs, and a jump address a is stored, the table entry a includes an address bit a and a tag bit a, the address bit a stores a high bit of the jump address a, the tag bit a stores tag information a, the table entry B includes an address bit B and a tag bit B, the address bit B stores a low bit of the jump address a, and the tag bit B stores a target first subsection of the target jump address B; the table item C and the table item D are unused table item pairs, the table item C comprises an address bit C and a label bit C, the address bit C stores a target second partition of a target jump address b, the label bit C stores label information C, and the table item D is an idle table item. The tag pairing bit of the target packet includes "10", where the first bit "1" indicates that the address bit C (i.e., the target address bit) in entry C is paired with the tag bit B (i.e., the second tag bit) in the used entry pair of entries a, B, and the second bit "0" indicates that the address bit of entry D is unpaired with the tag bit B (i.e., the second tag bit) in the used entry pair of entries a, B.

Therefore, according to "10" in the tag matching bit of the target packet, the target tag bit matching information of the target packet may be obtained, where the target tag bit matching information is that the address bit C (i.e., the target address bit) in the table entry C is matched with the tag bit B (i.e., the second tag bit) in the used table entry pair formed by the table entry a and the table entry B, and the address bit of the table entry D is not matched with the tag bit B (i.e., the second tag bit) in the used table entry pair formed by the table entry a and the table entry B.

Step 212, in the case that the target tag bit pairing information includes that the target address bit of the target entry is paired with the second tag bit of a used entry pair, acquiring a target first part of the target jump address of the target branch instruction from the second tag bit, acquiring a target second part of the target jump address from the target address bit, and forming the target first part and the target second part into the target jump address.

In the embodiment of the application, under the condition that the target tag bit pairing information comprises the target address bit of the target table item and the second tag bit of one used table item pair, acquiring the target first subsection of the target jump address of the target branch instruction from the second tag bit and the target second subsection of the target jump address from the target address bit, and then forming the target jump address by the target first subsection and the target second subsection, thereby realizing the acquisition of the jump address stored by using the idle tag bit of the used table item pair and the address bit of one idle table item.

Specifically, in some embodiments, where the target first branch is the upper bits of the target jump address, the target second branch is the lower bits of the target jump address; in other embodiments, where the target first partition is the lower order bits of the jump address, the target second partition is the upper order bits of the jump address.

This may be achieved by performing steps 209 to 212 to obtain a jump address stored with the free tag bits in the used entry pair and the address bits of one free entry.

Optionally, in some embodiments, after step 201, the method further comprises the following steps (step 213 to step 214):

step 213, acquiring an idle table entry pair when the idle tag bit does not exist in the used table entry pair.

In the embodiment of the application, under the condition that the used table entry pair does not have the idle tag bit, the idle table entry pair is acquired, the jump address is split into a first part and a second part, the first part is stored in the first address bit of the idle table entry pair, and the second part is stored in the second address bit of the idle table entry pair.

It should be noted that, the entries in the free entry pair are all free entries.

Step 214, splitting the jump address into the first partition and the second partition, storing the first partition in a first address bit in the free entry pair, and storing the second partition in a second address bit in the free entry pair.

In the embodiment of the application, the jump address is split into the first subsection and the second subsection, the first subsection is stored in the first address bit in the idle table entry pair, and the second subsection is stored in the second address bit in the idle table entry pair, so that the jump address is stored.

This can be achieved by performing steps 213 to 214, using the free entry pair to store the jump address in case no free tag bit is present in the used entry pair.

Optionally, in some embodiments, after step 201, the method further comprises the steps of (step 215 to step 217):

step 215, in the case that there is an occupied tag bit occupied by the pre-stored jump address in the used entry pair, acquiring the unoccupied remaining bits in the occupied tag bit.

In the embodiment of the application, under the condition that occupied tag bits occupied by the jump address stored in advance exist in the used table entry pairs, unoccupied residual bits in the occupied tag bits are obtained, and further under the condition that the number of bits of the residual bits is larger than that of the first subsection, an idle table entry is obtained.

The remaining bits are the remaining bits out of the bits occupied by the jump address in the tag bits. For example, the tag bits have sixteen bits, with eight bits occupied by the jump address, and the other eight bits are the remaining bits.

Step 216, obtaining one free entry in case the number of bits of the remaining bits is greater than the number of bits of the first partition.

In the embodiment of the application, by acquiring a free table entry in the case that the number of bits of the remaining bits is greater than the number of bits of the first partition, the first partition is further stored in the remaining bits, and the second partition is stored in the address bits of the free table entry.

Step 217, storing the first partition in the remaining bits and the second partition in address bits of the free entry.

In the embodiment of the application, the first subsection is stored in the residual bit, and the second subsection is stored in the address bit of the idle table entry, so that a part of a plurality of jump addresses is stored by using the redundant tag bit in the used table entry pair, and the utilization rate of the storage space is further improved.

It should be noted that, each packet has a corresponding tag matching bit, specifically, the tag matching bit may be in the form of a plurality of binary bits, for example, one packet includes 4 table entries, which are respectively an table entry a, an table entry B, an table entry C, and an table entry D, where the table entry a and the table entry B are used table entry pairs, a jump address a is stored, the table entry a includes an address bit a and a tag bit a, the address bit a stores a high bit of the jump address a, the tag bit a stores tag information a, the table entry B includes an address bit B and a tag bit B, the address bit B stores a low bit of the jump address a, the tag bit B includes a first sub-portion and a second sub-portion, the first sub-portion of the tag bit B stores a target first portion of the jump address C, and the second sub-portion of the tag bit B is not used; the table item C and the table item D are unused table item pairs, the table item C comprises an address bit C and a label bit C, the address bit C stores a target second partition of a target jump address b, the label bit C stores label information C, and the table item D comprises an address bit D and a label bit D and is an idle table item. At this time, the tag pair bits of the packet include "1000", the first bit "1" indicates that the address bit C of the entry C is paired with the first sub-portion of the tag bit b, the second bit "0" indicates that the address bit D of the entry D is unpaired with the first sub-portion of the tag bit b, the third bit "0" indicates that the address bit C of the entry C is unpaired with the second sub-portion of the tag bit b, and the fourth bit "0" indicates that the address bit D of the entry D is unpaired with the second sub-portion of the tag bit b.

By performing steps 215 to 217, it is possible to store a part of the plurality of jump addresses by using the tag bits redundant in the used table entry pair, thereby further improving the utilization of the storage space.

Optionally, in some embodiments, after step 204, the method further comprises the following steps (steps 218 to 220):

step 218, a first tag bit corresponding to the target branch instruction is obtained, and a target table entry to which the first tag bit belongs is determined.

In the embodiment of the application, the target address bit of the target table entry and the second tag bit of the corresponding used table entry pair are obtained by obtaining the first tag bit corresponding to the target branch instruction and determining the target table entry to which the first tag bit belongs.

Step 219, obtaining the target address bit of the target entry and the second tag bit of the corresponding used entry pair.

In the embodiment of the application, the target address bit of the target table entry and the second tag bit of the corresponding used table entry pair are acquired, so that the target first part of the target jump address of the target branch instruction is acquired from the second tag bit, the target second part of the target jump address is acquired from the target address bit, and then the target first part and the target second part form the target jump address.

Step 220, obtaining a target first portion of the target jump address of the target branch instruction from the second tag bit, and obtaining a target second portion of the target jump address from the target address bit, and forming the target jump address from the target first portion and the target second portion.

In the embodiment of the application, the target first subsection of the target jump address of the target branch instruction is acquired from the second label bit, the target second subsection of the target jump address is acquired from the target address bit, and then the target jump address is formed by the target first subsection and the target second subsection, so that the target jump address is acquired from the redundant label bit of the used table entry pair and the address bit of one table entry.

This is accomplished by performing steps 218 through 220 to obtain a target jump address from the redundant tag bits of the used entry pair and the address bits of one entry.

In the prior art, a packet includes a plurality of entries, in the case where the number of bits of the jump address is greater than the number of bits of the address bits of the entries, the entries of the packet are paired two by two, each pair of entries is stored with one jump address, for example, referring to fig. 3, a packet includes 4 entries, namely, an entry a, an entry B, an entry C, and an entry D, respectively, where the entry a includes an address bit a, a tag bit a, the entry B includes an address bit B, and a tag bit B, the entry C includes an address bit C, and a tag bit C, and the entry D includes an address bit D, in the case where the number of bits of the jump address is greater than the number of bits of the address bits of the entries, the entries of the packet are paired two pairs of entries, that is, the pair of entries formed by the entry a, the entry B, and the pair formed by the entry C, the entry D, and the pair of each pair of entries stores one jump address.

In this embodiment of the present application, a packet includes a plurality of entries, where the number of bits of the jump address is greater than the number of bits of the address bits of the entries, the entries of the packet are paired two by two, and the redundant tag bits of the used pair of entries and one free entry are utilized to store a jump address, for example, referring to fig. 4, a packet includes 4 entries, which are respectively an entry a, an entry B, an entry C, and an entry D, where the entry a includes an address bit a, a tag bit a, the entry B includes an address bit B, a tag bit B, the entry C includes an address bit C, a tag bit C, and the entry D includes an address bit D, where the number of bits of the jump address is greater than the number of bits of the address bits of the entries, the entries of the packet are paired two by two, and form two entry pairs, that is, an entry pair formed by the entry a and an entry C, an entry D.

The table item A and the table item B are used table item pairs, a jump address a is stored, the table item A comprises an address bit a and a tag bit a, the address bit a stores the high bit of the jump address a, the tag bit a stores tag information a, the table item B comprises an address bit B and a tag bit B, the address bit B stores the low bit of the jump address a, and the tag bit B stores a target first subsection of a target jump address B; the table item C and the table item D are unused table item pairs, the table item C comprises an address bit C and a label bit C, the address bit C stores a target second partition of a target jump address b, the label bit C stores label information C, and the table item D is an idle table item. The grouped entry pair bit includes a "10" where a "1" indicates that entry a and entry B are paired, a used entry pair, and a "0" indicates that entry C and entry D are an unused entry pair. The tag pairing bit of the target packet includes "10", where the first bit "1" indicates that the address bit C (i.e., the target address bit) in entry C is paired with the tag bit B (i.e., the second tag bit) in the used entry pair of entries a, B, and the second bit "0" indicates that the address bit of entry D is unpaired with the tag bit B (i.e., the second tag bit) in the used entry pair of entries a, B.

Alternatively, in some embodiments, for an entry of the FTB, one entry pair includes 4 slots and two tag bits, one sub-tag pair is created for each slot, each sub-tag pair representing the pairing of the corresponding slot with the tag bit.

In particular, the sub-tag pairs are in the form of a plurality of binary bits. For example, one FTB packet includes four FTB entries, namely, an entry L, an entry M, an entry N, and an entry P, where the entry L and the entry M are used entry pairs, the entry N and the entry P are unused entry pairs, and the entry N includes 4 slots, namely, a slot N1, a slot N2, a slot N3, and a slot N4, respectively, where the slot N1 stores a second portion of the jump address M; the method comprises the steps of grouping 8 label bits, wherein a table item L comprises two label bits, namely label bit L1 and label bit L2, a table item M comprises two label bits, namely label bit M1 and label bit M2, a table item N comprises two label bits, namely label bit N1 and label bit N2, a table item P comprises two label bits, namely label bit P1 and label bit P2, a first subsection of a jump address M is stored in the label bit M2 of the table item M, a sub-label matching bit N1 corresponding to the slot N1 comprises ' 00010000 ', wherein a 1 st bit ' 0 ' indicates that the slot N1 is unpaired with the label bit L1, a 2 nd bit ' 0 ' indicates that the slot N1 is unpaired with the label bit L2, a 3 rd bit ' 0 ' indicates that the slot N1 is unpaired with the label bit M1, a 4 th bit ' 1 ' indicates that the slot N1 is paired with the label bit M2, a 5 ' 0 ' indicates that the slot N1 is unpaired with the label bit N1, a 6 ' 0 ' indicates that the slot N1 is unpaired with the slot N2 ' 7 ' bit ' and a ' 0 ' bit P ' 1 ' and ' 1 ' is unpaired with the slot 2 ' 0 ' and ' bit P ' 1 ' 2 ' indicates that the slot 1 is unpaired with the label.

In summary, in the embodiment of the present application, by acquiring the jump address of the branch instruction, and in the case where the number of bits of the jump address is greater than the number of bits of the address bits of the entry, the used entry pair is acquired from the branch target buffer; under the condition that the used table entry pair has an idle tag bit, acquiring a table entry corresponding to the idle tag bit and an idle table entry; the jump address is split into a first subsection and a second subsection, the first subsection is stored in the idle tag bit, and the second subsection is stored in the address bit of the idle table item, so that the first subsection of storing the jump address by using the idle tag bit in the used table item pair is realized, the waste of the idle tag bit in the used table item pair is reduced, and the problem of waste of storage resources caused by using one tag bit in the table item pair to store tag information and the other tag bit in the table item pair to be redundant in the prior art is solved.

Referring to fig. 5, a storage device for a branch instruction jump address provided in an embodiment of the present application is applied to a branch target buffer, where the branch target buffer includes a plurality of entries, and each of the entries includes a tag bit and an address bit, and the device includes:

A first obtaining module 301, configured to obtain a jump address of a branch instruction, and obtain a used table entry pair from the branch target buffer when a bit number of the jump address is greater than a bit number of an address bit of the table entry;

a second obtaining module 302, configured to obtain, in a case where an idle tag bit exists in the used table entry pair, a table entry corresponding to the idle tag bit and an idle table entry;

the storage module 303 is configured to split the jump address into a first section and a second section, store the first section in the free tag bit, and store the second section in the address bit of the free entry.

Optionally, the branch target buffer includes a plurality of packets, each packet including a plurality of entry pairs, each entry pair including two of the entries; the apparatus further comprises:

a third obtaining module, configured to obtain label bit pairing information of the packet according to a preset label bit of the packet; and the bits in the label matching bits are in one-to-one correspondence with the corresponding table entry pairs in the packet.

The second obtaining module 302 is specifically configured to obtain, when the tag bit pairing information includes that the used table entry pair has the idle tag bit, a table entry corresponding to the idle tag bit and an idle table entry.

Optionally, the apparatus further includes:

a first setting module, configured to set, in a case where a first entry pair exists in the packet, a value of a bit corresponding to the first entry pair in a corresponding tag pairing bit to a first value; the idle tag bit exists in the tag bits of the entries of the first entry pair;

a second setting module, configured to set, in a case where a second entry pair exists in the packet, a value of a bit corresponding to the first entry pair in a corresponding tag pairing bit to a second value; and the idle tag bit does not exist in the tag bits of the entries of the second entry pair.

Optionally, the third obtaining module specifically includes:

a first determining sub-module, configured to determine, in the tag matching bits, that the tag bit matching information includes that the used entry pair has the idle tag bit, in a case where a value of a bit corresponding to the used entry pair is the first value.

Optionally, the first obtaining module 301 specifically includes:

the first acquisition sub-module is used for acquiring the item pairing information of the group according to the preset item pairing bit of the group; bits in the table item matching bits correspond to the corresponding table item pairs in the group one by one;

And the second acquisition sub-module is used for acquiring the used table item pairs from the corresponding groups when the table item pairing information comprises that the used table item pairs exist in the groups.

Optionally, the apparatus further includes:

a third setting module, configured to set, in a case where a third table entry pair that has been used exists in the packet, a value of a bit corresponding to the third table entry pair in the corresponding table entry pair to a third value;

and a fourth setting module, configured to set, in a case where an unused fourth entry pair exists in the packet, a value of a bit corresponding to the fourth entry pair in the corresponding entry pair to a fourth value.

Optionally, the first obtaining sub-module specifically includes:

a second determining submodule, configured to determine that, in a case where a bit having the value of the third value exists in the table entry pairing bits, the table entry pairing information includes that the used table entry pair exists in the packet.

Optionally, the apparatus further includes:

a fourth obtaining module, configured to obtain a first tag bit corresponding to a target branch instruction, and determine a target table entry to which the first tag bit belongs;

A fifth obtaining module, configured to obtain target table entry pairing information of the target group according to a target table entry pairing bit of the target group to which the target table entry belongs;

a sixth obtaining module, configured to obtain, when the target entry pairing information includes that the target entry is not paired with another entry in the target packet, target tag bit pairing information of the target packet according to a tag pairing bit of the target packet;

a seventh obtaining module, configured to obtain, when the target tag bit pairing information includes that the target address bit of the target entry is paired with the second tag bit of a used entry pair, a target first portion of the target jump address of the target branch instruction from the second tag bit, and a target second portion of the target jump address from the target address bit, and then combine the target first portion and the target second portion into the target jump address.

Optionally, the apparatus further includes:

an eighth obtaining module, configured to obtain an idle entry pair when the idle tag bit does not exist in the used entry pair;

the first storage module is used for splitting the jump address into the first subsection and the second subsection, storing the first subsection in a first address bit in the idle table entry pair, and storing the second subsection in a second address bit in the idle table entry pair.

Optionally, the apparatus further includes:

a ninth obtaining module, configured to obtain unoccupied remaining bits in the occupied tag bits when occupied tag bits occupied by a previously stored jump address exist in the used entry pair;

a tenth obtaining module, configured to obtain one of the idle entries when the number of bits of the remaining bits is greater than the number of bits of the first partition;

and the second storage module is used for storing the first subsection in the residual bit and storing the second subsection in the address bit of the free table entry.

Optionally, the apparatus further includes:

an eleventh obtaining module, configured to obtain a first tag bit corresponding to a target branch instruction, and determine a target table entry to which the first tag bit belongs;

a twelfth acquisition module, configured to acquire a target address bit of the target entry and a second tag bit of a corresponding used entry pair;

a thirteenth obtaining module, configured to obtain, from the second tag bit, a target first portion of a target jump address of the target branch instruction, and obtain, from the target address bit, a target second portion of the target jump address, and then combine the target first portion and the target second portion into the target jump address.

Fig. 6 is a block diagram of an electronic device 600, according to an example embodiment. For example, the electronic device 600 may be a mobile phone, a computer, a digital broadcast terminal, a messaging device, a game console, a tablet device, a medical device, an exercise device, a personal digital assistant, and the like.

Referring to fig. 6, an electronic device 600 may include one or more of the following components: a processing component 602, a memory 604, a power component 606, a multimedia component 608, an audio component 610, an input/output (I/O) interface 612, a sensor component 614, and a communication component 616.

The processing component 602 generally controls overall operation of the electronic device 600, such as operations associated with display, telephone calls, data communications, camera operations, and recording operations. The processing component 602 may include one or more processors 620 to execute instructions to perform all or part of the steps of the methods described above. Further, the processing component 602 can include one or more modules that facilitate interaction between the processing component 602 and other components. For example, the processing component 602 may include a multimedia module to facilitate interaction between the multimedia component 608 and the processing component 602.

The memory 604 is used to store various types of data to support operations at the electronic device 600. Examples of such data include instructions for any application or method operating on the electronic device 600, contact data, phonebook data, messages, pictures, multimedia, and so forth. The memory 604 may be implemented by any type or combination of volatile or nonvolatile memory devices such as Static Random Access Memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic or optical disk.

The power supply component 606 provides power to the various components of the electronic device 600. The power supply components 606 can include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power for the electronic device 600.

The multimedia component 608 includes a screen between the electronic device 600 and the user that provides an output interface. In some embodiments, the screen may include a Liquid Crystal Display (LCD) and a Touch Panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive input signals from a user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensor may not only sense demarcations of touch or sliding actions, but also detect durations and pressures associated with the touch or sliding operations. In some embodiments, the multimedia component 608 includes a front camera and/or a rear camera. When the electronic device 600 is in an operational mode, such as a shooting mode or a multimedia mode, the front-facing camera and/or the rear-facing camera may receive external multimedia data. Each front camera and rear camera may be a fixed optical lens system or have focal length and optical zoom capabilities.

The audio component 610 is for outputting and/or inputting audio signals. For example, the audio component 610 includes a Microphone (MIC) for receiving external audio signals when the electronic device 600 is in an operational mode, such as a call mode, a recording mode, and a voice recognition mode. The received audio signals may be further stored in the memory 604 or transmitted via the communication component 616. In some embodiments, audio component 610 further includes a speaker for outputting audio signals.

The I/O interface 612 provides an interface between the processing component 602 and peripheral interface modules, which may be a keyboard, click wheel, buttons, etc. These buttons may include, but are not limited to: homepage button, volume button, start button, and lock button.

The sensor assembly 614 includes one or more sensors for providing status assessment of various aspects of the electronic device 600. For example, the sensor assembly 614 may detect an on/off state of the electronic device 600, a relative positioning of the components, such as a display and keypad of the electronic device 600, the sensor assembly 614 may also detect a change in position of the electronic device 600 or a component of the electronic device 600, the presence or absence of a user's contact with the electronic device 600, an orientation or acceleration/deceleration of the electronic device 600, and a change in temperature of the electronic device 600. The sensor assembly 614 may include a proximity sensor configured to detect the presence of nearby objects in the absence of any physical contact. The sensor assembly 614 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 614 may also include an acceleration sensor, a gyroscopic sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

The communication component 616 is utilized to facilitate communication between the electronic device 600 and other devices, either in a wired or wireless manner. The electronic device 600 may access a wireless network based on a communication standard, such as WiFi, an operator network (e.g., 2G, 3G, 4G, or 5G), or a combination thereof. In one exemplary embodiment, the communication component 616 receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In one exemplary embodiment, the communication component 616 further includes a Near Field Communication (NFC) module to facilitate short range communications. For example, the NFC module may be implemented based on Radio Frequency Identification (RFID) technology, infrared data association (IrDA) technology, ultra Wideband (UWB) technology, bluetooth (BT) technology, and other technologies.

In an exemplary embodiment, electronic device 600 may be implemented by one or more Application Specific Integrated Circuits (ASICs), digital Signal Processors (DSPs), digital Signal Processing Devices (DSPDs), programmable Logic Devices (PLDs), field Programmable Gate Arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic elements for implementing a method of storing branch instruction jump addresses as provided by embodiments of the present application.

In an exemplary embodiment, a non-transitory computer-readable storage medium is also provided, such as memory 604, including instructions executable by processor 620 of electronic device 600 to perform the above-described method. For example, the non-transitory storage medium may be ROM, random Access Memory (RAM), CD-ROM, magnetic tape, floppy disk, optical data storage device, etc.

Fig. 7 is a block diagram of an electronic device 700, according to an example embodiment. For example, the electronic device 700 may be provided as a server. Referring to fig. 7, electronic device 700 includes a processing component 722 that further includes one or more processors and memory resources represented by memory 732 for storing instructions, such as application programs, executable by processing component 722. The application programs stored in memory 732 may include one or more modules that each correspond to a set of instructions. In addition, processing component 722 is configured to execute instructions to perform a method for storing branch instruction jump addresses provided by embodiments of the present application.

The electronic device 700 may also include a power supply component 726 configured to perform power management of the electronic device 700, a wired or wireless network interface 750 configured to connect the electronic device 700 to a network, and an input output (I/O) interface 758. The electronic device 700 may operate based on an operating system stored in memory 732, such as Windows Server, mac OS XTM, unixTM, linuxTM, freeBSDTM, or the like.

The embodiment of the application also provides a computer program product, which comprises a computer program, wherein the computer program realizes the storage method of the branch instruction jump address when being executed by a processor.

Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. This application is intended to cover any variations, uses, or adaptations of the application following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the application pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.

It is to be understood that the present application is not limited to the precise arrangements and instrumentalities shown in the drawings, which have been described above, and that various modifications and changes may be effected without departing from the scope thereof. The scope of the application is limited only by the appended claims.

The foregoing description of the preferred embodiments of the present application is not intended to limit the invention to the particular embodiments of the present application, but to limit the scope of the invention to the particular embodiments of the present application.

The foregoing has described in detail the methods, apparatuses, electronic devices and computer readable storage medium for storing branch instruction jump addresses provided in the present application, and specific examples have been applied to illustrate the principles and embodiments of the present application, where the foregoing examples are provided to assist in understanding the methods and core ideas of the present application; meanwhile, as those skilled in the art will have modifications in the specific embodiments and application scope in accordance with the ideas of the present application, the present description should not be construed as limiting the present application in view of the above.

Claims

1. A method of storing a branch instruction jump address for use in a branch target buffer, said branch target buffer comprising a plurality of entries, each of said entries comprising a tag bit and an address bit, said method comprising:

Splitting a jump address into a first part and a second part, storing the first part in the idle tag bit, and storing the second part in the address bit of the idle table item;

wherein said branch target buffer comprises a plurality of packets, each of said packets comprising a plurality of entry pairs, each of said entry pairs comprising two of said entries; each of the packets has a corresponding tag and entry alignment bit;

after splitting the jump address into a first partition and a second partition, storing the first partition in the free tag bit, and storing the second partition in the address bit of the free entry, the method further includes:

acquiring a first tag bit corresponding to a target branch instruction, and determining a target table item to which the first tag bit belongs;

acquiring target table item pairing information of the target group according to target table item pairing bits of the target group to which the target table item belongs;

and under the condition that the target table item pairing information comprises that the target table item is not paired with other table items in the target packet, acquiring target tag bit pairing information of the target packet according to tag pairing bits of the target packet.

2. The method of claim 1, wherein, in the case that there is an idle tag bit in the used entry pair, before obtaining an entry corresponding to the idle tag bit and an idle entry, the method further comprises:

acquiring label bit pairing information of the group according to preset label pairing bits of the group; bits in the tag matching bits correspond to corresponding table entry pairs in the packet one by one;

under the condition that the idle tag bit exists in the used table entry pair, acquiring the table entry corresponding to the idle tag bit and an idle table entry, wherein the method comprises the following steps:

and under the condition that the tag bit pairing information comprises that the used table entry pair has the idle tag bit, acquiring the table entry corresponding to the idle tag bit and an idle table entry.

3. The method according to claim 2, wherein the method further comprises:

setting a value of a bit corresponding to a first entry pair in a corresponding tag pairing bit to a first value in the case that the first entry pair exists in the packet; the idle tag bit exists in the tag bits of the entries of the first entry pair;

Setting a value of a bit corresponding to the first entry pair in a corresponding tag pair to a second value in the case that a second entry pair exists in the packet; and the idle tag bit does not exist in the tag bits of the entries of the second entry pair.

4. The method of claim 3, wherein the obtaining tag bit pair information of the packet according to the preset tag pair bits of the packet comprises:

in the tag pairing bits, if a value of a bit corresponding to the used entry pair is the first value, determining that the tag bit pairing information includes that the used entry pair has the idle tag bit.

5. The method of claim 2, wherein the obtaining the used entry pairs from the branch target buffer comprises:

acquiring item pairing information of the group according to preset item pairing bits of the group; bits in the table item matching bits correspond to the corresponding table item pairs in the group one by one;

and acquiring the used table item pairs from the corresponding grouping when the table item pairing information comprises the used table item pairs in the grouping.

6. The method of claim 5, wherein the method further comprises:

setting, in the case where there is a third entry pair that has been used in the packet, a value of a bit corresponding to the third entry pair in the corresponding entry pair to a third value;

in the case where there is an unused fourth entry pair in the packet, the value of the bit corresponding to the fourth entry pair in the corresponding entry pair is set to a fourth value.

7. The method of claim 6, wherein the obtaining the entry pairing information of the packet according to the preset entry pairing bits of the packet comprises:

in the case that there is a bit of the third value in the table entry pairing bits, determining that the table entry pairing information includes the used table entry pair being present in the packet.

8. The method according to claim 1, wherein the method further comprises:

and under the condition that the target tag bit pairing information comprises the target address bit of the target table item and the second tag bit of one used table item pair, acquiring a target first subsection of the target jump address of the target branch instruction from the second tag bit, acquiring a target second subsection of the target jump address from the target address bit, and then forming the target first subsection and the target second subsection into the target jump address.

9. The method of claim 1, wherein, in the case where the number of bits of the jump address is greater than the number of bits of the address bits of the entry, after obtaining the used entry pair from the branch target buffer, the method further comprises:

acquiring an idle table entry pair under the condition that the idle tag bit does not exist in the used table entry pair;

splitting the jump address into the first subsection and the second subsection, storing the first subsection in a first address bit in the free entry pair, and storing the second subsection in a second address bit in the free entry pair.

10. The method of claim 1, wherein, in the case where the number of bits of the jump address is greater than the number of bits of the address bits of the entry, after obtaining the used entry pair from the branch target buffer, the method further comprises:

under the condition that occupied tag bits occupied by the jump address stored in advance exist in the used table entry pairs, unoccupied residual bits in the occupied tag bits are acquired;

acquiring one free table item under the condition that the bit number of the residual bit is larger than that of the first subsection;

Storing the first partition in the remaining bits and the second partition in address bits of the free entry.

11. The method of claim 1, wherein the splitting the jump address into a first partition and a second partition, then storing the first partition in the free tag bit, and storing the second partition in the address bit of the free entry, the method further comprising:

acquiring a target address bit of the target table item and a second tag bit of a corresponding used table item pair;

the method comprises the steps of obtaining a target first subsection of a target jump address of the target branch instruction from the second tag bit, obtaining a target second subsection of the target jump address from the target address bit, and forming the target jump address by the target first subsection and the target second subsection.

12. A storage device for branch instruction jump addresses for use in a branch target buffer, said branch target buffer comprising a plurality of entries, each of said entries comprising a tag bit and an address bit, said device comprising:

the storage module is used for splitting the jump address into a first subsection and a second subsection, storing the first subsection in the idle tag bit and storing the second subsection in the address bit of the idle table item;

the apparatus further comprises:

And a sixth obtaining module, configured to obtain, when the target entry pairing information includes that the target entry is not paired with another entry in the target packet, target tag bit pairing information of the target packet according to a tag pairing bit of the target packet.

13. An electronic device, comprising: a processor;

a memory for storing the processor-executable instructions;

wherein the processor is configured to execute the instructions to implement the method of any one of claims 1 to 11.

14. A computer readable storage medium, characterized in that instructions in the computer readable storage medium, when executed by a processor of an electronic device, enable the electronic device to perform the method of any one of claims 1 to 11.