CN114598323A - Clock duty ratio calibration circuit - Google Patents

Clock duty ratio calibration circuit Download PDF

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Publication number
CN114598323A
CN114598323A CN202210094866.8A CN202210094866A CN114598323A CN 114598323 A CN114598323 A CN 114598323A CN 202210094866 A CN202210094866 A CN 202210094866A CN 114598323 A CN114598323 A CN 114598323A
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China
Prior art keywords
transistor
module
duty ratio
inverter
differential
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于金鑫
李秀冬
欧阳鹏
王博
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Jiangsu Qingwei Intelligent Technology Co ltd
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Jiangsu Qingwei Intelligent Technology Co ltd
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Priority to CN202210094866.8A priority Critical patent/CN114598323A/en
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/10—Calibration or testing
    • H03M1/1009—Calibration
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/156—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern

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  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Pulse Circuits (AREA)

Abstract

The invention discloses a clock duty ratio calibration circuit, comprising: the device comprises a duty ratio adjusting module, a single-ended to differential module, a duty ratio detecting module and a low-pass filter module, wherein the duty ratio adjusting module comprises a clock differential input end, a control voltage differential input end and a clock differential output end and is used for adjusting the duty ratio of an input clock signal; the input end of the single-ended to differential conversion module is connected with the clock differential output end of the duty ratio adjusting module and is used for converting a single-ended output signal of the duty ratio adjusting module into a differential output signal; the differential input end of the duty ratio detection module is connected with the output end of the single-end to differential module and is used for detecting the duty ratio of the adjusted clock; and the input end of the low-pass filter module is connected with the output end of the duty ratio detection module, and the output end of the low-pass filter module is connected with the control voltage differential input end of the duty ratio regulation module, and the low-pass filter module is used for performing low-pass filtering on the control voltage output by the duty ratio detection module and reducing control signal jitter.

Description

Clock duty ratio calibration circuit
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a clock duty ratio calibration circuit.
Background
In a high-speed serial transceiver, a high-speed Pipeline analog-to-digital converter (Pipeline ADC) and a high-frequency radio frequency module circuit, a clock signal with a 50% duty ratio can provide the maximum application efficiency and time margin, so that the normal operation and performance of a system are ensured. However, due to the increase of clock frequency, temperature variation, process variation, transmission delay, and the like, the clock duty ratio often deviates from an optimal value, and therefore, a clock duty ratio adjusting circuit is required to adjust the clock duty ratio, and the calibration accuracy and the calibration frequency range of the clock duty ratio calibration circuit in the related art are limited.
In view of the technical problem that the calibration of the clock duty ratio is difficult due to the limitations of the calibration accuracy and the calibration frequency of the conventional clock duty ratio adjusting circuit in the prior art, no effective solution has been proposed at present.
Disclosure of Invention
The invention discloses a clock duty ratio calibration circuit, which at least solves the technical problem that the clock duty ratio is difficult to calibrate due to the limitations of calibration precision and calibration frequency of the existing clock duty ratio regulation circuit in the prior art.
According to an aspect of the present invention, there is provided a clock duty calibration circuit, including: the device comprises a duty ratio adjusting module, a single-ended to differential module, a duty ratio detecting module and a low-pass filter module, wherein the duty ratio adjusting module comprises a clock differential input end, a control voltage differential input end and a clock differential output end and is used for adjusting the duty ratio of an input clock signal; the input end of the single-ended to differential conversion module is connected with the clock differential output end of the duty ratio adjusting module and is used for converting a single-ended output signal of the duty ratio adjusting module into a differential output signal; the differential input end of the duty ratio detection module is connected with the output end of the single-ended to differential conversion module and is used for detecting the duty ratio of the adjusted clock; and the input end of the low-pass filter module is connected with the output end of the duty ratio detection module, and the output end of the low-pass filter module is connected with the control voltage differential input end of the duty ratio regulation module, and the low-pass filter module is used for performing low-pass filtering on the control voltage output by the duty ratio detection module and reducing control signal jitter.
Optionally, the duty cycle adjusting module is composed of a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, a first current source and a second current source, wherein the first transistor, the second transistor, the third transistor and the fourth transistor are NMOS transistors in a diode connection form; and the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, and the tenth transistor are PMOS transistors.
Optionally, the clock differential input terminal is respectively connected with the gates of the first transistor and the second transistor; the control voltage differential input end is respectively connected with the grid electrodes of the third transistor and the fourth transistor; the sources of the first transistor and the second transistor are connected and connected with a first current source to the ground, and the sources of the third transistor and the fourth transistor are connected and connected with a second current source to the ground; drains of the first transistor and the third transistor are connected with a gate and a drain of the fifth transistor and a drain of the eighth transistor; the drains of the second transistor and the fourth transistor are connected with the grid and the drain of the sixth transistor and the drain of the seventh transistor; the source electrodes of the fifth transistor, the sixth transistor, the seventh transistor and the eighth transistor are connected with a power supply; a drain and a gate of the ninth transistor and a gate of the tenth transistor are connected to a drain of the seventh transistor; and a drain of the eighth transistor is connected to a drain of the tenth transistor; and the sources of the ninth transistor and the tenth transistor are grounded.
Optionally, the single-ended to differential conversion module is composed of a first resistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, and a sixth inverter, where the eleventh transistor, the twelfth transistor, the thirteenth transistor, and the fourteenth transistor are MOS transistors.
Optionally, the second inverter, the fourth inverter, and the fifth inverter are twice as large in size as the first inverter; the third inverter and the sixth inverter are four times as large as the first inverter; and the sizes of the thirteenth transistor and the fourteenth transistor are the same as the size of the MOS transistor in the second inverter.
Optionally, the input end of the single-ended to differential conversion module is connected to the gates of the eleventh transistor and the twelfth transistor and one end of the first resistor; the sources of the eleventh transistor and the twelfth transistor are respectively connected with the power supply and the ground, and the drains of the eleventh transistor and the twelfth transistor are both connected with the other end of the first resistor and connected with the input end of the first inverter; the output end of the first inverter is connected with the input ends of the second inverter and the fourth inverter; the output end of the second inverter is connected with the drains of the thirteenth transistor and the fourteenth transistor; the sources of the thirteenth transistor and the fourteenth transistor are connected with the input end of the third inverter, and the source of the thirteenth transistor is connected with the power supply and the source of the fourteenth transistor is grounded; the output end of the fourth phase inverter is connected with the input end of the fifth phase inverter, the output end of the fifth phase inverter is connected with the output end of the sixth phase inverter, and the output ends of the third phase inverter and the sixth phase inverter are respectively connected with the output end of the single-end differential conversion module.
Optionally, the duty cycle detection module is composed of a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, a twentieth transistor, a first capacitor, a second capacitor and a third current source, wherein the fifteenth transistor and the sixteenth transistor are NMOS transistors in a differential diode connection form; the seventeenth transistor, the eighteenth transistor, the nineteenth transistor, and the twentieth transistor are PMOS transistors; and the third current source is a direct current source.
Optionally, gates of the fifteenth transistor and the sixteenth transistor are respectively connected to the input end of the duty ratio detection module, sources of the fifteenth transistor and the sixteenth transistor are connected to the third current source, and drains of the fifteenth transistor and the sixteenth transistor are respectively connected to the output end of the duty ratio detection module; sources of the seventeenth transistor, the eighteenth transistor, the nineteenth transistor and the twentieth transistor are connected to a power supply; the grid and the drain of the seventeenth transistor, the drain of the eighteenth transistor and the grid of the nineteenth transistor are connected to the output end of the duty cycle detection module; the grid electrode and the drain electrode of the twentieth transistor, the drain electrode of the nineteenth transistor and the grid electrode of the eighteenth transistor are connected to the output end of the duty ratio detection module; and the lower polar plates of the first capacitor and the second capacitor are grounded, and the upper polar plates are respectively connected with the output end of the duty ratio detection module.
Optionally, the low pass filter module is composed of a second resistor, a third capacitor and a fourth capacitor.
Optionally, one end of the second resistor and one end of the third resistor are respectively connected to the output end of the duty ratio detection module, and the other end of the second resistor and the other end of the third resistor are respectively connected to the output end of the low-pass filter module; and the upper pole plates of the third capacitor and the fourth capacitor are respectively connected with the control voltage differential input end of the duty ratio adjusting module.
According to the clock duty ratio calibration circuit provided by the embodiment of the invention, the calibration of the clock duty ratio is realized through the duty ratio adjusting module, the single-ended to differential module, the duty ratio detecting module and the low-pass filter module. The duty ratio adjusting module comprises a clock differential input end, a control voltage differential input end and a clock differential output end, is used for adjusting the duty ratio of an input clock signal, and outputs a single-ended signal. The clock differential output end is connected with the input end of the single-end to differential module. The input end of the single-ended to differential module receives the single-ended signal output by the duty ratio adjusting module, and then the single-ended signal is converted into a differential signal to be output through the output end. The input end of the duty ratio detection module is respectively connected with the output end of the single-end to differential conversion module, and the duty ratio of the adjusted clock is detected. The input end of the low-pass filter module is connected with the output end of the duty ratio detection module, low-pass filtering is carried out on the control voltage output by the duty ratio detection module, control signal jitter is reduced, and then the differential voltage is connected with the input end of the duty ratio adjustment module through the output end. Therefore, through the mode, the clock duty ratio calibration circuit provided by the invention can finish the duty ratio calibration of the high-speed clock under the condition that an external reference source is not needed. And the technical problem that the clock duty ratio is difficult to calibrate due to the limitations of calibration precision and calibration frequency of the conventional clock duty ratio regulating circuit in the prior art is solved.
The above and other objects, advantages and features of the present invention will become more apparent to those skilled in the art from the following detailed description of specific embodiments thereof, taken in conjunction with the accompanying drawings.
Drawings
Some specific embodiments of the invention will be described in detail hereinafter, by way of illustration and not limitation, with reference to the accompanying drawings. The same reference numbers in the drawings identify the same or similar elements or components. Those skilled in the art will appreciate that the drawings are not necessarily drawn to scale. In the drawings:
FIG. 1 is a schematic diagram of a clock duty cycle calibration circuit in an embodiment in accordance with the invention;
FIG. 2 is a circuit schematic of the duty cycle adjustment module shown in FIG. 1;
FIG. 3 is a circuit schematic of the single-ended to differential module shown in FIG. 1;
FIG. 4 is a circuit schematic of the duty cycle detection module shown in FIG. 1; and
fig. 5 is a circuit schematic of the low pass filter module shown in fig. 1.
Detailed Description
It should be noted that, in the present disclosure, the embodiments and the features of the embodiments may be combined with each other without conflict. The present disclosure will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.
In order to make the technical solutions of the present disclosure better understood by those skilled in the art, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure, and it is obvious that the described embodiments are only some embodiments of the present disclosure, not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments disclosed herein without making any creative effort, shall fall within the protection scope of the present disclosure.
It should be noted that the terms "first," "second," and the like in the description and claims of the present disclosure and in the above-described drawings are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances for describing the embodiments of the disclosure herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of exemplary embodiments according to the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, and it should be understood that when the terms "comprises" and/or "comprising" are used in this specification, they specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof, unless the context clearly indicates otherwise.
Fig. 1 is a schematic diagram of a clock duty calibration circuit according to an embodiment of the present invention, and referring to fig. 1, the clock duty calibration circuit includes: the duty ratio adjusting module 10 comprises a clock differential input end, a control voltage differential input end and a clock differential output end, and is used for adjusting the duty ratio of an input clock signal; the input end of the single-ended to differential conversion module 20 is connected to the clock differential output end of the duty ratio adjusting module 10, and is configured to convert the single-ended output signal of the duty ratio adjusting module 10 into a differential output signal; the differential input end of the duty ratio detection module 30 is connected with the output end of the single-ended to differential conversion module 20, and is used for detecting the duty ratio of the adjusted clock; and the input end of the low-pass filter module 40 is connected to the output end of the duty ratio detection module 30, and the output end is connected to the control voltage differential input end of the duty ratio adjustment module 10, so as to perform low-pass filtering on the control voltage output by the duty ratio detection module 30 and reduce the jitter of the control signal.
As described in the background art, in a high-speed serial transceiver, a high-speed Pipeline analog-to-digital converter (Pipeline ADC) and a high-frequency rf module circuit, a clock signal with a 50% duty cycle can provide maximum application efficiency and time margin, thereby ensuring normal operation and performance of a system. However, due to the increase of clock frequency, temperature variation, process variation, transmission delay, and the like, the clock duty ratio often deviates from an optimal value, and therefore, a clock duty ratio adjusting circuit is required to adjust the clock duty ratio, and the calibration accuracy and the calibration frequency range of the clock duty ratio calibration circuit in the related art are limited.
In view of this, referring to fig. 1, the clock duty ratio calibration circuit provided in the present invention implements the calibration of the clock duty ratio through the duty ratio adjustment module 10, the single-ended to differential module 20, the duty ratio detection module 30, and the low pass filter module 40. The duty ratio adjusting module 10 includes a clock differential input terminal CLKin +, CLKin-, a control voltage differential input terminal Vc +, Vc-, and a clock differential output terminal CLKouta, and is configured to adjust a duty ratio of an input clock signal and output the duty ratio as a single-ended signal. The clock differential output CLKouta is connected to an input of the single-ended to differential module 20. The input terminal CLKin of the single-ended-to-differential module 20 receives the single-ended signal output by the duty ratio adjusting module 10, and then converts the single-ended signal into a differential signal to be output through the output terminals CLKout +, CLKout-. The input terminals CLK and CLK of the duty ratio detection module 30 are connected to the output terminals CLKout + and CLKout of the single-ended differential conversion module 20, respectively, and detect the duty ratio of the adjusted clock. The input end of the low pass filter module 40 is connected to the output end out +, out-of the duty ratio detection module 30, and is used for low pass filtering the control voltage output by the duty ratio detection module 30 to reduce the jitter of the control signal, and then connecting the differential voltage to the input end Vc +, Vc-of the duty ratio adjustment module 10 through the output end. Therefore, through the mode, the clock duty ratio calibration circuit provided by the invention can finish duty ratio calibration of a high-speed clock under the condition of not needing an external reference source. And the technical problem that the clock duty ratio is difficult to calibrate due to the limitations of calibration precision and calibration frequency of the conventional clock duty ratio regulating circuit in the prior art is solved.
In addition, referring to fig. 1, the clock duty calibration circuit provided by the present invention realizes clock duty calibration. Specifically, with the circuit provided by the present invention, the signal processing procedure is as follows: when the circuit starts to work, the control voltage difference input end Vc + is equal to Vc-, if the duty ratio of the input clock duty ratio CLKIn + signal is less than 50%, the duty ratio of the CLKIn-signal is more than 50%, the control voltage difference input end Vc + flows through a fifth transistor M in the duty ratio adjusting module 105Is less than the current flowing through the sixth transistor M6The duty ratio of the output CLKouta signal is also less than 50%, then the duty ratio of the output CLKout + signal of the single-end to differential module 20 is less than 50%, the duty ratio of the output CLKout-signal is more than 50%, the output VC + after passing through the feedback circuit duty ratio detection module 30 and the low pass filter module 40 is less than VC-, acting on the duty ratio adjustment module 10 to compensate the fifth transistor M in the duty ratio adjustment module 105And a sixth transistor M6So that the duty cycle of the final outputs CLKout + and CLKout-equals 50%.
In addition, the invention has high duty ratio calibration precision through the arrangement, and can realize the 1% duty ratio calibration precision in the clock working frequency of 500MHz-6 GHz.
Optionally, the duty cycle adjusting module 10 is composed of a first transistor M1A second transistor M2A third transistor M3A fourth transistor M4A fifth transistor M5And a sixth transistor M6The seventh transistor M7An eighth transistor M8The ninth transistor M9A tenth transistor M10, a first current source Id1And a second current source Id2Composition of, wherein the first transistor M1A second transistor M2A third transistor M3And a fourth transistor M4An NMOS transistor in a diode-connected form; and a fifth transistor M5A sixth transistor M6The seventh transistor M7An eighth transistor M8The ninth transistor M9And a tenth transistor M10Is a PMOS transistor.
Specifically, referring to FIG. 2, duty cycles are shownA circuit schematic of the ratio regulating module 10, wherein the first transistor M1-fourth transistor M4The same size, the fifth transistor M5And a sixth transistor M6Same size, first current Id1And a second current Id2The same DC current, the seventh transistor M7The tenth transistor M10A second-stage push-pull output stage is formed to continuously amplify the output signal and realize the superposition of the differential signal, when the duty ratio of the input clock signal is 50%, the output VC + of the duty ratio detection module 10 and the filter is equal to VC-, equal currents are output at points A and B when the clock signals CLKIn + and CLKIn-at the clock differential input end are started, equal currents are also output at points A and B by the control signals VC + and VC-, and the current at the point B passes through a fifth transistor M5The seventh transistor M7The ninth transistor M9The tenth transistor M10After the mirror image reaches the output node CLCoota and the eighth transistor M8So that the CLKouta output is a 50% clock signal; when the duty ratio of the input clock has deviation, for example less than 50%, the first transistor M1Is less than the second transistor M2Therefore, the output current at the point A is smaller than the output current at the point B, and flows through the eighth transistor M8Is less than the current flowing through the tenth transistor M10The duty ratio of the output signal of CLkouta is smaller than 50%, and the analysis of the duty ratio detection module can know that VC-is larger than VC + at the moment, so that the current interpolation caused by the error of the input clock duty ratio is compensated.
Alternatively, as shown in FIG. 2, the clock differential inputs CLKin +, CLKin-are connected to the first transistor M, respectively1And a second transistor M2A gate electrode of (1); the control voltage differential input terminals Vc-Vc + are respectively connected with the third transistor M3And a fourth transistor M4A gate electrode of (1); first transistor M1And a second transistor M2Is connected in parallel with a first current source Id1To ground, a third transistor M3And a fourth transistor M4Is connected with the source electrode of the first current source I in paralleld2To ground; first transistor M1And a third transistor M3Drain electrode of (1) and fifthTransistor M5And an eighth transistor M8Is connected with the drain electrode of the transistor; second transistor M2And a fourth transistor M4And the sixth transistor M6And a seventh transistor M7The drain electrodes of the first and second transistors are connected; fifth transistor M5A sixth transistor M6The seventh transistor M7An eighth transistor M8The source of the transistor is connected with a power supply VDD; seventh transistor M7And the ninth transistor M9And a tenth transistor M10The gate of (1) is connected; and an eighth transistor M8And a tenth transistor M10Is connected with the drain electrode of the transistor; and a ninth transistor M9And a tenth transistor M10Is grounded. Therefore, the effect of adjusting the duty ratio of the input clock signal by the duty ratio adjusting module 10 is achieved through the above connection mode.
Optionally, the single-ended to differential module 20 is formed by a first resistor R1Eleventh transistor M11The twelfth transistor M12Thirteenth transistor M13Fourteenth transistor M14A first inverter INV1And a second inverter INV2A third inverter INV3And a fourth inverter INV4The fifth inverter INV5And a sixth inverter INV6Composition of, wherein the eleventh transistor M11The twelfth transistor M12Thirteenth transistor M13And a fourteenth transistor M14Is a MOS transistor.
Specifically, referring to fig. 3, which shows a circuit schematic of the single-ended to differential module 20, the first resistor R1The effect of CLKin is to clamp the DC voltage point of input CLKin to about 0.5 VDD, reduce the duty cycle error introduced by the circuit, through the first inverter INV1Is driven and then divided into two signals, a thirteenth transistor M3Fourteenth transistor M4Is provided with a fifth inverter INV5The same delay ensures that the output differential signal has a smaller phase error at high frequency, and the CLKOUT + and CLKOUT-signals are the calibrated differential clock signal.
Optionally, a second inverter INV2And a fourth inverter INV4And a fifth inverter INV5Is the first inverter INV1Twice of; third inverter INV3And a sixth inverter INV6Is the first inverter INV1Four times that of; and a thirteenth transistor M13Fourteenth transistor M14Size of and second inverter INV2The MOS tubes in (1) have the same size. Wherein, the inverter INV1～INV6Dimension refers to inverter INV1～INV6Width to length ratio of middle transistor, thirteenth transistor M13And a fourteenth transistor M14Is referred to as a thirteenth transistor M13Fourteenth transistor M14Width to length ratio of (a). Therefore, the driving capability is enhanced through the above arrangement, and the effect of converting the single-ended signal into the differential signal by the single-ended-to-differential module 20 is further ensured.
Alternatively, referring to fig. 3, the input terminal CLKin of the single-ended-to-differential module 20 is connected to the eleventh transistor M11And a twelfth transistor M12And a first resistor R1One end of (a); eleventh transistor M11And a twelfth transistor M12Respectively connected with a power supply VDD and a ground, and a drain electrode and a first resistor R1Is connected to the first inverter INV1An input terminal of (1); first inverter INV1Is connected with the second inverter INV2And a fourth inverter INV4An input terminal of (1); second inverter INV2Is connected with the thirteenth transistor M13And a drain of the fourteenth transistor M14; the sources of the thirteenth transistor M13 and the fourteenth transistor M14 are connected to the third inverter INV3Of the thirteenth transistor M13A source connected to the power supply and a fourteenth transistor M14The source of (2) is grounded; fourth inverter INV4Is connected with the fifth inverter INV5The fifth inverter INV5Is connected with the sixth inverter INV6The output end of the third inverter INV3And a sixth inverter INV6The output ends of the two differential modules are respectively connected with a single-end differential moduleThe output terminals CLKout +, CLKout-of 20. Thus, in the above manner, the single-ended to differential module 20 achieves the effect of converting the single-ended output signal of the duty ratio adjusting module 10 into the differential output signal.
Optionally, the duty ratio detection module 30 is composed of a fifteenth transistor M15Sixteenth transistor M16Seventeenth transistor M17Eighteenth transistor M18Nineteenth transistor M19Twentieth transistor M20A first capacitor Cs1A second capacitor Cs2And a third current source Id3Composition of, wherein the fifteenth transistor M15And a sixteenth transistor M16An NMOS transistor in the form of a differential diode connection; seventeenth transistor M17Eighteenth transistor M18Nineteenth transistor M19And the twentieth transistor M20Is a PMOS transistor; and a third current source Id3Is a direct current source.
Specifically, referring to fig. 4, a circuit diagram of the duty cycle adjusting module 10 is shown, in which the fifteenth transistor M1 to the twentieth transistor M6And a first capacitor CS1And a second capacitor CS2An integrator in the form of a charge pump for the fifteenth transistor M of CLK + and CLK-if the duty cycle of the input CLK signal is not 50%1And a sixteenth transistor M2Different charging and discharging times will result in integrating the first capacitance CS1And a second capacitor CS2There are different integrated voltages, so the duty cycle detection module 30 can convert the duty cycle information of the input signal into differential control voltages out + and out-output, but the differential control signal contains clock frequency information, which needs to be low-pass filtered, and the output voltage out + is less than out when the CLK + duty cycle is greater than 50%, and the output voltage out + is greater than out when the CLK + duty cycle is less than 50%.
Alternatively, as shown with reference to fig. 4, a fifteenth transistor M15And a sixteenth transistor M16Respectively connected to the input terminals CLK +, CLK-, of the duty cycle detection module 30, and the source connected to the third current source Id3The drain is connected to the output end out + of the duty ratio detection module 30,out-; seventeenth transistor M17Eighteenth transistor M18Nineteenth transistor M19And a twentieth transistor M20The source is connected to a power supply VDD; seventeenth transistor M17Gate and drain of (1), eighteenth transistor M18Drain electrode of (1), nineteenth transistor M19Is connected to the output out + of the duty cycle detection block 30; twentieth transistor M20Gate and drain of (1), nineteenth transistor M19Drain electrode of (1), eighteenth transistor M18Is connected to the output out-of the duty cycle detection module 30; and a first capacitor Cs1And a second capacitor Cs2The lower pole plate of (2) is grounded, and the upper pole plate is respectively connected with the output end out + and out-of the duty ratio detection module 30. Thus, with the above arrangement, the duty ratio detection module 30 achieves an effect of detecting the duty ratio of the adjusted clock.
Optionally, the low pass filter module 40 is formed by a second resistor R2A third resistor R3A third capacitor C3And a fourth capacitance C4And (4) forming.
Specifically, referring to FIG. 5, which shows a circuit schematic of the low pass filter module 40, the second resistor R2A third capacitor C3And R3Third resistor R3A fourth capacitor C4A differential first-order low-pass filter is formed, which can output the gentle differential control voltages VC + and VC-after low-pass filtering the clock frequency information of the output differential control voltages out + and out-of the duty ratio detection module 30.
Optionally, a second resistor R2And a third resistor R3One end of the low pass filter is connected with the output end Vc + and Vc-of the low pass filter module 40, and the other end of the low pass filter is connected with the output end out + and out-of the duty ratio detection module 30; and a third capacitor C3And a fourth capacitance C4And the upper polar plate is respectively connected with the control voltage differential input end Vc + and Vc-of the duty ratio adjusting module 10. Therefore, in the above manner, the low-pass filter module 40 performs low-pass filtering on the control voltage output by the duty ratio detection module 30, so as to reduce the jitter of the control signal.
Therefore, according to the embodiment of the present invention, the provided clock duty ratio calibration circuit calibrates the clock duty ratio through the duty ratio adjusting module 10, the single-ended to differential module 20, the duty ratio detecting module 30, and the low-pass filter module 40. The duty ratio adjusting module 10 includes a clock differential input terminal CLKin +, CLKin-, a control voltage differential input terminal Vc +, Vc-, and a clock differential output terminal CLKouta, and is configured to adjust a duty ratio of an input clock signal and output the duty ratio as a single-ended signal. The clock differential output CLKouta is connected to an input of the single-ended to differential module 20. The input terminal CLKin of the single-ended-to-differential module 20 receives the single-ended signal output by the duty ratio adjusting module 10, and then converts the single-ended signal into a differential signal to be output through the output terminals CLKout +, CLKout-. The input terminals CLK + and CLK-of the duty cycle detection module 30 are connected to the output terminals CLKout +, CLKout-of the single-ended differential-to-differential module 20, respectively, to detect the duty cycle of the adjusted clock. The input end of the low pass filter module 40 is connected to the output end out +, out-of the duty ratio detection module 30, and is configured to perform low pass filtering on the control voltage output by the duty ratio detection module 30 to reduce the jitter of the control signal, and then connect the differential voltage to the input end Vc +, Vc-of the duty ratio adjustment module 10 through the output end. Therefore, through the mode, the clock duty ratio calibration circuit provided by the invention can finish the duty ratio calibration of the high-speed clock under the condition that an external reference source is not needed. Therefore, the technical problem that the clock duty ratio is difficult to calibrate due to the limitations of calibration precision and calibration frequency of the conventional clock duty ratio regulating circuit in the prior art is solved.
The relative arrangement of the components and steps, the numerical expressions, and numerical values set forth in these embodiments do not limit the scope of the present disclosure unless specifically stated otherwise. Meanwhile, it should be understood that the sizes of the respective portions shown in the drawings are not drawn in an actual proportional relationship for the convenience of description. Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate. In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values. It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.
Spatially relative terms, such as "above … …," "above … …," "above … … surface," "above," and the like, may be used herein for ease of description to describe one device or feature's spatial relationship to another device or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is turned over, devices described as "above" or "on" other devices or configurations would then be oriented "below" or "under" the other devices or configurations. Thus, the exemplary term "above … …" can include both an orientation of "above … …" and "below … …". The device may be otherwise variously oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
In the description of the present disclosure, it is to be understood that the orientation or positional relationship indicated by the directional terms such as "front, rear, upper, lower, left, right", "lateral, vertical, horizontal" and "top, bottom", etc., are generally based on the orientation or positional relationship shown in the drawings, and are presented only for the convenience of describing and simplifying the disclosure, and in the absence of a contrary indication, these directional terms are not intended to indicate and imply that the device or element being referred to must have a particular orientation or be constructed and operated in a particular orientation, and therefore, should not be taken as limiting the scope of the disclosure; the terms "inner and outer" refer to the inner and outer relative to the profile of the respective component itself.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims (10)

1. A clock duty cycle calibration circuit, comprising: a duty cycle adjusting module (10), a single-end to differential module (20), a duty cycle detecting module (30) and a low pass filter module (40), wherein
The duty ratio adjusting module (10) comprises a clock differential input end, a control voltage differential input end and a clock differential output end and is used for adjusting the duty ratio of an input clock signal;
the input end of the single-ended to differential conversion module (20) is connected with the clock differential output end of the duty ratio regulation module (10) and is used for converting a single-ended output signal of the duty ratio regulation module (10) into a differential output signal;
the differential input end of the duty ratio detection module (30) is connected with the output end of the single-ended to differential module (20) and is used for detecting the duty ratio of the adjusted clock; and
the input end of the low-pass filter module (40) is connected with the output end of the duty ratio detection module (30), and the output end of the low-pass filter module is connected with the control voltage differential input end of the duty ratio regulation module (10), so that the low-pass filter module is used for performing low-pass filtering on the control voltage output by the duty ratio detection module (30) and reducing control signal jitter.
2. The clock duty cycle calibration circuit of claim 1, wherein the duty cycle adjustment module (10) comprises: a first transistor (M)1) A second transistor (M)2) And a third transistor (M)3) A fourth transistor (M)4) A fifth transistor (M)5) And a sixth transistor (M)6) A seventh transistor (M)7) An eighth transistor (M)8) And a ninth transistor (M)9) A tenth transistor (M10), a first current source (I)d1) And a second current source (I)d2) Is composed of (a) wherein
The first transistor (M)1) The second transistor (M)2) The third transistor (M)3) And the fourth transistor (M)4) An NMOS transistor in a diode-connected form; and
the fifth transistor (M)5) The sixth transistor (M)6) The seventh transistor (M)7) The eighth transistor (M)8) The ninth transistor (M)9) And the tenth transistor (M)10) Is a PMOS transistor.
3. Clock duty cycle calibration circuit according to claim 2, wherein said clock differential inputs are connected to said first transistors (M), respectively1) And the second transistor (M)2) A gate electrode of (1);
the differential input ends of the control voltage are respectively connected with the third transistor (M)3) And the fourth transistor (M)4) A gate of (2);
the first transistor (M)1) And the second transistor (M)2) Is connected in parallel with the first current source (I)d1) To ground, the third transistor (M)3) And the fourth transistor (M)4) Is connected in parallel with the second current source (I)d2) To ground;
the first transistor (M)1) And the third transistor (M)3) And the fifth transistor (M)5) And the eighth transistor (M)8) The drain electrodes of the first and second transistors are connected;
the second transistor (M)2) And the fourth transistor (M)4) And the sixth transistor (M)6) And the seventh transistor (M)7) The drain electrodes of the first and second transistors are connected;
the fifth transistor (M)5) The sixth transistor (M)6) The seventh transistor (M)7) The eighth transistor (M)8) Is connected to a power supply (VDD);
the seventh transistor (M)7) And the ninth transistor (M)9) And a tenth transistor (M)10) The gate of (1) is connected; and
the eighth transistor (M)8) And the tenth transistor (M)10) Is connected with the drain electrode of the transistor; and
the ninth transistor (M)9) And the tenth transistor (M)10) Is grounded.
4. The clock duty cycle calibration circuit of claim 1, wherein the single-ended to differential module (20) is formed by a first resistor (R)1) An eleventh transistor (M)11) And a twelfth transistor (M)12) A thirteenth transistor (M)13) And a fourteenth transistor (M)14) The first Inverter (INV)1) A second Inverter (INV)2) And a third Inverter (INV)3) And a fourth Inverter (INV)4) And a fifth Inverter (INV)5) And a sixth Inverter (INV)6) Is composed of (a) wherein
The eleventh transistor (M)11) The twelfth transistor (M)12) The thirteenth transistor (M)13) And the fourteenth transistor (M)14) Is a MOS transistor.
5. The clock duty cycle calibration circuit of claim 4, wherein the second Inverter (INV)2) The fourth Inverter (INV)4) And the fifth Inverter (INV)5) Is the first Inverter (INV)1) Twice of;
the third Inverter (INV)3) And the sixth Inverter (INV)6) Is the first Inverter (INV)1) Four times that of; and
the thirteenth transistor (M)13) The fourteenth transistor (M)14) And the second Inverter (INV)2) The MOS tubes in (1) have the same size.
6. The clock duty cycle calibration circuit according to claim 4, wherein the input of the single-ended to differential module (20) is connected to the eleventh transistor (M)11) And the twelfth transistor (M)12) And the first resistor (R)1) One end of (a);
the eleventh transistor (M)11) And the twelfth transistor (M)12) Respectively connected to a power supply (VDD) and ground, and a drain both connected to said first resistor (R)1) Is connected to and connected to the first Inverter (INV)1) An input terminal of (1);
the first Inverter (INV)1) Is connected to the second Inverter (INV)2) And the fourth Inverter (INV)4) An input terminal of (1);
the second Inverter (INV)2) Is connected to the thirteenth transistor (M)13) And a drain of the fourteenth transistor (M14);
the sources of the thirteenth transistor (M13) and the fourteenth transistor (M14) are connected to the third Inverter (INV)3) Said thirteenth transistor (M)13) A source connected to the power supply and the fourteenth transistor (M)14) The source of (2) is grounded;
the fourth Inverter (INV)4) Is connected to the fifth Inverter (INV)5) The fifth Inverter (INV)5) Is connected to the sixth Inverter (INV)6) The third Inverter (INV)3) And the sixth Inverter (INV)6) The output ends of the single-end conversion differential module (20) are respectively connected with the output end of the single-end conversion differential module.
7. The clock duty cycle calibration circuit of claim 1, wherein the duty cycle detection module (30) comprises: a fifteenth transistor (M)15) Sixteenth transistor (M)16) Seventeenth transistor (M)17) Eighteenth transistor (M)18) Nineteenth transistor (M)19) The twentieth transistor (M)20) A first capacitor (C)s1) A second capacitor (C)s2) And a third current source (I)d3) Is composed of (A) wherein
The fifteenth transistor (M)15) And the sixteenth transistor (M)16) An NMOS transistor in the form of a differential diode connection;
the seventeenth transistor (M)17) The eighteenth transistor (M)18) The nineteenth transistor (M)19) And the twentieth transistor (M)20) Is a PMOS transistor; and
the third current source (I)d3) Is a direct current source.
8. Clock duty cycle calibration circuit according to claim 7, characterized in that said fifteenth transistor (M)15) And the sixteenth transistor (M)16) Respectively connected to the input of the duty cycle detection module (30), and the source is connected to the third current source (I)d3) The drain electrodes are respectively connected with the output end of the duty ratio detection module (30);
the seventeenth transistor (M)17) The eighteenth transistor (M)18) The nineteenth transistor (M)19) And the twentieth transistor (M)20) The source is connected to a power supply (VDD);
the seventeenth transistor (M)17) Gate and drain of (a), the eighteenth transistor (M)18) Drain of (1), nineteenth transistor (M)19) Is connected to the output of the duty cycle detection module (30);
the twentieth transistor (M)20) Gate and drain of (a), the nineteenth transistor (M)19) The eighteenth transistor (M)18) Is connected to the output of the duty cycle detection module (30); and
the first capacitor (C)s1) And said second capacitance (C)s2) The lower polar plate is grounded, and the upper polar plate is respectively connected with the output end of the duty ratio detection module (30).
9. The method of claim 1The clock duty cycle calibration circuit of (1), characterized in that the low-pass filter module (40) is formed by a second resistor (R)2) A third resistor (R)3) A third capacitor (C)3) And a fourth capacitance (C)4) And (4) forming.
10. Clock duty cycle calibration circuit according to claim 9, characterized in that said second resistance (R)2) And the third resistor (R)3) One end of the low pass filter module is connected with the output end of the duty ratio detection module (30) and the other end is connected with the output end of the low pass filter module (40); and
the third capacitance (C)3) And said fourth capacitance (C)4) And the upper polar plate is respectively connected with the control voltage differential input end of the duty ratio regulating module (10).
CN202210094866.8A 2022-01-26 2022-01-26 Clock duty ratio calibration circuit Pending CN114598323A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115576884A (en) * 2022-12-07 2023-01-06 北京超摩科技有限公司 Single-ended clock to differential circuit with adjustable duty cycle
CN117639735A (en) * 2024-01-23 2024-03-01 韬润半导体(无锡)有限公司 Duty cycle detection circuit and duty cycle adjustment system

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115576884A (en) * 2022-12-07 2023-01-06 北京超摩科技有限公司 Single-ended clock to differential circuit with adjustable duty cycle
CN115576884B (en) * 2022-12-07 2023-03-24 北京超摩科技有限公司 Duty ratio adjustable single-end clock-to-differential circuit
CN117639735A (en) * 2024-01-23 2024-03-01 韬润半导体(无锡)有限公司 Duty cycle detection circuit and duty cycle adjustment system
CN117639735B (en) * 2024-01-23 2024-03-29 韬润半导体(无锡)有限公司 Duty cycle detection circuit and duty cycle adjustment system

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