CN115576884B - Duty ratio adjustable single-end clock-to-differential circuit - Google Patents
Duty ratio adjustable single-end clock-to-differential circuit Download PDFInfo
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- CN115576884B CN115576884B CN202211560183.3A CN202211560183A CN115576884B CN 115576884 B CN115576884 B CN 115576884B CN 202211560183 A CN202211560183 A CN 202211560183A CN 115576884 B CN115576884 B CN 115576884B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
- G06F13/4072—Drivers or receivers
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/125—Discriminating pulses
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/156—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
- H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0002—Serial port, e.g. RS232C
Abstract
The application relates to a single-ended clock to differential circuit with adjustable duty cycle, include: the device comprises a duty ratio adjusting module, a differential conversion module, a duty ratio detecting module, a sampling comparator and a control module. The input end of the duty ratio adjusting module is connected with the output end of the control module; the output end is connected with the input end of the differential conversion module; the output end of the differential conversion module is connected with the input end of the duty ratio detection module; the output end of the duty ratio detection module is connected with the input end of the sampling comparator; the output end of the sampling comparator is connected with the input end of the control module. According to the technical scheme, the duty ratio of the clock input signal is adjusted through the duty ratio adjusting module according to the comparison result of the duty ratios of the first clock output signal and the second clock output signal output by the differential conversion module, so that the problem of the deterioration of the duty ratio of the clock signal is solved, and the problem of the deterioration of the jitter performance of a system caused by the deterioration of the duty ratio of the clock signal is solved.
Description
Technical Field
The application relates to the technical field of integrated circuit design, in particular to a single-ended clock-to-differential circuit with adjustable duty ratio.
Background
With the development of integrated circuit technology and the increasing bandwidth requirements for data communication, high speed and low power consumption become two major mainstream directions of SerDes (SERializer/DESerializer) technology. Low power high speed SerDes generally use a half rate architecture, i.e., the clock signal has half the frequency of the data signal. The half-rate structure can effectively reduce the rate of the clock signal, thereby reducing the design difficulty of the chip and the power consumption of the chip. However, half rate systems require both edges of the clock signal to sample, which results in the duty cycle of the clock signal directly affecting the jitter performance of the overall system. Especially when the data transfer rate is high, the rising and falling edges of the clock become slower due to the limitation of the operating frequency of the transistor. The variation of the external environment (process corner, temperature, power supply voltage) can cause the time mismatch of the rising edge and the falling edge of the logic gate circuit, thereby causing the duty ratio of the clock signal to be deteriorated, and finally causing the jitter performance of the system to be deteriorated.
Disclosure of Invention
In order to overcome the problem that in the related art, the time mismatch of the rising edge and the falling edge of a logic gate circuit is caused by the change of the external environment, so that the duty ratio of a clock signal is deteriorated, and finally the jitter performance of a system is deteriorated, at least to a certain extent, the application provides a single-ended clock-to-differential circuit with an adjustable duty ratio.
The scheme of the application is as follows:
a duty cycle adjustable single-ended clock-to-differential circuit comprising:
the device comprises a duty ratio adjusting module, a differential conversion module, a duty ratio detecting module, a sampling comparator and a control module;
the input end of the duty ratio adjusting module is connected with the output end of the control module; the output end of the differential conversion module is connected with the input end of the differential conversion module;
the output end of the differential conversion module is connected with the input end of the duty ratio detection module;
the output end of the duty ratio detection module is connected with the input end of the sampling comparator;
the output end of the sampling comparator is connected with the input end of the control module;
the duty ratio adjusting module is used for accessing a clock input signal and sending the clock input signal to the differential conversion module;
the differential conversion module is used for carrying out differential processing on the clock input signal and outputting a first clock output signal and a second clock output signal;
the duty ratio detection module is used for detecting the duty ratios of the first clock output signal and the second clock output signal and sending the duty ratios of the first clock output signal and the second clock output signal to the sampling comparator;
the sampling comparator is used for generating a comparison result of the duty ratios of the first clock output signal and the second clock output signal and sending the comparison result to the control module;
the control module is used for outputting different control signals to the duty ratio adjusting module according to the comparison result;
the duty ratio adjusting module is used for adjusting the duty ratio of the clock input signal according to the control signal so as to adjust the duty ratios of the first clock output signal and the second clock output signal.
Preferably, the control signal is a multi-digit control signal;
the duty cycle adjustment module includes:
the digital control circuit comprises a first NAND gate logic circuit, a second NAND gate logic circuit and a digital control duty cycle unit;
the digitally controlled duty cycle unit includes: the first regulating inverter, the second regulating inverter, the first switch capacitor array group and the second switch capacitor array group;
the input end of the first regulating inverter is connected with a high-order control signal in the clock input signal and the multi-order control signal; the output end of the first switch capacitor array group is connected with the first switch capacitor array group;
the input end of the second regulating inverter is connected with the first switch capacitor array group; the output end of the first switch capacitor array group is connected with the first switch capacitor array group;
the second switched capacitor array group outputs the clock input signal;
the input end of the first NAND gate logic circuit is respectively connected with a high-digit control signal and a low-digit control signal in the multi-digit control signals; the output end of the first switch capacitor array group is connected with the first switch capacitor array group;
the input end of the second NAND gate logic circuit is respectively connected with a low-order control signal in the multi-order control signals and the output end of the first regulating inverter; and the output end of the second switch capacitor array group is connected with the second switch capacitor array group.
Preferably, the switched capacitor includes: a first NMOS (N-Metal-Oxide-Semiconductor) transistor and a second NMOS transistor;
the source electrode and the drain electrode of the first NMOS transistor are grounded, and the grid electrode is connected with the source electrode of the second NMOS transistor;
the grid electrode of the second NMOS transistor is connected with the multi-digit control signal, and the drain electrode of the second NMOS transistor is output.
Preferably, the control module is specifically configured to set both high-order bits and low-order bits of the initial multi-order bit control signal to be 0 when the duty ratio of the first clock output signal is smaller than that of the second clock output signal, and perform +1 processing on the low-order bits of the multi-order bit control signal until the duty ratio of the first clock output signal is greater than that of the second clock output signal;
when the duty ratio of the first clock output signal is larger than that of the second clock output signal, the high digit number of the initial multi-digit control signal is set to be 1, and the low digit number of the initial multi-digit control signal is set to be 0, and the low digit number of the multi-digit control signal is subjected to +1 processing until the duty ratio of the first clock output signal is smaller than that of the second clock output signal.
Preferably, the control module is further configured to, after performing +1 processing on the low-order bits of the multi-order control signal, perform-1 processing on the low-order bits of the multi-order control signal until the duty ratio of the first clock output signal is greater than that of the second clock output signal for the first time, until the duty ratio of the first clock output signal is less than that of the second clock output signal, and perform +1 processing on the low-order bits of the multi-order control signal;
after the low-order bits of the multi-order control signal are processed by +1, the low-order bits of the multi-order control signal are processed by-1 until the duty ratio of the first clock output signal is smaller than that of the second clock output signal for the first time, and then the low-order bits of the multi-order control signal are processed by +1 until the duty ratio of the first clock output signal is larger than that of the second clock output signal.
Preferably, the multi-bit control signal comprises one high bit and four low bits;
the first switch capacitor array group and the second switch capacitor array group are 4-bit switch capacitor arrays, and the number ratio of capacitors in the arrays is 8:4:2:1.
preferably the digitally controlled duty cycle unit is multi-stage.
Preferably, the slip difference module comprises:
a first differential inverter, a second differential inverter, a third differential inverter, a fourth differential inverter, a fifth differential inverter, a sixth differential inverter, a seventh differential inverter, an eighth differential inverter, and a CMOS (Complementary Metal Oxide Semiconductor) transmission gate;
the input end of the first rotating differential phase inverter is connected with a clock input signal, and the output end of the first rotating differential phase inverter is respectively connected with the input end of the second rotating differential phase inverter and the input end of the CMOS transmission gate;
the output end of the second rotating differential phase inverter is connected with the input end of the third rotating differential phase inverter;
the output end of the third rotating differential phase inverter is respectively connected with the input end of the fourth rotating differential phase inverter and the input end of the eighth rotating differential phase inverter;
the output end of the fourth differential inverter outputs the first clock output signal;
the output end of the fifth-rotation differential phase inverter is respectively connected with the input end of the sixth-rotation differential phase inverter and the input end of the seventh-rotation differential phase inverter;
the output end of the sixth slip differential inverter outputs the second clock output signal;
the output end of the seventh-rotation differential phase inverter is connected with the input end of the fourth-rotation differential phase inverter;
and the output end of the eighth-rotation differential phase inverter is connected with the input end of the sixth-rotation differential phase inverter.
Preferably, the outputs of the first inverting differential inverter and the CMOS transmission gate are in-phase clock signals;
the output of the first rotating differential inverter and the output of the second rotating differential inverter are inverted clock signals;
the time delay of the CMOS transmission gate is the same as that of the second differential inverter.
Preferably, the duty cycle detection module includes: the duty ratio detection circuit comprises a first duty ratio detection branch circuit and a second duty ratio detection branch circuit which are connected in parallel;
a first resistor is arranged on the first duty ratio detection branch;
a second resistor is arranged on the second duty ratio detection branch;
and a capacitor is connected between the first duty ratio detection branch and the second duty ratio detection branch.
The technical scheme provided by the application can comprise the following beneficial effects: the single-ended clock to differential circuit with adjustable duty cycle in this application includes: the device comprises a duty ratio adjusting module, a differential conversion module, a duty ratio detecting module, a sampling comparator and a control module. The input end of the duty ratio adjusting module is connected with the output end of the control module; the output end is connected with the input end of the differential conversion module; the output end of the differential conversion module is connected with the input end of the duty ratio detection module; the output end of the duty ratio detection module is connected with the input end of the sampling comparator; the output end of the sampling comparator is connected with the input end of the control module. During implementation, the duty ratio adjusting module is connected with a clock input signal and sends the clock input signal to the differential conversion module; the differential conversion module performs differential processing on the clock input signal and outputs a first clock output signal and a second clock output signal; the duty ratio detection module detects the duty ratios of the first clock output signal and the second clock output signal and sends the duty ratios of the first clock output signal and the second clock output signal to the sampling comparator; the sampling comparator generates a comparison result of the duty ratios of the first clock output signal and the second clock output signal and sends the comparison result to the control module; the control module outputs different control signals to the duty ratio adjusting module according to the comparison result; and finally, the duty ratio adjusting module adjusts the duty ratio of the clock input signal according to the control signal so as to adjust the duty ratios of the first clock output signal and the second clock output signal. According to the technical scheme, the duty ratio of the clock input signal is adjusted through the duty ratio adjusting module according to the comparison result of the duty ratios of the first clock output signal and the second clock output signal output by the differential conversion module, so that the problem that the change of an external environment causes the time mismatching of a rising edge and a falling edge of a logic gate circuit, the duty ratio of the clock signal deteriorates is solved, and the problem that the jitter performance of a system deteriorates due to the deterioration of the duty ratio of the clock signal is solved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and together with the description, serve to explain the principles of the application.
Fig. 1 is a schematic structural diagram of a single-ended clock-to-differential circuit with adjustable duty cycle according to an embodiment of the present application;
FIG. 2 is a schematic structural diagram of a duty cycle adjusting module according to an embodiment of the present application;
fig. 3 is a schematic structural diagram of a switched capacitor according to an embodiment of the present application;
FIG. 4 is a schematic structural diagram of a differential transfer module according to an embodiment of the present application;
fig. 5 is a schematic structural diagram of a duty ratio detection module according to an embodiment of the present application;
FIG. 6 is a schematic diagram of the duty cycle of a clock signal as a function of the NMOS capacitance magnitude of the first and second trim inverters output as provided by one embodiment of the present application;
FIG. 7 is a schematic diagram of control logic for a control module provided in one embodiment of the present application;
FIG. 8A is a schematic diagram illustrating duty cycles of a first clock output signal and a second clock output signal as a function of a control signal according to an embodiment of the present application;
fig. 8B is a schematic diagram of the duty ratio of the first clock output signal and the second clock output signal varying with the control signal according to another embodiment of the present application.
Reference numerals: a duty ratio adjusting module-1; a first nand gate logic circuit-11; a second nand gate logic circuit-12; a digital control duty cycle unit-13; a first regulating inverter-131; a second regulating inverter-132; a first switched capacitor array group-133; a first NMOS transistor-1331; a second NMOS transistor-1332; a second switched capacitor array group-134; a differential transfer module-2; a first inverting differential inverter-21; a second slip differential inverter-22; a third slip differential inverter-23; a fourth-slip differential inverter-24; a fifth-slip differential inverter-25; a sixth-revolution differential inverter-26; a seventh-rotation differential inverter-27; an eighth-revolution differential inverter-28; CMOS transmission gate-29; a duty ratio detection module-3; a sampling comparator-4; and a control module-5.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.
Fig. 1 is a schematic structural diagram of a duty-cycle adjustable single-ended clock-to-differential circuit according to an embodiment of the present application, and referring to fig. 1, the duty-cycle adjustable single-ended clock-to-differential circuit includes:
the device comprises a duty ratio adjusting module 1, a differential conversion module 2, a duty ratio detecting module 3, a sampling comparator 4 and a control module 5;
the input end of the duty ratio adjusting module 1 is connected with the output end of the control module 5; the output end is connected with the input end of the differential conversion module 2;
the output end of the differential conversion module 2 is connected with the input end of the duty ratio detection module 3;
the output end of the duty ratio detection module 3 is connected with the input end of the sampling comparator 4;
the output end of the sampling comparator 4 is connected with the input end of the control module 5;
the duty ratio adjusting module 1 is used for accessing a clock input signal and sending the clock input signal to the differential conversion module 2;
the differential conversion module 2 is used for performing differential processing on the clock input signal and outputting a first clock output signal and a second clock output signal;
the duty ratio detection module 3 is configured to detect duty ratios of the first clock output signal and the second clock output signal, and send the duty ratios of the first clock output signal and the second clock output signal to the sampling comparator 4;
the sampling comparator 4 is used for generating a comparison result of the duty ratios of the first clock output signal and the second clock output signal and sending the comparison result to the control module 5;
the control module 5 is used for outputting different control signals to the duty ratio adjusting module 1 according to the comparison result;
the duty ratio adjusting module 1 is configured to adjust a duty ratio of a clock input signal according to a control signal to adjust duty ratios of a first clock output signal and a second clock output signal.
As shown in fig. 1, CKIN is a clock input signal, CKOUT1 is a first clock output signal, and CKOUT2 is a second clock output signal.
In specific practice, the duty ratio adjusting module 1 is a single-ended clock duty ratio adjusting module 1, the differential conversion module 2 is a single-ended clock differential conversion module 2, and single-ended clock input is adopted in the embodiment, so that the power consumption of a traditional differential clock transmission chip is effectively reduced, and the low-power-consumption design is met.
Referring to fig. 2, the duty ratio adjusting module 1 includes:
a first nand gate logic circuit 11, a second nand gate logic circuit 12 and a digital control duty cycle unit 13;
the digital control duty unit 13 includes: a first regulating inverter 131, a second regulating inverter 132, a first switched capacitor array group 133, and a second switched capacitor array group 134;
the input end of the first regulating inverter 131 is connected to the clock input signal and the high-order control signal in the multi-order control signal; the output end is connected with the first switched capacitor array group 133;
the input end of the second regulating inverter 132 is connected with the first switched capacitor array group 133; the output end is connected with the second switched capacitor array group 134;
the second switched capacitor array group 134 outputs a clock input signal;
the input end of the first nand gate logic circuit 11 is respectively connected to a high digital control signal and a low digital control signal in the multi-digital control signals; the output end is connected with the first switched capacitor array group 133;
the input end of the second nand gate logic circuit 12 is respectively connected to the low-order control signal of the multi-order control signals and the output end of the first regulating inverter 131; the output terminal is connected to the second switched capacitor array group 134.
It should be noted that, as shown in fig. 1-2, the control signal is a multi-bit control signal S <4>, wherein the multi-bit control signal includes one high bit and four low bits, S <4> is the high bit control signal, and S <3 > is the low bit control signal. The first switched capacitor array group 133 and the second switched capacitor array group 134 are both 4-bit switched capacitor arrays, SA <3 > controls the previous capacitor array of the digital control duty cycle unit 13, and the number ratio of the capacitor arrays is 8:4:2:1, SB & lt 3 & gt is that the number ratio of the capacitor arrays is also 8:4:2:1.
referring to fig. 3, the switched capacitor includes: a first NMOS transistor 1331 and a second NMOS transistor 1332;
the source and drain of the first NMOS transistor 1331 are grounded, and the gate is connected to the source of the second NMOS transistor 1332;
the gate of the second NMOS transistor 1332 is connected to the multi-bit control signal, and the drain is the output.
It is understood that, as shown in fig. 3, the capacitor array unit is composed of two NMOS transistors, the source and drain of the first NMOS transistor 1331 are grounded to form an NMOS capacitor, the gate is connected to the source of the second NMOS transistor 1332, the gate of the second NMOS transistor 1332 is connected to the digital control signal, and the drain is the output.
When the switch controlled by S in fig. 3 is closed, the NMOS capacitor switches in the outputs of the first trim inverter 131 and the second trim inverter 132 of the high speed transmission link. Since the capacitance of the NMOS capacitor gradually increases when the gate voltage is higher than the threshold voltage of the NMOS transistor, the end stage of the rising edge output from the first and second trim inverters 131 and 132 is affected by the capacitance to be gentle, and the beginning stage of the falling edge is affected by the capacitance to be gentle, as shown in fig. 6. As can be seen from fig. 6, the duty ratio of the clock signal can be effectively changed by changing the size of the NMOS capacitor connected to the outputs of the first and second trim inverters 131 and 132. The SA <3 >. When the high-bit control signal S <4> =0, SA <3 > =4' b0000, sb<3; when the digital control signal S <4> =1, SB <3 > =4' b0000, sa < -3. When S <4> =0, a linear increase of S <3 > may linearly increase the duty ratio of the output clock; when S <4> =1, a linear increase of S <3 >.
In a specific practice, the digital control duty cycle unit 13 is in multiple stages, and the adjustment range of the duty cycle can be increased by increasing the number of stages of the digital duty cycle control unit, wherein the adjustment range of the duty cycle is larger as the number of stages is larger.
Based on this, the control module 5 is specifically configured to set both high-order bits and low-order bits of the initial multi-order bit control signal to be 0 when the duty ratio of the first clock output signal is smaller than the second clock output signal, and to make the low-order bits of the multi-order bit control signal perform +1 processing until the duty ratio of the first clock output signal is larger than the second clock output signal; then, the low digit of the multi-digit control signal is processed by-1 until the duty ratio of the first clock output signal is smaller than that of the second clock output signal, and then the low digit of the multi-digit control signal is processed by + 1;
or when the duty ratio of the first clock output signal is larger than that of the second clock output signal, setting the high digit number of the initial multi-digit control signal to be 1 and the low digit number to be 0, and enabling the low digit number of the multi-digit control signal to be subjected to +1 processing until the duty ratio of the first clock output signal is smaller than that of the second clock output signal; then, the low-order bits of the multi-order control signal are processed by-1 until the duty ratio of the first clock output signal is larger than that of the second clock output signal, and then the low-order bits of the multi-order control signal are processed by + 1.
Referring to fig. 4, the differential transfer module 2 includes:
a first rotating differential inverter 21, a second rotating differential inverter 22, a third rotating differential inverter 23, a fourth rotating differential inverter 24, a fifth rotating differential inverter 25, a sixth rotating differential inverter 26, a seventh rotating differential inverter 27, an eighth rotating differential inverter 28, and a CMOS transmission gate 29;
the input end of the first rotating differential inverter 21 is connected with a clock input signal, and the output end of the first rotating differential inverter 21 is respectively connected with the input end of the second rotating differential inverter 22 and the input end of the CMOS transmission gate 29;
the output end of the second rotating differential phase inverter 22 is connected with the input end of the third rotating differential phase inverter 23;
the output end of the third-to-differential inverter 23 is connected to the input end of the fourth-to-differential inverter 24 and the input end of the eighth-to-differential inverter 28, respectively;
the output terminal of the fourth inverting differential inverter 24 outputs the first clock output signal;
the output end of the fifth-rotation differential inverter 25 is connected with the input end of the sixth-rotation differential inverter 26 and the input end of the seventh-rotation differential inverter 27 respectively;
the output of the sixth differential inverter 26 outputs the second clock output signal;
the output end of the seventh-order differential inverter 27 is connected to the input end of the fourth-order differential inverter 24;
the output of the eighth-revolution differential inverter 28 is connected to the input of the sixth-revolution differential inverter 26.
It should be noted that the outputs of the first differential inverter 21 and the CMOS transmission gate 29 are in-phase clock signals;
the outputs of the first and second differential inverters 21 and 22 are inverted clock signals;
the delay time of the CMOS transmission gate 29 is the same as the second differential inverter 22.
The 2-way slip module shown in fig. 4 comprises first to eighth slip inverters 21 to 28 and one CMOS transmission gate 29. The outputs of the first inverting differential inverter 21 and the CMOS transmission gate 29 are in-phase clock signals; the outputs of the first and second differential inverters 21 and 22 are inverted clock signals. The delay time of the CMOS transmission gate 29 is the same as the second differential inverter 22, thus ensuring that the outputs are fully differential. The seventh-rotation differential inverter 27 and the eighth-rotation differential inverter 28 are used to further secure the output clock differential characteristic.
Referring to fig. 5, the duty detection module 3 includes: the first duty ratio detection branch circuit and the second duty ratio detection branch circuit are connected in parallel;
a first resistor is arranged on the first duty ratio detection branch;
a second resistor is arranged on the second duty ratio detection branch;
and a capacitor is connected between the first duty ratio detection branch and the second duty ratio detection branch.
In specific practice, the duty ratio detection module 3 forms a low-pass filter, takes out an output direct-current component of the differential signal, and when the duty ratio of the differential clock is greater than 50%, CKOUTP _ DC is greater than CKOUTN _ DC; when the duty cycle of the differential clock is less than 50%, CKOUTP _ DC is less than CKOUTN _ DC. The sampling comparator 4 with higher gain can change the magnitude relation between CKOUTP _ DC and CKOUTN _ DC into logic 0 or 1, and when CKOUTP _ DC is larger than CKOUTN _ DC, the sampling comparator 4 outputs logic 1; when CKOUTP _ DC is less than CKOUTN _ DC, the sampling comparator 4 outputs logic 0.
In specific practice, as shown in fig. 7, after power-up, the control module 5 (Microcontroller Unit, MCU) detects the initial output of the sampling comparator 4, and if S =0, it indicates that the duty ratio of the first clock output signal is smaller than that of the second clock output signal, i.e., the duty ratio of CKOUTP is smaller than 50%, when the control module 5 sets S <4> =00000, S4 > =0 such that SA < 0> =0000, sb < 0> = 0>. Control module 5 performs +1 processing on S <3 > at which the duty ratio of output CKOUTP increases, CKOUTP _ DC increases, and CKOUTN _ DC decreases. The control block 5 constantly detects the state of the output of the sampling comparator 4, and if the state is still 0 at this time, the control block 5 causes S <3 > to continue the +1 process. Control block 5 then continues to detect the state of the output S of sampling comparator 4 until S becomes 1, indicating that the duty cycle of CKOUTP is greater than 50% at this time. Then, the control module 5 performs a-1 process on S <3 > until S changes from 1 to 0, and then performs a +1 process.
Alternatively, after power-up, the control module 5 detects the initial output of the comparator, and if S =1, it indicates that the duty ratio of the first clock output signal is greater than that of the second clock output signal, i.e., the duty ratio of CKOUTP is greater than 50%, when the control module 5 sets S <4> =10000, S < -4 > =1 such that SB < 0> =0000, sa < -3 > = 0>. The MCU makes S <3 > and 0> perform +1 processing, and the duty ratio of the output CKOUTP is reduced, CKOUTP _ DC is reduced, and CKOUTN _ DC is increased. The MCU constantly detects the state of the output of the sampling comparator 4, and if it is still 1, the control module 5 makes S <3 > to continue +1 processing. The control module 5 continues to detect the output of the sampling comparator 4 until S changes from 1 to 0, at which time the duty cycle of CKOUTP is less than 50%. Then, the control module 5 performs a-1 process on S <3 > until S changes from 0 to 1, and then performs a +1 process. The waveforms in both cases are shown in fig. 8A and 8B.
It can be understood that, in the technical solution in this embodiment, the duty ratio of the clock input signal is adjusted by the duty ratio adjusting module according to the comparison result of the duty ratios of the first clock output signal and the second clock output signal output by the differential conversion module, so that the problem that the change of the external environment causes the time mismatch of the rising edge and the falling edge of the logic gate circuit, thereby causing the duty ratio of the clock signal to deteriorate is solved, and the problem that the duty ratio deterioration of the clock signal causes the jitter performance deterioration of the system is solved.
It is understood that the same or similar parts in the above embodiments may be mutually referred to, and the same or similar parts in other embodiments may be referred to for the content which is not described in detail in some embodiments.
It should be noted that, in the description of the present application, the terms "first", "second", etc. are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. Further, in the description of the present application, the meaning of "a plurality" means at least two unless otherwise specified.
Any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing specific logical functions or steps of the process, and the scope of the preferred embodiments of the present application includes other implementations in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the present application.
It should be understood that portions of the present application may be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, the various steps or methods may be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, any one or combination of the following techniques, which are known in the art, may be used: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application specific integrated circuit having an appropriate combinational logic gate circuit, a Programmable Gate Array (PGA), a Field Programmable Gate Array (FPGA), or the like.
It will be understood by those skilled in the art that all or part of the steps carried out in the method of implementing the above embodiments may be implemented by hardware related to instructions of a program, which may be stored in a computer readable storage medium, and the program, when executed, includes one or a combination of the steps of the method embodiments.
In addition, functional units in the embodiments of the present application may be integrated into one processing module, or each unit may exist alone physically, or two or more units are integrated into one module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode. The integrated module, if implemented in the form of a software functional module and sold or used as a stand-alone product, may also be stored in a computer readable storage medium.
The storage medium mentioned above may be a read-only memory, a magnetic or optical disk, etc.
In the description herein, reference to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
Although embodiments of the present application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present application, and that variations, modifications, substitutions and alterations may be made to the above embodiments by those of ordinary skill in the art within the scope of the present application.
Claims (10)
1. A duty cycle adjustable single-ended clock-to-differential circuit, comprising:
the device comprises a duty ratio adjusting module, a differential conversion module, a duty ratio detecting module, a sampling comparator and a control module;
the input end of the duty ratio adjusting module is connected with the output end of the control module; the output end is connected with the input end of the differential conversion module;
the output end of the differential conversion module is connected with the input end of the duty ratio detection module;
the output end of the duty ratio detection module is connected with the input end of the sampling comparator;
the output end of the sampling comparator is connected with the input end of the control module;
the duty ratio adjusting module is used for accessing a clock input signal and sending the clock input signal to the differential conversion module;
the differential conversion module is used for carrying out differential processing on the clock input signal and outputting a first clock output signal and a second clock output signal;
the duty ratio detection module is used for detecting the duty ratios of the first clock output signal and the second clock output signal and sending the duty ratios of the first clock output signal and the second clock output signal to the sampling comparator;
the sampling comparator is used for generating a comparison result of the duty ratios of the first clock output signal and the second clock output signal and sending the comparison result to the control module;
the control module is used for outputting different control signals to the duty ratio adjusting module according to the comparison result;
the duty ratio adjusting module is used for adjusting the duty ratio of the clock input signal according to the control signal so as to adjust the duty ratios of the first clock output signal and the second clock output signal.
2. The circuit of claim 1, wherein the control signal is a multi-bit control signal;
the duty cycle adjustment module includes:
the digital control circuit comprises a first NAND gate logic circuit, a second NAND gate logic circuit and a digital control duty cycle unit;
the digitally controlled duty cycle unit includes: the first regulating inverter, the second regulating inverter, the first switch capacitor array group and the second switch capacitor array group;
the input end of the first regulating inverter is connected with a high-order control signal in the clock input signal and the multi-order control signal; the output end of the first switch capacitor array group is connected with the first switch capacitor array group;
the input end of the second regulating inverter is connected with the first switched capacitor array group; the output end of the first switch capacitor array group is connected with the first switch capacitor array group;
the second switched capacitor array group outputs the clock input signal;
the input end of the first NAND gate logic circuit is respectively connected with a high-order control signal and a low-order control signal in the multi-order control signals; the output end of the first switch capacitor array group is connected with the first switch capacitor array group;
the input end of the second NAND gate logic circuit is respectively connected with a low-order control signal in the multi-order control signals and the output end of the first regulating inverter; the output end of the second switch capacitor array group is connected with the second switch capacitor array group.
3. The circuit of claim 2, wherein the switched capacitor comprises: a first NMOS transistor and a second NMOS transistor;
the source electrode and the drain electrode of the first NMOS transistor are grounded, and the grid electrode is connected with the source electrode of the second NMOS transistor;
the grid electrode of the second NMOS transistor is connected with the multi-digit control signal, and the drain electrode of the second NMOS transistor is output.
4. The circuit of claim 2, wherein the control module is specifically configured to set both high and low bits of the initial multi-bit control signal to 0 when the duty cycle of the first clock output signal is less than the second clock output signal, and to cause the low bit of the multi-bit control signal to perform +1 processing until the duty cycle of the first clock output signal is greater than the second clock output signal;
when the duty ratio of the first clock output signal is larger than that of the second clock output signal, the high digit number of the initial multi-digit control signal is set to be 1, and the low digit number of the initial multi-digit control signal is set to be 0, and the low digit number of the multi-digit control signal is subjected to +1 processing until the duty ratio of the first clock output signal is smaller than that of the second clock output signal.
5. The circuit of claim 4, wherein the control module is further configured to, after +1 processing the low order bits of the multi-bit control signal, until the duty cycle of the first clock output signal is greater than that of the second clock output signal for the first time, perform-1 processing on the low order bits of the multi-bit control signal until the duty cycle of the first clock output signal is less than that of the second clock output signal, and then perform +1 processing on the low order bits of the multi-bit control signal;
after the low-order bits of the multi-order control signal are processed by +1, the low-order bits of the multi-order control signal are processed by-1 until the duty ratio of the first clock output signal is smaller than that of the second clock output signal for the first time, and then the low-order bits of the multi-order control signal are processed by +1 until the duty ratio of the first clock output signal is larger than that of the second clock output signal.
6. The circuit of claim 2, wherein the multi-bit control signal comprises one high bit and four low bits;
the first switch capacitor array group and the second switch capacitor array group are 4-bit switch capacitor arrays, and the number ratio of capacitors in the arrays is 8:4:2:1.
7. the circuit of claim 2, wherein the digitally controlled duty cycle unit is multi-stage.
8. The circuit of claim 1, wherein the differential conversion module comprises:
the CMOS transmission device comprises a first rotating differential inverter, a second rotating differential inverter, a third rotating differential inverter, a fourth rotating differential inverter, a fifth rotating differential inverter, a sixth rotating differential inverter, a seventh rotating differential inverter, an eighth rotating differential inverter and a CMOS transmission gate;
the input end of the first rotating differential phase inverter is connected with a clock input signal, and the output end of the first rotating differential phase inverter is respectively connected with the input end of the second rotating differential phase inverter and the input end of the CMOS transmission gate;
the output end of the second rotating differential phase inverter is connected with the input end of the third rotating differential phase inverter;
the output end of the third rotating differential phase inverter is respectively connected with the input end of the fourth rotating differential phase inverter and the input end of the eighth rotating differential phase inverter;
the output end of the fourth differential inverter outputs the first clock output signal;
the output end of the fifth-rotation differential phase inverter is respectively connected with the input end of the sixth-rotation differential phase inverter and the input end of the seventh-rotation differential phase inverter;
the output end of the sixth slip differential inverter outputs the second clock output signal;
the output end of the seventh-rotation differential phase inverter is connected with the input end of the fourth-rotation differential phase inverter;
and the output end of the eighth-rotation differential phase inverter is connected with the input end of the sixth-rotation differential phase inverter.
9. The circuit of claim 8, wherein the outputs of the first inverting differential inverter and the CMOS transmission gate are in-phase clock signals;
the output of the first rotating differential inverter and the output of the second rotating differential inverter are inverted clock signals;
the time delay of the CMOS transmission gate is the same as that of the second differential inverter.
10. The circuit of claim 1, wherein the duty cycle detection module comprises: the first duty ratio detection branch circuit and the second duty ratio detection branch circuit are connected in parallel;
a first resistor is arranged on the first duty ratio detection branch;
a second resistor is arranged on the second duty ratio detection branch;
and a capacitor is connected between the first duty ratio detection branch and the second duty ratio detection branch.
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| CN202211560183.3A CN115576884B (en) | 2022-12-07 | 2022-12-07 | Duty ratio adjustable single-end clock-to-differential circuit |
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