JP5701564B2 - Semiconductor integrated circuit and measurement temperature detection method - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit and a measurement temperature detection method, and more particularly to a semiconductor integrated circuit which is an RC oscillation circuit and a measurement temperature detection method using the semiconductor integrated circuit.

  In general, an RC oscillation circuit (RC-ADC) using a resistance sensor such as a thermistor resistance is known. Also, a method for detecting temperature (measured temperature) using the RC oscillation circuit is known.

  As such an RC oscillation circuit, for example, there is a temperature measurement oscillation circuit described in Patent Document 1. In the oscillation circuit for temperature measurement described in Patent Document 1, in order to reduce the influence of the ON resistance of the transistor on the measurement result, switching of charging and discharging of the capacitor is performed using a clocked inverter or the like. Both describe that the influence of the ON resistance of the clocked inverter that drives the reference resistor or thermistor is reduced by oscillating through the reference resistor or thermistor.

JP-A-10-26560

  However, in the technique described in Patent Document 1, since the influence of the ON resistance of the transistor remains small, the influence of the remaining ON resistance may be a problem. For example, when the power supply voltage is lowered, the influence of the remaining ON resistance becomes large, so the influence of the remaining ON resistance does not become large (the influence of the ON resistance is small). There is a problem that the operation guaranteed voltage becomes.

  Further, a measurement temperature error may occur due to the influence of the remaining ON resistance, internal delay time T, and the like.

FIG. 8 shows a circuit diagram of a specific example of an RC oscillation circuit for detecting a measured temperature, which is a conventional semiconductor integrated circuit. The RC oscillation circuit 100 shown in FIG. 8 includes an inverter inv1, an inverter inv2, an inverter inv3, an inverter inv4, an inverter inv5, an inverter inv6, a thermistor resistance element R _T , a reference resistance element R _S , a capacitor C _S , and a capacitor C _VR . It is prepared for.

The thermistor resistance element _RT is a sensor resistance element whose resistance value changes logarithmically with changes in temperature, and the reference resistance element _RS is a resistance element whose resistance value hardly changes depending on the environment (measurement temperature). . The RC oscillation circuit 100 shown in FIG. 8 includes an oscillation frequency f _T due to RC oscillation of the thermistor resistor element _RT , the capacitor _CS, and the capacitor C _VR , and a reference resistor element _RS , capacitor _CS, and capacitor C _VR . This is a circuit for detecting the measured temperature by calculating the ratio (frequency ratio) of the oscillation frequency f _S due to RC oscillation.

FIG. 9 shows operation waveforms during RC oscillation of the RC oscillation circuit 100 shown in FIG. In FIG. 9, by the inverter inv1 to HiZ (high impedance) state shows a RC oscillator (oscillation frequency fT) operation waveforms of the reference resistance element _{R S} and capacitor _{C S} and the capacitor _{C VR.} As shown in FIG. 9, during the period t1, the voltage value of the node IN becomes higher based on the time constants of the reference resistor element _RS , the capacitor _CS, and the capacitor _CVR . During the period t1, the level of the input voltage of the inverter inv4 is L (low) level. When the voltage value of the node IN increases and reaches the threshold value of the inverter inv4, the input voltage level of the inverter inv4 becomes H (high) level, the output becomes L level, and the L level voltage is input to the inverter inv3. Will be. As a result, the voltage at the node IN is rapidly increased by the inverter inv3 (FIG. 9, timing T1). At the same time, the input voltage of the inverter inv2 becomes H level and the output voltage becomes L level. As a result, the voltage value of the node RS becomes 0V.

During the next period t2 beyond the timing T1, the voltage value of the node IN becomes lower based on the time constants of the reference resistance element _RS , the capacitor _CS, and the capacitor _CVR . During the period t2, the level of the input voltage of the inverter inv4 is H level. When the voltage value of the node IN decreases and becomes less than the threshold value of the inverter inv4, the input voltage level of the inverter inv4 becomes L level, the output becomes H level, and the H level voltage is input to the inverter inv3. become. As a result, the voltage at the node IN is rapidly lowered by the inverter inv3 (FIG. 9, timing T2). At the same time, the input voltage of the inverter inv2 becomes L level and the output voltage becomes H level. Thereby, the voltage value of the node RS becomes the power supply voltage by the inverter inv2.

  By repeating the above operation, the RC oscillation circuit 100 repeats the RC oscillation operation. The oscillation operation is affected by the ON resistance r of the inverters inv1 and inv2 and the internal delay time T. FIG. 10 shows a specific example of a circuit diagram of the inverters inv1 to inv6. Here, the inverters inv1 to inv6 are all inverters having the same configuration (however, the inverters inv1 and 2 are different from the input signals input to the inverters inv3 to inv6 in that the signals enb_inv1, enb_inv2, signals en_inv1, and en_inv1 10, the inverters inv1 to inv6 are configured to include two PMOS field effect transistors and two NMOS field effect transistors. An ON resistance is generated due to the PMOS field effect transistor and the NMOS field effect transistor, and, as shown in Fig. 11, in the RC oscillation circuit 100, from the inverter inv4 to the inverter inv1, and from the inverter inv4 to Internal delay time T of up to converter inv2 occurs.

Considering the influence of the ON resistance r and the internal delay time T, the oscillation frequency can be expressed by the equation shown in FIG. FIG. 12A shows the oscillation frequency f _T when the thermistor resistance element _RT is oscillated, and FIG. 12B shows the oscillation frequency f _T when the reference resistance element _RS is oscillated. _S is shown.

Ideally, ON resistance r is the resistance Rt of the thermistor resistance element R _T, sufficiently smaller than the resistance value Rs of the reference resistance element R _S, and the proportion of internal delay time 2T occupies the oscillation period If the frequency ratio is sufficiently small, it is possible to cancel out error factors such as variations in the capacitance values (capacitance value Cs and capacitance value Cvr) of the capacitor C _S and the capacitor C _VR by calculating the frequency ratio f _S / f _T. = F _S / f _T ≈R _T / R _S

Therefore, the temperature characteristic of the thermistor resistance element _RT can be obtained. By obtaining correlation data (a table of measurement temperatures with respect to frequency ratio) between the frequency ratio and measurement temperature in advance, the measurement temperature can be calculated from the frequency ratio obtained as described above. In this way, the measured temperature can be detected by the RC oscillation circuit 100.

  However, the ON resistance r and the internal delay time T of the inverters inv1 and inv2 are not constant values, but change depending on operating conditions such as voltage and measurement temperature, and the PMOS field effect transistors of the inverters inv1 and inv2 Due to the influence of variations in the threshold value Vt of the NMOS field-effect transistor, each device also changes, so the oscillation frequency changes. As described above, the measurement temperature table with respect to the frequency ratio obtained in advance and the measurement The frequency ratio at the time of temperature detection is deviated, causing a problem of measurement temperature error.

  The present invention has been proposed to solve the above-described problems, and eliminates the influence of the ON resistance of the inverter and the internal delay time, and can detect the measurement temperature appropriately and the measurement. An object is to provide a temperature detection method.

In order to achieve the above object, in the semiconductor integrated circuit according to claim 1, the input side is connected to the second electrode of the first capacitor whose first electrode is connected to the ground, and the first bias voltage is applied . 1 inverter, a second inverter whose input side is connected to the output side of the first inverter, an input side connected to the output side of the second inverter, and one end connected to the second electrode of the first capacitor An output side is connected to the other end of the thermistor resistance element, a third inverter to which a second bias voltage is applied , an input side is connected to the output side of the second inverter, and one end is connected to the second electrode of the first capacitor. is connected to the output side to the other end of a connected reference resistance element, and a fourth inverter which third bias voltage is applied, an input side connected to the output side of the first inverter, and the second Output side to the second electrode of the second capacitor a first electrode is connected is connected to the second electrode of the capacitor, and a fifth inverter that said first bias voltage is applied, the first bias voltage, The level is adjusted so that the oscillation frequency determined by the first capacitor, the second capacitor, and the reference resistance element is a predetermined frequency, and the second bias voltage is the first bias voltage, And the third bias voltage is generated based on the first bias voltage and either the operating state or the high impedance state. the voltage of the second signal to determine whether, is generated based on the third inverter operation state, and the fourth inverter High- An-impedance state, each of the first inverter and the fifth inverter operates in transition time corresponding prior Symbol first bias voltage.

The semiconductor integrated circuit according to claim 2, in the semiconductor integrated circuit according to claim 1, wherein the first bias voltage, the third high-inverters impedance state, and the fourth inverter as operating state, The level is adjusted so that the oscillation frequency determined by the first capacitor, the second capacitor, and the reference resistance element becomes a predetermined frequency.

The semiconductor integrated circuit according to claim 3 includes a bias circuit that outputs the first bias voltage, the voltage level of which is adjusted based on an input signal in the semiconductor integrated circuit according to claim 1 or 2, It said first inverter and the fifth inverter, wherein the first bias voltage is applied from the bias circuit, and operates in the transition time corresponding to the voltage level of the first bias voltage.
The semiconductor integrated circuit according to claim 4, in the semiconductor integrated circuit according to any one of claims 1 to 3, wherein the second inverter, the first bias voltage is applied, and the first It operates with a transition time according to the bias voltage.

The measurement temperature detection method according to claim 5, wherein the first inverter is connected to the second electrode of the first capacitor, the first electrode of which is connected to the ground, and the first bias voltage is applied to the first inverter. A second inverter having an input side connected to the output side of the inverter, and the other end of a thermistor resistance element having an input side connected to the output side of the second inverter and one end connected to the second electrode of the first capacitor. A third inverter connected to the output side, to which a second bias voltage is applied , and a reference resistance element having an input side connected to the output side of the second inverter and one end connected to the second electrode of the first capacitor. It is connected to the output side to the other end, and a fourth inverter which third bias voltage is applied, an input side connected to the output side of the first inverter, and a second electrode of the first capacitor Is output side connected to the second electrode of the second capacitor is first electrode is connected, the the fifth inverter first bias voltage is applied, wherein the first bias voltage, said first capacitor, said first The level is adjusted so that the oscillation frequency determined by the two capacitors and the reference resistance element becomes a predetermined frequency, and the second bias voltage includes the first bias voltage and an operating state or a high impedance state. And the third bias voltage is generated based on the voltage of the first signal that determines which one of the second signal and the second bias voltage that determines whether the first bias voltage and the operating state or the high impedance state are to be generated. and voltage is generated based on the third inverter operation state, and the fourth inverter is high impedance state, before Each of the first inverter and the fifth inverter operates in transition time in accordance with the prior SL first bias voltage, the semiconductor integrated circuit, the third high-inverters impedance state, and the fourth inverter the behavior like as state, the first capacitor, the second capacitor, and the first oscillation frequency based on the reference resistance element, and measuring a first voltage level of the first bias voltage when the predetermined oscillation frequency and the third inverter the operating state, and the fourth inverter a high impedance state, when the first bias voltage of the first voltage level is applied to the first inverter and the fifth inverter Measuring a second oscillation frequency based on the first capacitor, the second capacitor, and the thermistor resistance element; Calculating a frequency ratio between two oscillation frequencies and the first oscillation frequency for each measurement temperature by changing the measurement temperature, obtaining a correspondence relationship between the measurement temperature and the frequency ratio; impedance state, and the fourth inverter as operating state, the first capacitor, the second capacitor, and a third oscillation frequency based on the reference resistance element, wherein in a case where a predetermined oscillation frequency a second voltage level of the first bias voltage is measured, and said third inverter to operate state, and the fourth inverter a high impedance state, the said first bias voltage of the second voltage level the A fourth oscillation circuit based on the first capacitor, the second capacitor, and the thermistor resistance element when applied to one inverter and the fifth inverter; By measuring the number, and calculates the frequency ratio of the said fourth oscillation frequency third oscillation frequency, comprising: a calculated frequency ratio, and the correspondence relation, and a step of calculating a measured temperature based on.

  According to the present invention, it is possible to eliminate the influence of the ON resistance of the inverter and the internal delay time and appropriately detect the measured temperature.

It is a schematic block diagram which shows a specific example of schematic structure of the RC oscillation circuit which concerns on this Embodiment. It is a circuit diagram which shows a specific example of the inverter which concerns on this Embodiment. It is a circuit diagram which shows a specific example of the bias circuit which concerns on this Embodiment. It is a circuit diagram which shows a specific example of the bias switch which concerns on this Embodiment. According to this embodiment. It is a circuit diagram which shows a specific example of an inverter. It is a wave form diagram for demonstrating a specific example of the calibration operation | movement which concerns on this Embodiment. It is a schematic block diagram which shows schematic structure of the modification of the RC oscillation circuit which concerns on this Embodiment. It is a schematic block diagram which shows a specific example of schematic structure of the conventional RC oscillation circuit. It is a wave form diagram which shows a specific example of the oscillation operation | movement waveform of the conventional RC oscillation circuit. It is a schematic block diagram of a specific example of an inverter for explaining an ON resistance r of the inverter. It is explanatory drawing for demonstrating the internal delay time T of RC oscillation circuit. Is an explanatory view for explaining the oscillation frequency, (1) shows the oscillation frequency f _T at the oscillation in the thermistor resistance element R _T, (2) the oscillation during the oscillation of the reference resistance elements R _S The frequency f _S is shown.

  Hereinafter, a semiconductor integrated circuit according to an embodiment of the present invention will be described in detail with reference to the drawings. Note that in this embodiment, a case where a semiconductor integrated circuit is applied to an RC oscillation circuit (RC-ADC) will be described in detail.

  FIG. 1 shows a schematic configuration diagram of an example of a schematic configuration of the RC oscillation circuit according to the present embodiment. FIG. 2 shows a schematic configuration diagram of a bias circuit and a bias switch for applying a bias voltage to the RC oscillation circuit of the present embodiment.

The RC oscillation circuit 10 shown in FIG. 1 includes an inverter inv11, an inverter inv21, an inverter inv31, an inverter inv41, an inverter inv51, an inverter inv61, a thermistor resistance element R _T , a reference resistance element R _S , a capacitor C _VR , and a capacitor C _S. It is prepared for. In the RC oscillation circuit 10 of the present embodiment, the inverter inv11, the inverter inv21, the inverter inv31, the inverter inv41, the inverter inv51, and the inverter inv61 are formed on the same semiconductor chip (inside the semiconductor chip). Further, the thermistor resistance element R _T , the reference resistance element R _S , the capacitor C _VR , and the capacitor C _S are formed outside the semiconductor chip. The inverted output of the inverter inv11 is connected via the node RT to the thermistor resistance element _{R T.} The inverted output of the inverter inv21 is connected via a node RS in reference resistance element _{R S.} The inverted output of the inverter inv31 is connected via a node CS to one electrode of the capacitor C _S. Input of the inverter inv41 is connected via the node IN to one electrode of the capacitor _{C VR.}

The capacitor C _VR has one electrode connected to the thermistor resistance element R _T , the reference resistance element R _S , the capacitor C _S , and the inverter inv41, and the other electrode connected to the ground. The ground is not limited to 0V and may be a predetermined voltage.

  Further, the inverter inv51 has an input connected to the inverted output of the inverter inv41 and an inverted output connected to the inputs of the inverter inv11 and the inverter inv21.

The bias circuit 12 has a function of generating and outputting the bias signal pbias and the bias signal nbias in accordance with the input signal code <7: 0>. A specific example of the bias circuit 12 is shown in FIG. FIG. 3 shows a case where the bias circuit 12 is configured as a circuit corresponding to an 8-bit DAC. However, the bias circuit 12 is not particularly limited, and the voltage levels of the bias signal pbias and the bias signal nbias that are output according to the input signal ( Any device having a function of adjusting (voltage value) may be used. As shown in FIG. 3, in the bias circuit 12, the decoding circuit 20 and cells 22 ₀ to 22 composed of a PMOS field effect transistor and an NMOS field effect transistor for outputting the bias signal pbias corresponding to each code of the input signal. A cell 22 ₂₅₅ is provided, and similarly, cells 24 ₀ to 24 _{255 including} a PMOS field effect transistor and an NMOS field effect transistor for outputting the bias signal nbias are provided. Thus, in the bias circuit 12, when the input signal increases, the voltage value of the bias signal pbias increases, and at the same time, the voltage value of the bias signal nbias decreases.

  On the other hand, the bias switch 14 and the bias switch 16 are based on the bias signal pbias and the bias signal nbias generated by the bias circuit 12 and the signal enb_inv1 and the signal en_inv1 or the signal enb_inv2 and the signal en_inv2, respectively. It has a function of generating nbias_inv11 or bias signal pbias_inv21 and bias signal nbias_inv21. As shown in the conventional RC oscillation circuit 100 of FIG. 8, since the signal inb_inv1 and the signal en_inv1 are conventionally input to the inverter inv11 and the signal enb_inv2 and the signal en_inv2 are applied to the inverter inv21, the inverter inv11 and the inverter inv21 Then, it is necessary to apply a bias voltage in consideration of these signals (voltages). Therefore, in the present embodiment, the bias signal pbias_inv11 and the bias signal nbias_inv11 are generated using the bias switch 14 shown in FIG. 4, and the bias signal pbias_inv21 and the bias signal nbias_inv21 are generated using the bias switch 16.

In the present embodiment, the bias circuit 12 generates the bias signal pbias and the bias signal nbias that have the predetermined oscillation frequency f _S when RC oscillation is performed by the reference resistor element _RS .

  The bias circuit 12, the bias switch 14, and the bias switch 16 may be formed inside the semiconductor chip in which the inverter inv is formed, or may be formed outside the semiconductor chip.

  Next, a specific example of the inverters inv11 to in51 is shown in FIG. In order to simplify the description, the inverters inv11 to in51 are collectively referred to as inverters inv without being distinguished, and the inverters inv11 to in51 are denoted by numerals 11 to 51. As shown in FIG. 5, the inverter inv of the present embodiment is configured to include two PMOS field effect transistors P1 and P2 and two NMOS field effect transistors N1 and N2.

  In the inverter inv31, the inverter inv41, and the inverter inv51, the bias signal pbias generated by the bias circuit 12 is input to the gate of the PMOS field effect transistor P1. The bias signal nbias generated by the bias circuit 12 is input to the NMOS field effect transistor N1. The input signal of the inverter inv is input to the gates of the PMOS field effect transistor P2 and the NMOS field effect transistor N2. On the other hand, in the inverter inv11, a signal pbias_inv11 corresponding to the bias signal pbias generated by the bias switch 14 is input to the gate of the PMOS field effect transistor P1. A signal nbias_inv11 corresponding to the bias signal nbias generated by the bias switch 14 is input to the NMOS field effect transistor N1. The input signal of the inverter inv is input to the gates of the PMOS field effect transistor P2 and the NMOS field effect transistor N2. On the other hand, in the inverter inv21, a signal pbias_inv21 corresponding to the bias signal pbias generated by the bias switch 16 is input to the gate of the PMOS field effect transistor P1. A signal nbias_inv21 corresponding to the bias signal nbias generated by the bias switch 16 is input to the NMOS field effect transistor N1. The input signal of the inverter inv is input to the gates of the PMOS field effect transistor P2 and the NMOS field effect transistor N2.

  Thus, the inverter inv receives a bias voltage corresponding to the bias signal pbias and the bias signal nbias, and the ON resistances of the PMOS field effect transistors P1 and P2 and the NMOS field effect transistors N1 and N2 change according to the bias voltage. Therefore, in the inverter inv, the mutual conductance gm changes, and the time for transition from the L level to the H level and the time for transition from the H level to the L level change according to the bias voltage.

  Next, the operation of detecting the measurement temperature of the RC oscillation frequency by the RC oscillation circuit 10 of the present embodiment will be described.

First, a table of measured temperatures with respect to the frequency ratio is created in advance. When creating the table, a reference oscillation frequency (hereinafter referred to as a reference oscillation frequency) is determined in advance for how many Hz the oscillation operation using the reference resistance element _RS is oscillated. The reference oscillation frequency is determined in consideration of variations in the threshold value Vt of the PMOS field effect transistor and NMOS field effect transistor of the inverter inv, operating voltage conditions, and the like.

Once the reference oscillation frequency is determined, adjustment (calibration) is performed by the bias circuit 12 so that the oscillation operation using the reference resistance element _RS oscillates at the reference oscillation frequency. A waveform diagram of the calibration operation at this time is shown in FIG.

Specifically, first, the inverter inv11 is set to the HiZ state, and the inverter inv21 is operated to perform an oscillation operation using the reference resistance element _RS .

Further, the input signal code <7: 0> of the bias circuit 12 is sequentially changed from 00h to 01h and further to 02h, and the selection of the cell 22 and the cell 24 to be operated is sequentially changed. Accordingly, the voltage level of the bias signal pbias gradually rises from the GND level, and at the same time, the voltage level of the bias signal nbias is gradually processed from the power supply voltage level. As the bias signal pbias and the bias signal nbias change, the mutual conductance gm of the inverters inv11 to inv51 changes, and the oscillation frequency f _S gradually decreases as shown in FIG. When the oscillation frequency f _S coincides with (or can be regarded as coincident with) the reference oscillation frequency, the change of the input signal code <7: 0> is stopped.

Next, in the state where the input signal code <7: 0> at the time of the stop is fixed, the inverter inv11 is operated, the inverter inv21 is set to the HiZ state, and the oscillation operation using the thermistor resistance element _RT is performed. to measure the frequency _{f T.} That is, an oscillation operation using the thermistor resistance element _RT is performed in a state where the bias signal pbias and the bias signal nbias when the oscillation frequency f _S matches the reference oscillation frequency are applied (the same voltage level is applied). to measure the frequency _{f T.}

The calibration operation with the reference resistance element _RS described above, the measurement of the oscillation frequency f _T with the thermistor resistance element _RT after calibration, and the measurement temperature are changed for each measurement temperature, and the frequency ratio f _S / the f _T is calculated for each measured temperature, to create a table of measured temperature with respect to the frequency ratio.

When detecting the actual measurement temperature, first, calibration with the reference resistance element _RS is performed in the same manner as in the table creation described above.

Next, in the same way as when the table is created as described above to measure the oscillation frequency f _T using a thermistor resistor element R _T, calculates the frequency ratio f _{S /} f _T. Then, the measured frequency is detected by checking the calculated frequency ratio f _S / f _T against the previously created table and calculating it.

As described above, in the present embodiment, the inverters inv11 to inv51 include the bias signal pbias and the bias signal nbias generated by the bias circuit 12, or the bias signals pbias_inv11 and nbias_inv11 based on the bias signal pbias and the bias signal nbias. , pbias_inv21, nbias_inv21 is the time of calibration of the reference resistance element _{R S,} the oscillation frequency _{f S} of the reference resistance element _{R S} is applied so that the reference oscillation frequency.

In the detection operation of the temperature measured by the RC oscillation circuit 10 of the present embodiment, in advance, the reference resistance elements R _S by calibration and the calibration after the bias signal pbais and thermistor resistance element in a state where the voltage level was fixed bias signal nbias by measuring the oscillation frequency f _T by R _T, it performs the calculation of the frequency ratio f _{S /} f _T for each measurement temperature in advance to obtain a table of measured temperature with respect to the frequency ratio. When the measured temperature is actually detected, the calibration frequency is measured with the reference resistance element _RS , and the oscillation frequency f _T is measured by the thermistor resistance element _RT to obtain the frequency ratio. f _S / f _T is calculated, and the measured temperature is detected by checking with the table.

As described above, in the present embodiment, the calibration by the reference resistance element _RS is performed in consideration of the ON resistance r of the PMOS field effect transistor and the NMOS field effect transistor which change depending on the operating conditions such as voltage and temperature, and the influence of the internal delay time T. performed Deployment, by further measuring the oscillation frequency f _T of the thermistor resistance element R _T after calibration, and the oN resistance r given to frequency ratio f _{S /} f _T, it is possible to eliminate the influence of the internal delay time T . Since the calibration using the reference resistance element _RS is performed at the time of measurement temperature detection in the same manner as at the time of measurement temperature table creation for the frequency ratio, the same state as at the time of table creation is basically reproduced. In addition, the influence of the internal delay time T can be eliminated.

  In addition, since the influence of the variation in the threshold value Vt of the PMOS field effect transistor and the NMOS field effect transistor is eliminated, the detection accuracy of the measurement temperature can be improved.

Further, in the RC oscillation circuit 10 according to the present embodiment, the reference resistance element RS is calibrated in consideration of the influence of the ON resistance, and a table of the measured temperature with respect to the frequency ratio is created. The power supply voltage range in which the influence of the ON resistance is small as in the conventional RC oscillation circuit as shown in Patent Document 1 does not become the operation guarantee voltage.
(Modification)
A modification of the RC oscillation circuit is shown in FIG. In the RC oscillation circuit 10 (FIG. 1) described above, the inverters inv11 to inv51 are configured to receive a bias signal. In the RC oscillation circuit 50 shown in FIG. 7, only the inverters inv11 and inv21 are provided. A bias signal (bias voltage) is applied. An input signal to which no bias signal is applied is input to the inverters inv31 to inv51.
This will be described with reference to FIG. Specifically, in the inverter inv11, the signal pbias_inv11 corresponding to the bias signal pbias generated by the bias switch 14 is input to the gate of the PMOS field effect transistor P1. A signal nbias_inv11 corresponding to the bias signal nbias generated by the bias switch 14 is input to the NMOS field effect transistor N1. The input signal of the inverter inv is input to the gates of the PMOS field effect transistor P2 and the NMOS field effect transistor N2. On the other hand, in the inverter inv21, a signal pbias_inv21 corresponding to the bias signal pbias generated by the bias switch 16 is input to the gate of the PMOS field effect transistor P1. A signal nbias_inv21 corresponding to the bias signal nbias generated by the bias switch 16 is input to the NMOS field effect transistor N1. The input signal of the inverter inv is input to the gates of the PMOS field effect transistor P2 and the NMOS field effect transistor N2. On the other hand, in the inverters inv31 to in51, the input signal of the inverter inv is input to both the gates of the PMOS field effect transistors P1 and P2 and the gates of the NMOS field effect transistors N1 and N2.
Effect on the oscillation period of the time (oscillation frequency), the capacitor C _VR, capacity C _S, the resistance value of the thermistor resistance element R _T, the resistance of the reference resistance element R _S, is greater by ON resistance r, the internal delay Time T has little effect. Therefore, even when a bias signal (bias voltage) is applied only to the inverters inv11 and inv21 as in the RC oscillation circuit 50 shown in FIG. 7, the inverters inv11 and inv21 are applied by applying the bias voltage. The time for transition from the L level to the H level and the time for transition from the H level to the L level vary according to the bias voltage.
Also in the RC oscillator circuit 50, in the same manner as described above, the inverter inv11 and the inverter INV21, the bias voltage, during the calibration of the reference resistance element _{R S,} the oscillation of the reference resistance element _{R S} frequency _{f S} is the reference oscillation frequency It is applied so that Also, the detection operation of the measured temperature by the RC oscillation circuit 50 is performed in the same manner as described above, with the thermistor resistor in a state where the voltage level of the bias signal pbais and the bias signal nbias is fixed in advance after calibration by the reference resistor element _RS . by measuring the oscillation frequency f _T by element R _T, it performs the calculation of the frequency ratio f _{S /} f _T for each measurement temperature in advance to obtain a table of measured temperature with respect to the frequency ratio. When the measured temperature is actually detected, the calibration frequency is measured with the reference resistance element _RS , and the oscillation frequency f _T is measured by the thermistor resistance element _RT to obtain the frequency ratio. f _S / f _T is calculated, and the measured temperature is detected by checking with the table.
As described above, since the calibration using the reference resistance element _RS is performed at the time of detecting the measurement temperature, as in the case of creating the table of the measurement temperature with respect to the frequency ratio, the effect of the present invention can be obtained.

  The specific configurations of the bias circuit 12, the bias switch 14, the bias switch 16, and the inverter inv are merely examples, and are not limited to the configurations.

10, 50 RC oscillator circuit 12 the bias circuit 14, 16 bias switch inv11, inv21, inv31, inv41, inv51, inv61 inverter _{R T} thermistor resistance element _{R S} reference resistance element _{C VR} capacitor _{C S} capacitor

Claims (5)

A first inverter having an input connected to a second electrode of a first capacitor, the first electrode of which is connected to ground, and a first bias voltage applied ;
A second inverter having an input side connected to the output side of the first inverter;
A third bias voltage is applied by connecting the output side to the other end of the thermistor resistance element having one end connected to the output side of the second inverter and one end connected to the second electrode of the first capacitor. An inverter;
The fourth inverter is connected to the output side of the second inverter and connected to the other end of the reference resistance element having one end connected to the second electrode of the first capacitor, and a third bias voltage is applied . An inverter;
An input side is connected to an output side of the first inverter, and an output side is connected to a second electrode of a second capacitor in which a first electrode is connected to a second electrode of the first capacitor , and the first bias voltage is applied. A fifth inverter,
With
The level of the first bias voltage is adjusted so that an oscillation frequency determined by the first capacitor, the second capacitor, and the reference resistance element becomes a predetermined frequency,
The second bias voltage is generated based on the first bias voltage and a voltage of a first signal that determines whether to be in an operating state or a high impedance state,
The third bias voltage is generated based on the first bias voltage and a voltage of a second signal that determines whether to be in an operating state or a high impedance state,
Said third inverter operation state, and a fourth inverter a high impedance state, each of the first inverter and the fifth inverter operates in transition time in accordance with the prior SL first bias voltage,
Semiconductor integrated circuit. It said first bias voltage, the third high-inverters impedance state, and the fourth inverter as operating state, set the first capacitor, the second capacitor, and the oscillation frequency determined by the reference resistance element in advance The level has been adjusted to the desired frequency,
The semiconductor integrated circuit according to claim 1. A bias circuit for outputting the first bias voltage whose voltage level is adjusted based on an input signal;
Said first inverter and the fifth inverter, wherein the first bias voltage from the bias circuit is applied, and to operate in the transition time corresponding to the voltage level of the first bias voltage, according to claim 1 or claim 2 A semiconductor integrated circuit according to 1. 4. The semiconductor integrated circuit according to claim 1, wherein the second inverter operates with a transition time corresponding to the first bias voltage, to which the first bias voltage is applied. 5. A first inverter having an input connected to a second electrode of a first capacitor, the first electrode of which is connected to ground, and a first bias voltage applied ;
A second inverter having an input side connected to the output side of the first inverter;
A third bias voltage is applied by connecting the output side to the other end of the thermistor resistance element having one end connected to the output side of the second inverter and one end connected to the second electrode of the first capacitor. An inverter;
The fourth inverter is connected to the output side of the second inverter and connected to the other end of the reference resistance element having one end connected to the second electrode of the first capacitor, and a third bias voltage is applied . An inverter;
An input side is connected to an output side of the first inverter, and an output side is connected to a second electrode of a second capacitor in which a first electrode is connected to a second electrode of the first capacitor , and the first bias voltage is applied. A fifth inverter,
With
The level of the first bias voltage is adjusted so that an oscillation frequency determined by the first capacitor, the second capacitor, and the reference resistance element becomes a predetermined frequency,
The second bias voltage is generated based on the first bias voltage and a voltage of a first signal that determines whether to be in an operating state or a high impedance state,
The third bias voltage is generated based on the first bias voltage and a voltage of a second signal that determines whether to be in an operating state or a high impedance state,
Said third inverter operation state, and a fourth inverter a high impedance state, each of the first inverter and the fifth inverter operates in transition time in accordance with the prior SL first bias voltage, In semiconductor integrated circuits,
The third high-inverters impedance state, and the fourth inverter as operating state, the first capacitor, the second capacitor, and the first oscillation frequency based on the reference resistance element, a predetermined oscillation Measuring a first voltage level of the first bias voltage at a frequency;
And said third inverter the behavior state and the high impedance state the fourth inverter, the when the first bias voltage of the first voltage level is applied to the first inverter and the fifth inverter A second oscillation frequency based on the first capacitor, the second capacitor, and the thermistor resistance element is measured, and a frequency ratio between the second oscillation frequency and the first oscillation frequency is measured by changing a measurement temperature. Calculating for each temperature and obtaining the correspondence between the measured temperature and the frequency ratio;
The third high-inverters impedance state, and the fourth inverter as operating state, the first capacitor, the second capacitor, and the third oscillation frequency based on the reference resistance element, a predetermined oscillation Measuring a second voltage level of the first bias voltage at a frequency;
And said third inverter the behavior state and the high impedance state the fourth inverter, the when the first bias voltage of the second voltage level is applied to the first inverter and the fifth inverter A fourth oscillation frequency based on the first capacitor, the second capacitor, and the thermistor resistance element is measured to calculate a frequency ratio between the fourth oscillation frequency and the third oscillation frequency, and the calculated frequency ratio Calculating a measured temperature based on the correspondence relationship;
Measuring temperature detection method comprising:

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