JP2009031093A5 - - Google Patents
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- JP2009031093A5 JP2009031093A5 JP2007194512A JP2007194512A JP2009031093A5 JP 2009031093 A5 JP2009031093 A5 JP 2009031093A5 JP 2007194512 A JP2007194512 A JP 2007194512A JP 2007194512 A JP2007194512 A JP 2007194512A JP 2009031093 A5 JP2009031093 A5 JP 2009031093A5
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- 238000009966 trimming Methods 0.000 claims 28
- 230000000875 corresponding Effects 0.000 claims 12
- 238000005520 cutting process Methods 0.000 claims 8
- 238000001514 detection method Methods 0.000 claims 6
- 238000011105 stabilization Methods 0.000 claims 3
Claims (4)
直列接続されたｎ個（ｎは１以上の整数）の第１〜第ｎの抵抗素子と、前記第１〜第ｎの抵抗素子の各々に対応して並列接続された第１〜第ｎのスイッチング素子と、を有する可変抵抗回路と、
基準電圧を発生する基準電圧源と、
前記被測定電源の電圧を前記可変抵抗回路と所定の抵抗素子とで構成される抵抗分割回路によって分圧することで生じる中点電圧と、前記基準電圧とを比較し、前記中点電圧と前記基準電圧との大小関係が反転した場合に、前記被測定電源の電圧が所定電圧に到達したことを示すために出力信号の状態を反転させる比較回路と、
前記比較回路の出力信号が反転した場合、またはテストモード時の場合に、所定周波数のクロック信号を生成する発振回路と、
前記クロック信号の１／２ｋ−１周波数（ｋ＝２、３、…、ｎ）の分周信号を生成する分周回路と、
前記クロック信号に対応して設けられ、内部に配置されたトリミング用導通素子の切断前では前記クロック信号を前記第１のスイッチング素子の制御端子に出力する一方、前記トリミング用導通素子の切断後には前記第１のスイッチング素子をオン状態またはオフ状態に維持させる信号を出力する第１の抵抗値設定回路と、
前記１／２ｋ−１周波数の分周信号の各々に対応して設けられ、内部に配置されたトリミング用導通素子の切断前では前記１／２ｋ−１周波数の分周信号を各々に対応する第２〜第ｎのスイッチング素子の制御端子に出力する一方、前記トリミング用導通素子の切断後には前記第２〜第ｎのスイッチング素子をオン状態またはオフ状態に維持させる信号を出力する第２〜第ｎの抵抗値設定回路と、
前記テストモード時の場合は前記比較回路の出力信号を外部に出力し、通常モード時の場合は１／２ｎ−１周波数の分周信号が前記分周回路から出力された場合に前記比較回路の出力信号を外部に出力するモード選択回路を備え、
前記第１〜第ｎの抵抗素子の抵抗比は、それぞれ２ｉ−１（ｉ＝１、２、…、ｎ）となるように設定されている電圧検出回路において、
テストモードに移行してから前記モード選択回路の出力信号が反転するまでの時間を測定し、当該測定した時間から前記発振回路の発振周期を除算することにより、前記可変抵抗回路のトリミング量を検出し、当該トリミング量に応じて前記第１〜第ｎの抵抗値設定回路における前記トリミング用導通素子の切断処理を行う、
ことを特徴とするトリミング方法。 A voltage detection circuit for detecting that the voltage of the power source to be measured has reached a predetermined voltage,
N (n is an integer of 1 or more) first to nth resistance elements connected in series and first to nth resistance elements connected in parallel corresponding to each of the first to nth resistance elements. A variable resistance circuit having a switching element;
A reference voltage source for generating a reference voltage;
The midpoint voltage generated by dividing the voltage of the power source to be measured by a resistance dividing circuit composed of the variable resistance circuit and a predetermined resistance element is compared with the reference voltage, and the midpoint voltage and the reference A comparison circuit that inverts the state of the output signal to indicate that the voltage of the power supply to be measured has reached a predetermined voltage when the magnitude relationship with the voltage is reversed;
An oscillation circuit that generates a clock signal having a predetermined frequency when the output signal of the comparison circuit is inverted or in a test mode;
A frequency dividing circuit for generating a frequency - divided signal of 1/2 k-1 frequency (k = 2, 3,..., N) of the clock signal;
The clock signal is provided corresponding to the clock signal, and the clock signal is output to the control terminal of the first switching element before cutting of the trimming conductive element disposed therein. A first resistance value setting circuit for outputting a signal for maintaining the first switching element in an on state or an off state;
The 1/2 k-1 frequency divided signal is provided corresponding to each of the 1/2 k-1 frequency divided signals, and corresponds to the 1/2 k-1 frequency divided signals before the trimming conductive element is cut. Output to a control terminal of the second to n-th switching elements to be output, and outputs a signal for maintaining the second to n-th switching elements in an on state or an off state after the trimming conductive element is disconnected. To nth resistance value setting circuit;
In the test mode, the output signal of the comparison circuit is output to the outside, and in the normal mode, when the frequency division signal of 1/2 n-1 frequency is output from the frequency division circuit, the comparison circuit With a mode selection circuit that outputs the output signal of
In the voltage detection circuit in which the resistance ratio of the first to nth resistance elements is set to be 2 i-1 (i = 1, 2,..., N), respectively.
Measure the time from the transition to the test mode to the inversion of the output signal of the mode selection circuit, and detect the trimming amount of the variable resistance circuit by dividing the oscillation period of the oscillation circuit from the measured time And cutting the trimming conductive element in the first to nth resistance value setting circuits according to the trimming amount.
A trimming method characterized by the above.
直列接続されたｎ個（ｎは１以上の整数）の第１〜第ｎの抵抗素子と、前記第１〜第ｎの抵抗素子の各々に対応して並列接続された第１〜第ｎのスイッチング素子と、を有する可変抵抗回路と、
基準電圧を発生する基準電圧源と、
前記被測定電源の電圧を前記可変抵抗回路と所定の抵抗素子とで構成される抵抗分割回路によって分圧することで生じる中点電圧と、前記基準電圧とを比較し、前記中点電圧と前記基準電圧との大小関係が反転した場合に、前記被測定電源の電圧が所定電圧に到達したことを示すために出力信号の状態を反転させる比較回路と、
前記比較回路の出力信号が反転した場合、またはテストモード時の場合に、所定周波数のクロック信号を生成する発振回路と、
前記クロック信号の１／２ｋ−１周波数（ｋ＝２、３、…、ｎ）の分周信号を生成する分周回路と、
前記クロック信号に対応して設けられ、内部に配置されたトリミング用導通素子の切断前では前記クロック信号を前記第１のスイッチング素子の制御端子に出力する一方、前記トリミング用導通素子の切断後には前記第１のスイッチング素子をオン状態またはオフ状態に維持させる信号を出力する第１の抵抗値設定回路と、
前記１／２ｋ−１周波数の分周信号の各々に対応して設けられ、内部に配置されたトリミング用導通素子の切断前では前記１／２ｋ−１周波数の分周信号を各々に対応する第２〜第ｎのスイッチング素子の制御端子に出力する一方、前記トリミング用導通素子の切断後には前記第２〜第ｎのスイッチング素子をオン状態またはオフ状態に維持させる信号を出力する第２〜第ｎの抵抗値設定回路と、
前記テストモード時の場合、前記比較回路の出力信号が反転するまでの間、前記クロック信号を外部に出力する出力するモード選択回路を備え、
前記第１〜第ｎの抵抗素子の抵抗比は、それぞれ２ｉ−１（ｉ＝１、２、…、ｎ）となるように設定されている電圧検出回路において、
テストモードに移行してから前記モード選択回路の出力信号が反転して一定となるまでの期間、前記モード選択回路の出力信号の立ち上がり及び立ち下がりに同期してカウントを行い、当該カウント値からトリミング量を検出し、当該トリミング量に応じて前記第１〜第ｎの抵抗値設定回路における前記トリミング用導通素子の切断処理を行う、
ことを特徴とするトリミング方法。 A voltage detection circuit for detecting that the voltage of the power source to be measured has reached a predetermined voltage,
N (n is an integer of 1 or more) first to nth resistance elements connected in series and first to nth resistance elements connected in parallel corresponding to each of the first to nth resistance elements. A variable resistance circuit having a switching element;
A reference voltage source for generating a reference voltage;
The midpoint voltage generated by dividing the voltage of the power source to be measured by a resistance dividing circuit composed of the variable resistance circuit and a predetermined resistance element is compared with the reference voltage, and the midpoint voltage and the reference A comparison circuit that inverts the state of the output signal to indicate that the voltage of the power supply to be measured has reached a predetermined voltage when the magnitude relationship with the voltage is reversed;
An oscillation circuit that generates a clock signal having a predetermined frequency when the output signal of the comparison circuit is inverted or in a test mode;
A frequency dividing circuit for generating a frequency - divided signal of 1/2 k-1 frequency (k = 2, 3,..., N) of the clock signal;
The clock signal is provided corresponding to the clock signal, and the clock signal is output to the control terminal of the first switching element before cutting of the trimming conductive element disposed therein. A first resistance value setting circuit for outputting a signal for maintaining the first switching element in an on state or an off state;
The 1/2 k-1 frequency divided signal is provided corresponding to each of the 1/2 k-1 frequency divided signals, and corresponds to the 1/2 k-1 frequency divided signals before the trimming conductive element is cut. Output to a control terminal of the second to n-th switching elements to be output, and outputs a signal for maintaining the second to n-th switching elements in an on state or an off state after the trimming conductive element is disconnected. To nth resistance value setting circuit;
In the case of the test mode, a mode selection circuit for outputting the clock signal to the outside is provided until the output signal of the comparison circuit is inverted.
In the voltage detection circuit in which the resistance ratio of the first to nth resistance elements is set to be 2 i-1 (i = 1, 2,..., N), respectively.
During the period from the transition to the test mode until the output signal of the mode selection circuit is inverted and becomes constant, the count is performed in synchronization with the rise and fall of the output signal of the mode selection circuit, and trimming is performed from the count value. Detecting the amount, and cutting the trimming conductive element in the first to nth resistance value setting circuits according to the trimming amount,
A trimming method characterized by the above.
直列接続されたｎ個（ｎは１以上の整数）の第１〜第ｎの抵抗素子と、前記第１〜第ｎの抵抗素子の各々に対応して並列接続された第１〜第ｎのスイッチング素子と、を有する可変抵抗回路と、
基準電圧を発生する基準電圧源と、
前記被測定電源の電圧を前記可変抵抗回路と所定の抵抗素子とで構成される抵抗分割回路によって分圧することで生じる中点電圧と、前記基準電圧とを比較し、前記中点電圧と前記基準電圧との大小関係が反転した場合に、前記被測定電源の電圧が所定電圧に到達したことを示すために出力信号の状態を反転させる比較回路と、
テストモード時及び通常モード時に、所定周波数のクロック信号を外部から入力するために用いる外部クロック端子と、
前記クロック信号の１／２ｋ−１周波数（ｋ＝２、３、…、ｎ）の分周信号を生成する分周回路と、
前記クロック信号に対応して設けられ、内部に配置されたトリミング用導通素子の切断前では前記クロック信号を前記第１のスイッチング素子の制御端子に出力する一方、前記トリミング用導通素子の切断後には前記第１のスイッチング素子をオン状態またはオフ状態に維持させる信号を出力する第１の抵抗値設定回路と、
前記１／２ｋ−１周波数の分周信号の各々に対応して設けられ、内部に配置されたトリミング用導通素子の切断前では前記１／２ｋ−１周波数の分周信号を各々に対応する第２〜第ｎのスイッチング素子の制御端子に出力する一方、前記トリミング用導通素子の切断後には前記第２〜第ｎのスイッチング素子をオン状態またはオフ状態に維持させる信号を出力する第２〜第ｎの抵抗値設定回路と、
前記テストモード時の場合は前記比較回路の出力信号を外部に出力し、通常モード時の場合は１／２ｎ−１周波数の分周信号が前記分周回路から出力された場合に前記比較回路の出力信号を外部に出力するモード選択回路を備え、
前記第１〜第ｎの抵抗素子の抵抗比は、それぞれ２ｉ−１（ｉ＝１、２、…、ｎ）となるように設定されている電圧検出回路において、
テストモードに移行した後、外部からクロック信号を入力し、テストモードに移行してから前記モード選択回路の出力信号が反転するまでの期間、前記クロック信号の立ち上がり及び立ち下がりに同期してカウントを行い、当該カウント値からトリミング量を検出し、当該トリミング量に応じて前記第１〜第ｎの抵抗値設定回路における前記トリミング用導通素子の切断処理を行う、
ことを特徴とするトリミング方法。 A voltage detection circuit for detecting that the voltage of the power source to be measured has reached a predetermined voltage,
N (n is an integer of 1 or more) first to nth resistance elements connected in series and first to nth resistance elements connected in parallel corresponding to each of the first to nth resistance elements. A variable resistance circuit having a switching element;
A reference voltage source for generating a reference voltage;
The midpoint voltage generated by dividing the voltage of the power source to be measured by a resistance dividing circuit composed of the variable resistance circuit and a predetermined resistance element is compared with the reference voltage, and the midpoint voltage and the reference A comparison circuit that inverts the state of the output signal to indicate that the voltage of the power supply to be measured has reached a predetermined voltage when the magnitude relationship with the voltage is reversed;
An external clock terminal used for inputting a clock signal of a predetermined frequency from the outside during the test mode and the normal mode;
A frequency dividing circuit for generating a frequency - divided signal of 1/2 k-1 frequency (k = 2, 3,..., N) of the clock signal;
The clock signal is provided corresponding to the clock signal, and the clock signal is output to the control terminal of the first switching element before cutting of the trimming conductive element disposed therein. A first resistance value setting circuit for outputting a signal for maintaining the first switching element in an on state or an off state;
The 1/2 k-1 frequency divided signal is provided corresponding to each of the 1/2 k-1 frequency divided signals, and corresponds to the 1/2 k-1 frequency divided signals before the trimming conductive element is cut. Output to a control terminal of the second to n-th switching elements to be output, and outputs a signal for maintaining the second to n-th switching elements in an on state or an off state after the trimming conductive element is disconnected. To nth resistance value setting circuit;
In the test mode, the output signal of the comparison circuit is output to the outside, and in the normal mode, when the frequency division signal of 1/2 n-1 frequency is output from the frequency division circuit, the comparison circuit With a mode selection circuit that outputs the output signal of
In the voltage detection circuit in which the resistance ratio of the first to nth resistance elements is set to be 2 i-1 (i = 1, 2,..., N), respectively.
After the transition to the test mode, a clock signal is input from the outside, and during the period from the transition to the test mode to the inversion of the output signal of the mode selection circuit, counting is performed in synchronization with the rise and fall of the clock signal. Performing a cutting process on the trimming conductive element in the first to n-th resistance value setting circuits according to the trimming quantity, detecting a trimming quantity from the count value,
A trimming method characterized by the above.
直列接続されたｎ個（ｎは１以上の整数）の第１〜第ｎの抵抗素子と、前記第１〜第ｎの抵抗素子の各々に対応して並列接続された第１〜第ｎのスイッチング素子と、を有する可変抵抗回路と、
基準電圧を発生する基準電圧源と、
前記被測定電源と前記可変抵抗回路との間に設けられ、前記被測定電源の電圧の制御に用いられる電圧制御用トランジスタと、
前記電圧制御用トランジスタの出力電圧を前記可変抵抗回路と所定の抵抗素子とで構成される抵抗分割回路によって分圧することで生じる中点電圧と前記基準電圧とを入力とし、前記中点電圧と前記基準電圧とが一致するように前記電圧制御用トランジスタのゲート端子電圧を制御する誤差増幅器と、
テストモード時に、所定周波数のクロック信号を外部から入力するために用いる外部クロック端子と、
前記クロック信号の１／２ｋ−１周波数（ｋ＝２、３、…、ｎ）の分周信号を生成する分周回路と、
前記クロック信号に対応して設けられ、内部に配置されたトリミング用導通素子の切断前では前記クロック信号を前記第１のスイッチング素子の制御端子に出力する一方、前記トリミング用導通素子の切断後には前記第１のスイッチング素子をオン状態またはオフ状態に維持させる信号を出力する第１の抵抗値設定回路と、
前記１／２ｋ−１周波数の分周信号の各々に対応して設けられ、内部に配置されたトリミング用導通素子の切断前では前記１／２ｋ−１周波数の分周信号を各々に対応する第２〜第ｎのスイッチング素子の制御端子に出力する一方、前記トリミング用導通素子の切断後には前記第２〜第ｎのスイッチング素子をオン状態またはオフ状態に維持させる信号を出力する第２〜第ｎの抵抗値設定回路を備え、
前記第１〜第ｎの抵抗素子の抵抗比は、それぞれ２ｉ−１（ｉ＝１、２、…、ｎ）となるように設定されている電圧安定化回路において、
外部からクロック信号を入力し、前記電圧安定化回路の出力信号が所定電圧に到達するまでの期間、前記クロック信号の立ち上がり及び立ち下がりに同期してカウントを行い、当該カウント値からトリミング量を検出し、当該トリミング量に応じて前記第１〜第ｎの抵抗値設定回路における前記トリミング用導通素子の切断処理を行う、
ことを特徴とするトリミング方法。 A voltage stabilization circuit that stabilizes the voltage of the power supply to be measured to a predetermined voltage,
N (n is an integer of 1 or more) first to nth resistance elements connected in series and first to nth resistance elements connected in parallel corresponding to each of the first to nth resistance elements. A variable resistance circuit having a switching element;
A reference voltage source for generating a reference voltage;
A voltage control transistor provided between the power source to be measured and the variable resistance circuit and used to control a voltage of the power source to be measured;
The midpoint voltage generated by dividing the output voltage of the voltage control transistor by a resistance dividing circuit composed of the variable resistance circuit and a predetermined resistance element and the reference voltage are input, and the midpoint voltage and the An error amplifier that controls a gate terminal voltage of the voltage control transistor so that a reference voltage matches,
An external clock terminal used for inputting a clock signal of a predetermined frequency from the outside during the test mode;
A frequency dividing circuit for generating a frequency - divided signal of 1/2 k-1 frequency (k = 2, 3,..., N) of the clock signal;
The clock signal is provided corresponding to the clock signal, and the clock signal is output to the control terminal of the first switching element before cutting of the trimming conductive element disposed therein. A first resistance value setting circuit for outputting a signal for maintaining the first switching element in an on state or an off state;
The 1/2 k-1 frequency divided signal is provided corresponding to each of the 1/2 k-1 frequency divided signals, and corresponds to the 1/2 k-1 frequency divided signals before the trimming conductive element is cut. Output to a control terminal of the second to n-th switching elements to be output, and outputs a signal for maintaining the second to n-th switching elements in an on state or an off state after the trimming conductive element is disconnected. To nth resistance value setting circuit,
In the voltage stabilization circuit in which the resistance ratio of the first to nth resistance elements is set to be 2 i-1 (i = 1, 2,..., N), respectively.
A clock signal is input from the outside, and during the period until the output signal of the voltage stabilization circuit reaches a predetermined voltage, the clock signal is counted in synchronization with the rise and fall of the clock signal, and the trimming amount is detected from the count value And cutting the trimming conductive element in the first to nth resistance value setting circuits according to the trimming amount.
A trimming method characterized by the above.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2007194512A JP4852004B2 (en) | 2007-07-26 | 2007-07-26 | Trimming method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2007194512A JP4852004B2 (en) | 2007-07-26 | 2007-07-26 | Trimming method |
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| Publication Number | Publication Date |
|---|---|
| JP2009031093A JP2009031093A (en) | 2009-02-12 |
| JP2009031093A5 true JP2009031093A5 (en) | 2010-05-27 |
| JP4852004B2 JP4852004B2 (en) | 2012-01-11 |
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| Application Number | Title | Priority Date | Filing Date |
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| JP2007194512A Active JP4852004B2 (en) | 2007-07-26 | 2007-07-26 | Trimming method |
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Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5208011B2 (en) * | 2009-02-13 | 2013-06-12 | セイコーインスツル株式会社 | Memory circuit device |
| JP2012151186A (en) * | 2011-01-17 | 2012-08-09 | Seiko Instruments Inc | Resistance division circuit and voltage detection circuit |
| CN103926441B (en) * | 2014-04-25 | 2017-03-22 | 湖南银河电气有限公司 | Novel voltage divider |
| JP7242124B2 (en) | 2018-07-26 | 2023-03-20 | エイブリック株式会社 | VOLTAGE DETECTION CIRCUIT, SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09200023A (en) * | 1996-01-11 | 1997-07-31 | Kawasaki Steel Corp | Power supply voltage detection circuit |
| JP4368547B2 (en) * | 2001-09-06 | 2009-11-18 | 株式会社リコー | Voltage detection circuit |
| JP2003086700A (en) * | 2001-09-14 | 2003-03-20 | Mitsubishi Electric Corp | Semiconductor device |
| JP4229636B2 (en) * | 2001-11-13 | 2009-02-25 | 株式会社ルネサステクノロジ | Semiconductor device |
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2007
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