JP4973579B2 - CR oscillation circuit - Google Patents

Description

  The present disclosure generally relates to an oscillation circuit, and more particularly to a CR oscillation circuit with a variable oscillation frequency.

  In an integrated circuit such as a microcontroller, a CR oscillation circuit (or a ring oscillator or the like) using a capacitor (C) and a resistor (R) is built in the chip, and a clock signal of the microcontroller is supplied from the built-in oscillation circuit. is there. This is because the start-up time until the output frequency is stabilized is long in an oscillation circuit using a crystal resonator or a ceramic resonator, so use a CR oscillation circuit or ring oscillator with a short start-up time even if the oscillation frequency accuracy is low. This may be desirable.

  FIG. 1 is a diagram illustrating an example of a configuration of a general CR oscillation circuit. This CR oscillation circuit is described in FIG. In FIG. 1, IV1, IV2, and IV3 are inverter circuits, C1 and C2 are capacitors, R1 is a resistor, and ND1 to ND4 are nodes in the oscillation circuit. GND indicates a GND potential (0 V).

  FIG. 2 is a diagram showing waveforms at various parts during operation of the circuit of FIG. (A) shows the potential waveform of ND1, (b) shows the potential waveform of ND2, (c) shows the potential waveform of ND3, and (d) shows the potential waveform of ND4. As shown in FIG. 2, the waveforms of ND1, ND2, and ND3 are rectangular waves that are general output waveforms of a CMOS circuit. Further, ND4 has a waveform in which, due to capacitive coupling between ND4 and ND2, the potential of ND4 changes in the same direction as ND2 following the change in potential of ND2, and then is gradually charged / discharged by the potential of ND3. Become. It is assumed that the power supply voltage is 3.3V. In this way, a CR oscillation circuit can be realized with the simple circuit configuration of FIG.

  FIG. 3 is a diagram illustrating another example of the configuration of the oscillation circuit. This oscillation circuit is shown in Patent Document 3. In FIG. 3, IV1 and IV4 indicate inverter circuits, C1 and C2 indicate capacitors, NMn (n is an integer), NMOS transistors, and PMn (n is an integer) indicate PMOS transistors. Vdd is a positive power supply (for example, 3 V), and GND is a GND potential (0 V). Further, NDn (n is an integer) indicates a node in the oscillation circuit, VBGR indicates a constant voltage generated from the band gap circuit, PB indicates a bias potential of the PMOS transistor, and NB indicates a bias potential of the NMOS transistor. In FIG. 3, the nodes and elements corresponding to the circuit of FIG.

  In the circuit of FIG. 3, one end of the capacitor C1 is driven by an inverter composed of PM3 and NM3 that uses a constant voltage VBGR as a power source, and the signal amplitude of the node ND5 is controlled to be constant regardless of temperature. In order to design the frequency so as not to depend on temperature, the circuit is configured so that the currents flowing in PM2 and NM1 are constant regardless of temperature. A bias potential is applied to PB and NB so that the current flowing through PM2 and NM1 is constant.

  In the circuit of FIG. 3, the bias generation circuits for generating the PB and NB potentials are all integrated on the chip, and a circuit configuration as described below is adopted in order to generate a current independent of temperature. It was. In order to generate a constant current, a potential generated by passing a current through a resistor is matched with a reference voltage by feedback control. Considering the temperature dependence of on-chip resistance, make the reference voltage temperature dependent. If the resistance value increases as temperature rises, the reference voltage also has a positive temperature dependency that increases with temperature, and the temperature dependency of the resistance is offset by the temperature dependency of the reference voltage. Is designed to be temperature independent. With such a circuit, an oscillation circuit in which the oscillation frequency is constant with respect to temperature and power supply voltage has been provided.

  FIG. 4 is a diagram showing still another example of the configuration of the oscillation circuit. This oscillation circuit is shown in Patent Document 4 or Patent Document 5. In FIG. 4, IVn (n is an integer) indicates an inverter circuit, C1 and C2 indicate capacitances, NMn (n is an integer) indicates an NMOS transistor, and PMn (n is an integer) indicates a PMOS transistor. Vdd is a positive power supply (for example, 3 V), and NDn (n is an alphanumeric character) indicates a node inside the oscillation circuit. GND is a GND potential (0 V), PMnG (n is an integer) indicates a gate signal of the PMOS transistor, and NMnG (n is an integer) indicates a gate signal of the NMOS transistor. 4, nodes and elements corresponding to the circuits of FIGS. 1 and 3 are referred to by the same reference numerals.

In the oscillation circuit of FIG. 4, the resistance value of the circuit of FIG. 1 is replaced with a variable resistance value by a transfer gate. The oscillation frequency can be controlled by adjusting the resistance value.
JP-A-53-060149 JP-A-63-182909 JP 2005-217762 A Japanese Patent No. 2770314 JP 2002-33644 A

  The above CR oscillation circuit has the following problems.

  In the circuit of FIG. 1, by using C1, C2, and R1, it has succeeded in realizing an oscillation frequency that does not depend on the power supply voltage (see Patent Document 3), but when the resistance R1 depends on temperature, There is a drawback that it is difficult to suppress oscillation frequency fluctuations. When R1 in FIG. 1 is integrated in, for example, a chip, it is practically difficult to reduce the temperature dependence of the resistor R1. In addition, when the resistance and capacitance values fluctuate due to manufacturing variations, the oscillation frequency also fluctuates. That is, the circuit of FIG. 1 has a problem that the oscillation frequency fluctuates when the resistance and capacitance values fluctuate due to manufacturing variations, and the oscillation frequency fluctuates when the resistance value changes due to temperature fluctuations. It was.

  In the circuit of FIG. 3, the temperature dependence of the resistance is offset by the temperature dependence of the built-in reference voltage designed in advance, and bias potentials PB and NB that charge and discharge C1 and C2 with a constant current are generated, and the temperature of the oscillation frequency Aims to improve variability. However, a circuit for generating bias potentials NB and PB for charging and discharging C1 and C2 with a constant current is required. Further, in order to make the signal amplitude of the node ND4 constant regardless of the power supply voltage and temperature, it is necessary to supply VBGR, and a circuit for generating this VBGR potential is also required.

  One purpose of using the built-in (on-chip) CR oscillation circuit is in applications that frequently stop and start the oscillation circuit. By using a CR oscillation circuit with a short startup time, the waiting time when starting the oscillation circuit Is to reduce the power consumption during the waiting time. The second purpose is to eliminate the need for a ceramic resonator connected to the outside of the chip, and to reduce the number of pins and component costs.

  From the viewpoint of achieving the first object, the CR oscillation circuit using a complicated bias circuit such as the circuit of FIG. 3 has a longer start-up time of the oscillation circuit by the time required for stabilization of the bias circuit. In addition, there is a problem that the power consumption of the bias circuit itself is large. That is, although the purpose is to reduce power consumption, there is a problem that power consumption increases due to an increase in power consumption and an increase in start-up time in the complex bias circuit itself.

  In the circuit of FIG. 4, since the oscillation frequency can be changed by using the resistor R1 of the circuit of FIG. 1 as a variable resistor, a special bias circuit is not necessary, and the problem of an increase in current in the bias circuit can be avoided. However, the circuit of FIG. 4 has the following problems.

  For example, an allowable value of manufacturing variation of the capacitance value is set to ± 20%, for example, with respect to the center value, and an allowable value of manufacturing variation of the resistance value is set to, for example, ± 20% with respect to the center value. In this case, the value of the CR time constant composed of a certain fixed resistance and capacitance is 0.64 times at the minimum and 1.44 times at the maximum with respect to the center value. In other words, the oscillation frequency of an oscillation circuit composed of a certain fixed resistor and capacitor is 0.69 times at the minimum with respect to the design center and varies by 1.56 times at the maximum.

  Patent Document 4 discloses a method of adjusting the oscillation frequency of a CR oscillation circuit using a quartz crystal circuit for a watch. In principle, the resistance value is variable as in the circuit of FIG. 4, and the oscillation frequency of the higher frequency CR oscillation circuit is adjusted based on a low-power-consumption reference oscillation circuit (for example, the above-mentioned crystal oscillation circuit). it can. However, the resistance used in the built-in CR oscillation circuit generally has a temperature dependency of, for example, about ± 5%.

  It is assumed that the temperature fluctuation of the built-in resistor is, for example, about ± 5% between the low temperature side and the high temperature side with respect to room temperature. In this case, the value of the CR time constant composed of a fixed resistance and capacitance when temperature fluctuation, capacitance value manufacturing variation, and resistance value manufacturing variation are taken into consideration is 0. 608 times, up to 1.512 times. That is, the oscillation frequency of an oscillation circuit composed of a certain fixed resistor and capacitor varies by a minimum of 0.661 times and a maximum of 1.64 times with respect to the design center.

  In order to adjust the actual frequency to, for example, about ± 1% with respect to the desired target frequency, the adjustment increment of the CR time constant must be sufficiently small. The CR time constant value composed of a certain fixed resistance and capacitance is 0.608 times as small as the center value due to manufacturing variations in capacitance values, manufacturing variations in resistance values, and temperature changes in resistance values. Consider a case where the maximum fluctuation is 1.512 times. At this time, for example, if only the resistance value is adjusted as shown in FIG. 4, in order to adjust the oscillation frequency to the design center value, the resistance value of the resistor constituted by R2, R3, R4, and R5 in FIG. Can be changed from 0.661 times to 1.64 times with respect to the design center. Also, the resolution of the resistance adjustment must be about 1%.

  That is, the resistance value of the resistor composed of R2, R3, R4, and R5 in FIG. 4 must be changed from 0.66 to 1.64 in increments of 0.01 with the center value being 1.00. . In order to be able to change from 0.66 to 1.64 in 0.01 steps, the total number of steps (number of steps) is about 100. That is, unless the resistance value of the circuit of FIG. 4 is changed with a resolution of about 7 bits, the frequency cannot be adjusted so as to be within a range of about ± 1% from the desired target frequency.

  In the circuit of FIG. 4, if the circuit is configured so that the resistance value composed of R2 to R5 can be changed with, for example, 7-bit resolution, 127 pairs of PMOS and NMOS (transfer gates) are required. The circuit scale becomes very large. The junction capacitance of 127 sets of transfer gates becomes the parasitic capacitance of ND3. Also in the connection nodes (nodes such as NDR2R3 and NDR3R4) of the respective resistors, the junction capacitance of the transfer gate that functions as a switch becomes a parasitic capacitance. For this reason, when the resolution of the resistance adjustment is increased, the parasitic capacitance of the circuit portion constituting the CR time constant increases exponentially.

  As described above, in the circuit of FIG. 4, if the resolution of the resistance adjustment is increased (for example, about 7 bits) so that it can be set within a range of, for example, about ± 1% from the desired target frequency, the circuit scale becomes very large. There is a problem of growing. Further, when the resolution of the resistance adjustment is increased (for example, about 7 bits), the parasitic capacitance of the circuit portion constituting the CR time constant increases exponentially, making it difficult to oscillate at a high frequency. is there.

  In view of the above, a CR oscillation circuit that solves the problem of fluctuations in oscillation frequency due to manufacturing variations in resistors and capacitors and temperature changes in resistors is desired.

  In addition, a CR oscillation circuit that does not increase current consumption of the entire circuit by adding a bias circuit or the like for improving fluctuations in oscillation frequency is desired. In addition, by increasing the resolution of resistance adjustment, the circuit scale becomes very large, and the parasitic capacitance of the circuit part that constitutes the CR time constant increases exponentially, making it difficult to oscillate at high frequencies. Such a circuit is desired.

  The CR oscillation circuit has a first resistance fine adjustment in which a positive power supply and a first output terminal are coupled by a plurality of current paths via a plurality of first PMOS transistors and a plurality of first resistors. A second resistance fine adjustment circuit coupled between the circuit and the negative power supply and the second output terminal through a plurality of first NMOS transistors and a plurality of second resistors through a plurality of current paths; The first output terminal and the third output terminal are coupled by a plurality of current paths via a plurality of second PMOS transistors and a plurality of third resistors, and the second output terminal And a third resistor and a third resistor and a resistor coarse adjustment circuit coupled through a plurality of current paths via a plurality of third resistors and a plurality of second NMOS transistors, The resistance value interposed between the third output terminal and the negative power supply and the third output terminal And adjusting the oscillation frequency by adjusting the anti-value variable.

  According to at least one embodiment of the present invention, it is possible to solve the problem that the oscillation frequency fluctuates due to manufacturing variations of resistors and capacitors and temperature changes of resistors. Further, by hierarchizing the resistance value adjustment mechanism, an increase in circuit scale can be suppressed even if the resolution of the resistance value adjustment is increased. As a result, a CR oscillation circuit having a realistic circuit scale and high adjustment resolution can be realized. Further, since the total number of elements for frequency adjustment can be reduced, the parasitic capacitance of the circuit can be reduced, and oscillation can be performed at a higher frequency. In addition, since a complicated bias circuit is not used in this configuration, the problem of an increase in startup time can be avoided and the problem of an increase in current consumption in the bias circuit can be avoided.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 7 is a diagram showing a variable resistance circuit portion of an embodiment of the CR oscillation circuit. In FIG. 7, PMn (n is an integer) is a PMOS transistor, NMn (n is an integer) is an NMOS transistor, Vdd is a positive power supply (eg 3V), and GND is a negative power supply (eg ground potential 0V). , NDn (n is an alphanumeric character) indicates a node inside the oscillation circuit. NAn (n is an integer) is a NAND circuit, NOn (n is an integer) is a NOR circuit, RFn (n is an integer) is a resistance of a fine adjustment circuit, and RCn (n is an integer) is a resistance of a coarse adjustment circuit. , IV3 indicates an inverter, and IV3O indicates an output of the inverter IV3. Further, SELLn (n is an integer) and SELLnX (n is an integer) are fine adjustment circuit selection signals, SELUn (n is an integer) and SELUnX (n is an integer) are coarse adjustment circuit selection signals, and CTUNE1 is a coarse adjustment. The circuit is shown. FTUNEP1 is a fine adjustment circuit on the PMOS side, FTUNEN1 is a fine adjustment circuit on the NMOS side, PS is a coupling node between the PMOS side fine adjustment circuit and the coarse adjustment circuit, and NS is a coarse adjustment circuit with the NMOS side fine adjustment circuit. The connection node to the circuit is shown.

  The first resistance fine adjustment circuit FTUNEP1, which is a PMOS fine adjustment circuit, is connected between the positive power supply Vdd and the first output terminal PS, and a plurality of first PMOS transistors PM12 to PM15 and a plurality of first PMOS transistors PM12 to PM15. Are coupled by a plurality of current paths through the resistors RF1 to RF3. The second resistance fine adjustment circuit FTUNEN1, which is a fine adjustment circuit on the NMOS side, includes a plurality of first NMOS transistors NM12 to NM15 and a plurality of second NMOSs between the negative power supply GND and the second output terminal NS. The resistors RF4 to RF6 are coupled through a plurality of current paths. The coarse resistance adjustment circuit CTUNE1 includes a plurality of second PMOS transistors PM8 to PM11 and a plurality of third resistors RC1 to RC4 between the first output terminal PS and the third output terminal ND4. Couple in current path. The coarse resistance adjustment circuit CTUNE1 is further connected between the second output terminal NS and the third output terminal ND4 via the plurality of third resistors RC1 to RC4 and the plurality of second NMOS transistors NM8 to NM11. Couple with multiple current paths. The resistance values (10R) of the third resistors RC1 to RC4 are larger than the resistance values (R) of the first resistors RF1 to RF3 and the resistance values (R) of the second resistors RF4 to RF6. With this configuration, the resistance value interposed between the positive power supply Vdd and the third output terminal ND4 and the resistance value interposed between the negative power supply GND and the third output terminal ND4 are variably adjusted. be able to.

  More specifically, in the first resistance fine adjustment circuit FTUNEP1, a plurality of first resistors RF1 to RF3 are connected in series. The drains of the first PMOS transistors PM12 to PM15 are connected to a node (NDRF1, NDRF1RF2, NDRF2RF3, PS) at one end of each first resistor. Further, the sources of the plurality of first PMOS transistors PM12 to PM15 are connected to the positive power supply Vdd. By making one of the plurality of first PMOS transistors PM12 to PM15 conductive by selection signals SELL1X to SELL4X designated from an external decoder or the like, the positive power supply Vdd and the first output terminal PS Determine the resistance value between.

  In the second resistance fine adjustment circuit FTUNEN1, a plurality of second resistors RF4 to RF6 are connected in series. The drains of the first NMOS transistors NM12 to NM15 are connected to nodes (NDRF4, NDRF4RF5, NDRF5RF6, NS) at one end of the second resistors RF4 to RF6. Further, the sources of the plurality of first NMOS transistors NM12 to NM15 are connected to the negative power supply GND. By making one of the plurality of first NMOS transistors NM12 to NM15 conductive by selection signals SELL1 to SELL4 designated from an external decoder or the like, the negative power supply GND and the second output terminal NS Determine the resistance value between.

  In the coarse resistance adjustment circuit CTUNE1, a plurality of third resistors RC1 to RC4 are connected in series. The drains of the second PMOS transistors PM8 to PM11 and the drains of the second NMOS transistors NM8 to NM11 are connected to nodes (NDRC1, NDRC1RC2, NDRC2RC3, and NDRC3RC4) of one end of the third resistors RC1 to RC4. . Further, the sources of the plurality of second PMOS transistors PM8 to PM11 are connected to the first output terminal PS, and the sources of the plurality of second NMOS transistors NM8 to NM11 are connected to the second output terminal NS. The resistance value between the first output terminal PS and the third output terminal ND4 is determined by turning on one of the plurality of second PMOS transistors PM8 to PM11. Selection of the conduction transistor at this time is performed by setting one of selection signals SELU1 to SELU4 designated by an external decoder or the like to HIGH when the output of the inverter IV3 is HIGH. In addition, the resistance value between the second output terminal NS and the third output terminal ND4 is determined by turning on one of the plurality of second NMOS transistors NM8 to NM11. Selection of the conduction transistor at this time is performed by setting one of selection signals SELU1X to SELU4X designated by an external decoder or the like to LOW when the output of the inverter IV3 is LOW.

  The circuit in FIG. 7 replaces the inverter IV3 and the resistor R1 in the CR oscillation circuit in FIG. By replacing the inverter IV3 and the resistor R1 with the circuit of FIG. 7, the oscillation frequency can be variably adjusted by making the resistance value one of the resistance value and the capacitance value that determine the oscillation frequency variable.

  Specifically, as shown in FIG. 1, such a CR oscillation circuit capable of adjusting the oscillation frequency receives a first inverter IV1 having a first node ND1 as an output terminal and a first node ND1 as inputs. And a second inverter IV2 having an end and a second node ND2 as an output end. The CR oscillation circuit further includes a third inverter IV3 having the second node ND2 as an input terminal and a third node ND3 as an output terminal, a fourth node ND4 serving as an input terminal of the first inverter IV1, and a third node ND4. And a capacitive element C1 connecting the two nodes ND2. Here, the resistance adjustment circuit including the first fine resistance adjustment circuit FTUNEP1, the second fine resistance adjustment circuit FTUNEN1, and the coarse resistance adjustment circuit CTUNE1 shown in FIG. 7 includes the third node ND3 and the fourth node. Provided with ND4. The third output terminal ND4 shown in FIG. 7 receives an input from the third node ND3 on the gate sides of the plurality of second PMOS transistors PM8 to PM11 and the gate sides of the plurality of second NMOS transistors NM8 to NM11. 1 is connected to the fourth node ND4 shown in FIG.

  In the resistance adjustment circuit, the plurality of NAND circuits NA1 to NA4 drive the gates of the plurality of second PMOS transistors PM8 to PM11, respectively. The plurality of NOR circuits NO1 to NO4 drive the gates of the plurality of second NMOS transistors NM8 to NM11, respectively. The signal IV3O of the third node ND3 is input as a common signal to one of the two inputs of the plurality of NAND circuits NA1 to NA4 and the plurality of NOR circuits NO1 to NO4. Selection signals SELU1 to SELU4 designated from the outside are supplied to the other inputs of the NAND circuits NA1 to NA4. Further, select signals SELU1X to SELU4X designated from the outside are supplied to the other inputs of the NOR circuits NO1 to NO4.

  The features of the circuit of FIG. 7 will be described below. In the conventional circuit of FIG. 4, it has been explained as a problem of the conventional circuit that the circuit scale increases when the resolution of the resistance adjustment is increased. In addition, the conventional circuit of FIG. 4 has the following problems.

  In the circuit of FIG. 4, when the switches MOS, PM4 to PM6, and NM4 to NM6 are all OFF, the resistance value of the resistor becomes R2 + R3 + R4 + R5 (the resistance values of R2, R3, R4, and R5 are also R2, R3, R4, R5). On the other hand, the resistance when PM4 and NM4 are ON and the remaining switch MOSs are OFF is RMOS + R3 + R4 + R5 (the ON resistance of PM4 and NM4 is represented by RMOS). The resistance when PM5 and NM5 are ON and the remaining switch MOSs are OFF is RMOS + R4 + R5. The resistance when PM6 and NM6 are ON and the remaining switch MOSs are OFF is RMOS + R5.

  In other words, a difference corresponding to the ON resistance of the switch MOS is generated in addition to the resistance being switched between when the resistance value is maximum and other times. For this reason, if the change amount of the resistance value is made constant, the resistance values of R2 and R3 cannot be made the same, and the design must be made in consideration of the ON resistance of the switch MOS, resulting in a complicated design. is there.

  FIG. 5 is a diagram showing a modification of the circuit of FIG. The circuit of FIG. 5 is obtained by improving only the variable resistance portion of FIG. The difference between the circuit of FIG. 5 and the circuit of FIG. 4 is only NM7 and PM7, so the operation of this part will be described. In FIG. 5, elements having the same functions as those of the circuit of FIG. 4 and corresponding nodes are denoted by the same reference numerals, and redundant description is omitted. A symbol R attached to R2 to R5 indicates that the resistance value is R, for example.

  By connecting NM7 with Vdd applied to the gate and PM7 with GND potential applied to the gate in series with R2, the selectable resistance values are RMOS + R2 + R3 + R4 + R5, RMOS + R3 + R4 + R5, RMOS + R4 + R5, and RMOS + R5. By improving the circuit of FIG. 4 as shown in FIG. 5, the problem that the step of the resistance to be switched is affected by the ON resistance of the MOS can be avoided. However, the resistance of the variable resistance circuit is the sum of the resistances R2 to R5 and the resistance of the switch MOS. That is, the conventional circuit of FIG. 4 and the circuit of FIG. 5 have a problem that the ON resistance of the switch MOS is added in addition to the problem that the circuit scale increases when the resolution is increased. As one of the circuits for solving the problems shown in FIGS. 4 and 5, a circuit configuration as shown in FIG. 6 can be adopted.

  FIG. 6 is a diagram illustrating an example of a variable resistance circuit that replaces IV3 and R1 in FIG. In FIG. 6, PMn (n is an integer) is a PMOS transistor, NMn (n is an integer) is an NMOS transistor, Vdd is a positive power supply (for example, 3 V), GND is a GND potential (0 V), and NDn (n is an integer). Alphanumeric characters indicate nodes inside the oscillation circuit. NAn (n is an integer) is a NAND circuit, NOn (n is an integer) is a NOR circuit, Rn (n is an integer) is a resistor, IV3 is an inverter, and IV3O is an output of the inverter IV3. SELn (n is an integer) and SELnX (n is an integer) indicate selection signals. A symbol R attached to R2 to R5 indicates that the resistance value is R, for example. In FIG. 6, elements having the same functions as the circuits of FIGS. 1, 3, 4, 5, etc. and corresponding nodes are denoted by the same reference numerals.

  Control is performed so that only one of SEL1 to SEL4 becomes H and only a signal complementary to SEL1X to SEL4X becomes L. For example, when SEL1 is H, SEL2 to SEL4 are L, SEL1X is L, and SEL2X to SEL4X are H, if ND2 is H, only PM8 is turned ON. The variable resistance is R2 + R3 + R4 + R5. At this time, PM9 to PM11 and NM8 to NM11 are OFF.

  In order to change the resistance value, it is only necessary to change the signal set to H among SEL1 to SEL4. SEL1 to SEL4 and SEL1X to SEL4X can be generated by a decoder circuit. For example, when SEL3 is H, SEL3X is L, SEL1, SEL2, and SEL4 are L, and SEL1X, SEL2X, and SEL4X are H, PM10 and NM10 are selected as drive transistors. When ND2 is H, only PM10 is ON, and when ND2 is L, only NM10 is ON. At this time, the resistance of the variable resistance circuit of FIG. 6 is R4 + R5.

  By adopting the circuit configuration as shown in FIG. 6, it is possible to avoid the problem of the circuit shown in FIG. 5, that is, the problem that the ON resistance of the switch MOS is added as the resistance of the variable resistance circuit. The PM8, NM8, PM9, NM9, PM10, NM10, PM11, and NM11 in FIG. 6 that drive the node at one end of the resistor are the MOSs whose sources are connected to the power supply, similar to IV3 in FIG. Is advantageous in that the series resistance is small compared to the configuration of FIG.

  The circuit of FIG. 6 has an advantage that the ON resistance of the switch MOS is not added as the resistance of the variable resistance circuit compared to the circuit of FIG. 5, but the resistance adjustment resolution is reduced as in the circuits of FIGS. The problem that the circuit scale increases exponentially when the value is increased has not been solved. In the resistance adjustment circuit shown in FIG. 7 described above, a hierarchical resistance adjustment function is realized, and the circuit scale is reduced.

  In the coarse adjustment circuit CTUNE1 shown in FIG. 7, reference numeral 10R attached to RC1 to RC4 indicates that the resistance value of these resistors is 10R, for example. Since the circuit configuration of CTUNE1 is almost the same as the circuit of FIG. 6, the ON resistance of the switch MOS is not connected in series as compared to the circuits of FIGS. 4 and 5 as in the circuit of FIG. It can be said that there is.

  Control is performed so that only one of SELU1 to SELU4 becomes H and only a signal complementary to SELU1X to SELU4X becomes L. For example, when SELU1 is H, SELU2 to SELU4 are L, SELU1X is L, and SELU2X to SELU4X are H, if ND2 is L, only PM8 is turned ON. The variable resistance is RC1 + RC2 + RC3 + RC4. At this time, PM9 to PM11 and NM8 to NM11 are OFF.

  In order to change the resistance value, it is only necessary to change the signal of H among SELU1 to SELU4. SELU1 to SELU4 and SELU1X to SELU4X can be generated in the decoder circuit. For example, when SELU2 is H, SELU2X is L, SELU1, SELU3, and SELU4 are L, and SELU1X, SELU3X, and SELU4X are H, PM9 and NM9 are selected as drive transistors. When ND2 is L, only PM9 is ON, and when ND2 is H, only NM9 is ON. At this time, the resistance of the variable resistance circuit is RC2 + RC3 + RC4. By changing the resistance value using SELU1 to SELU4 and SELU1X to SELU4X, for example, in the example of FIG. 7, the resistance value can be selected from 10R, 20R, 30R, and 40R.

  The circuit of FIG. 6 differs from the circuit of FIG. 7 in that a fine adjustment circuit is prepared in addition to the resistance coarse adjustment circuit CTUNE1 in FIG. The operation of the resistance fine adjustment circuit FTUNEP1 will be described. SELL1X to SELL4X serve as selection signals for fine adjustment resistors. For example, when SELL1X is L and SELL2X to SELL4X are H, PM12 is ON, PM13, PM14, and PM15 are OFF, and the resistance of FTUNEP1 is RF1 + RF2 + RF3. When SELL2X is L, SELL1X, SELL3X, and SELL4X are H, PM13 is ON, PM12, PM14, and PM15 are OFF. The resistance of FTUNEP1 is RF2 + RF3. The resistance selected by PM12 to PM15 is connected to PS and supplied to the source of the PMOS of CTUNE1. By setting any one of SELL1X to SELL4X to L, the resistance connected to PS can select any one of 0, R, 2R, and 3R in the example of FIG.

  When ND2 is L, ND4 is H. The time constant at which ND4 changes from L to H is adjusted by the capacitance and the resistance of the circuit of FIG. For example, when SELL1X is L and SELL2X to SELL4X are H, PM12 is ON, PM13, PM14, and PM15 are OFF, and the resistance of FTUNEP1 is RF1 + RF2 + RF3. The resistance of FTUNEP1 is 3R. For example, when SELU1 is H, SELU2 to SELU4 are L, SELU1X is L, and SELU2X to SELU4X are H, if ND2 is L, only PM8 is turned ON. The variable resistance is RC1 + RC2 + RC3 + RC4. The resistance value of CTUNE1 is 40R. Since the 3R, which is the resistance value of FTUNEP1, is connected to the source of PM8 via PS, the total resistance value is 43R.

  In this way, the total resistance can be changed to 16 in the case of FIG. 7 by changing the resistance of the ancestor adjustment circuit CTUNE1 and the resistance of the fine adjustment circuit FTUNEP1, respectively. In the above description, the operation when ND2 is L has been described. When ND2 is H, the fine adjustment circuit FTUNEN1 on the NMOS side finely adjusts the value of the resistor connected to NS, so that The constant can be adjusted. At this time, by setting SELL1 to SELL4 and SELL1X to SELL4X as complementary signals, the resistance of the fine adjustment circuit connected to PS and the resistance of the fine adjustment circuit connected to NS can be set to the same value. it can.

  As in the circuit of FIG. 7, the circuit scale can be reduced by layering the resistance adjustment. In FIG. 7, for the sake of simplifying the drawing, a case of 2 bits for fine adjustment, 2 bits for coarse adjustment, and a total of 4 bits is shown. In the circuit of FIG. 4, 16 sets of MOS switches are required to achieve 16-bit resistance value adjustment in 4 bits. On the other hand, in the circuit of FIG. 7, the resistance value can be changed in 16 ways with 4 sets of MOS switches in the fine adjustment circuit, 4 sets of MOS switches in the coarse adjustment circuit, and 8 sets of MOS switches in total. FIG. 7 shows the case of 2 bits + 2 bits for the sake of simplicity. However, in order to realize the adjustment resolution of about 8 bits that is actually required, for example, the fine adjustment circuit is composed of 4 bits and coarse adjustment circuits. The adjustment circuit is 4 bits. In this case, the number of MOS switches in the fine adjustment circuit is 16, and the number of MOS switches in the coarse adjustment circuit is 16. The total number of switches is 32 sets. On the other hand, when the 8-bit adjustment resolution is realized by the circuit of FIG. 4, the number of necessary MOS switches is 256 sets.

  As shown in the circuit of FIG. 7, by providing a fine adjustment circuit on the power source side, that is, between PS and Vdd and between NS and GND, the potentials of PS and NS are made close to the power source potentials Vdd and GND, respectively. be able to. As a result, the voltage between the gate and source of the MOS transistor of the coarse adjustment circuit can be used as the largest potential, and the ON resistance of the MOS transistor is kept as small as possible, and the hierarchy by fine adjustment and coarse adjustment is realized. The advantage that it can be obtained.

  FIG. 8 is a diagram illustrating a circuit example of the CR oscillation circuit when the capacitance is variable. The circuit of FIG. 8 is shown to explain the features of the circuit of FIG. 7 in comparison with other circuits. In FIG. 8, PMn (n is an integer) is a PMOS transistor, NMn (n is an integer) is an NMOS transistor, GND is a GND potential (0V), NDn (n is an alphanumeric character) is a node inside the oscillation circuit, R1 Represents a resistance, and IVn (n is an integer) represents an inverter. Cn (n is an integer) indicates a capacity, and PM16G, NM16G, PM17G, and NM17G indicate gate signals of PM16, NM16, PM17, and NM17, respectively. In FIG. 8, elements having the same functions as those in the circuits of FIGS. 1, 3, 4, 5, 6 and the like and corresponding nodes are given the same reference numerals to indicate the corresponding relationship.

  In the conventional circuit of FIG. 4, the oscillation frequency is adjusted by adjusting the resistance value. On the other hand, in the circuit of FIG. 8, the oscillation frequency is adjusted by adjusting the capacitance value while keeping the resistance R1 constant.

  In other words, a circuit that adjusts the oscillation frequency by changing the capacitance value when the oscillation frequency deviates from the target frequency due to manufacturing variations in capacitance values, manufacturing variations in resistance values, or temperature changes in resistance values. It has a configuration. In FIG. 8, numerical values of 1 pF and 0.1 pF attached to C1 to C6 indicate examples of values of C1 to C6. When PM16G and PM17G are H, NM16G and NM17G are L, PM16, PM17, NM16 and NM17 are OFF. At this time, the capacity of ND4 is only C1 and C2. When PM16G is L, PM17G is H, NM16G is H, and NM17G is L, NM16 and PM16 are ON, NM17 and PM17 are OFF, so C3 and C4 are also connected to ND4 through PM16 and NM16. Since PM17 and NM17 are OFF, C5 and C6 are not connected to ND4. That is, when PM16G is L, PM17G is H, NM16G is H, and NM17G is L, the capacities of ND4 are C1, C2, C3, and C4.

When PM16G is set to L, PM17G is set to L, NM16G is set to H, and NM17G is set to H, NM16, PM16, NM17, and PM17 are turned on. Therefore, ND4 includes PM16, NM16.
, PM17, and NM17, C3, C4, C5, and C6 are also connected. That is, when PM16G is L, PM17G is L, NM16G is H, and NM17G is H, the capacities of ND4 are C1, C2, C3, C4, C5, and C6.

  As described above, by adopting a configuration such as the circuit of FIG. 8, it is possible to adjust the oscillation frequency by changing the capacitance value. However, the circuit configuration as shown in FIG. 8 has the following problems.

  For example, when both the capacitance value and the resistance value become smaller than the design values due to manufacturing variations in both the capacitance value and the resistance value, in the circuit of FIG. 8, PM16, NM16, PM17, and NM17 are turned on, and the capacitance value of the node ND4 To adjust the oscillation frequency to the target frequency. In FIG. 8, only two sets of the MOS switches PM16, NM16, PM17, and NM17 are shown for the sake of simplicity, but in an actual circuit, the number necessary for frequency adjustment is prepared. And

  When PM16, NM16, PM17, and NM17 are turned on, C3, C4, C5, and C6 are connected to the node ND4 in addition to C1 and C2. At this time, the drain and source junction capacitances of PM16, NM16, PM17, and NM17 are also connected to ND4. Furthermore, since PM16G and PM17G are L and NM16G and NM17G are H, the gate capacities of PM16, PM17, NM16 and NM17 are also connected to the node ND4. That is, in the circuit for adjusting the oscillation frequency by changing the capacitance value as shown in FIG. 8, in addition to the capacitance to be connected for adjustment, the gate capacitance of the MOS switch, the drain and source junction capacitance are connected to ND4. There is a problem that parasitic capacitance increases.

  On the other hand, in the circuit of FIG. 7, due to manufacturing variations in capacitance values and manufacturing variations in resistance values, even when both the capacitance value and the resistance value are smaller than the design value, parasitic capacitance is generated. Has an advantage that only the junction capacitance of the MOS switch is required. That is, as in the circuit of FIG. 7, the effect of the parasitic capacitance of the element for frequency adjustment can be minimized by switching the resistance instead of the capacitor to adjust the oscillation frequency.

  Before explaining the parasitic capacitance at the time of frequency adjustment in FIG. 7, the principle that the parasitic capacitance can be reduced with the simpler circuit of FIG. 6 will be explained. In the variable resistance circuit of FIG. 6, when both the capacitance value and the resistance value are smaller than the design value due to the manufacturing variation of the capacitance value and the manufacturing variation of the resistance value, by increasing the resistance value, Bring the oscillation frequency closer to the target frequency. For this purpose, for example, SEL1 is H, SEL1X is L, SEL2 to SEL4 are L, and SEL2X to SEL4X are H. When PM8 or NM8 is ON, PM9 to PM11, and NM9 to NM11 are OFF, the resistance value is maximized. Even in this case, the parasitic capacitance connected to R2, R3, R4, and R5 is only the junction capacitance of the drains of PM8 to PM11 and NM8 to NM11, and the junction capacitance on the source side is not connected to the resistor. This is the difference between the circuit of FIG. 6 and the circuit of FIG.

  Furthermore, even when the resistance value is set to the maximum, since PM9 to PM11 and NM9 to NM11 are OFF, no channel is formed, and the gate capacitances of these MOS transistors are not connected to the resistors. This is also different from the circuits of FIGS. That is, by adopting a circuit configuration for adjusting the resistance value as shown in FIG. 6, it is possible to realize an advantage that the source side junction capacitance and the gate capacitance of the unselected switch MOS do not become a parasitic capacitance. The coarse adjustment circuit CTUNE1 of the circuit of FIG. 7 also has an advantage that the gate capacitance of the unselected switch MOS does not become a parasitic capacitance because the resistance value is adjusted based on substantially the same configuration and principle as the circuit of FIG.

  FIG. 9 is a diagram showing a circuit when the conventional circuit of FIG. 4 is hierarchized like the circuit of FIG. Comparing the inventive circuit of FIGS. 9 and 7 makes the advantages of FIG. 7 more apparent as will be described below.

  In FIG. 9, PMn (n is an integer) is a PMOS transistor, NMn (n is an integer) is an NMOS transistor, Vdd is a positive power supply (for example, 3V), GND is a GND potential (0V), NDn (n is an integer). Alphanumeric characters indicate nodes inside the oscillation circuit. RFn (n is an integer) is the resistance of the fine adjustment circuit, RCn (n is an integer) is the resistance of the coarse adjustment circuit, IVn (n is an integer) is the inverter, and NMnG (n is an integer) is the gate of the NMOS transistor. The signal, PMnG (n is an integer), indicates the gate signal of the PMOS transistor. In FIG. 9, elements having the same functions as the circuits of FIGS. 1, 3, 4, 5, 6, and the like and corresponding nodes are given the same reference numerals to indicate the correspondence. Symbols R and 10R attached to each resistor indicate examples of the respective resistance values.

  The MOS switch composed of NM20, NM21, NM22, NM23, PM20, PM21, PM22, and PM23 in FIG. 9 functions as a circuit for finely adjusting the resistance value by switching between RF11, RF12, and RF13. Further, the MOS switch composed of NM24, NM25, NM26, NM27, PM24, PM25, PM26, and PM27 functions as a coarse adjustment circuit for coarsely adjusting the resistance value by switching RC11, RC12, RC13, and RC14. Since the method of switching the resistance value and the total resistance value switched are apparent from the description of FIGS. 4, 5, and 7, detailed description of the operation is omitted.

  For example, a circuit configuration in which the conventional circuit of FIG. 4 is modified and hierarchized as shown in FIG. 9 is possible. Although it is possible to adjust the oscillation frequency by adjusting the resistance value by adopting the circuit of FIG. 9, the number of MOS transistors connected in series is the circuit of the invention of FIG. 7 as compared with the circuit of FIG. It can be seen that there is one more. For this reason, there is a problem that the influence of the ON resistance of the MOS switch is large.

  9 is compared with the coupling portion of the coarse adjustment circuit and the fine adjustment circuit in FIG. 7, the coupling portion NDRF13 of the coarse adjustment circuit and the fine adjustment circuit in FIG. This circuit corresponds to the nodes PS and NS. That is, in the circuit of FIG. 7, the PMOS side fine adjustment circuit and the NMOS side fine adjustment circuit are prepared independently, so that the parasitic capacitance of this part is halved compared to the circuit of FIG. Has been reduced.

  In the circuit of FIG. 7, the junction of the MOS transistor serving as the parasitic capacitance of the node PS is the drain of PM15, the source of PM8, the source of PM9, the source of PM10, and the source junction of PM11. A total of five junction capacitances become parasitic capacitances. On the other hand, in the circuit of FIG. 9, the junction of the MOS transistor that becomes the parasitic capacitance of the node NDRF13 is the junction of NM23, PM23, NM24, PM24, NM25, PM25, NM26, PM26, NM27, PM27. A total of 10 junction capacitances become parasitic capacitances. Similarly, for the node NS, a total of five junction capacitances are NS parasitic capacitances.

  As described above, in the circuit of FIG. 7, the fine adjustment circuit is provided on each of the PMOS side and the NMOS side, thereby realizing the feature that the parasitic capacitance of the coupling node of the fine adjustment circuit and the coarse adjustment circuit can be reduced. . Thereby, compared with the conventional circuit of FIG. 4, the parasitic capacitance is reduced, and oscillation at a higher frequency is possible.

  FIG. 10 is a diagram illustrating an example of the relationship between the oscillation frequency of the circuit of FIG. 7 and the set value of the adjustment bit. A total of 8 bits are used, 4 bits for setting the fine adjustment circuit and 4 bits for adjustment of the coarse adjustment circuit. The 8-bit set value is shown on the horizontal axis, and the oscillation period is shown on the vertical axis. An example of operation when the oscillation frequency is adjusted to 2 MHz (the cycle is 500 ns) is shown. The value on the horizontal axis represents an 8-bit set value with 4 bits for coarse adjustment as the upper level and 4 bits for fine adjustment as the lower level. The setting that minimizes the number of selected resistors is 0, and the setting that maximizes the number of selected resistors is 256.

  As the resistance of the fine adjustment circuit in FIG. 7, 16 resistance values can be selected from 0Ω to 15 kΩ (in the center value at the time of manufacture) in 1 kΩ increments. Also, as the resistance of the coarse adjustment circuit, the circuit can be selected from 16 types of resistances of 58 kΩ, 63 kΩ, 68 kΩ, 74 kΩ, 79 kΩ, 86 kΩ, 93 kΩ, 100 kΩ, 108 kΩ, 117 kΩ, 126 kΩ, 136 kΩ, 147 kΩ, 159 kΩ, 172 kΩ, 172 kΩ, 186 kΩ. Configured. The difference between these resistors is the resistance value of the resistor corresponding to RC1 to RC3 in FIG. Further, the minimum resistance of 58 kΩ is the resistance value of the resistance corresponding to RC4 in FIG. The capacitances C1 and C2 were 1.23 pF, and the relationship between the period and the set bit was obtained by simulation.

  The range of fluctuation of the value due to the manufacturing variation of the resistor is 0.8 to 1.2 times the central value, and the width of the variation of the value due to the manufacturing variation of the capacitance is 0.8 to 1.2 times the central value. The circuit constant is set so that the oscillation frequency can be adjusted to the target frequency (target cycle) within the range. The resistance value of the coarse adjustment circuit CTUNE1 was selected so as to be approximately a geometric sequence. The resistance value of the fine adjustment circuit is assumed to be an equidistant sequence for simplicity.

  FIG. 10 shows a case where the capacitance and the resistance are 1.2 times larger than the manufacturing center value (C = 1.2, R = 1.2), and 1.0 times (C = 1). 0.0, R = 1.0) and 0.8 times (C = 0.8, R = 0.8). In these three cases, the lower 4 bits are shown when the lower 4 bits are fixed to 0 and changed in 16 ways by coarse adjustment, and the lower 4 bits corresponding to the fine adjustment circuit in the vicinity of the cycle 500 ns Represents the value of the period obtained when V is also changed.

  When the capacitance and resistance are 1.2 times larger than the center value, 1.0 times, and 0.8 times, the setting values are different, but the target period of 500 ns is achieved. It can be seen that there are setting values that can be set. When the capacitance and resistance become 1.2 times as large as the center value, the set value may be reduced so as to reduce the number of resistors to be selected. In the case of 1.0 times, the vicinity of the center may be used as the set value. When it is 0.8 times, the set value may be increased so as to increase the number of resistors to be selected. Thus, by selecting an approximate resistance value with the coarse adjustment circuit and further finely adjusting the resistance with the fine adjustment circuit, the oscillation frequency of the CR oscillation circuit can be brought close to the target frequency (in this example, 500 ns).

  As described above, the circuit of FIG. 7 can realize a circuit with a large frequency adjustment resolution by reducing the circuit scale. Further, it is possible to provide a circuit that oscillates at a higher frequency by reducing parasitic capacitance as compared with the conventional circuit. Since a complicated bias circuit is not used, the problem of current increase in the bias circuit can be avoided.

  FIG. 11 is a diagram illustrating a modification of the resistance adjustment circuit. In FIG. 11, PMn (n is an integer) is a PMOS transistor, NMn (n is an integer) is an NMOS transistor, GND is a GND potential (0 V), and NDn (n is an alphanumeric character) is a node inside the oscillation circuit. . NAn (n is an integer) is a NAND circuit, NOn (n is an integer) is a NOR circuit, RFn (n is an integer) is a resistance of a fine adjustment circuit, and RCn (n is an integer) is a resistance of a coarse adjustment circuit. , IV3 indicates an inverter, and IV3O indicates an output of the inverter IV3. Further, SELLn (n is an integer) indicates a selection signal for the fine adjustment circuit, and SELUn (n is an integer) indicates a selection signal for the coarse adjustment circuit. Further, CTUNE1 is a coarse adjustment circuit, FTUNEN11 to FTUNEN14 are NMOS fine adjustment circuits, PS1 to PS4 are coupling nodes between the PMOS fine adjustment circuit and the coarse adjustment circuit, and NS1 to NS4 are NMOS fine adjustment circuits. A node connected to the coarse adjustment circuit is shown. In FIG. 11, elements having the same functions as those of the circuit of FIG. 7 and the like and corresponding nodes are denoted by the same reference numerals. In addition, for convenience of illustration, a part of the illustration is omitted.

  Since the circuit of FIG. 11 operates in substantially the same manner as the circuit of FIG. 7, a detailed description thereof will be omitted, and differences from the circuit of FIG. 7 will be described.

  In the circuit of FIG. 7, the sources of the PMOS transistors of the coarse adjustment circuit are all the common node PS, and the fine adjustment circuit is connected to the node PS. On the other hand, in the circuit of FIG. 11, the sources of the PMOS, PM8, PM9, PM10, and PM11 of the coarse adjustment circuit are independent and are PS1, PS2, PS3, and PS4. In the circuit configuration example, independent fine adjustment circuits are connected to PS1, PS2, PS3, and PS4. In FIG. 11, the fine adjustment circuit on the PMOS side is omitted and not shown. Similarly, in the circuit of FIG. 11, the sources of NMOS, NM8, NM9, NM10, and NM11 are also independent nodes NS1, NS2, NS3, and NS4. An independent fine adjustment circuit can be connected to NS1, NS2, NS3, and NS4. FTUNEN 111 and FTUNEN 14 shown in the figure indicate this fine adjustment circuit. In FIG. 11, only the FTUNEN 11 connected to NS1 and the FTUNEN 14 connected to NS4 are shown for the sake of simplicity.

  As shown in FIG. 11, by connecting independent fine adjustment circuits to the sources of the PMOS and NMOS of the coarse adjustment circuit, the junction capacitances of PS1 to PS4 and NS1 to NS4 are further reduced compared to the circuit of FIG. can do. 7 and 11 show an example in which the selection bit of the fine adjustment circuit is 2 bits and the selection bit of the coarse adjustment circuit is 2 bits, the number of bits is limited to the exemplified number. It is not a thing and it is good also as arbitrary numbers as needed. When the configuration as shown in FIG. 11 is used, the number of fine adjustment circuits increases as compared to the circuit shown in FIG. In order to mitigate this increase in circuit scale and reduce parasitic capacitance, an intermediate configuration between the circuit configuration of FIG. 7 and the circuit configuration of FIG. 11 may be employed. In other words, in FIG. 11, independent fine adjustment circuits are not provided for all NS1 to NS4. For example, NS1 and NS2 are provided as a common node, one fine adjustment circuit is provided therein, and NS3 and NS4 are provided as different common nodes. For example, another fine adjustment circuit can be connected. The same applies to the PMOS side, and a separate fine adjustment circuit may be provided for each of PS1 to PS4, or two PMOS side fine adjustment circuits may be provided by dividing PS1 to PS4 into two groups. As described above, various changes can be made to the configurations of the fine adjustment circuit and the coarse adjustment circuit.

  FIG. 12 is a diagram illustrating another example of the configuration of the CR oscillation circuit. In FIG. 12, PMn (n is an integer) is a PMOS transistor, NMn (n is an integer) is an NMOS transistor, Vdd is a positive power supply (for example, 3 V), GND is a GND potential (0 V), NDn (n (Alphanumeric) indicates a node inside the oscillation circuit. NAn (n is an integer) is a NAND circuit, NOn (n is an integer) is a NOR circuit, RFn (n is an integer) is a resistance of a fine adjustment circuit, and RCn (n is an integer) is a resistance of a coarse adjustment circuit. . IV2 and IV3 are inverters, IV3O is an output of the inverter IV3, SELLn (n is an integer) is a selection signal for a fine adjustment circuit, and SELUn (n is an integer) is a selection signal for a coarse adjustment circuit. Further, CTUNE1 is a coarse adjustment circuit, FTUNEP1 is a PMOS fine adjustment circuit, FTUNEN1 is an NMOS fine adjustment circuit, PS is a coupling node between the PMOS fine adjustment circuit and the coarse adjustment circuit, and NS is an NMOS fine adjustment circuit. The coupling node of the adjustment circuit and the coarse adjustment circuit is shown. C1 and C2 are capacitors for determining the time constant of the CR oscillation circuit, and CB1 and CB2 are capacitors for biasing AMP1. AMP1 is an amplifier circuit (source self-bias amplifier) corresponding to IV1 of the circuits of FIGS. 1 and 4, PMA1 and NMA1 are PMOS transistors and NMOS transistors constituting AMP1, and RB1 and RB2 are resistors for biasing AMP1. Indicates. In FIG. 12, elements having the same functions as those of the circuit of FIG. 7 and the like and corresponding nodes are denoted by the same reference numerals. The numerical values attached to the resistance and the capacitance indicate numerical examples of the resistance and the capacitance.

  CTUNE1, FTUNEP1, and FTUNEN1 are partially omitted in order to simplify the drawing, but operate in the same manner as the circuit of FIG. 7 or FIG. The description of the operation of these parts is the same as the description of FIGS. 7 and 11, and will be omitted. Only the parts specific to the circuit of FIG. 12 will be described.

  In FIG. 1, FIG. 4, FIG. 7, and FIG. 11, the description has been made assuming that the circuit that amplifies the signal at the node ND4 of the oscillation circuit is the inverter IV1. The circuit of FIG. 12 is different in that IV1 is replaced with AMP1.

  As shown in the waveform diagram of FIG. 2D, the potential of ND4 is charged and discharged with a CR time constant, so that the period of the intermediate potential is long. The function of amplifying this ND4 signal and shaping it into a rectangular wave as shown in the ND1 waveform of FIG. 2 is required for IV1 of FIG.

  In the conventional circuit of FIG. 1, when the ND4 signal is in the vicinity of the logic threshold value of IV1, there are two contradictory demands: IV1 can sufficiently amplify the signal, and IVIV current consumption should be kept as small as possible. It was necessary to balance and design the size of IV1. That is, the mutual conductance gm, which is the ratio of the input potential change to the output current change, and the current flowing through IV1 cannot be designed independently in the conventional circuit of FIG. 1, and the ND4 signal is amplified at high speed. Therefore, when trying to output to ND1, the current in IV1 increases.

  In the circuit of FIG. 12, in order to improve this problem, IV1 is replaced with AMP1, gm of AMP1 (ratio of output current to input voltage when the potential of ND4 changes), bias current flowing through AMP1, and The circuit is configured so that can be selected independently. When the waveform of ND4 is amplified by the inverter IV1 in FIG. 1, if the current consumption is set to a certain value, the gm when the input signal is in the vicinity of the logic threshold value is substantially determined. This is because the source of the PMOS constituting the inverter is connected to Vdd, the source of NMOS is connected to GND, and the maximum current flows when the input is near the logic threshold. If an attempt is made to amplify the ND4 signal at high speed, the current flowing through IV1 also increases.

  On the other hand, in AMP1 of FIG. 12, the source potential of PMA1 is automatically set to a potential lower than Vdd by RB1 × average current due to the average current flowing through RB1. For this reason, even if the L (gate length, channel length) of the PMOS transistor is designed to be smaller than when the source is set to Vdd, an average current equivalent to that of the inverter IV1 having a larger L can be realized. it can. Similarly, on the NMOS side, L of NMA1 and the average current flowing through NMA1 can be designed independently. Since the source potential of NMA1 is higher than GND by the product of the average current flowing through NMA1 and the resistance value of RB2, the average current can be selected by appropriately selecting the value of RB2 even if NMA1 is designed to be small. Can be designed. CB1 and CB2 function as smoothing capacitors for keeping the current flowing through RB1 and RB2 constant.

  FIG. 13 is a diagram showing the effect of AMP1 in FIG. In FIG. 13, the current flowing through IV1 of the conventional circuit of FIG. 1 and the current flowing through AMP1 of FIG. 12 are shown, and the horizontal axis indicates time. For example, if the currents flowing when the input potentials of IV1 and AMP1 are close to the logic threshold are designed to be equal, there is a difference depending on the difference between L of IV1 and L of AMP1, but the output (ND1 and ND1 ′ ) Has the same value. For PMA1 and NMA1, the channel length L is designed to be small, and the source potential is, for example, 0.5 V lower than Vdd and 0.5 V higher than GND. Therefore, even when the same ND4 signal is amplified, the current flowing period is short in the case of AMP1 in FIG. Thereby, the effect of reducing the average current can be obtained while realizing the same gm as IV1 in FIG. A broken line in FIG. 13 indicates a current flowing through IV1 in FIG. The solid line in FIG. 13 indicates the current flowing through AMP1 in FIG. The shaded portion in FIG. 13 indicates the current (charge, product of current and time) that can be reduced by AMP1 in FIG.

  That is, by adopting the configuration of AMP1 as shown in FIG. 12 and using RB1, CB1, RB2, and CB2, the average current and the mutual conductance gm can be designed independently. As a result, the effect of current reduction can be obtained by minimizing the channel length (gate length) L of PMA1 and NMA1. By using such an amplifier circuit AMP1 in combination with the hierarchical resistance adjustment circuit as described with reference to FIGS. 7 and 11, it is possible to obtain an effect of further reducing power consumption.

  FIG. 14 is a diagram illustrating an example of a configuration of an oscillation circuit having a frequency adjustment function. 14, GND is a GND potential (0V), NDn (n is an alphanumeric character) is a node inside the oscillation circuit, RT1 is a variable resistance circuit shown in FIG. 7, for example, and IV1, IV2, IV3, and IVX1 are inverters Indicates. C1 and C2 are capacitors for determining the time constant of the CR oscillation circuit, and CX1 and CX2 are capacitances of the crystal oscillation circuit. RX1 is a resistance of the crystal oscillation circuit, and BUF1 and BUFX1 are buffer circuits. Further, CLKO is an oscillation output of the CR oscillation circuit, COUNT1 is a counter circuit, COUNT1O is a control signal based on the result of COUNT1, OSCX1 is a crystal oscillation circuit, and NDX0 and NDX1 are nodes of the crystal oscillation circuit. XTAL1 is a crystal resonator, and CKRTCO is an output of the crystal oscillation circuit. In FIG. 14, elements having the same functions as the circuits of FIGS. 1, 4, 7, etc. and corresponding nodes are denoted by the same reference numerals.

  In FIG. 14, the variable resistor RT1 is controlled by COUNT1O. In the description of the circuit of FIG. 7, it has been described that the oscillation frequency of the CR oscillation circuit including IV1, IV2, IV3, C1, and C2 can be adjusted by variably adjusting the resistance value by the circuit of FIG. The variable resistor in FIG. 7 corresponds to the variable resistor RT1 in FIG. FIG. 14 shows an example in which the ND2 signal of this oscillation circuit is supplied to the outside by the buffer circuit BUF1.

  One of the purposes of using the CR oscillation circuit is to apply to applications where frequency accuracy may be moderate, and where a short start-up time is desirable. Even in such an application, for example, in the case of a microcontroller (MCU) or the like, it is often the case that a crystal oscillator circuit for a watch is always operating. This is because a quartz crystal circuit for a watch often has an oscillation frequency as low as 32768 Hz and a steady consumption current as small as several μA. As described above, when the watch crystal oscillation circuit that can expect high frequency accuracy is operating, the oscillation frequency of the CR oscillation circuit is adjusted by combining the circuit of FIG. 7 and the watch crystal oscillation circuit. be able to.

  The circuit of FIG. 14 shows a circuit configuration example in such a case. An outline of the operation of the circuit of FIG. 14 will be briefly described. CLKO is the output of the CR oscillation circuit of FIG. CKRTCO is, for example, an output of 32768 Hz output from the crystal oscillation circuit OSCX1. Both are compared by the counter circuit COUNT1, and the frequency of CLKO can be adjusted. For example, since the period of 32768 Hz is 30.5 μsec, the frequency of CLKO can be known by multiplying the number of rises of CLKO during this 30.5 μsec period. For example, when CLKO is to be adjusted to 2 MHz, the rising edge of CLKO should be 61 times in a period of 30.5 μsec. By increasing the measurement period as necessary, the frequency measurement accuracy of CLKO can be increased. COUNT1O is generated based on this measurement result, and control is performed so that the value of RT1 approaches the target frequency. COUNT1O changes the resistance value of RT1 by changing the setting bit of FIG.

  With the circuit configuration as shown in FIG. 14, the oscillation frequency of the CR oscillation circuit can be dynamically adjusted as necessary. FIG. 14 shows an example in which the frequency of the CR oscillation circuit is adjusted based on the clock oscillation circuit output 32768 Hz. However, if the external clock input is selected as shown in FIG. The frequency of the CR oscillation circuit can be adjusted based on the external clock signal.

  FIG. 15 is a diagram showing a circuit example in which the COUNT1 portion of FIG. 14 is changed. In FIG. 15, CLKO indicates an oscillation output of the CR oscillation circuit, COUNT1 indicates a counter circuit, and COUNT1O indicates a control signal based on the result of COUNT1. CKRTCO represents an output of the crystal oscillation circuit, CKIN represents an arbitrary external clock input, SELCK represents a selector for selecting either CKRTCO or CKIN, and SELCKO represents an output of SELCK.

  In FIG. 15, elements having the same functions as those of the circuit of FIG. 14 and the like and corresponding nodes are denoted by the same reference numerals. In FIG. 15, COUNT1 and COUNT1O operate in the same manner as the circuit of FIG.

  In the circuit of FIG. 14, the method of measuring the frequency of CLKO based on the clock crystal oscillator circuit output CKRTCO has been described. As shown in FIG. 15, if the period used as the reference of COUNT1 is configured to be switched to the external clock CKIN by the selector SELCK, the frequency of the CR oscillation circuit output CLKO can be measured using CKIN as a reference. With such a configuration, for example, there is an advantage that the oscillation frequency of the CR oscillation circuit can be adjusted in accordance with the clock of another LSI to be communicated. If the absolute accuracy of the frequency of the communication partner's LSI clock is not sufficient, even if the frequency of the CR oscillation circuit is calibrated based on the clock for the crystal oscillation circuit OSCX1 in FIG. It is not always close. In such a case, it is preferable to adjust the frequency of the CR oscillation circuit based on the clock cycle of the other party rather than adjusting the frequency of the CR oscillation circuit based on a certain absolute value.

  As described above, the oscillation frequency of the CR oscillation circuit can be adjusted based on a desired reference clock by combining the configuration of the circuit of FIG. 14 or the circuit of FIG. 15 with the circuit of FIG. It becomes like this.

  As mentioned above, although this invention was demonstrated based on the Example, this invention is not limited to the said Example, A various deformation | transformation is possible within the range as described in a claim.

It is a figure which shows an example of a structure of a general CR oscillation circuit. It is a figure which shows the waveform of each part at the time of operation | movement of the circuit of FIG. It is a figure which shows another example of a structure of an oscillation circuit. It is a figure which shows another example of a structure of an oscillation circuit. It is a figure which shows the modification of the circuit of FIG. It is a figure which shows an example of the variable resistance circuit which replaces IV3 and R1 of FIG. It is a figure which shows the variable resistance circuit part of the Example of CR oscillation circuit. It is a figure which shows the circuit example of CR oscillation circuit when a capacity | capacitance is made variable. FIG. 8 is a diagram showing a circuit when the conventional circuit of FIG. 4 is hierarchized like the circuit of FIG. 7. It is a figure which shows an example of the relationship between the oscillation frequency of the circuit of FIG. 7, and the setting value of an adjustment bit. It is a figure which shows the modification of a resistance adjustment circuit. It is a figure which shows another example of a structure of CR oscillation circuit. It is a figure which shows the effect of the amplifier circuit of FIG. It is a figure which shows an example of a structure of the oscillation circuit which has a frequency adjustment function. It is a figure which shows the circuit example which changed the counter part of FIG.

Explanation of symbols

FTUNEP1 First resistance fine adjustment circuit Vdd Positive power supply PS First output terminals PM12 to PM15 First PMOS transistors RF1 to RF3 First resistor FTUNEN1 Second resistance fine adjustment circuit GND Negative power supply NS Second Output terminals NM12 to NM15 first NMOS transistors RF4 to RF6 second resistor CTUNE1 coarse resistance adjustment circuits PM8 to PM11 second PMOS transistors RC1 to RC4 third resistors NM8 to NM11 second NMOS transistors

Claims (5)

A first resistance fine-tuning circuit that couples a positive power supply and a first output terminal through a plurality of first PMOS transistors and a plurality of first resistors through a plurality of current paths;
A second resistance fine adjustment circuit that couples the negative power supply and the second output terminal via a plurality of first NMOS transistors and a plurality of second resistors through a plurality of current paths;
The first output terminal and the third output terminal are coupled by a plurality of current paths via a plurality of second PMOS transistors and a plurality of third resistors, and the second output terminal A coarse resistance adjustment circuit coupled between the third output terminal via a plurality of third resistors and a plurality of second NMOS transistors through a plurality of current paths, The oscillation frequency is adjusted by variably adjusting the resistance value interposed between the third output terminal and the resistance value interposed between the negative power supply and the third output terminal. CR oscillation circuit. In the first resistance fine adjustment circuit, the plurality of first resistors are connected in series, the drain of each first PMOS transistor is connected to a node at one end of each first resistor, and the plurality of first resistors are connected. The source of one PMOS transistor is connected to the power supply on the positive side, and one of the plurality of first PMOS transistors is turned on to connect the power supply on the positive side and the first output terminal. Determine the resistance value between
In the second resistance fine adjustment circuit, the plurality of second resistors are connected in series, the drain of each first NMOS transistor is connected to a node at one end of each second resistor, and the plurality of second resistors are connected. The source of one NMOS transistor is connected to the negative power supply, and one of the plurality of first NMOS transistors is turned on to connect the negative power supply and the second output terminal. Determine the resistance value between
In the coarse resistance adjustment circuit, the plurality of third resistors are connected in series, and the drain of each second PMOS transistor and the drain of each second NMOS transistor are connected to a node at one end of each third resistor. The sources of the plurality of second PMOS transistors are connected to the first output terminal, the sources of the plurality of second NMOS transistors are connected to the second output terminal, and the plurality of second PMOS transistors are connected to the second output terminal. A resistance value between the first output terminal and the third output terminal is determined by bringing one of the PMOS transistors into a conductive state, and one of the plurality of second NMOS transistors is determined. 2. The CR oscillation circuit according to claim 1, wherein a resistance value between the second output terminal and the third output terminal is determined by bringing the second output terminal into a conductive state.   2. The CR oscillation circuit according to claim 1, wherein a resistance value of the third resistor is larger than a resistance value of the first resistor and a resistance value of the second resistor. A first inverter having a first node as an output end;
A second inverter having the first node as an input terminal and the second node as an output terminal;
A third inverter having the second node as an input end and a third node as an output end;
A capacitance element connecting the fourth node as the input terminal of the first inverter and the second node; the first resistance fine adjustment circuit; and the second resistance fine adjustment circuit. And a resistance adjustment circuit including the rough resistance adjustment circuit are provided between the third node and the fourth node, and the gates of the plurality of second PMOS transistors and the plurality of second NMOSs 2. The CR oscillation circuit according to claim 1, wherein an input from the third node is received on a gate side of the transistor, and the third output terminal is connected to the fourth node. The resistance adjustment circuit is:
A plurality of NAND circuits respectively driving the gates of the plurality of second PMOS transistors;
A plurality of NOR circuits that respectively drive the gates of the plurality of second NMOS transistors, and a signal of the third node is input as a common signal to the plurality of NAND circuits and the plurality of NOR circuits. The CR oscillation circuit according to claim 4.

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