CN103325422B - SRAM sequence testing circuit and method of testing - Google Patents

SRAM sequence testing circuit and method of testing Download PDF

Info

Publication number
CN103325422B
CN103325422B CN201310303166.6A CN201310303166A CN103325422B CN 103325422 B CN103325422 B CN 103325422B CN 201310303166 A CN201310303166 A CN 201310303166A CN 103325422 B CN103325422 B CN 103325422B
Authority
CN
China
Prior art keywords
circuit
input
output terminal
sram
signal
Prior art date
Application number
CN201310303166.6A
Other languages
Chinese (zh)
Other versions
CN103325422A (en
Inventor
王林
Original Assignee
苏州兆芯半导体科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 苏州兆芯半导体科技有限公司 filed Critical 苏州兆芯半导体科技有限公司
Priority to CN201310303166.6A priority Critical patent/CN103325422B/en
Publication of CN103325422A publication Critical patent/CN103325422A/en
Application granted granted Critical
Publication of CN103325422B publication Critical patent/CN103325422B/en

Links

Abstract

Present invention is disclosed a kind of SRAM sequence testing circuit and method of testing, described test circuit comprises SRAM memory cell and test circuit unit, described test circuit unit comprises the first mode commutation circuit be connected with described SRAM memory cell, the edge signal trigger circuit be connected with described first mode commutation circuit, the second mode switching circuit be connected with described edge signal trigger circuit.First mode commutation circuit has the first Enable Pin, second mode switching circuit has the second Enable Pin, control different according to the first Enable Pin with the signal of the second Enable Pin, the first annular oscillation circuit and the second annular oscillation circuit can be formed respectively in test circuit, by measuring the output oscillation period of two annular oscillation circuits, thus accurately obtain the time value that SRAM memory cell reads data.The present invention completes by auto-placement tool, has that measuring error is little, precision is high, measure simple advantage.

Description

SRAM sequence testing circuit and method of testing
Technical field
The present invention relates to the element circuit field of static RAM (SRAM), especially relate to a kind of sequence testing circuit that the timing indicator parameter of SRAM is tested and method of testing.
Background technology
After semiconductor technology enters deep sub-micron era, under chip can be operated in the frequency of hundreds of MHz or upper GHz, the frequency of operation of the SRAM of its inside is likely higher.But in chip testing, due to the impact of packaging and testing board, the clock signal that external testing provides often can only reach tens or at the most 100 frequencies of MHz.
Under foregoing background, the test of chip is now generally a large amount of depends on built-in self-test (BIST) circuit, and the advantage of BIST circuit is not only the robotization of test, and because does not need the test access through outside, so can realize high speed test.The BIST circuit of SRAM is also called memory built in self test of sram (MBIST) circuit, and its inside comprises test signal generation circuit and SRAM output judges comparator circuit.MBIST circuit is tested SRAM under the control of chip internal high-frequency clock, if test is correct, not only proves that SRAM function is correct, also represent that the SRAM clock period can not be greater than test clock cycle, like this, the external world can obtain the test data of SRAM clock period.But except the SRAM clock period, it is also the important timing indicator parameter of SRAM that SRAM data reads the time (be called for short Tcq), and by traditional MBIST circuit, this parameter cannot be measured and obtain.
The Tcq now measuring SRAM generally adopts circuit shown in Fig. 1, comprise the input end that two road gate IM0, the delay circuit ID0 with a plurality of delay unit, multi-channel gating device IM1, the first phase inverter I0 and the second phase inverter I1 and the D-latch ID1 for sampling, the clock synchronous input signal CK of SRAM and read data output signal DO are connected respectively to two road gate IM0 and D-latch ID1.This circuit by the time delay between measuring-signal CK and the clock signal C K_DFF of D-latch ID1, thus measures the data read time Tcq obtaining SRAM.Shown in composition graphs 2, concrete measuring principle is: when the enable signal OSCE of two road gates is logical zero, signal CK is through two road gate IM0, delay circuit ID0, signal OSC_OUT is become after multi-channel gating device IM1 and the first phase inverter I0, the clock signal C K_DFF of D-latch is converted to again after the phase-modulation of the second phase inverter, different delay units is selected by the enable signal Delay_Sel of multi-channel gating device, the waveform that during measurement, circuit produces as shown in Figure 2, play output signal DO from the rising edge of measuring-signal CK in figure to export time of data and be the SRAM that will measure and read data time Tcq, after often selecting a delay unit, enable signal OSCE is set to logical one, make two road gate IM0, selected delay unit, multi-channel gating device IM1 and the first phase inverter I0 forms an annular oscillation circuit, annular oscillation circuit output waveform as shown in Figure 3, measure the oscillation frequency obtaining the output signal OSC_OUT of annular oscillation circuit, obtain the time delay of signal CK to signal CK_DFF, D-latch ID1 measures until can be latched into correct data, now measure the Tcq that namely time delay obtained equals SRAM.
But the shortcoming that this circuit exists is: (1) relates to more manual layout design, expend time in more, efficiency is lower, as the precision for ensureing Tcq measurement, delay circuit ID0 needs manual completing, otherwise the circuit layout generated due to automatic placement and routing's instrument postpones to have very large uncertainty, and the precision causing Tcq to measure is uncontrollable; (2) precision of Tcq measurement is lower, as measured Tcq failure by delay cell Delay1, and measure Tcq success by delay cell Delay2, so Tcq is just between the time delay and the time delay of Delay2 of Delay1, and measuring error is minimum is the difference of two time delays; (3) measure the process of Tcq comparatively loaded down with trivial details, need constantly to adjust Delay_Sel until the output data of correct latch SRAM.And every bar time-delay access all will form separately annular oscillation circuit measures its frequency to obtain each time delay, when needing higher measuring accuracy, often place a large amount of time-delay access, to ensure that time-delay access had both covered larger reference time delay, cover as far as possible many time delay dot interlaces again.
Summary of the invention
The object of the invention is to the defect overcoming prior art, a kind of SRAM sequence testing circuit and method of testing are provided, by measuring the output oscillation period of two annular oscillation circuits in test circuit, accurately obtaining the time value that SRAM memory cell reads data.
For achieving the above object, the present invention proposes following technical scheme: a kind of SRAM sequence testing circuit, comprise SRAM memory cell and test circuit unit, described SRAM memory cell comprises address signal input end, clock signal input terminal and reading data signal output terminal, and described test circuit unit comprises:
First mode commutation circuit, input end is connected with described reading data signal output terminal;
Edge signal trigger circuit, input end is connected with the output terminal of described first mode commutation circuit;
Second mode switching circuit, input end is connected with the output terminal of described edge signal trigger circuit, output terminal is connected with described clock signal input terminal;
Described first mode commutation circuit has the first Enable Pin, and described second mode switching circuit has the second Enable Pin.
Preferably, when the first Enable Pin controls first mode commutation circuit access reading data signal output terminal, when second Enable Pin controls the second mode switching circuit access edge signal trigger circuit output terminal, described SRAM memory cell, first mode commutation circuit, edge signal trigger circuit and the second mode switching circuit form the first annular oscillation circuit;
When the first Enable Pin control first mode commutation circuit accesses the output terminal of the second mode switching circuit, described first mode commutation circuit, edge signal trigger circuit and the second mode switching circuit form the second annular oscillation circuit.
Described first mode commutation circuit adopts two road gates, wherein an input end is connected with the reading data signal output terminal of described SRAM by the first Sheffer stroke gate, another input end is connected with the output terminal of described second mode switching circuit, and output terminal is connected with the input end of described edge signal trigger circuit by the first phase inverter.
Described edge signal trigger circuit comprise delay unit, the second phase inverter, the second Sheffer stroke gate and same or door, described delay unit input end is connected with described first inverter output, described second inverter input is connected with described delay unit output terminal, wherein an input end is connected with the output terminal of described second phase inverter described second Sheffer stroke gate, another input end is connected with described first Enable Pin, described with or door wherein an input end is connected with the output terminal of described second Sheffer stroke gate, another input end is connected with described delay unit input end.
Described second mode switching circuit adopts two road gates, wherein an input end through the 3rd phase inverter with described with or door output terminal is connected, another input end inputs external testing input clock signal, output terminal is connected with the clock signal input terminal of described SRAM.
Described test circuit unit also comprises:
Address production electric circuit, input end is connected with described edge signal trigger circuit output terminal;
3rd mode switching circuit, input end is connected with described address production electric circuit output terminal, output terminal is connected with described address signal input end.
Described address production electric circuit adopts clock synchronization circuit, and its Enable Pin is the second Enable Pin.
Described 3rd mode switching circuit adopts two road gates, and another input termination external address input signal, its Enable Pin is the second Enable Pin.
Another object of the present invention is also based on SRAM sequence testing circuit, discloses a kind of SRAM time sequence test method, comprises the following steps:
Step one, first Enable Pin controls first mode commutation circuit access reading data signal output terminal, second Enable Pin controls the second mode switching circuit access edge signal trigger circuit output terminal, is measured the output oscillation period of described first annular oscillation circuit by external testing instrument;
Step 2, the first Enable Pin controls the output terminal that first mode commutation circuit accesses the second mode switching circuit, is measured the output oscillation period of described second annular oscillation circuit by external testing instrument.
Step 3, by measuring the output oscillation period of two annular oscillation circuits obtained, calculates the data read time of SRAM memory cell.
Preferably, before output oscillation period of measurement first annular oscillation circuit, trigger SRAM memory cell by external schema and carry out primary address reading, the address value of reading remains on described reading data signal output terminal.
Triggered by external schema and comprise: the second Enable Pin controls the second mode switching circuit input external testing input clock signal, the 3rd mode switching circuit input external address input signal respectively, and described external testing input clock signal triggers SRAM memory cell and reads outside address input signal.
Beneficial effect of the present invention is: the measured value of (1) Tcq is obtained by output value oscillation period of two annular oscillation circuits, and the measurement of circuit layout form on Tcq does not affect, and can be completed by auto-placement tool completely, efficiency is high; (2) error is little, measures accurately high; (3) measurement simply, easily realizes, and compared with prior art, saves the time that adjustment selected by a large amount of delay circuit.
Accompanying drawing explanation
Fig. 1 is the SRAM sequence testing circuit principle schematic of prior art;
Fig. 2 is the waveform schematic diagram of Fig. 1 circuit when carrying out Tcq and measuring;
Fig. 3 is the output waveform schematic diagram of the annular oscillation circuit formed in Fig. 1;
Fig. 4 is the principle schematic of SRAM sequence testing circuit of the present invention;
Fig. 5 is the waveform schematic diagram of Fig. 4 circuit when carrying out Tcq and measuring;
Fig. 6 is the output waveform schematic diagram of the second annular oscillation circuit formed in Fig. 4 circuit;
Fig. 7 is the schematic flow sheet of SRAM time sequence test method of the present invention.
Embodiment
Below in conjunction with accompanying drawing of the present invention, clear, complete description is carried out to the technical scheme of the embodiment of the present invention.
Disclosed a kind of SRAM sequence testing circuit, by forming two annular oscillation circuits, measure the output oscillation period of two annular oscillation circuits respectively, thus accurately obtain the time value that SRAM memory cell reads data, to overcome, the measuring accuracy existed in existing Tcq measuring method is low, process is loaded down with trivial details, it is many to expend time in, inefficient problem.
As shown in Figure 4, disclosed a kind of SRAM sequence testing circuit comprises: SRAM memory cell I10, first mode commutation circuit I5, edge signal trigger circuit, second mode switching circuit I8, address production electric circuit I9 and the 3rd mode switching circuit I11, described SRAM memory cell I10 is the effective clock synchronization circuit of rising edge clock, comprise signal input part and signal output part, described signal input part comprises clock signal input terminal, write enable signal input end, address signal input end, write data signal input end, described clock signal input terminal is used for input clock synchronizing signal CK, the rising edge of signal CK triggers the operation that SRAM memory cell I10 once reads or writes, described write enable signal input end is used for the effective write enable signal WEB of input low level, and definition high level is logical one, and low level is logical zero, namely when the signal WEB inputted is logical zero, triggers SRAM memory cell I10 and carries out write operation, described address signal input end is connected with the output terminal of described 3rd mode switching circuit I11, for inputting the address date produced by external schema or address production electric circuit I9, write data signal input part is used for after SRAM memory cell I10 is triggered by signal WEB, and data input signal D1 is write in input, data is write in SRAM memory cell I10, the signal output part of described SRAM memory cell I10 comprises reading data signal output terminal, and for exporting read data output signal DO, the data read by SRAM memory cell I10 export.
In preferred embodiment of the present invention, described first mode commutation circuit I5 selects has two input ends, two road gates of an output terminal and the first Enable Pin, one of them input end is connected with the reading data signal output terminal of described SRAM memory cell I10 by the first Sheffer stroke gate I6, another input end is connected with the output terminal of described second mode switching circuit I8, described first Enable Pin is used for incoming control signal OSCE, for controlling the output of first mode commutation circuit I5, namely when signal OSCE is logical zero, first mode commutation circuit I5 exports the logical inverse of read data output signal DO, when signal OSCE is logical one, first mode commutation circuit I5 output signal then selects the output signal of the second mode switching circuit I8.
In preferred embodiment of the present invention, described edge signal trigger circuit comprise delay unit I3, second phase inverter I2, second Sheffer stroke gate I1 and same or door I0, the output terminal of described first mode commutation circuit I5 through the first phase inverter I4 respectively with the input end of described delay unit I3, a wherein input end that is same or door I0 is connected, the input signal defining described edge signal trigger circuit is NODEO, the i.e. output signal of first mode commutation circuit I5 after the first phase inverter I4, the output terminal of described delay unit I3 is connected with a wherein input end of described second Sheffer stroke gate I1 through the second phase inverter I2, another input end incoming control signal of described second Sheffer stroke gate I1 OSCE, the i.e. control signal of described edge signal trigger circuit, when signal OSCE is logical zero, the logic change of described edge signal trigger circuit to input signal NODEO responds, as long as namely signal NODEO occur once from logical one to logical zero or logical zero to the saltus step of logical one, then edge signal trigger circuit export the low pulse that a logic is " 0 ", pulse width was determined by the time delay of delay unit I3, when signal OSCE is logical one, described delay unit I3, the second phase inverter I2 and the second Sheffer stroke gate I1 locking, the output signal of described edge signal trigger circuit will be always the logical inverse of input signal NODE0.Described another input end that is same or door I0 is connected with the output terminal of described second Sheffer stroke gate I1.
Certainly, the edge signal trigger circuit in the present invention can be replaced by other forms of circuit, as long as replacement circuit can complete the identical work of the edge signal trigger circuit in the present invention.
In preferred embodiment of the present invention, described second mode switching circuit I8 selects equally has two input ends, two road gates of an output terminal and the second Enable Pin, for selecting the clock input signal exporting SRAM, described output terminal that is same or door I0 is connected with a wherein input end of described second mode switching circuit I8 through the 3rd phase inverter I7, another input end access external testing input clock signal CK_EXT of described second mode switching circuit I8, output terminal is connected with the clock signal input terminal of described SRAM, Enable Pin access signal MD_EX, for selecting the clock input signal of SRAM, namely when signal MD_EX is logical zero, the clock signal input terminal of SRAM inputs logical inverse that is same or door I0 output signal, when signal MD_EX is logical one, the clock signal input terminal input external testing input clock signal CK_EXT of SRAM.Signal MD_EX is also the enable signal of address production electric circuit I9 and the 3rd mode switching circuit I11 simultaneously, and the Enable Pin of both accesses respectively.
In preferred embodiment of the present invention, described address production electric circuit I9 selects the effective clock synchronization circuit of rising edge, its input end output terminal that is same with described or door I0 is connected, output terminal is connected with a wherein input end of described 3rd mode switching circuit, controlled by signal MD_EX, and trigger OPADD by the rising edge of the output signal OSC_OUT of edge signal trigger circuit.Certainly, address production electric circuit I9 in the present invention can be replaced by any form, the address production electric circuit that meets arbitrary address width S RAM, as long as the address that address production electric circuit produces can realize the measurement that SRAM of the present invention reads data time, namely can be the present invention and adopted.
In preferred embodiment of the present invention, described 3rd mode switching circuit I11 selects the two road gates with two input ends, an output terminal and the 3rd Enable Pin equally, its another input end access external address input signal A_EXT, output terminal is connected with the address signal input end of described SRAM.When enable signal MD_EX is logical zero, the address signal that the address signal input end input of described SRAM is exported by address production electric circuit I9; When the second enable signal MD_EX is logical one, the address signal input end input external address input signal A_EXT of described SRAM.
When the second enable signal MD_EX and the first enable signal OSCE is logical zero, described SRAM memory cell I10, first mode commutation circuit I5, edge signal trigger circuit and the second mode switching circuit I8 form the first annular oscillation circuit; When described first enable signal OSCE is logical one, described first mode commutation circuit I5, the first phase inverter I4, with or door I0, the 3rd phase inverter I7 and the second mode switching circuit I8 form the second annular oscillation circuit.
The present invention is based on SRAM sequence testing circuit, further disclose a kind of SRAM time sequence test method, for measuring the reading data time Tcq of SRAM.Here only comprise two address location AddrH and AddrL for SRAM, describe the method for testing of SRAM sequence testing circuit, shown in composition graphs 7, comprise the following steps:
The first step, trigger SRAM memory cell by external schema and carry out primary address reading, the address value of reading remains on the read data output terminal of described SRAM.
Write enable signal WEB is set to logical zero, and trigger SRAM memory cell and write data to address location, write logical one at address location AddrH, address location AddrL writes logical zero.When signal MD_EX is set to logical one, control the second mode switching circuit I8 and the 3rd mode switching circuit I11 and export external timing signal CK_EXT and external address input signal A_EXT respectively, the rising edge of external timing signal CK_EXT triggers SRAM memory cell to the digital independent in address location AddrL one time, the output data of such SRAM memory cell I10 are logical zero, from the characteristic of SRAM output interface, the data that its output signal DO once will read before maintenance before upper once SRAM read operation occurs.
Second step, first Enable Pin controls first mode commutation circuit access reading data signal output terminal, second Enable Pin controls the second mode switching circuit access edge signal trigger circuit output terminal, is measured the output oscillation period of described first annular oscillation circuit by external testing instrument.
Write enable signal WEB is set to logical one, when the second Enable Pin signal MD_EX is converted to logical zero by logical one, address production electric circuit I9 OPADD AddrH, therefore the address signal input end A of SRAM is by receiver address AddrH, the logic transition of the second Enable Pin MD_EX causes input signal NODEO and occurs by the transformation of logical one to logical zero, after edge signal trigger circuit sense the logic change of input end signal NODEO, it is " 0 " low pulse that signal OSC_OUT exports a logic, the negative edge of low pulse is after the 3rd phase inverter I7 and the second mode switching circuit I8, the clock signal C K triggering SRAM jumps to logical one by logical zero, trigger a SRAM to the read operation of address AddrH, therefore SRAM output signal DO will become logical one from logical zero, at the rising edge of low pulse, cause the OPADD of address production electric circuit I9 to change, be namely changed to address AddrL by address AddrH.
The change that the output signal of SRAM becomes logical one from logical zero can cause the change of signal NODE0 simultaneously, signal NODE0 is as the input signal of edge signal trigger circuit, it changes and then causes edge signal trigger circuit on signal OSC_OUT, again export a low pulse, the output of address production electric circuit I9 is again reverted to AddrH by current low pulse after triggering SRAM is to the read operation of AddrL, therefore, as long as the second enable signal MD_EX is maintained " 0 ", first enable signal OSCE is maintained " 1 ", SRAM just will constantly read the data in address location AddrH and address location AddrL repeatedly, and a low pulses generation is just had at set intervals on signal OSC_OUT.
Shown in composition graphs 5 oscillogram, for the oscillogram that test circuit produces when measuring Tcq, it is the clock period of clock signal C K from the last rising edge of clock signal C K to a rear rising edge, be the reading time of SRAM memory cell to address input data, be defined as Tx, but this time have passed through first mode commutation circuit I5 successively, first phase inverter, with or door I0, the delay of the 3rd phase inverter I7 and the second mode switching circuit I8, so want to obtain accurate SRAM to read data time Tcq, just need to deduct to output to from signal D0 the time delay producing new signal CK rising edge, be defined as Tosc.As can be seen from the oscillogram shown in Fig. 5, Tcq is the difference of Tx and Tcq, as long as so measure the value of Tx and Tcq, just can obtain the exact value of Tcq.When measuring Tx, the second enable signal MD_EX and the first enable signal OSCE is all set to logical zero, by the oscillation period of the output signal OSC_OUT of external testing instrument ranging pulse signal trigger, obtains Tx.
3rd step, the first Enable Pin controls the output terminal that first mode commutation circuit accesses the second mode switching circuit, is measured the output oscillation period of described second annular oscillation circuit by external testing instrument.
First enable signal OSCE is set to logical one, now first mode commutation circuit I5, the first phase inverter I4, with or door I0, the 3rd phase inverter I7 and the second mode switching circuit I8 form the second annular oscillation circuit, signal OSC_OUT output waveform as shown in Figure 6, measure the oscillation period of the output signal OSC_OUT of the second annular oscillation circuit, can obtain outputting to from signal D0 the time delay producing new signal CK rising edge, be defined as Ty, from annular oscillation circuit principle, Tosc=Ty/2.
4th step, by measuring the output oscillation period of two annular oscillation circuits obtained, calculates the data read time of SRAM memory cell.
By formula Tcq=Tx-Tosc, can measure and obtain SRAM reading data cycle T cq.
SRAM memory cell in the present invention can be the SRAM of arbitrary address width, arbitrarily input and output bit wide, and is not limited only to the above-mentioned SRAM memory cell only having two address locations and an input and output position.
Technology contents of the present invention and technical characteristic have disclosed as above; but those of ordinary skill in the art still may do all replacement and the modification that do not deviate from spirit of the present invention based on teaching of the present invention and announcement; therefore; scope should be not limited to the content that embodiment discloses; and various do not deviate from replacement of the present invention and modification should be comprised, and contained by present patent application claim.

Claims (10)

1.SRAM sequence testing circuit, comprises SRAM memory cell and test circuit unit, and described SRAM memory cell comprises address signal input end, clock signal input terminal and reading data signal output terminal, it is characterized in that, described test circuit unit comprises:
First mode commutation circuit, input end is connected with described reading data signal output terminal;
Edge signal trigger circuit, input end is connected with the output terminal of described first mode commutation circuit;
Second mode switching circuit, input end is connected with the output terminal of described edge signal trigger circuit, output terminal is connected with described clock signal input terminal;
Described first mode commutation circuit has the first Enable Pin, and described second mode switching circuit has the second Enable Pin;
When the first Enable Pin controls first mode commutation circuit access reading data signal output terminal, when second Enable Pin controls the second mode switching circuit access edge signal trigger circuit output terminal, described SRAM memory cell, first mode commutation circuit, edge signal trigger circuit and the second mode switching circuit form the first annular oscillation circuit;
When the first Enable Pin control first mode commutation circuit accesses the output terminal of the second mode switching circuit, described first mode commutation circuit, edge signal trigger circuit and the second mode switching circuit form the second annular oscillation circuit.
2. SRAM sequence testing circuit according to claim 1, it is characterized in that, described first mode commutation circuit adopts two road gates, wherein an input end is connected with described reading data signal output terminal by the first Sheffer stroke gate, another input end is connected with the output terminal of described second mode switching circuit, and output terminal is connected with the input end of described edge signal trigger circuit by the first phase inverter.
3. SRAM sequence testing circuit according to claim 2, it is characterized in that, described edge signal trigger circuit comprise delay unit, second phase inverter, second Sheffer stroke gate and same or door, described delay unit input end is connected with described first inverter output, described second inverter input is connected with described delay unit output terminal, a described second Sheffer stroke gate wherein input end is connected with the output terminal of described second phase inverter, another input end is connected with described first Enable Pin, described with or door wherein an input end be connected with the output terminal of described second Sheffer stroke gate, another input end is connected with described delay unit input end.
4. SRAM sequence testing circuit according to claim 3, it is characterized in that, described second mode switching circuit adopts two road gates, wherein an input end through the 3rd phase inverter with described with or door output terminal is connected, another input end inputs external testing input clock signal, output terminal is connected with described clock signal input terminal.
5. SRAM sequence testing circuit according to claim 3, is characterized in that, described test circuit unit also comprises:
Address production electric circuit, input end is connected with described edge signal trigger circuit output terminal;
3rd mode switching circuit, input end is connected with described address production electric circuit output terminal, output terminal is connected with described address signal input end.
6. SRAM sequence testing circuit according to claim 5, is characterized in that, described address production electric circuit adopts clock synchronization circuit, and its Enable Pin is the second Enable Pin.
7. SRAM sequence testing circuit according to claim 5, is characterized in that, described 3rd mode switching circuit adopts two road gates, and another input termination external address input signal, its Enable Pin is the second Enable Pin.
8. the SRAM time sequence test method of SRAM sequence testing circuit according to claim 1, is characterized in that, comprise the following steps:
Step one, first Enable Pin controls first mode commutation circuit access reading data signal output terminal, second Enable Pin controls the second mode switching circuit access edge signal trigger circuit output terminal, is measured the output oscillation period of described first annular oscillation circuit by external testing instrument;
Step 2, the first Enable Pin controls the output terminal that first mode commutation circuit accesses the second mode switching circuit, is measured the output oscillation period of described second annular oscillation circuit by external testing instrument;
Step 3, by measuring the output oscillation period of two annular oscillation circuits obtained, calculates the data read time of SRAM memory cell.
9. SRAM time sequence test method according to claim 8, it is characterized in that, before output oscillation period of measurement first annular oscillation circuit, trigger SRAM memory cell by external schema and carry out primary address reading, the address value of reading remains on described reading data signal output terminal.
10. SRAM time sequence test method according to claim 9, it is characterized in that, triggered by external schema and comprise: the second Enable Pin controls the second mode switching circuit input external testing input clock signal, the 3rd mode switching circuit input external address input signal respectively, and described external testing input clock signal triggers SRAM memory cell and reads outside address input signal.
CN201310303166.6A 2013-07-17 2013-07-17 SRAM sequence testing circuit and method of testing CN103325422B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201310303166.6A CN103325422B (en) 2013-07-17 2013-07-17 SRAM sequence testing circuit and method of testing

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201310303166.6A CN103325422B (en) 2013-07-17 2013-07-17 SRAM sequence testing circuit and method of testing

Publications (2)

Publication Number Publication Date
CN103325422A CN103325422A (en) 2013-09-25
CN103325422B true CN103325422B (en) 2016-03-23

Family

ID=49194114

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201310303166.6A CN103325422B (en) 2013-07-17 2013-07-17 SRAM sequence testing circuit and method of testing

Country Status (1)

Country Link
CN (1) CN103325422B (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106158044B (en) * 2015-04-17 2019-06-18 中芯国际集成电路制造(上海)有限公司 The test circuit and test method of SRAM access time
CN107293329A (en) * 2016-03-30 2017-10-24 中芯国际集成电路制造(上海)有限公司 A kind of access time measuring circuit
CN106155857B (en) * 2016-07-13 2018-06-22 无锡中微亿芯有限公司 The storage unit read-write detecting system and method for FPGA electrification reset processes
CN106782669B (en) * 2016-11-23 2020-04-10 上海华力微电子有限公司 Self-calibration extensible SRAM delay test circuit
CN107068192B (en) * 2017-03-31 2020-02-07 上海华虹宏力半导体制造有限公司 Local clock signal generation circuit for timing measurement of memory
CN109994144B (en) * 2019-04-23 2020-05-26 江苏科大亨芯半导体技术有限公司 SRAM output path time sequence test circuit and test method
CN110047551B (en) * 2019-04-23 2020-05-22 江苏科大亨芯半导体技术有限公司 SRAM input path time sequence test circuit and test method

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5502678A (en) * 1994-09-30 1996-03-26 Sgs-Thomson Microelectronics, Inc. Full memory chip long write test mode
CN1662996A (en) * 2002-06-25 2005-08-31 富士通株式会社 Semiconductor memory

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5013394B2 (en) * 2005-09-13 2012-08-29 ルネサスエレクトロニクス株式会社 Semiconductor integrated circuit device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5502678A (en) * 1994-09-30 1996-03-26 Sgs-Thomson Microelectronics, Inc. Full memory chip long write test mode
CN1662996A (en) * 2002-06-25 2005-08-31 富士通株式会社 Semiconductor memory

Also Published As

Publication number Publication date
CN103325422A (en) 2013-09-25

Similar Documents

Publication Publication Date Title
US9128153B2 (en) Micro-granular delay testing of configurable ICs
US9257164B2 (en) Circuits and methods for DQS autogating
US7368931B2 (en) On-chip self test circuit and self test method for signal distortion
US8229683B2 (en) Test circuit for bias temperature instability recovery measurements
CA2695373C (en) Circuit device and method of measuring clock jitter
CN103258561B (en) The data output timing control circuit of semiconductor device
US7149903B1 (en) System and method for signal delay in an adaptive voltage scaling slack detector
US8164966B2 (en) Variable-loop-path ring oscillator test circuit and systems and methods utilizing same
EP1416354B1 (en) Programmable frequency multiplier
JP4307445B2 (en) Integrated circuit device having test circuit for measuring AC characteristic of built-in memory macro
CN105445653B (en) Integrated circuit with low power scan trigger
CN101363900B (en) Method for testing FPGA device
CN101273559B (en) Strobe technique for time stamping a digital signal
US7613972B2 (en) Semiconductor integrated circuit, and designing method and testing method thereof
CN102778673B (en) Radar return signal high-precision distance simulation method and device as well as target simulator
CN102073033B (en) Method for generating high-precision stepping delay capable of dynamic calibration
CN202121568U (en) Time-digital converter
US7439724B2 (en) On-chip jitter measurement circuit
US20060002239A1 (en) Precise time measurement apparatus and method
US6452459B1 (en) Circuit for measuring signal delays of synchronous memory elements
JP5023539B2 (en) Semiconductor device and signal processing method
US9711189B1 (en) On-die input reference voltage with self-calibrating duty cycle correction
US6144262A (en) Circuit for measuring signal delays of asynchronous register inputs
CN1375830A (en) Semiconductor storage apparatus
CN103257569B (en) Time measuring circuit, method and system

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant