CN110047551B

CN110047551B - SRAM input path time sequence test circuit and test method

Info

Publication number: CN110047551B
Application number: CN201910328774.XA
Authority: CN
Inventors: 朱建银; 张吉利; 周俊; 林福江; 马建强
Original assignee: Jiangsu Keda Hengxin Semiconductor Technology Co ltd
Current assignee: Jiangsu Keda Hengxin Semiconductor Technology Co ltd
Priority date: 2019-04-23
Filing date: 2019-04-23
Publication date: 2020-05-22
Anticipated expiration: 2039-04-23
Also published as: CN110047551A

Abstract

The invention discloses a sequential test circuit and a test method for an SRAM input path, wherein the sequential test circuit for the SRAM input path comprises an induction DFF, induction logic, a TDF control circuit, an SRAM to be tested, an input two-way selector MUX, a clock control module and an EDA tool; the TDF control circuit comprises a monitoring circuit, an initialization circuit, an SRAM read-write control circuit, an input MUX switching control circuit and a comparison circuit, wherein the input side DFF and the SRAM read-write control circuit of the SRAM are connected with the input end of the SRAM through an input two-way selector MUX, and the input MUX switching control circuit is connected with the input two-way selector MUX; an induction logic is arranged between the input side DFF and the induction DFF of the SRAM to be tested, and the input side DFF and the induction DFF of the SRAM to be tested are connected in series to form a scan chain. The SRAM input path time sequence test circuit and the method can test the TDF of the input path of the SRAM and ensure the reliability of a chip.

Description

SRAM input path time sequence test circuit and test method

Technical Field

The invention relates to the technical field of SRAM (static random access memory) testing, in particular to an input path time sequence testing circuit and a testing method.

Background

In digital circuits, Static Random Access Memories (SRAMs) are widely used, and the area ratio of SRAMs in some chips is very high. Therefore, how to eliminate the chips with SRAM manufacturing defects is an important issue for mass production test. The built-in self-built test circuit technology (BIST) is a common high-speed test means, and realizes the high-speed automatic test of the SRAM by matching a special test circuit on the periphery of the SRAM circuit. The BIST can Test whether the basic functions in the SRAM are normal, the defect is that whether manufacturing defects exist on the input path from the input to the SRAM cannot be tested, and both Stack-At-fault (SAF) and Test-Delay-fault (TDF) cannot be tested. Still other testing techniques such as SCAN test can only test SAF and cannot measure TDF.

Disclosure of Invention

In view of the deficiencies of the prior art, it is an object of the present invention to provide a SRAM input path timing test circuit. The technical scheme is as follows:

a SRAM input path time sequence test system comprises an inducing DFF, a TDF control circuit, an SRAM to be tested, an input two-way selector MUX, a clock control module and an EDA tool;

the TDF control circuit comprises an initialization circuit, a monitoring circuit, an SRAM read-write control circuit, an input MUX switching control circuit and a comparison circuit, wherein the input side DFF and the SRAM read-write control circuit of the SRAM are connected with the input end of the SRAM through an input two-way selector MUX, and the input MUX switching control circuit is connected with the input two-way selector MUX;

an induction logic is arranged between the input side DFF and the induction DFF of the SRAM to be tested, the input side DFF and the induction DFF of the SRAM to be tested are connected in series to form a scan chain, the induction logic is used for enabling an input signal of the SRAM to be tested to generate a normal read-write command, and the monitoring circuit is connected with the input side DFF;

the EDA tool is used for generating a Scan enable signal Scan enable and a test pattern, the clock control module OCC is used for generating a test clock, the shift clock is used for inputting the test pattern into a Scan chain and outputting a test result from the Scan chain, and two function clock pulses are needed for executing a time sequence test;

in the input period, the Scan enable signal Scan enable is 1, and after the input is completed, the Scan enable signal Scan enable is 0, and after the clock control module OCC generates two consecutive function clock pulses, the Scan enable signal Scan enable is 1.

The second objective of the present invention is to provide a method for testing the timing sequence of the input path of the SRAM, which is applied to the test circuit. Which comprises the following steps:

the monitoring circuit detects the rising edge of the second function clock pulse, and detects whether the input signal of the SRAM to be detected is a read-write SRAM command;

when the input signal of the SRAM to be detected is a command for writing the SRAM, the SRAM represents that a numerical value is written in the SRAM to be detected, and the detection circuit records the first numerical value and the address of the first numerical value;

the input MUX switching control circuit switches the input two-way selector MUX to the SRAM read-write control circuit;

the monitoring circuit sends the written first value to the comparison circuit and informs the SRAM read-write control circuit to read the first value from the SRAM to be tested;

the comparison circuit compares the detected first value with the value read out from the SRAM to be tested, and if not equal, the SRAM to be tested is defective.

As a further improvement of the present invention, the comparing circuit compares the written first value with the value read from the SRAM to be tested, and if not equal, it indicates that the SRAM to be tested is defective, and then the method further includes:

the read-write control circuit restores the numerical value in the SRAM to be tested to an initial value;

the input MUX switching control circuit switches the input two-way selector MUX to the output terminal of the input side DFF.

As a further improvement of the present invention, the monitoring circuit detects a rising edge of the second function clock pulse, and detects whether an input signal of the SRAM to be tested is a read/write SRAM command, and then further includes:

when the input signal of the SRAM to be detected is detected to be an SRAM reading command, the monitoring circuit sends an address for reading the SRAM to be detected to the comparison circuit;

after receiving the address, the comparison circuit inquires the initial value of the address;

the comparison circuit compares the data output by the SRAM to be tested with the initial value of the address, and if the data are not equal, the SRAM to be tested is indicated to be defective.

The invention has the beneficial effects that:

the SRAM input path time sequence test circuit and the method can test the TDF of the input path of the SRAM and increase the test coverage rate, thereby ensuring the reliability of the chip, and particularly increasing the test of the TDF for chips with harsh use environments, such as industrial grade chips, even military industry, aerospace grade chips and the like, and better ensuring the normal work of the chip. The circuit added by the scheme is low in cost, extra workload is not needed when the pattern is generated, the cost is low, and the method is an effective test method which can be implemented.

The foregoing description is only an overview of the technical solutions of the present invention, and in order to make the technical means of the present invention more clearly understood, the present invention may be implemented in accordance with the content of the description, and in order to make the above and other objects, features, and advantages of the present invention more clearly understood, the following preferred embodiments are described in detail with reference to the accompanying drawings.

Drawings

FIG. 1 is a first schematic diagram illustrating a sequential testing circuit of an SRAM input path according to an embodiment of the present invention;

FIG. 2 is a second schematic diagram illustrating a structure of an SRAM input path timing test circuit according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of the induction logic in an embodiment of the present invention;

FIG. 4 is a waveform diagram during testing in an embodiment of the present invention;

FIG. 5 is a diagram illustrating an SRAM input path timing test method according to an embodiment of the present invention.

Detailed Description

The present invention is further described below in conjunction with the following figures and specific examples so that those skilled in the art may better understand the present invention and practice it, but the examples are not intended to limit the present invention.

Examples

As shown in fig. 1-2, the SRAM input path timing test circuit in the embodiment of the present invention includes an inducing DFF, a TDF control circuit, an SRAM to be tested, an input two-way selector MUX, a clock control module, and an EDA tool;

an induction logic is arranged between the input side DFF and the induction DFF of the SRAM to be tested, the input side DFF and the induction DFF of the SRAM to be tested are connected in series to form a scan chain, the induction logic is used for enabling the input signal of the SRAM to be tested to generate a normal read-write command, and the monitoring circuit is connected with the input side DFF. The scan chain is shown in fig. 2 as solid line a. The purpose of the inducing logic is to make the input signal of the SRAM generate normal read-write command, because the TDF control circuit will start to work only when the read-write command occurs. Fig. 3 is a schematic diagram of the induction logic in this embodiment. In actual testing, a plurality of such inducing circuits may be added as needed.

The clock control module OCC is used for generating test clocks, and the shift clocks comprise a shift clock and two function clock pulses, wherein the shift clock inputs the test pattern into a Scan chain and outputs a test result from the Scan chain, and the two function clock pulses are needed for executing the time sequence test;

The waveform of the test flow is shown in fig. 4, where during the period of inputting shift in and shift out, Scan enable signal Scan enable is 1, after inputting shift in, Scan enable signal Scan enable is 0, and after clock control module OCC generates two consecutive function clock pulses, Scan enable signal Scan enable is 1, and then shift out is entered.

The initialization circuit is used for initializing each address of the SRAM to be tested, and the monitoring circuit is used for detecting a Scan enable signal, a function clock pulse and an input signal of the SRAM to be tested. The input MUX switching control circuit is used for cooperating with the SRAM read-write control circuit to work. When the SRAM read-write control circuit needs to access the SRAM to be tested, the input MUX switching circuit switches the SRAM input signal to the SRAM read-write control circuit, and the input signal of the SRAM to be tested is switched to the input side DFF after the SRAM read-write control circuit completes the read-write operation.

In this embodiment, the input end of the to-be-tested SRAM includes a data write end D, an address write end ADDR, a read/write enable end WEB, a chip select signal end CEB, and a clock input end, and the output end of the to-be-tested SRAM is a data read end Q.

As shown in fig. 5, the method for testing the timing of the SRAM input path according to the embodiment of the present invention is applied to the above test circuit, and the method includes the following steps:

s10, detecting the rising edge of the second function clock pulse by the monitoring circuit, and detecting whether the input signal of the SRAM to be detected is a read-write SRAM command;

s11, when the input signal of the SRAM to be tested is detected to be a command of writing the SRAM, the input signal represents that a numerical value is written in the SRAM to be tested, and the detection circuit records the first numerical value and the address of the first numerical value;

s12, the input MUX switching control circuit switches the input two-way selector MUX to the SRAM read-write control circuit;

s13, the monitoring circuit sends the written first value to the comparison circuit and informs the SRAM read-write control circuit to read the first value from the SRAM to be tested;

s14, the comparison circuit compares the detected first value with the value read out from the SRAM to be tested, if not equal, it represents that the SRAM to be tested is defective.

In this embodiment, after step S14, the method further includes the following steps:

s15, the read-write control circuit restores the numerical value in the SRAM to be tested to an initial value;

and S16, the input MUX switching control circuit switches the input two-way selector MUX to the output end of the input side DFF.

In this embodiment, after the step 10, the following steps are further included:

s21, when the input signal of the SRAM to be tested is detected to be a SRAM reading command, the monitoring circuit sends the address of the SRAM to be tested reading command to the comparison circuit;

s22, after receiving the address, the comparison circuit inquires the initial value of the address;

s23, comparing the data output by the SRAM to be tested with the initial value of the address by the comparison circuit, if not equal, it represents that the SRAM to be tested is defective.

The above embodiments are merely preferred embodiments for fully illustrating the present invention, and the scope of the present invention is not limited thereto. The equivalent substitution or change made by the technical personnel in the technical field on the basis of the invention is all within the protection scope of the invention. The protection scope of the invention is subject to the claims.

Claims

1. An SRAM input path timing sequence test circuit, characterized by: the device comprises an induction DFF, a TDF control circuit, an SRAM to be tested, an input two-way selector MUX, a clock control module and an EDA tool;

the EDA tool is used for generating Scan enable signals Scan enable and test patterns, the clock control module is used for generating test clocks, and the test clocks comprise a shift clock used for inputting the test patterns into a Scan chain and outputting test results from the Scan chain and two functional lock pulses needed for executing time sequence test;

during the input period, the Scan enable signal Scan enable is 1, after the input is finished, the Scan enable signal Scan enable is 0, and after the clock control module generates two continuous function clock pulses, the Scan enable signal Scan enable is 1.

2. An SRAM input path timing test method applied to the test circuit of claim 1, comprising the steps of:

when the input signal of the SRAM to be tested is detected to be a command for writing the SRAM, the SRAM to be tested represents that a numerical value is written in the SRAM to be tested, and the monitoring circuit records a first numerical value and an address of the first numerical value;

3. The method of claim 2, wherein the comparison circuit compares the written first value with the read value in the SRAM under test, and if not, indicates that the SRAM under test is defective, and further comprising:

the SRAM read-write control circuit restores the numerical value in the SRAM to be tested to an initial value;

4. The method according to claim 2, wherein the monitoring circuit detects a rising edge of the second function clock pulse, and detects whether the input signal of the SRAM to be tested is a read/write SRAM command, and further comprising: