CN111312323B

CN111312323B - SRAM (static random Access memory) timing sequence test circuit and method and memory

Info

Publication number: CN111312323B
Application number: CN202010168161.7A
Authority: CN
Inventors: 徐柯; 王林; 陈根华
Original assignee: Spreadtrum Communications Shanghai Co Ltd
Current assignee: Spreadtrum Communications Shanghai Co Ltd
Priority date: 2020-03-11
Filing date: 2020-03-11
Publication date: 2022-04-22
Anticipated expiration: 2040-03-11
Also published as: CN111312323A

Abstract

The embodiment of the application provides an SRAM time sequence test circuit, an SRAM time sequence test method and a memory. The SRAM time sequence test circuit comprises a first mode switching circuit and a second mode switching circuit, and when the SRAM time sequence test circuit measures the data reading time of the SRAM memory cell, the read clock signal input end generates a rising edge at intervals by utilizing the short-time pulse interference phenomenon generated when the read data signal output end of the SRAM memory cell continuously outputs '0', so that the read data signal output end can continuously output. The combination of the SRAM memory cell and the SRAM timing test circuit can generate stable and measurable oscillation output, and the SRAM timing test circuit can independently generate stable and measurable oscillation output, so that data reading time can be obtained according to two oscillation outputs.

Description

SRAM (static random Access memory) timing sequence test circuit and method and memory

Technical Field

The embodiment of the application relates to a chip technology, in particular to a circuit and a method for testing SRAM (static random access memory) time sequence and a memory.

Background

After the semiconductor technology enters a deep submicron era, the chip can work at a frequency of hundreds of MHz or GHz, and the working frequency of a Static Random Access Memory (SRAM) inside the chip is possibly higher. However, in chip testing, due to the influence of the package and the tester, the clock signal provided by external testing can only reach the frequency of tens or at most one hundred MHz.

In the foregoing background, testing of chips today typically relies heavily on built-in self-test (BIST) circuits, which have the advantage of not only automation of testing, but also the ability to achieve high speed testing because no external test paths need to be passed through. The BIST circuit of the SRAM is also called a memory built-in self test (MBIST) circuit, and includes therein a test signal generation circuit and an SRAM output judgment comparison circuit. The MBIST circuit tests the SRAM under the control of a high-speed clock in the chip, if the test is correct, the function of the SRAM is proved to be correct, and the clock period of the SRAM is not larger than the clock period of the test, so that the test data of the clock period of the SRAM can be obtained from the outside. However, besides the clock period of the SRAM, the data reading time (Tcq) of the SRAM is also an important timing index parameter of the SRAM, and this parameter cannot be measured by the conventional MBIST circuit.

Disclosure of Invention

The embodiment of the application provides an SRAM time sequence test circuit, an SRAM time sequence test method and a memory, so that a short-time pulse interference phenomenon generated when a double-port SRAM memory adopting a Single-end reading mode continuously outputs '0' is utilized, a stable measurable oscillation output can be generated by the combination of a double-port SRAM memory unit and the SRAM time sequence test circuit, and measurement of data reading time of the double-port SRAM memory unit adopting the Single-end reading mode is realized.

In a first aspect, an embodiment of the present application provides an SRAM timing test circuit, which is applied to a dual-port SRAM memory cell, where the dual-port SRAM memory cell reads a data signal stored in the SRAM memory cell in a Single-ended Single-end reading manner, where the SRAM memory cell includes a clock signal input end and a read data signal output end;

the SRAM timing test circuit includes:

the input end of the first mode switching circuit is connected with the read data signal output end;

the input end of the second mode switching circuit is connected with the output end of the first mode switching circuit, and the output end of the second mode switching circuit is connected with the clock signal input end;

when measuring the data reading time of the SRAM memory cell:

the first mode switching circuit, the second mode switching circuit and the dual-port SRAM memory unit form a first ring-shaped oscillation circuit, and a first oscillation period of the first ring-shaped oscillation circuit is obtained through testing;

the first mode switching circuit and the second mode switching circuit form a second ring oscillation circuit, and a first oscillation period of the second ring oscillation circuit is tested.

Optionally, when the first mode switching circuit is connected to a read data signal output terminal and the second mode switching circuit is connected to the test mode selection circuit output terminal, the first ring oscillator circuit is formed;

the second ring oscillator circuit is formed when the first mode switching circuit is switched in at the output of the second mode switching circuit.

Optionally, the SRAM timing test circuit further includes: and the input end of the edge signal trigger circuit is connected with the first mode switching circuit, and the output end of the edge signal trigger circuit is connected with the input end of the second mode switching circuit so as to generate an edge trigger signal according to the inversion of the digital signal output by the read data signal output end to form the first ring oscillator circuit and the second ring oscillator circuit.

Optionally, the edge signal trigger circuit is further configured to select a test mode; wherein the test mode comprises:

when the relation between the output signal of the edge signal trigger circuit and the output signal of the first mode switching circuit is a logical inverse, the edge signal trigger circuit is a measuring mode, and the first ring oscillator circuit and the second ring oscillator circuit both correspond to the testing mode;

the output signal of the edge signal trigger circuit is the same as the output signal of the first mode switching circuit in logic, and is a measuring mode, and the first ring oscillation circuit and the second ring oscillation circuit both correspond to the testing mode.

Optionally, the first mode switching circuit includes a first two-way gate;

and the first two-way gate is provided with a first enabling end, one input end of the first two-way gate is connected with the read data signal output end, the other input end of the first two-way gate is connected with the output end of the second mode switching circuit, and the output end of the first two-way gate is connected with the test mode selection circuit.

Optionally, the test mode selection circuit includes a first inverter and a second gate;

the second two-way gate is provided with a second enabling end, one input end of the second two-way gate is connected with the output end of the first two-way gate, the other input end of the second two-way gate is connected with the output end of the first two-way gate through the first phase inverter, and the output end of the second two-way gate is connected with the input end of the second mode switching circuit.

Optionally, the second mode switching circuit includes a third gate-two, a fourth gate-two and a second inverter;

the third two-way gate is provided with a third enabling end, one input end receives an external test clock signal, the other input end is connected with the output end of the second two-way gate, and the output end is connected with the clock signal input end;

the fourth two-way gate is provided with a second enabling end, one input end of the fourth two-way gate is connected with the output end of the third two-way gate, the other input end of the fourth two-way gate is connected with the output end of the third two-way gate through the second phase inverter, and the output end of the fourth two-way gate is connected with one input end of the first two-way gate.

Optionally, the SRAM timing test circuit further includes: and the input end of the delay circuit is connected with the output end of the first mode switching circuit, and the output end of the delay circuit is connected with the input end of the test mode selection circuit.

In a second aspect, an embodiment of the present application provides a memory, including a dual-port SRAM memory cell and the SRAM timing test circuit according to any one of the first aspects, where the SRAM timing test circuit is configured to measure a data read time of the dual-port SRAM memory cell.

In a third aspect, an embodiment of the present application provides an SRAM timing test method, which is applied to the SRAM timing test circuit according to any one of the first aspects, where the method includes:

controlling the first mode switching circuit to be connected to the read data signal output end, and controlling the second mode switching circuit to be connected to the test mode selection circuit output end to obtain the output oscillation period of the first ring-shaped oscillation circuit;

controlling the first mode switching circuit to access the output end of the second mode switching circuit to obtain the output oscillation period of the second ring oscillation circuit;

and calculating the data reading time of the SRAM memory cell according to the output oscillation periods of the two ring oscillation circuits.

Optionally, before obtaining the output oscillation period of the first ring oscillator circuit, the method further includes:

and triggering the reading of one address in the dual-port SRAM memory unit at a time through an external mode, wherein the read address value is kept at the read data signal output end.

Optionally, the triggering by the external mode includes: and controlling the second mode switching circuit to input an external test input clock signal, wherein the external test input clock signal triggers the SRAM storage unit to read the external address input signal.

The embodiment of the application provides an SRAM timing test circuit, a method and a memory, wherein the SRAM timing test circuit comprises a first mode switching circuit, an edge signal trigger circuit and a second mode switching circuit, when the SRAM timing test circuit measures the data reading time of a dual-port SRAM memory unit, the short-time pulse interference phenomenon generated when the read data signal output end of the dual-port SRAM memory unit continuously outputs '0' is utilized, the edge signal trigger circuit generates a rising edge at intervals, so that the read clock signal input end generates a rising edge at intervals, and the read data signal output end can continuously output, therefore, the combination of the dual-port SRAM memory unit and the SRAM timing test circuit can generate stable measurable oscillation output, and the SRAM timing test circuit can independently generate stable measurable oscillation output, thereby obtaining a data read time from the two oscillation outputs. Also, the test mode may be selected according to the edge signal flip-flop circuit, in which one test mode is to obtain Tcq0 by oscillating the output twice, and the other test mode is to obtain Tcq1 by oscillating the output twice.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to these drawings without inventive exercise.

FIG. 1 is a circuit for measuring data read time of an SRAM;

FIG. 2 is a schematic diagram of waveforms of the circuit of FIG. 1 during a Tcq measurement;

FIG. 3 is a schematic diagram of an output waveform of the second ring oscillator circuit formed in FIG. 1;

FIG. 4 is a waveform diagram illustrating a glitch according to an embodiment of the present application;

FIG. 5 is a schematic diagram of a dual-port SRAM timing test circuit according to an embodiment of the present disclosure;

FIG. 6 is a waveform schematic of the output of the first ring oscillator circuit of the circuit of FIG. 5 when a Tcq0 measurement is taken;

FIG. 7 is a schematic diagram of an output waveform of the second ring oscillator circuit formed in FIG. 5;

FIG. 8 is a waveform schematic of the output of the first ring oscillator circuit of the circuit of FIG. 5 when a Tcq1 measurement is taken;

fig. 9 is a flowchart illustrating an SRAM timing testing method according to an embodiment of the present application.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

FIG. 1 is a circuit for measuring data reading time of an SRAM. In the circuit shown in fig. 1, two ring oscillation circuits are mainly used, and the output oscillation periods of the two ring oscillation circuits are respectively measured, so that an accurate Tcq value is obtained. When the enable signal MD _ EX is 0 and the enable signal OSCE is 0, the first oscillation circuit is formed by I0 to I8, the oscillation cycle of which is Tx, and the waveform is shown in fig. 2. When the enable signal MD _ EX is 0 and the enable signal OSCE is 0, a first oscillation circuit is formed by I0-I8, the waveform of which is as shown in fig. 2, and is a waveform diagram generated by the test circuit when Tcq is measured, a clock cycle of the clock signal CK from a previous rising edge to a next rising edge of the clock signal CK, that is, a reading time of the address input data by the SRAM memory cell, is defined as Tx, but this time is sequentially delayed by the first mode switching circuit I5, the first inverter, the exclusive nor gate I0, the third inverter I11 and the second mode switching circuit I8, so that it is necessary to subtract a delay time from the output of the signal D0 to the generation of a new rising edge of the signal CK to define Tosc in order to obtain an accurate SRAM read data time Tcq. As can be seen from the waveform diagram shown in fig. 2, Tcq is the difference between Tx and Tosc, so that the accurate value of Tcq can be obtained by measuring the values of Tx and Tosc. The oscillation period of the output signal OSC _ OUT of the pulse signal trigger is measured by an external test instrument to obtain Tx.

Then MD _ EX is kept at 0, the enable signal OSCE is set to 1 from 0, the second ring oscillator is composed of I11, I8, I5, I4 and I0, the output waveform of the signal OSC _ OUT is as shown in fig. 3, the oscillation period of the output signal OSC _ OUT of the second ring oscillator circuit is measured, the delay time from the output of the signal D0 to the generation of a new rising edge of the signal CK is obtained, which is defined as Ty, and Tosc is Ty/2 according to the principle of the ring oscillator circuit.

Therefore, Tcq is Tx-Ty/2, and the SRAM read data period Tcq can be measured.

Although the SRAM read data period Tcq can be measured using the circuit shown in fig. 1, the SRAM shown in fig. 1 is a single-port SRAM having an address signal input terminal a, a clock signal input terminal CK, a write enable signal input terminal WEB, a write data signal input terminal DI, and a read data signal input terminal DO. Since the single-port SRAM cell has only one address signal input terminal, the data signal cannot be read through the read data signal input terminal DO when the data signal is written through the write data signal input terminal DI.

As shown in fig. 5, the dual-port SRAM memory cell has a read address signal input terminal AA, a write address signal input terminal AB, a read clock signal input terminal CKA, a write clock signal input terminal CKB, a read enable signal input terminal CEBA, a write enable signal input terminal CEBB, a write data signal input terminal DI, and a read data signal output terminal DO. Therefore, the dual-port SRAM memory cell can simultaneously perform the operation of writing data signals and reading data signals. In order to avoid mutual interference between reading and writing, the dual-port SRAM memory unit is designed by adopting an 8T cell in a Single-end reading mode, so that the dual-port SRAM memory unit has better stability. While the single-end unique reading method generates a short-time pulse interference phenomenon (DO glitch) at the read data signal output terminal when "0" is continuously read through the read data signal output terminal DO, as shown in fig. 4, after the previous cycle reads "0" and before the next cycle reads "0", a short-time "1" pulse is generated, so that the read data time Tcq of the dual-port SRAM memory cell adopting the single-end reading method cannot be measured by using the method for measuring the read data period Tcq of the single-port SRAM shown in fig. 1.

Therefore, the present application provides an SRAM timing test circuit: when the dual-port SRAM memory cell employs a single-end read method, a short-time pulse interference phenomenon may occur at the read data signal output terminal, and according to the waveform diagram shown in fig. 4, when the read data signal output terminal continuously outputs a data signal of "0", a short-time "1" pulse may be generated after reading "0" in the previous cycle and before reading "0" in the next cycle. Therefore, the data signal output by the read data signal output terminal can be continuously inverted between '1' and '0', and then the SRAM timing test circuit provided by the application can be used for providing a stable read data clock signal for the dual-port SRAM memory cell, so that the read data signal output terminal outputs '0' at intervals, and outputs '1' between two times of outputting '0'. Therefore, the double-port SRAM memory cell and the SRAM time sequence test circuit generate stable and measurable oscillation output, and the SRAM time sequence test circuit can also independently generate stable and measurable oscillation output, so that the measurement of the data reading time of the double-port SRAM memory cell adopting a single-end reading mode is realized according to the two oscillation outputs.

Fig. 5 is a schematic diagram of a dual-port SRAM timing test circuit according to an embodiment of the present disclosure. It should be noted that fig. 5 shows a schematic diagram including the dual-port SRAM timing test circuit 1000 and the dual-port SRAM memory cell I11. The dual-port SRAM timing test circuit comprises: a first mode switching circuit I0, an edge signal trigger circuit 100, a second mode switching circuit 200 and a delay circuit I7. Wherein the content of the first and second substances,

the dual-port SRAM memory unit I11 is a clock synchronization circuit with an effective clock rising edge, the read clock signal input terminal CKA is used for inputting a clock synchronization signal, the rising edge of the clock signal triggers the dual-port SRAM memory unit I11 to perform a read operation, the write clock signal input terminal CKB is used for inputting a clock synchronization signal, and the rising edge of the clock signal triggers the dual-port SRAM memory unit I11 to perform a write operation.

The read enable signal input terminal CEBA is used for inputting an active low read enable signal CEBA, which defines a high level as logic "1" and a low level as logic "0", for example, when the input signal CEBA is logic "0", a read operation of the read data signal output terminal DO in the SRAM memory cell I11 is triggered, and a data signal is read from the SRAM memory cell I11 through the read data signal output terminal DO; the write enable signal input terminal CEBB is used for inputting an active low write enable signal CEBB, for example, when the input signal CEBB is logic "0", a write operation of the write data signal input terminal DI in the SRAM memory cell I11 is triggered, and data is written into the SRAM memory cell I11 through the write data signal input terminal DI. The read address signal input terminal AA is used to determine the address of the read data signal, and the write address signal input terminal AB is used to determine the address of the data signal to be written.

In an embodiment of the present application, optionally, as shown in fig. 5, the first mode switching circuit I0 adopts a two-way gate having two input terminals, one output terminal and one enable terminal, the input terminal a is connected to the read data signal output terminal DO, the input terminal B is connected to the output terminal of the second mode switching circuit 200, and the enable terminal is connected to the enable signal OSCE, which is used for controlling the output of the first mode switching circuit I0, that is, when the enable signal OSCE is logic "0", the first mode switching circuit I0 outputs the data signal input through the input terminal B; when the enable signal OSCE is logic "1", the first mode switching circuit I0 outputs the read data output signal DO.

In an embodiment of the present application, optionally, as shown in fig. 5, the edge signal triggering circuit 100 includes an inverter I1, a two-way gate I2, a two-way gate I3, a two-way gate I5, a delay unit I4, and an or not gate I6. The input end A of the two-way gate I2 is connected with the output end of the two-way gate I0, the input end B is connected with the output end of the two-way gate I0 through an inverter I1, and the enable end is connected with an enable signal MD _ SEL for controlling the output of the two-way gate I2, namely when the enable signal MD _ SEL is logic '0', the two-way gate I2 outputs a data signal input through the input end B; when the enable signal MD _ SEL is logic "1", the two-way gate I2 outputs the data signal input through the input terminal a.

The input end A of the two-way gate I3 is connected with the output end of the two-way gate I0 through an inverter I1, the input end B is connected with the output end of the two-way gate I0, the enable end is connected with an enable signal MD _ SEL for controlling the output of the two-way gate I3, namely when the enable signal MD _ SEL is logic '0', the two-way gate I3 outputs a data signal input through the input end B; when the enable signal MD _ SEL is logic "1", the two-way gate I3 outputs the data signal input through the input terminal a.

For the two-way gate I2 and the two-way gate I3, the enable signal MD _ SEL is used for selecting the test mode, and when MD _ SEL sets logic "0", the data reading time Tcq0 in FIG. 4 is measured; when MD _ SEL sets logic "1", it is used to measure the data read time Tcq1 in fig. 4.

The input end A of the two-way gate I5 is connected with the output end of the two-way gate I2 through a delay unit I4, the input end B inputs an external data signal '0', the enable end is connected with an enable signal OCSE for controlling the output of the two-way gate I5, namely when the enable signal OSCE is logic '0', the two-way gate I5 outputs the data signal input through the input end B; when the enable signal OSCE is logic "1", the two-way gate I5 outputs the data signal input through the input terminal a.

The nor gate I6 has one input terminal connected to the output terminal of the two-way gate I3, the other input terminal connected to the output terminal of the two-way gate I5, and the output terminal connected to the second mode switching circuit 200 through the delay circuit I7.

For the edge signal triggering circuit 100, the input signal is "NODE", and the output signal is "OSC _ OUT". When OSCE is logic "1" and MD _ SEL is logic "0", the edge triggered circuit 100 is sensitive to the falling edge of "NODE", i.e. whenever "NODE" makes a transition from "1" to "0", the output "OSC _ OUT" of the edge triggered circuit 100 outputs a pulse "1", i.e. generates a rising edge, and the pulse width is determined by the delay time of the delay unit I4. When "OSCE" is logic "0" and "MD _ SEL" is logic "0", it can be known from logic analysis that the output signal "OSC _ OUT" of the edge signal triggering circuit 100 will always be the logical inverse of the input signal "NODE".

When "OSCE" is logic "1" and "MD _ SEL" is logic "1", the edge triggered circuit 100 is sensitive to the rising edge of "NODE", i.e. whenever "NODE" makes a transition from "0" to "1", the output "OSC _ OUT" of the edge triggered circuit 100 outputs a pulse of "1", i.e. generates a rising edge, and the pulse width is determined by the delay time of the delay unit I4. When "OSCE" is logic "0" and "MD _ SEL" is logic "1", it is known from logic analysis that the output signal of the edge signal flip-flop will always be the same logic of the input signal "NODE".

In an embodiment of the present application, optionally, as shown in fig. 5, the second mode switching circuit 200 includes a gate router I8, a gate router I10, and an inverter I9. The input end a of the two-way gate I8 receives an external test clock signal, the input end B is connected with the output end of the nor gate I6 through the delay circuit I7, and the enable end is connected with the enable signal MD _ EXT for controlling the output of the two-way gate I8, that is, when the enable signal MD _ EXT is logic "0", the two-way gate I8 transmits a data signal input by a signal "OSC _ OUT" to the read clock signal input end CKA; when the enable signal MD _ EXT is logic "1", the two-way gate I8 delivers the external clock signal received through the input terminal a to the read clock signal input terminal CKA.

The input end A of the two-way gate I10 is connected with the output end of the two-way gate I8 through an inverter I9, the input end B is connected with the output end of the two-way gate I8, the enable end is connected with an enable signal MD _ SEL for controlling the output of the two-way gate I10, namely when the enable signal MD _ SEL is logic '0', the two-way gate I10 transmits a data signal input through the input end B to the input end B of the two-way gate I0; when the enable signal MD _ SEL is logic "1", the two-way gate I10 transmits the data signal received through the input terminal A to the input terminal B of the two-way gate I0.

That is, when the enable signal OSCE is logic "0" and the enable signal MD _ SEL is logic "0", the digital signal "NODE" output by the two-way gate I0 is the same as the digital signal logic supplied to the read clock signal input terminal CKA; when the enable signal OSCE is logic "0" and the enable signal MD _ SEL is logic "1", the digital signal "NODE" output by the two-way gate I0 is logically opposite to the digital signal supplied to the read clock signal input terminal CKA.

When the enable signal MD _ EXT is logic "0" and the enable signal OSCE is logic "1", the first mode switching circuit I0, the edge signal trigger circuit 100, the second mode switching circuit 200, and the two-port SRAM memory cell I11 form a first ring oscillation circuit whose oscillation period can be measured.

When the enable signal MD _ EXT is logic "0" and the enable signal OSCE is logic "0", the first mode switching circuit I0, the test mode selection circuit 100, and the second mode switching circuit 200 form a second ring oscillation circuit, and the oscillation period of the second ring oscillation circuit can be measured.

When the enable signal MD _ SEL is logic "0", the first ring oscillator circuit specifically includes: the two-port SRAM comprises a two-port gate I0, a two-port gate I3, a NOR gate I6, a delay circuit I7, a two-port gate I8 and a two-port SRAM storage unit I11; the second ring oscillation circuit specifically includes: the two-way gate I0, the two-way gate I3, the NOR gate I6, the delay circuit I7, the two-way gate I8 and the two-way gate I10 obtain Tcq0 in the figure 4 through calculation according to the oscillation period of the first ring oscillation circuit and the oscillation period of the second ring oscillation circuit.

When the enable signal MD _ SEL is logic "1", the first ring oscillator circuit specifically includes: the two-way gate I0, the inverter I1, the two-way gate I3, the NOR gate I6, the delay circuit I7, the two-way gate I8 and the dual-port SRAM storage unit I11, and the second ring oscillator circuit specifically comprises: the two-way gate I0, the inverter I1, the two-way gate I3, the NOR gate I6, the delay circuit I7, the two-way gate I8, the inverter I9 and the two-way gate I10 are used for obtaining Tcq1 in the figure 4 through calculation according to the oscillation period of the first ring oscillation circuit and the oscillation period of the second ring oscillation circuit.

It should be noted that, in some embodiments, the dual-port SRAM timing test circuit 1000 and the dual-port SRAM memory cell I11 may be integrated together to form a memory. The structure of the memory formed by integrating the dual-port SRAM timing test circuit 1000 and the dual-port SRAM memory cell I11 is shown in fig. 5, so that when the data reading time of the dual-port SRAM memory cell I11 needs to be tested, the SRAM timing test circuit 1000 is used to test the data reading time of the dual-port SRAM memory cell I11. The structure of the SRAM timing test circuit 1000 may be the structure of the SRAM timing test circuit 1000 provided in any of the embodiments.

The SRAM time sequence testing method is used for measuring the data reading time Tcq0 and Tcq1 of the dual-port SRAM. Here, the dual-port SRAM memory cell only includes the address cell Addr as an example, and a test method of the SRAM test circuit is described, and as shown in fig. 9, the SRAM timing test method includes the following steps:

and S101, triggering reading of one address in the dual-port SRAM memory unit at a time through an external mode, wherein the read address value is kept at the read data signal output end.

Specifically, the write enable signal CEBB input by the write enable signal input terminal CEBB is "0", which triggers the dual-port SRAM memory cell to write data into the address cell Addr, and writes the digital signal "0" into the address cell Addr. Setting MD _ EXT to be logic '1', controlling the two-way gate I4 to output an external test clock signal CK _ EXT, triggering the dual-port SRAM memory cell to read data in the address unit Addr once by the rising edge of the external test clock signal CK _ EXT, so that the output data of the dual-port SRAM memory cell I11 is logic '0', and knowing the characteristics of the output interface of the dual-port SRAM memory cell, the output signal DO of the dual-port SRAM memory cell keeps the data read in the previous time before the next read operation of the dual-port SRAM memory cell occurs.

S102, controlling the first mode switching circuit to be connected to the read data signal output end, and controlling the second mode switching circuit to be connected to the test mode selection circuit output end to obtain the output oscillation period of the first ring oscillation circuit.

And S103, controlling the first mode switching circuit to be connected to the output end of the second mode switching circuit to obtain the output oscillation period of the second ring oscillation circuit.

And S104, calculating the data reading time of the SRAM memory cell according to the output oscillation periods of the two ring oscillation circuits.

For S102-S104, the description is made in terms of different test patterns. The test mode is determined by the enable signal MD _ SEL controlling the output of the two-way gate I2. When MD _ SEL is logic "0", test Tcq0, specifically:

setting MD _ EXT to logic "1" and OSCE to logic "1", when the read clock signal CKA is a rising edge, the read data output signal output terminal DO outputs "0", but due to the short-time pulse interference phenomenon (DO glitch), the read data output signal output terminal DO outputs "1" before outputting "0" this time. Thus, the read data output signal output DO delivers a "1" to the input of the test mode select circuit, i.e., NODE is 1. Since MD _ SEL is logic "0", the output of the two-way gate I2 receives the data signal through the input terminal B, i.e. the signal output by the two-way gate I2 is "0", and the output of the two-way gate I3 receives the data signal through the input terminal B, i.e. the signal output by the two-way gate I3 is "1". The output of the two-way gate I2 passes through the delay unit I4 and then is input to the input end a of the two-way gate I5, because OSCE is set to logic "1", the output of the two-way gate I5 receives the data signal through the input end a, but because of the existence of the delay unit I4, when the signal output by the two-way gate I3 is "1", the output of the two-way gate I5 is still the corresponding signal when the data output signal output end DO outputs "0", that is, the output of the two-way gate I5 is "1". Therefore, the nor gate I6 outputs "0", i.e., the signal "OSC _ OUT" is "0". At this time, MD _ EXT is set to logic "0", the signal OSC _ OUT is transmitted to the read clock signal CKA through the two-way selector I8, so that the read clock signal CKA has a falling edge. When the delay time of the delay unit I4 is reached, the output of the two-way gate I5 is inverted from "1" to "0", the signal "OSC _ OUT" is still "0" according to the characteristics of the nor gate I6, and the read clock signal CKA is still in a low pulse.

When the data signal output from the read data output signal output terminal DO is switched from "1" to "0", that is, when the next "0" is output according to the rising edge of the read clock signal CKA, NODE is 0. The output of the two-way gate I2 receives a data signal through the input end B, namely the signal output by the two-way gate I2 is '1', and the output of the two-way gate I3 receives a data signal through the input end B, namely the signal output by the two-way gate I3 is '0'. The output of the two-way gate I2 passes through the delay unit I4 and then is input to the input end a of the two-way gate I5, because OSCE is set to logic "1", the output of the two-way gate I5 receives the data signal through the input end a, but because of the existence of the delay unit I4, when the signal output by the two-way gate I3 is "0", the output of the two-way gate I5 is still the corresponding signal when the data output signal output end DO outputs "1", that is, the output of the two-way gate I5 is "0". Therefore, the nor gate I6 outputs "1", i.e., the signal "OSC _ OUT" is "1", generating a rising edge. At this time, since MD _ EXT is logic "0", the signal OSC _ OUT is supplied to the read clock signal CKA through the two-way selector I8, so that the read clock signal CKA has a rising edge as a next clock signal, and the read data output signal output terminal DO outputs "0" next time. When the delay time of the delay unit I4 is reached, the output of the two-way gate I5 is inverted from "0" to "1", the signal OSC _ OUT is inverted from "1" to "0" according to the characteristics of the nor gate I6, a falling edge is generated, and the read clock signal CKA is also inverted from "1" to "0", and a falling edge is generated.

Before outputting "0" next time, the read data output signal output terminal DO still outputs "1" first, and due to the existence of the delay unit I4, there is a time difference between the inversion time of the data signal output by the two-way gate I5 and the inversion time of the data signal output by the two-way gate I3. Therefore, as long as MD _ EXT is maintained at "0", OSCE is maintained at "1", MD _ SEL is maintained at "0", the dual port SRAM cell will repeatedly read address Addr, and OSC _ OUT will have a high pulse generated at intervals.

The test circuit waveforms are as shown in fig. 6, and are waveform diagrams generated by the test circuit when Tcq0 is measured, and a clock period of the clock signal CKA is from a previous rising edge to a next rising edge of the clock signal CKA, which is a reading time of the address input data by the dual-port SRAM memory cell, and is defined as Tx. Here, this time Tx passes through the delay of the time Tcq0 of the read data "0" at the data signal output terminal DO in the dual port SRAM memory cell, the two-way gate I0, the two-way gate I3, the nor gate I6, the delay circuit I7, and the two-way gate I8 in sequence, so that in order to obtain the read data time Tcq0 of accurate read data, the delay time from outputting "0" from the signal output terminal D0 to generating a rising edge of the new clock signal CKA needs to be subtracted, which is defined as Tosc. As can be seen from the waveform diagram shown in fig. 6, Tcq0 is the difference between Tx and Tosc, so that the accurate value of Tcq0 can be obtained by measuring the values of Tx and Tosc. When Tx is measured, the enabling signal MD _ EXT is set to be logic '0', the enabling signal OSCE is set to be logic '1', and the oscillation period of the output signal OSC _ OUT of the pulse signal trigger is measured through an external testing instrument to obtain Tx. As can be seen from the waveform shown in fig. 6, Tcq0 is Tx-Tosc.

After the value of Tx is measured, "OSCE" is set to 0, and a second ring oscillator circuit is formed by the two-way gate I0, the two-way gate I3, the NOR gate I6, the delay circuit I7, the two-way gate I8 and the two-way gate I10. The waveform of OSC _ OUT is as shown in fig. 7, and the period of oscillation of the control signal OSC _ OUT outputted from the second ring oscillator circuit is measured, so that the delay time from outputting the data signal from the data signal output terminal DO to generating a new rising edge of the signal CKA, which is defined as Ty, is obtained, and Tosc is Ty/2 according to the principle of the ring oscillator circuit.

The data fetch period Tcq0 corresponding to the data read signal input DO can be measured by the formula Tcq0 being Tx-Tosc and the formula Tosc being Ty/2.

When MD _ SEL is logic "1", Tcq1 is tested, specifically:

setting MD _ EXT to logic "1" and OSCE to logic "1", when the read clock signal CKA is a rising edge, the read data output signal output terminal DO outputs "0", but due to the short-time pulse interference phenomenon (DO glitch), the read data output signal output terminal DO outputs "1" before outputting the next "0". Thus, the read data output signal output DO delivers a "1" to the input of the test mode select circuit, i.e., NODE is 1. Since MD _ SEL is logic "1", the output of the two-way gate I2 receives the data signal through the input terminal a, i.e. the signal output by the two-way gate I2 is "1", and the output of the two-way gate I3 receives the data signal through the input terminal a, i.e. the signal output by the two-way gate I3 is "0". The output of the two-way gate I2 passes through the delay unit I4 and then is input to the input terminal B of the two-way gate I5, because OSCE is set to logic "1", the output of the two-way gate I5 receives the data signal through the input terminal a, but because of the existence of the delay unit I4, when the signal output by the two-way gate I3 is "0", the output of the two-way gate I5 is still the corresponding signal when the data output signal output terminal DO outputs "0", that is, the output of the two-way gate I5 is "0". Therefore, the nor gate I6 outputs "1", i.e., the signal "OSC _ OUT" is "1", generating a rising edge. At this time, MD _ EXT is set to logic "0", the signal OSC _ OUT is transmitted to the read clock signal CKA through the two-way selector I8, so that the read clock signal CKA has a rising edge as the next clock signal, and the read data output signal output terminal DO outputs "0" next time.

When the delay time of the delay unit I4 is reached, the output of the two-way gate I5 is inverted from "0" to "1", and according to the characteristics of the nor gate I6, the signal "OSC _ OUT" is inverted from "1" to "0", generating a falling edge. At this time, since MD _ EXT is set to logic "0", the signal OSC _ OUT is transmitted to the read clock signal CKA through the two-way selector I8, so that the read clock signal CKA has a falling edge.

When the data signal output from the read data output signal output terminal DO is switched from "1" to "0", that is, when the next "0" is output according to the rising edge of the read clock signal CKA, NODE is 0. The output of the two-way gate I2 receives a data signal through the input end A, namely the signal output by the two-way gate I2 is '0', and the output of the two-way gate I3 receives a data signal through the input end A, namely the signal output by the two-way gate I3 is '1'. The output of the two-way gate I2 passes through the delay unit I4 and then is input to the input end A of the two-way gate I5, and since OSCE is set to logic "1", the output of the two-way gate I5 receives a data signal through the input end A. However, due to the existence of the delay unit I4, when the signal output by the two-way gate I3 is "1", the output of the two-way gate I5 is still the signal corresponding to the output of "1" from the data output signal output terminal DO, i.e. the output of the two-way gate I5 is "1". Therefore, the nor gate I6 still outputs "0", and the read clock signal CKA is still at a low pulse.

When the delay time of the delay unit I4 is reached, the output of the two-way gate I5 is inverted from "1" to "0", the NOR gate I6 still outputs "0" according to the characteristics of the NOR gate I6, and the read clock signal CKA is still in a low pulse.

Before the next "0" is output according to the rising edge of the read clock signal CKA, the read data signal output terminal DO outputs "1" first, that is, between two times of outputting "0", and the read data signal output terminal DO outputs "1", so that the data signal output from the read data signal output terminal DO is switched from "0" to "1". At this time, it can be seen from the above analysis that the output of the not gate I6 is inverted from "0" to "1", resulting in a rising edge. At this time, since MD _ EXT is logic "0", the signal OSC _ OUT is supplied to the read clock signal CKA through the two-way selector I8, so that the read clock signal CKA has a rising edge as the next clock signal, and the read data output signal output terminal DO outputs "0" next time.

Before outputting "0" next time, the read data output signal output terminal DO still outputs "1" first, and due to the existence of the delay unit I4, there is a time difference between the inversion time of the data signal output by the two-way gate I5 and the inversion time of the data signal output by the two-way gate I3. Therefore, as long as MD _ EXT remains "0", OSCE remains "1", MD _ SEL remains "1", the dual-port SRAM cell will repeatedly read address Addr, and OSC _ OUT will have a high pulse generated at intervals.

The test circuit waveforms are as shown in fig. 8, which is a waveform diagram generated by the test circuit when Tcq1 is measured, and the clock period of the clock signal CKA is from the previous rising edge to the next rising edge of the clock signal CKA, i.e. the read time of the address input data by the dual-port SRAM memory cell, is defined as Tx. Here, this time Tx passes through the delay of the time Tcq1 of the read data "1" at the data signal output terminal DO in the dual port SRAM memory cell, the two-way gate I0, the inverter I1, the two-way gate I3, the nor gate I6, the delay circuit I7, and the two-way gate I8 in sequence, so that in order to obtain the accurate read data time Tcq0, the delay time from the output of "1" at the read data signal output terminal D0 to the generation of the rising edge of the new clock signal CKA needs to be subtracted, which is defined as Tosc. As can be seen from the waveform diagram shown in fig. 8, Tcq1 is the difference between Tx and Tosc, so that the accurate value of Tcq0 can be obtained by measuring the values of Tx and Tosc. When Tx is measured, the enabling signal MD _ EXT is set to be logic '0', the enabling signal OSCE is set to be logic '1', and the oscillation period of the output signal OSC _ OUT of the pulse signal trigger is measured through an external testing instrument to obtain Tx. As can be seen from the waveform shown in fig. 8, Tcq1 is Tx-Tosc.

After the value of Tx is measured, "OSCE" is set to 0, and a second ring oscillator circuit is formed by the two-way gate I0, the inverter I1, the two-way gate I3, the NOR gate I6, the delay circuit I7, the two-way gate I8, the inverter I9 and the two-way gate I10. The waveform of OSC _ OUT is still as shown in fig. 7, and the oscillation period of the control signal OSC _ OUT outputted from the second ring oscillator circuit is measured, so that the delay time from outputting the data signal from the data signal output terminal DO to generating a new rising edge of the signal CKA, which is defined as Ty, is obtained, and Tosc is Ty/2 according to the principle of the ring oscillator circuit.

The data fetch period Tcq1 corresponding to the data read signal input DO can be measured by the formula Tcq1 being Tx-Tosc and the formula Tosc being Ty/2.

It should be noted that the components in the peripheral circuit may be replaced with other components or other combinations of multiple components, as long as the replaced components can achieve the functions of the original components. For example, the edge signal flip-flop circuit composed of I2, I3, I4, I5, and I6 in fig. 5 may be replaced by other types of circuits as long as the replacement circuit can perform the same function as the test mode selection unit in the fig..

Those of ordinary skill in the art will understand that: all or a portion of the steps of implementing the above-described method embodiments may be performed by hardware associated with program instructions. The program may be stored in a computer-readable storage medium. When executed, the program performs steps comprising the method embodiments described above; and the aforementioned storage medium includes: various media that can store program codes, such as ROM, RAM, magnetic or optical disks.

Finally, it should be noted that: the above embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present application.

Claims

1. The SRAM time sequence test circuit is applied to a dual-port SRAM memory unit, the dual-port SRAM memory unit reads data signals stored in the SRAM memory unit in a Single-end reading mode, and the SRAM memory unit comprises a clock signal input end and a read data signal output end;

the SRAM timing test circuit includes:

the first mode switching circuit comprises a first two-way gate; the first two-way gate is provided with a first enabling end, one input end of the first two-way gate is connected with the read data signal output end, the other input end of the first two-way gate is connected with the output end of the second mode switching circuit, and the output end of the first two-way gate is connected with the test mode selection circuit;

when measuring the data reading time of the SRAM memory cell:

2. The SRAM timing test circuit of claim 1,

when the first mode switching circuit is connected with a read data signal output end and the second mode switching circuit is connected with a test mode selection circuit output end, the first ring-shaped oscillation circuit is formed;

3. The SRAM timing test circuit of claim 1 or 2, further comprising: and the input end of the edge signal trigger circuit is connected with the first mode switching circuit, and the output end of the edge signal trigger circuit is connected with the input end of the second mode switching circuit so as to generate an edge trigger signal according to the inversion of the digital signal output by the read data signal output end to form the first ring oscillator circuit and the second ring oscillator circuit.

4. The SRAM timing test circuit of claim 3, wherein the edge signal triggers the circuit to further perform a test mode selection; wherein the test mode comprises:

5. The SRAM timing test circuit of claim 1, wherein the test mode selection circuit comprises a first inverter and a second strobe;

6. The SRAM timing test circuit of claim 5, wherein the second mode switching circuit comprises a third gate-two, a fourth gate-two, and a second inverter;

7. The SRAM timing test circuit of claim 6, further comprising: and the input end of the delay circuit is connected with the output end of the first mode switching circuit, and the output end of the delay circuit is connected with the input end of the test mode selection circuit.

8. A memory comprising a dual port SRAM memory cell and the SRAM timing test circuit of any one of claims 1-7, wherein the SRAM timing test circuit is configured to measure a data read time of the dual port SRAM memory cell.

9. An SRAM timing test method applied to the SRAM timing test circuit of any one of claims 1-7, the method comprising:

10. The method of claim 9, wherein prior to obtaining the output oscillation period of the first ring oscillator circuit, further comprising:

11. The method of claim 10, wherein triggering via an external mode comprises: and controlling the second mode switching circuit to input an external test input clock signal, wherein the external test input clock signal triggers the SRAM storage unit to read the external address input signal.