CN106158044B - The test circuit and test method of SRAM access time - Google Patents
The test circuit and test method of SRAM access time Download PDFInfo
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Abstract
This application provides the test circuit of SRAM access time a kind of and test methods.The test circuit includes: SRAM memory, preset output circuit, additional test circuits and first mode switching circuit, and SRAM memory includes the first clock signal input terminal and reading data signal output end；Preset output circuit includes second clock signal input part, and second clock signal input part is connected with the first clock signal input terminal；The first end of additional test circuits is connected with second clock signal input part；The first input end of first mode switching circuit is connected with reading data signal output end, second input terminal is connected with second clock signal input part, the first clock signal input terminal, output end is connected with the second end of additional test circuits, wherein, first mode switching circuit includes enable signal end.The test circuit by the reference cycle with when real period make the difference and can accurately obtain access time of SRAM.
Description
Technical Field
The present disclosure relates to the field of static random access memories, and in particular, to a circuit and a method for testing access time of an SRAM.
Background
Static Random Access Memory (SRAM) is a common type of random access memory and is widely used in the field of integrated circuits. The access time is characterized by the effective delay from the rising edge of a clock signal (CLK) to output data (Q) in the read operation, and is an important access time parameter index for measuring the performance of the SRAM, so that the accurate measurement of the access time of the SRAM is crucial to IP verification.
In the prior art, a test structure as shown in fig. 1 is often used to measure the access time of the SRAM, and the method measures the access time by using the delay difference, and the principle is as follows: the access time of the SRAM is calculated by the delay of the delay chain by reducing the delay on the reference circuit from the correct sampling of the Q output of the SRAM by the latch (DFF) until the DFF cannot sample the correct data.
The structure has a measurement error caused by the self delay of the first-stage delay unit, which affects the measurement precision, the delay chain is formed by connecting a group of delay units in series, and the delay of the CLK signal is adjusted through the gear control signal, so that only the interval of the SRAM access time can be measured by the method, and an accurate value cannot be obtained.
In order to reduce the measurement error of the SRAM access time, a test circuit capable of accurately measuring the SRAM access time is needed.
Disclosure of Invention
The application aims to provide a test circuit and a test method for SRAM access time, so as to solve the problem that the access time of an SRAM cannot be accurately tested by a test structure in the prior art.
In order to achieve the above object, according to one aspect of the present application, there is provided a test circuit for SRAM access time, the test circuit including an SRAM memory, a preset output circuit, an additional test circuit, and a first mode switching circuit. The SRAM memory comprises a first clock signal input end and a read data signal output end and is used for reading and writing data; the preset output circuit comprises a second clock signal input end, wherein the second clock signal input end is connected with the first clock signal input end and is used for resetting the signal of the reading signal output end; an additional test circuit, a first end of which is connected with the second clock signal input end; and the first mode switching circuit is used for switching the test circuit into different working modes to calculate the access time of the SRAM, and comprises an enabling signal end.
Further, the first mode switching circuit employs a three-way gate, wherein a first input terminal is connected to the read data signal output terminal through a first inverter, a second input terminal is connected to an output terminal of the second mode switching circuit, and a third input terminal is directly connected to the read data signal output terminal.
Further, the additional test circuit includes a delay unit, an and gate, an or gate and a second inverter, wherein one input terminal of the and gate is connected to the output terminal of the first mode switching circuit, the other input terminal of the and gate is connected to the first clock signal input terminal, an input terminal of the second inverter is connected to the output terminal of the and gate, and an output terminal of the second inverter is connected to the input terminal of the delay unit; the output end of the delay unit is connected with one input end of the or gate, wherein the delay unit comprises a plurality of delay subunits which are sequentially connected end to end; the output terminal of the or gate is connected to the first input terminal of the second mode switching circuit.
In order to achieve the above object, according to another aspect of the present application, there is provided a method for testing an SRAM access time, for testing an SRAM by the above test circuit for an SRAM access time, the method comprising: measuring an output oscillation period of a first ring oscillator circuit, wherein the first ring oscillator circuit comprises an additional test circuit and a first mode switching circuit; measuring an output oscillation period of the second ring oscillation circuit, wherein the second ring oscillation circuit comprises an SRAM memory, a preset output circuit, an additional test circuit and a second mode switching circuit; and the output oscillation period of the first ring oscillation circuit is differed from the output oscillation period of the second ring oscillation circuit to obtain the time for reading the storage signal by the SRAM.
Further, the preset output circuit includes a signal reset terminal, the signal reset terminal includes a first signal reset terminal and a second signal reset terminal, and the measuring the output oscillation period of the second ring oscillator circuit includes: after receiving a clock signal, acquiring the state of a signal resetting end of the preset output circuit; judging whether the signal resetting end is effective or not according to the state; measuring a first oscillation period of the output of the second ring oscillator circuit when the first signal reset terminal is active; and measuring a second oscillation period of the second ring oscillator circuit output when the second signal reset terminal is active.
Further, measuring a first oscillation period of the output of the second ring oscillator circuit while the first signal reset terminal is active comprises: detecting a falling edge of the clock signal; resetting data at an output terminal of the SRAM memory to a low level signal when the falling edge is detected; when the rising edge adjacent to the falling edge is detected, the output end of the SRAM memory is changed from the low-level signal to a high-level signal; and taking the oscillation period output by the second ring oscillation circuit when the output end of the SRAM memory is a high level signal as the first oscillation period.
Further, measuring a second oscillation period of the second ring oscillator circuit output when the second signal reset terminal is active comprises: detecting a falling edge of the clock signal; resetting the data at the output end of the SRAM memory to a high level signal when the falling edge is detected; when the rising edge adjacent to the falling edge is detected, the output end of the SRAM memory is changed from the high-level signal to a low-level signal; and taking the oscillation period output by the second ring oscillation circuit when the output end of the SRAM memory is a low level signal as the second oscillation period.
Further, before measuring the output oscillation period of the first ring oscillation circuit, the SRAM access time testing method further includes: controlling the SRAM memory to read address data; and storing the read address data at the output end of the SRAM memory.
In order to achieve the above object, according to another aspect of the present invention, a storage medium is provided, where the storage medium includes a stored program, and when the program runs, a device on which the storage medium is located is controlled to execute the above described SRAM access time test method.
In order to achieve the above object, according to another aspect of the present invention, a processor for running a program is provided, wherein the program is run to execute the above SRAM access time testing method.
By applying the technical scheme of the application, the test circuit is switched into different working modes through the first mode switching circuit, when the second input end of the first mode switching circuit works, the first mode switching circuit and the additional test circuit form a reference circuit, and the working period of the reference circuit is measured to obtain a reference period; when the first input end of the first mode switching circuit works, the SRAM memory, the first mode switching circuit and the additional test circuit form a real-time circuit, the real-time period of the reading circuit is measured to obtain the real-time period, and the reference period is differed from the real-time period to obtain the access time of the SRAM, namely the access time. Because the access time of the SRAM is obtained by adjusting the delay of the CLK signal through the gear control signal CK _ SEL in the prior art, delay errors can be caused by adjusting the delay of the CLK signal, and the test circuit in the application measures the access time of the SRAM by making a difference between the reference period and the real-time period, thereby avoiding the influence of the error of the delay unit on the accuracy of the access time of the SRAM, solving the problem that the access time of the SRAM cannot be accurately measured in the prior art and achieving the effect of accurately measuring the access time of the SRAM.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate embodiments of the application and, together with the description, serve to explain the application and are not intended to limit the application. In the drawings:
FIG. 1 shows a schematic diagram of a prior art SRAM access time test circuit;
FIG. 2 shows a schematic diagram of a test circuit for SRAM access time of an embodiment;
FIG. 3 is a flow chart of a method for testing SRAM access time according to an embodiment of the present invention;
FIG. 4 shows a schematic diagram of an SRAM access time test circuit in accordance with a preferred embodiment of the present invention; and
fig. 5 shows a signal variation diagram of the SRAM access time test circuit.
Detailed Description
It should be noted that the following detailed description is exemplary and is intended to provide further explanation of the disclosure. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments according to the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, and it should be understood that when the terms "comprises" and/or "comprising" are used in this specification, they specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof, unless the context clearly indicates otherwise.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged under appropriate circumstances in order to facilitate the description of the embodiments of the invention herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Exemplary embodiments according to the present application will now be described in more detail with reference to the accompanying drawings. These exemplary embodiments may, however, be embodied in many different forms and should not be construed as limited to only the embodiments set forth herein. It is to be understood that these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and the same devices are denoted by the same reference numerals, and thus the description thereof will be omitted.
As described in the background of the invention, the test structure in the prior art cannot accurately measure the access time of the SRAM, and in order to solve the above problems, the present application provides a test circuit and method for the access time of the SRAM.
FIG. 2 is a schematic diagram of a test circuit for SRAM access time according to an embodiment of the present invention. As shown in fig. 2, the test circuit for SRAM access time includes an SRAM memory 10, a preset output circuit 30, an additional test circuit 50, and a first mode switching circuit 60. Wherein,
an SRAM memory 10 including a first clock signal input terminal 11 and a read data signal output terminal 13 for reading and writing data;
a preset output circuit 30, including a second clock signal input terminal 31, where the second clock signal input terminal 31 is connected to the first clock signal input terminal 11, and is used for resetting the signal at the read signal output terminal;
an additional test circuit 50, a first terminal 51 connected to the second clock signal input terminal 31;
a first mode switching circuit 60, a first input terminal 61 is connected to the read data signal output terminal 13, a second input terminal 63 is connected to the second clock signal input terminal 31 and the first clock signal input terminal 11, an output terminal 65 is connected to the second terminal 53 of the additional test circuit, for switching the test circuit into different operation modes to calculate the SRAM access time, and the first mode switching circuit 60 includes an enable signal terminal 67.
The test circuit switches the test circuit into different working modes through the first mode switching circuit, when the second input end of the first mode switching circuit works, the first mode switching circuit and the additional test circuit form a reference circuit, and the working period of the reference circuit is measured to obtain a reference period; when the first input end of the first mode switching circuit works, the SRAM memory, the first mode switching circuit and the additional test circuit form a real-time circuit, the real-time period of the reading circuit is measured to obtain the real-time period, and the reference period is differed from the real-time period to obtain the access time of the SRAM, namely the access time. Because the access time of the SRAM is obtained by adjusting the delay of the CLK signal through the gear control signal CK _ SEL in the prior art, delay errors can be caused by adjusting the delay of the CLK signal, and the test circuit in the application measures the access time of the SRAM by making a difference between the reference period and the real-time period, thereby avoiding the influence of the error of the delay unit on the accuracy of the access time of the SRAM, solving the problem that the access time of the SRAM cannot be accurately measured in the prior art and achieving the effect of accurately measuring the access time of the SRAM.
In order to better control the switching of the read/write modes of the SRAM cell, it is preferable that the test circuit further includes a second mode switching circuit, a first input terminal of which is connected to the first terminal of the additional test circuit, a second input terminal of which is used for receiving a write data signal, and an output terminal of which is connected to the second clock signal input terminal, and the second mode switching circuit includes an enable terminal. When the enable end is invalid, the second input end is gated by the second mode switching circuit, and the data is written into the SRAM unit by the first clock signal of the SRAM unit according to the write data signal of the second input end of the second mode switching circuit; when the enable terminal is valid, the second mode switching circuit gates the first input terminal to test the access time of the SRAM.
In a preferred embodiment of the present application, the test circuit preferably includes a first ring oscillator circuit and a second ring oscillator circuit, wherein the first ring oscillator circuit includes the first mode switching circuit, an additional test circuit, and a second mode switching circuit; the second ring oscillation circuit comprises the SRAM memory, the first mode switching circuit, the additional test circuit and the second mode switching circuit, so that the access time of the SRAM can be obtained quickly and accurately by testing the oscillation periods of the first ring oscillation circuit and the second ring oscillation circuit and then subtracting the periods of the first ring oscillation circuit and the second ring oscillation circuit.
In order to more accurately control the switching between different operating modes and further accurately measure the access time of the SRAM, it is preferable that the first mode switching circuit employs a three-way gate, in which a first input terminal is connected to the read data signal output terminal through a first inverter, a second input terminal is connected to the output terminal of the second mode switching circuit, and a third input terminal is directly connected to the read data signal output terminal.
In a preferred embodiment of the present application, it is preferable that the additional test circuit includes a delay unit, an and gate, an or gate, and a second inverter, wherein one input terminal of the and gate is connected to the output terminal of the first mode switching circuit, the other input terminal of the and gate is connected to the first clock signal input terminal, an input terminal of the second inverter is connected to the output terminal of the and gate, and an output terminal of the second inverter is connected to the input terminal of the delay unit; the output end of the delay unit is connected with one input end of the or gate, wherein the delay unit comprises a plurality of delay subunits which are sequentially connected end to end; the output terminal of the or gate is connected to the first input terminal of the second mode switching circuit. The additional test circuit not only comprises a delay unit, but also comprises an AND gate, an OR gate and a second inverter, and the addition of the logic circuits can more accurately control the working mode of the circuit, so that the access time of the SRAM can be more accurately measured.
FIG. 3 is a flow chart of a method for testing SRAM access time according to an embodiment of the present invention. As shown in fig. 3, the method for testing the access time of the SRAM includes the following steps:
step S102, measuring an output oscillation period of a first ring oscillation circuit, wherein the first ring oscillation circuit comprises an additional test circuit and a first mode switching circuit;
step S104, measuring the output oscillation period of the second ring oscillation circuit, wherein the second ring oscillation circuit comprises an SRAM memory, a preset output circuit, an additional test circuit and a second mode switching circuit;
and step S106, subtracting the output oscillation period of the first ring oscillation circuit from the output oscillation period of the second ring oscillation circuit to obtain the time for reading the storage signal by the SRAM.
In the test method, the first ring oscillation circuit does not comprise the SRAM memory and the preset output circuit in the second ring oscillation circuit, so that the period of the first ring oscillation circuit is shorter than the output oscillation period of the second ring oscillation circuit, the access time of the SRAM memory can be accurately obtained by subtracting the second ring oscillation circuit from the first ring oscillation circuit, the delay of a clock signal does not need to be adjusted through a gear control signal, and the influence of the delay of an additional test circuit in the prior art on the access time of an SRAM unit is further avoided.
In order to measure the time of the rising edge and the falling edge of the read storage signal of the SRAM memory at the same time, it is preferable that the preset output circuit includes a signal reset terminal, the signal reset terminal includes a first signal reset terminal and a second signal reset terminal, and the measuring the output oscillation period of the second ring oscillation circuit includes: after receiving a clock signal, acquiring the state of a signal resetting end of the preset output circuit; judging whether the signal resetting end is effective or not according to the state; measuring a first oscillation period of the output of the second ring oscillator circuit when the first signal reset terminal is active; and measuring a second oscillation period of the second ring oscillator circuit output when the second signal reset terminal is active.
The time for reading the low level and the high level of the SRAM is different, so in order to accurately obtain the time for reading the low level signal and the high level signal of the SRAM, the access time for reading the low level and the high level of the SRAM is respectively tested.
In a preferred embodiment of the present application, measuring a first oscillation period of the output of the second ring oscillator circuit when the first signal reset terminal is active comprises: detecting a falling edge of the clock signal; resetting data at an output terminal of the SRAM memory to a low level signal when the falling edge is detected; changing the output end of the SRAM memory from the low level signal to a high level signal when a rising edge adjacent to the falling edge is detected; and taking the oscillation period of the output of the second ring oscillation circuit measured when the output of the SRAM memory is at a high level signal as a first oscillation period. And the difference is made between the measured oscillation period of the first ring oscillation circuit and the first oscillation period, so that the time for reading the high-level signal in the storage signal by the SRAM can be accurately obtained.
In order to further accurately detect the second oscillation period of the output of the second ring oscillator circuit, it is preferable that measuring the second oscillation period of the output of the second ring oscillator circuit when the second signal reset terminal is active includes: detecting a rising edge of the clock signal; resetting data at an output terminal of the SRAM memory to a high level signal when the rising edge is detected; when a rising edge adjacent to the falling edge is detected, changing the output end of the SRAM memory from a high level signal to a low level signal; and taking the oscillation period output by the second ring oscillation circuit measured when the output end of the SRAM memory is a low level signal as the second oscillation period, and subtracting the measured oscillation period of the first ring oscillation circuit from the second oscillation period, so as to accurately obtain the time for the SRAM memory to read the low level signal in the storage signal.
In a preferred embodiment of the present application, before measuring the output oscillation period of the first ring oscillator circuit, the SRAM access time test method further preferably includes: controlling the SRAM memory to read address data; the read address data is stored at the output end of the SRAM memory, so that the subsequent test circuit can conveniently test the data access time of the SRAM memory.
In order to make the technical solutions of the present application more clear to those skilled in the art, the technical solutions of the present application will be described in detail by using the test circuit of fig. 4.
As shown in fig. 4, the test circuit for SRAM access time includes an SRAM memory 10, a preset output circuit 30, an additional test circuit 50, a three-way gate 70 and a two-way gate 90, the SRAM memory 10 includes a first clock signal input terminal 11 and a read data signal output terminal 13; the preset output circuit 30 comprises a second clock signal input terminal 31, a first signal reset terminal 33 and a second signal reset terminal 35, and the first clock signal input terminal 11 is connected with the second clock signal input terminal 31; the additional test circuit 50 comprises a delay cell 500, an and gate 510, an or gate 520 and a second inverter 530.
The three-way gate 70 comprises three input terminals, a first input terminal 71 is connected to the read data signal output terminal 75 through a first inverter 80, a second input terminal 73 is connected to an output terminal 97 of the two-way gate 90, a third input terminal 75 is directly connected to the read data signal output terminal 13, and the three-way gate 70 further comprises three enable signal terminals, namely a first enable signal terminal 77 and a second enable signal terminal 79; a third enable signal terminal 81; the two-way gate 90 includes a first input terminal 91, a second input terminal 93, an enable terminal 95 and an output terminal 97, the first input terminal 91 is connected to the first terminal 301 of the additional test circuit, the second input terminal 93 is used for receiving a write data signal, and the enable terminal 95 is used for receiving an enable signal.
When the signal of the enable terminal 95 of the two-way gate 90 is invalid, the two-way gate 90 gates the second input terminal 93, and the SRAM memory 10 performs a write operation.
When the signal of the enable terminal 95 of the two-way gate 90 is valid, the two-way gate 90 gates the first input terminal 91, and the three-way gate 70 gates the first enable signal terminal 77, so that the output terminal 97 of the two-way gate 90 is directly connected to the second input terminal 73 of the three-way gate 70, that is, the test circuit only includes the two-way gate 90, the three-way gate 70 and the additional test circuit 50 without passing through the SRAM memory 10 and the preset output circuit 30, to form a first ring oscillator circuit, and the signal change of the circuit is as shown in fig. 5, the frequency of the first ring oscillator circuit is measured, and the reference oscillation period T0 is further calculated.
When the signal of the enable terminal 95 of the two-way gate 90 is valid, the two-way gate 90 gates the first input terminal 91, the second enable signal terminal 77 or the third enable signal terminal 81 of the three-way gate 70 is valid, the output terminal thereof is connected to the first terminal of the additional test circuit 50, and the signal of the additional test circuit 50 is input to the first input terminal 91 of the two-way gate 90 through the second terminal thereof, so as to form a second oscillating circuit.
When detecting that the first clock signal of the SRAM memory 10 is a falling edge, the first signal reset terminal 33 of the preset output circuit 30 is asserted, the signal of the read data signal output terminal 13 is reset to a low level signal, the second enable signal terminal 77 of the three-way gate 70 is asserted, the second input terminal 73 of the three-way gate 70 is gated, the output signal of the three-way gate 70 is transmitted to the additional test circuit 50, the output signal is a signal stored in the SRAM, the output signal of the additional test circuit 50 is transmitted to the first input terminal 91 of the two-way gate 90, when the rising edge adjacent to the falling edge of the first clock signal is detected, the output end of the SRAM memory is changed from a low level signal to a high level signal, fig. 5 is a schematic diagram showing the signal change of the circuit at this time, and the frequency of the second ring oscillator circuit at this time is measured, and the first oscillation period T1 of the second ring oscillator circuit is further calculated.
When the first clock signal of the SRAM memory 10 is detected to be a falling edge, the second signal reset terminal 35 of the preset output circuit 30 is enabled, the signal of the read data signal output terminal 13 is reset to be a high level signal, the third enable signal terminal 79 of the three-way gate 70 is enabled, the third input terminal 75 of the three-way gate 70 is gated, the signal output by the three-way gate 70 is transmitted to the additional test circuit 50, the output signal is an inverted signal of the SRAM storage signal, the output signal of the additional test circuit 50 is transmitted to the first input terminal 91 of the two-way gate 90, when a rising edge adjacent to the falling edge of the first clock signal is detected, the output terminal of the SRAM memory is changed from the high level signal to a low level signal, the frequency of the second ring oscillator circuit at the moment is measured, and the second oscillation period of the second ring oscillator circuit is further calculated.
Finally, the first oscillation period of the second ring oscillation circuit is differed from the reference period, and the access time of the SRAM to the high-level signal in the stored signals is calculated; and the second oscillation period of the second ring oscillation circuit is differed from the reference period, and the access time of the SRAM to the low-level signal in the storage signals is calculated. According to fig. 5, the first oscillation period T1 is calculated to be 608ps, the reference period T0 is calculated to be 435ps, and thus the access time of the SRAM memory to the high level signal in the stored signal is calculated to be 173 ps.
From the above description, it can be seen that the above-described embodiments of the present application achieve the following technical effects:
1) the test circuit switches the test circuit into different working modes through the first mode switching circuit, when the second input end of the first mode switching circuit works, the first mode switching circuit and the additional test circuit form a reference circuit, and the working period of the reference circuit is measured to obtain a reference period; when the first input end of the first mode switching circuit works, the SRAM memory, the first mode switching circuit and the additional test circuit form a real-time circuit, the real-time period of the reading circuit is measured to obtain the real-time period, and the reference period is differed from the real-time period to obtain the access time of the SRAM, namely the access time. Because the access time of the SRAM is obtained by adjusting the delay of the CLK signal through the gear control signal CK _ SEL in the prior art, delay errors can be caused by adjusting the delay of the CLK signal, and the test circuit in the application measures the access time of the SRAM by making a difference between the reference period and the real-time period, thereby avoiding the influence of the error of the delay unit on the accuracy of the access time of the SRAM, solving the problem that the access time of the SRAM cannot be accurately measured in the prior art and achieving the effect of accurately measuring the access time of the SRAM.
2) According to the testing method, the first ring oscillation circuit does not comprise the SRAM and the preset output circuit in the second ring oscillation circuit, so that the period of the first ring oscillation circuit is shorter than the output oscillation period of the second ring oscillation circuit, the access time of the SRAM can be accurately obtained by subtracting the second ring oscillation circuit from the first ring oscillation circuit, the delay of a clock signal does not need to be adjusted through a gear control signal, and the influence of the delay of an additional testing circuit in the prior art on the access time of an SRAM unit is avoided.
In order to achieve the above object, according to another aspect of the present invention, an embodiment of the present invention further provides a storage medium, where the storage medium includes a stored program, where when the program runs, a device on which the storage medium is located is controlled to execute the above described SRAM access time test method.
In order to achieve the above object, according to another aspect of the present invention, an embodiment of the present invention further provides a processor, where the processor is configured to execute a program, where the program executes the above method for testing the SRAM access time.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (10)
1. A test circuit for SRAM access time, the test circuit comprising:
the SRAM memory comprises a first clock signal input end and a read data signal output end and is used for reading and writing data;
the preset output circuit comprises a second clock signal input end, wherein the second clock signal input end is connected with the first clock signal input end and is used for resetting the signal of the read data signal output end;
an additional test circuit, a first end of which is connected with the second clock signal input end; and
and the first mode switching circuit is connected with the read data signal output end, the second input end is connected with the second clock signal input end and the first clock signal input end, and the output end is connected with the second end of the additional test circuit and used for switching the test circuit into different working modes to calculate the access time of the SRAM, wherein the first mode switching circuit comprises an enabling signal end.
2. The test circuit of claim 1, further comprising a second mode switching circuit having a first input coupled to the first terminal of the additional test circuit, a second input for receiving a write data signal, and an output coupled to the second clock signal input, wherein the second mode switching circuit includes an enable terminal.
3. The test circuit of claim 2, wherein the test circuit comprises a first ring oscillator circuit and a second ring oscillator circuit, wherein,
the first ring oscillator circuit comprises the first mode switching circuit, an additional test circuit and a second mode switching circuit;
the second ring oscillation circuit includes the SRAM memory, a preset output circuit, a first mode switching circuit, an additional test circuit, and a second mode switching circuit.
4. The test circuit of claim 2, wherein the first mode switching circuit employs a three-way gate, wherein a first input is coupled to the read data signal output via a first inverter, a second input is coupled to the output of the second mode switching circuit, and a third input is coupled directly to the read data signal output.
5. The test circuit of claim 4, wherein the additional test circuit comprises a delay unit, an AND gate, an OR gate, and a second inverter, wherein,
one input end of the AND gate is connected with the output end of the first mode switching circuit, the other input end of the AND gate is connected with the first clock signal input end,
the input end of the second inverter is connected with the output end of the AND gate, and the output end of the second inverter is connected with the input end of the delay unit;
the output end of the delay unit is connected with one input end of the OR gate, wherein the delay unit comprises a plurality of delay subunits which are sequentially connected end to end;
the output end of the OR gate is connected with the first input end of the second mode switching circuit.
6. A method for testing SRAM access time, wherein the SRAM is tested by the SRAM access time testing circuit according to any one of claims 1 to 5, the method comprising:
measuring an output oscillation period of a first ring oscillator circuit, wherein the first ring oscillator circuit comprises a first mode switching circuit, an additional test circuit, and a second mode switching circuit;
measuring an output oscillation period of a second ring oscillation circuit, wherein the second ring oscillation circuit comprises an SRAM memory, a preset output circuit, a first mode switching circuit, an additional test circuit and a second mode switching circuit;
and subtracting the output oscillation period of the first ring oscillation circuit from the output oscillation period of the second ring oscillation circuit to obtain the time for reading the storage signal by the SRAM.
7. The method of claim 6, wherein the preset output circuit comprises a signal reset terminal, the signal reset terminal comprises a first signal reset terminal and a second signal reset terminal, and measuring the output oscillation period of the second ring oscillator circuit comprises:
after receiving a clock signal, acquiring the state of a signal resetting end of the preset output circuit;
judging whether the signal resetting end is effective or not according to the state;
measuring a first oscillation period of the second ring oscillator circuit output while the first signal reset terminal is active;
measuring a second oscillation period of the second ring oscillator circuit output while the second signal reset terminal is active.
8. The method of claim 7, wherein measuring a first oscillation period of the second ring oscillator circuit output while the first signal reset terminal is active comprises:
detecting a falling edge of the clock signal;
resetting data at an output terminal of the SRAM memory to a low level signal when the falling edge is detected;
when a rising edge adjacent to the falling edge is detected, setting the output end of the SRAM memory to be a high level signal from the low level signal; and
taking an oscillation period of the second ring oscillation circuit output measured when the output of the SRAM memory is the high level signal as the first oscillation period.
9. The method of claim 7, wherein measuring a second oscillation period of the second ring oscillator circuit output while the second signal reset terminal is active comprises:
detecting a falling edge of the clock signal;
resetting data at an output terminal of the SRAM memory to a high level signal when the falling edge is detected;
when a rising edge adjacent to the falling edge is detected, setting the output end of the SRAM memory to be a low level signal from the high level signal; and
and taking the oscillation period output by the second ring oscillation circuit measured when the output end of the SRAM memory is the low level signal as the second oscillation period.
10. The method of testing SRAM access time of claim 7, wherein prior to measuring the output oscillation period of the first ring oscillator circuit, the method of testing SRAM access time further comprises:
controlling the SRAM memory address and data;
storing data in an address of the SRAM memory.
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| CN106782669B (en) * | 2016-11-23 | 2020-04-10 | 上海华力微电子有限公司 | Self-calibration extensible SRAM delay test circuit |
| CN109192239A (en) * | 2018-07-25 | 2019-01-11 | 上海交通大学 | The on-chip test circuit and test method of SRAM memory |
| CN109726162B (en) * | 2019-02-28 | 2022-03-18 | 天津芯海创科技有限公司 | Self-adaptive parallel clock sequence detection device and method |
| CN110851331B (en) * | 2019-11-13 | 2021-11-16 | 中国电子科技集团公司第五十八研究所 | On-chip monitoring circuit of antifuse Field Programmable Gate Array (FPGA) |
| CN111341376B (en) * | 2020-03-11 | 2022-06-24 | 展讯通信（上海）有限公司 | SRAM (static random Access memory) timing sequence test circuit and test method |
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