CN110968148A - Timing calibration method and device and timer - Google Patents
Timing calibration method and device and timer Download PDFInfo
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Abstract
The invention relates to a timing calibration method, a device and a timer, wherein the method comprises the following steps: sampling an internal low-frequency clock signal of the timer by using a high-frequency clock signal; and calibrating the timer according to the sampling result. According to the technical scheme provided by the invention, the internal low-frequency clock signal of the timer is sampled by using the high-frequency clock signal, and the timer is calibrated according to the sampling result, so that the problem of inaccurate timing when the internal low-frequency clock signal of the timer triggers the timer to count time is solved, and the requirements of low cost and low power consumption of a user are met.
Description
Technical Field
The invention relates to the technical field of chip clock calibration, in particular to a timing calibration method, a timing calibration device and a timer.
Background
Clock sources for current IC (Integrated Circuit) chips include: an internal RC oscillator and an external crystal oscillator. Wherein the internal RC oscillator comprises: a HIRC high frequency oscillator and a LIRC low frequency oscillator; the external crystal oscillator includes: a HOSC high-frequency oscillator and a LOSC low-frequency oscillator; the external crystal oscillator has high crystal oscillation precision and is slightly influenced by temperature; the internal RC oscillator has low clock accuracy and is greatly affected by temperature.
The HIRC and LIRC inside the IC Chip are calibrated once at normal temperature during CP/FT (Chip combining/Final Test) so that the output clock frequency approaches a theoretical value, and the calibration value is written in OTP (One-time Password), which is used by the IC Chip later. But this calibration value is not modifiable, i.e. is only a calibration value at one temperature.
In practical applications, when an RTC (Real _ Time Clock) timer uses an external low-frequency Clock, timing is really accurate, but sometimes, in order to save an external low-frequency crystal oscillator, or in a low-power sleep mode, both the external crystal oscillator and the internal HIRC need to be turned off, and only the internal LIRC can be used. When the internal LIRC is used as a timing clock, the clock frequency has an error of about 2% due to the temperature influence, which inevitably results in inaccurate timing.
Disclosure of Invention
In order to overcome the problems in the related art at least to a certain extent, the invention provides a timing calibration method, a device and a timer, so as to solve the problem of inaccurate timing when a low-frequency clock signal in the timer triggers the timer to count time in the prior art.
According to a first aspect of the embodiments of the present invention, there is provided a timing calibration method, including:
sampling an internal low-frequency clock signal of the timer by using a high-frequency clock signal;
and calibrating the timer according to the sampling result.
Preferably, the calibrating the timer according to the sampling result includes:
calculating a compensation value according to the sampling result;
and reading the current time of the timer, and compensating the compensation value on the current time to obtain the calibrated time.
Preferably, the calculating a compensation value according to the sampling result includes:
acquiring the actual sampling times of the high-frequency clock signal within a preset sampling duration;
calculating the theoretical sampling times of the high-frequency clock signal within a preset sampling duration;
and calculating a compensation value according to the difference value of the actual sampling times and the theoretical sampling times.
Preferably, the compensating the compensation value at the current time includes:
if the actual sampling times are larger than the theoretical sampling times, increasing the absolute value of the compensation value at the current time; alternatively, the first and second electrodes may be,
and if the actual sampling times are less than the theoretical sampling times, reducing the absolute value of the compensation value at the current time.
Preferably, a ratio of the frequency of the high frequency clock signal to the frequency of the internal low frequency clock signal is greater than a preset value.
Preferably, the high frequency clock signal includes: an external high frequency clock signal of the timer.
Preferably, the sampling the internal low frequency clock signal of the timer by using the high frequency clock signal includes:
after the timer normally runs or after the timer is awakened from sleep, the internal low-frequency clock signal of the timer is sampled by using the high-frequency clock signal.
Preferably, the internal low frequency clock signal is a LIRC clock signal.
Preferably, the high frequency clock signal is a HOSC clock signal.
According to a second aspect of embodiments of the present invention, there is provided a timing calibration apparatus, including:
the sampling module is used for sampling an internal low-frequency clock signal of the timer by using a high-frequency clock signal;
and the calibration module is used for calibrating the timer according to the sampling result.
Preferably, the calibration module comprises:
the calculation module is used for calculating a compensation value according to the sampling result;
and the compensation module is used for reading the current time of the timer and compensating the compensation value on the current time to obtain the calibrated time.
Preferably, the calculation module is specifically configured to:
acquiring the actual sampling times of the high-frequency clock signal within a preset sampling duration;
calculating the theoretical sampling times of the high-frequency clock signal within a preset sampling duration;
and calculating a compensation value according to the difference value of the actual sampling times and the theoretical sampling times.
Preferably, the obtaining of the actual sampling times of the high-frequency clock signal within the preset sampling duration includes:
responding to the interruption of the sampling module, and obtaining the actual sampling times according to the interruption times;
alternatively, the first and second electrodes may be,
and reading the numerical value of the state register of the sampling module, and obtaining the actual sampling times according to the numerical value.
Preferably, the obtaining of the actual sampling times of the high-frequency clock signal within the preset sampling duration specifically includes:
and acquiring the actual sampling times of the high-frequency clock signal within the preset sampling duration through a counting register.
According to a third aspect of embodiments of the present invention, there is provided a timer, including: such as the timing calibration device described above.
The technical scheme provided by the embodiment of the invention can have the following beneficial effects:
the internal low-frequency clock signal of the timer is sampled by the high-frequency clock signal, and the timer is calibrated according to the sampling result, so that the problem of inaccurate timing when the internal low-frequency clock signal of the timer triggers the timer is solved, and the requirements of low cost and low power consumption of a user are met.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.
FIG. 1 is a flow chart illustrating a method of timing calibration according to an exemplary embodiment;
FIG. 2 is a waveform schematic diagram of a LIRC clock signal shown in accordance with an exemplary embodiment;
FIG. 3 is a waveform schematic diagram illustrating a LIRC clock signal being sampled, according to an exemplary embodiment;
FIG. 4 is a flow chart illustrating a method of timing calibration in accordance with another exemplary embodiment;
FIG. 5 is a schematic block diagram illustrating a timing calibration apparatus in accordance with an exemplary embodiment;
FIG. 6 is a schematic block diagram illustrating a timing calibration apparatus in accordance with another exemplary embodiment.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the invention, as detailed in the appended claims.
Fig. 1 is a flow chart illustrating a method of timing calibration, as shown in fig. 1, according to an exemplary embodiment, the method comprising:
step S11, sampling the internal low-frequency clock signal of the timer by using the high-frequency clock signal;
and step S12, calibrating the timer according to the sampling result.
It should be noted that the timing calibration method provided in this embodiment is suitable for use in an integrated chip.
According to the technical scheme, the internal low-frequency clock signal of the timer is sampled by the high-frequency clock signal, the timer is calibrated according to the sampling result, the problem that timing is inaccurate when the internal low-frequency clock signal of the timer triggers the timer is solved, and the requirements of low cost and low power consumption of a user are met.
Preferably, the calibrating the timer according to the sampling result includes:
calculating a compensation value according to the sampling result;
and reading the current time of the timer, and compensating the compensation value on the current time to obtain the calibrated time.
It can be understood that, in the technical scheme provided by this embodiment, the timer timing calibration method is simple, the operation is convenient, the implementation is easy, the cost is low, and the user experience is high.
Preferably, the calculating a compensation value according to the sampling result includes:
acquiring the actual sampling times of the high-frequency clock signal within a preset sampling duration;
calculating the theoretical sampling times of the high-frequency clock signal within a preset sampling duration;
and calculating a compensation value according to the difference value of the actual sampling times and the theoretical sampling times.
Preferably, the calculating a compensation value according to the difference between the actual sampling frequency and the theoretical sampling frequency specifically includes: according to the formula: the compensation value is (actual sampling number-theoretical sampling number)/theoretical sampling number, or the compensation value is (theoretical sampling number-actual sampling number)/theoretical sampling number.
It should be noted that the preset sampling duration is configured according to the user requirement.
It should be noted that, within the preset sampling duration, the actual sampling times of the high-frequency clock signal may be implemented by a counting register; the calculation of the theoretical sampling times of the high-frequency clock signal within the preset sampling duration can be realized by software. The technical scheme provided by the embodiment combines software and hardware, is convenient to operate and easy to implement, and has low cost and high user experience.
Preferably, the compensating the compensation value at the current time includes:
if the actual sampling times are larger than the theoretical sampling times, increasing the absolute value of the compensation value at the current time; alternatively, the first and second electrodes may be,
and if the actual sampling times are less than the theoretical sampling times, reducing the absolute value of the compensation value at the current time.
For ease of understanding, the following is illustrated:
the frequency of the high-frequency clock signal is assumed to be 8MHz, the frequency of the internal low-frequency clock signal of the timer is assumed to be 10KHz, and the preset sampling time duration is 1 s.
In the preset sampling duration 1s, the high-frequency clock signal should be sampled 8000000 times theoretically, and if the actual sampling number displayed by the counting register of the sampling module is greater than 8000000, which indicates that the sampling time of the high-frequency clock signal is longer, i.e., the low-frequency clock signal is slower, the error value (i.e., the absolute value of the compensation value) needs to be added to the current time, which is the time currently displayed by the timer (in seconds) (1+ (actual sampling number-8000000)/8000000).
Conversely, if the actual number of samples displayed by the count register of the sampling module is less than 8000000, indicating that the low frequency clock signal is faster, then the error value (i.e., the absolute value of the offset) needs to be subtracted from the current time, which is the time currently displayed by the timer (in seconds) (1- (8000000-actual number of samples)/8000000).
Preferably, a ratio of the frequency of the high frequency clock signal to the frequency of the internal low frequency clock signal is greater than a preset value.
It can be understood that the core of the timing calibration is to sample the low-frequency clock signal inside the timer by using the high-frequency clock signal with high precision to obtain a sampling value, then obtain a compensation value by means of software calculation, and obtain the calibrated timing data according to the compensation value. Because the low-frequency clock signal inside the timer is generally a signal of several KHz to several hundred KHz, the high-frequency clock signal is selected as a clock of MHz order as much as possible. If the frequency difference between the high-frequency clock signal and the low-frequency clock signal is not large, the timing calibration effect of the timer is greatly influenced.
It will be appreciated that the frequency of the high frequency clock signal should be at least 2 times the frequency of the low frequency clock signal, according to the sampling law.
Preferably, the high frequency clock signal includes: an external high frequency clock signal of the timer.
Preferably, the sampling the internal low frequency clock signal of the timer by using the high frequency clock signal includes:
after the timer normally runs or after the timer is awakened from sleep, the internal low-frequency clock signal of the timer is sampled by using the high-frequency clock signal.
It can be understood that, if the external high-frequency clock signal of the timer is used to sample the low-frequency clock signal inside the timer, the timing calibration of the timer can be realized only when the high-frequency clock signal exists. Therefore, after the timer normally runs or after the timer is awakened from sleep, the internal low-frequency clock signal of the timer is sampled by using the high-frequency clock signal.
Preferably, the internal low frequency clock signal is a LIRC clock signal.
Preferably, the high frequency clock signal is a HOSC clock signal.
Fig. 2 shows a waveform diagram of the low frequency clock signal as the LIRC clock signal. Referring to fig. 2, the count of the timer is incremented by 1 upon each rising edge of the LIRC clock signal. The frequency of the LIRC clock signal illustrated in fig. 2 is 10 KHz.
Fig. 3 shows a waveform diagram of the use of the HOSC clock signal to sample the biased LIRC clock signal. Referring to fig. 3, within a preset sampling time duration of 1 second, the HOSC clock signal samples the LIRC clock signal, and the counting register of the sampling module times the actual sampling times.
It can be understood that the external crystal oscillator and the internal HIRC need to be closed, only the internal LIRC clock signal can be used for timing, the high-precision HOSC clock signal is used for sampling the LIRC clock signal with deviation, a high-frequency clock signal is not required to be additionally introduced, the timing precision is improved through calibration compensation, the cost is low, the power consumption is low, and the user experience is high.
Fig. 4 is a flow chart illustrating a method of timing calibration, as shown in fig. 4, according to an example embodiment, the method comprising:
step S21, sampling the internal low-frequency clock signal of the timer by using the high-frequency clock signal;
step S22, acquiring the actual sampling times of the high-frequency clock signal within a preset sampling duration;
step S23, calculating the theoretical sampling times of the high-frequency clock signal within the preset sampling duration;
step S24, calculating a compensation value according to the difference value of the actual sampling times and the theoretical sampling times;
step S25, reading the current time of the timer;
step S26, if the actual sampling times are larger than the theoretical sampling times, the absolute value of the compensation value is increased in the current time;
step S27, if the actual sampling times are less than the theoretical sampling times, the absolute value of the compensation value is reduced at the current time;
and step S28, outputting the calibrated time.
Preferably, a ratio of the frequency of the high frequency clock signal to the frequency of the internal low frequency clock signal is greater than a preset value.
Preferably, the high frequency clock signal includes: an external high frequency clock signal of the timer.
Preferably, the sampling the internal low frequency clock signal of the timer by using the high frequency clock signal includes:
after the timer normally runs or after the timer is awakened from sleep, the internal low-frequency clock signal of the timer is sampled by using the high-frequency clock signal.
Preferably, the internal low frequency clock signal is a LIRC clock signal.
Preferably, the high frequency clock signal is a HOSC clock signal.
According to the technical scheme, the internal low-frequency clock signal of the timer is sampled by the high-frequency clock signal, the timer is calibrated according to the sampling result, the problem that timing is inaccurate when the internal low-frequency clock signal of the timer triggers the timer is solved, and the requirements of low cost and low power consumption of a user are met.
Fig. 5 is a schematic block diagram illustrating a timing calibration apparatus 100 according to an exemplary embodiment, the apparatus 100, as shown in fig. 5, comprising:
a sampling module 101, configured to sample an internal low-frequency clock signal of the timer by using a high-frequency clock signal;
and the calibration module 102 is configured to calibrate the timer according to the sampling result.
According to the technical scheme, the internal low-frequency clock signal of the timer is sampled by the high-frequency clock signal, the timer is calibrated according to the sampling result, the problem that timing is inaccurate when the internal low-frequency clock signal of the timer triggers the timer is solved, and the requirements of low cost and low power consumption of a user are met.
Referring to fig. 6, preferably, the calibration module 102 includes:
a calculating module 1021, configured to calculate a compensation value according to the sampling result;
the compensation module 1022 is configured to read a current time of the timer, and compensate the compensation value at the current time to obtain a calibrated time.
It can be understood that, in the technical scheme provided by this embodiment, the timer timing calibration method is simple, the operation is convenient, the implementation is easy, the cost is low, and the user experience is high.
Preferably, the calculating module 1021 is specifically configured to:
acquiring the actual sampling times of the high-frequency clock signal within a preset sampling duration;
calculating the theoretical sampling times of the high-frequency clock signal within a preset sampling duration;
and calculating a compensation value according to the difference value of the actual sampling times and the theoretical sampling times.
Preferably, the calculating a compensation value according to the difference between the actual sampling frequency and the theoretical sampling frequency specifically includes: according to the formula: the compensation value is (actual sampling number-theoretical sampling number)/theoretical sampling number, or the compensation value is (theoretical sampling number-actual sampling number)/theoretical sampling number.
It should be noted that the preset sampling duration is configured according to the user requirement.
Preferably, the obtaining of the actual sampling times of the high-frequency clock signal within the preset sampling duration includes:
responding to the interruption of the sampling module, and obtaining the actual sampling times according to the interruption times;
alternatively, the first and second electrodes may be,
and reading the numerical value of the state register of the sampling module, and obtaining the actual sampling times according to the numerical value.
Preferably, the obtaining of the actual sampling times of the high-frequency clock signal within the preset sampling duration specifically includes:
and acquiring the actual sampling times of the high-frequency clock signal within the preset sampling duration through a counting register.
It should be noted that, within the preset sampling duration, the actual sampling times of the high-frequency clock signal may be implemented by a counting register; the calculation of the theoretical sampling times of the high-frequency clock signal within the preset sampling duration can be realized by software. The technical scheme provided by the embodiment combines software and hardware, is convenient to operate and easy to implement, and has low cost and high user experience.
According to the technical scheme, the internal low-frequency clock signal of the timer is sampled by the high-frequency clock signal, the timer is calibrated according to the sampling result, the problem that timing is inaccurate when the internal low-frequency clock signal of the timer triggers the timer is solved, and the requirements of low cost and low power consumption of a user are met.
Preferably, the compensating the compensation value at the current time includes:
if the actual sampling times are larger than the theoretical sampling times, increasing the absolute value of the compensation value at the current time; alternatively, the first and second electrodes may be,
and if the actual sampling times are less than the theoretical sampling times, reducing the absolute value of the compensation value at the current time.
For ease of understanding, the following is illustrated:
the frequency of the high-frequency clock signal is assumed to be 8MHz, the frequency of the internal low-frequency clock signal of the timer is assumed to be 10KHz, and the preset sampling time duration is 1 s.
In the preset sampling duration 1s, the high-frequency clock signal should be sampled 8000000 times theoretically, and if the actual sampling number displayed by the counting register of the sampling module is greater than 8000000, which indicates that the sampling time of the high-frequency clock signal is longer, i.e., the low-frequency clock signal is slower, the error value (i.e., the absolute value of the compensation value) needs to be added to the current time, which is the time currently displayed by the timer (in seconds) (1+ (actual sampling number-8000000)/8000000).
Conversely, if the actual number of samples displayed by the count register of the sampling module is less than 8000000, indicating that the low frequency clock signal is faster, then the error value (i.e., the absolute value of the offset) needs to be subtracted from the current time, which is the time currently displayed by the timer (in seconds) (1- (8000000-actual number of samples)/8000000).
Preferably, a ratio of the frequency of the high frequency clock signal to the frequency of the internal low frequency clock signal is greater than a preset value.
It can be understood that the core of the timing calibration is to sample the low-frequency clock signal inside the timer by using the high-frequency clock signal with high precision to obtain a sampling value, then obtain a compensation value by means of software calculation, and obtain the calibrated timing data according to the compensation value. Because the low-frequency clock signal inside the timer is generally a signal of several KHz to several hundred KHz, the high-frequency clock signal is selected as a clock of MHz order as much as possible. If the frequency difference between the high-frequency clock signal and the low-frequency clock signal is not large, the timing calibration effect of the timer is greatly influenced.
It will be appreciated that the frequency of the high frequency clock signal should be at least 2 times the frequency of the low frequency clock signal, according to the sampling law.
Preferably, the high frequency clock signal includes: an external high frequency clock signal of the timer.
Preferably, the sampling the internal low frequency clock signal of the timer by using the high frequency clock signal includes:
after the timer normally runs or after the timer is awakened from sleep, the internal low-frequency clock signal of the timer is sampled by using the high-frequency clock signal.
It can be understood that, if the external high-frequency clock signal of the timer is used to sample the low-frequency clock signal inside the timer, the timing calibration of the timer can be realized only when the high-frequency clock signal exists. Therefore, after the timer normally runs or after the timer is awakened from sleep, the internal low-frequency clock signal of the timer is sampled by using the high-frequency clock signal.
Preferably, the internal low frequency clock signal is a LIRC clock signal.
Preferably, the high frequency clock signal is a HOSC clock signal.
A timer is shown according to an exemplary embodiment comprising: such as the timing calibration device described above.
According to the technical scheme, the internal low-frequency clock signal of the timer is sampled by the high-frequency clock signal, the timer is calibrated according to the sampling result, the problem that timing is inaccurate when the internal low-frequency clock signal of the timer triggers the timer is solved, and the requirements of low cost and low power consumption of a user are met.
It is understood that the same or similar parts in the above embodiments may be mutually referred to, and the same or similar parts in other embodiments may be referred to for the content which is not described in detail in some embodiments.
It should be noted that the terms "first," "second," and the like in the description of the present invention are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. Further, in the description of the present invention, the meaning of "a plurality" means at least two unless otherwise specified.
Any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing specific logical functions or steps of the process, and alternate implementations are included within the scope of the preferred embodiment of the present invention in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the present invention.
It should be understood that portions of the present invention may be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, the various steps or methods may be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, any one or combination of the following techniques, which are known in the art, may be used: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application specific integrated circuit having an appropriate combinational logic gate circuit, a Programmable Gate Array (PGA), a Field Programmable Gate Array (FPGA), or the like.
It will be understood by those skilled in the art that all or part of the steps carried by the method for implementing the above embodiments may be implemented by hardware related to instructions of a program, which may be stored in a computer readable storage medium, and when the program is executed, the program includes one or a combination of the steps of the method embodiments.
In addition, functional units in the embodiments of the present invention may be integrated into one processing module, or each unit may exist alone physically, or two or more units are integrated into one module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode. The integrated module, if implemented in the form of a software functional module and sold or used as a stand-alone product, may also be stored in a computer readable storage medium.
The storage medium mentioned above may be a read-only memory, a magnetic or optical disk, etc.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.
Claims (15)
1. A timing calibration method, comprising:
sampling an internal low-frequency clock signal of the timer by using a high-frequency clock signal;
and calibrating the timer according to the sampling result.
2. The method of claim 1, wherein calibrating the timer according to the sampling result comprises:
calculating a compensation value according to the sampling result;
and reading the current time of the timer, and compensating the compensation value on the current time to obtain the calibrated time.
3. The method of claim 2, wherein calculating the compensation value based on the sampling result comprises:
acquiring the actual sampling times of the high-frequency clock signal within a preset sampling duration;
calculating the theoretical sampling times of the high-frequency clock signal within a preset sampling duration;
and calculating a compensation value according to the difference value of the actual sampling times and the theoretical sampling times.
4. The method of claim 3, wherein the compensating the compensation value at the current time comprises:
if the actual sampling times are larger than the theoretical sampling times, increasing the absolute value of the compensation value at the current time; alternatively, the first and second electrodes may be,
and if the actual sampling times are less than the theoretical sampling times, reducing the absolute value of the compensation value at the current time.
5. The method of claim 1, wherein a ratio of the frequency of the high frequency clock signal to the frequency of the internal low frequency clock signal is greater than a predetermined value.
6. The method of claim 1,
the high frequency clock signal includes: an external high frequency clock signal of the timer.
7. The method of claim 1, wherein sampling the internal low frequency clock signal of the timer with the high frequency clock signal comprises:
after the timer normally runs or after the timer is awakened from sleep, the internal low-frequency clock signal of the timer is sampled by using the high-frequency clock signal.
8. The method according to any one of claims 1 to 7, wherein the internal low frequency clock signal is a LIRC clock signal.
9. The method according to any one of claims 1 to 7, wherein the high frequency clock signal is a HOSC clock signal.
10. A timing calibration device, comprising:
the sampling module is used for sampling an internal low-frequency clock signal of the timer by using a high-frequency clock signal;
and the calibration module is used for calibrating the timer according to the sampling result.
11. The apparatus of claim 10, wherein the calibration module comprises:
the calculation module is used for calculating a compensation value according to the sampling result;
and the compensation module is used for reading the current time of the timer and compensating the compensation value on the current time to obtain the calibrated time.
12. The apparatus of claim 11, wherein the computing module is specifically configured to:
acquiring the actual sampling times of the high-frequency clock signal within a preset sampling duration;
calculating the theoretical sampling times of the high-frequency clock signal within a preset sampling duration;
and calculating a compensation value according to the difference value of the actual sampling times and the theoretical sampling times.
13. The apparatus of claim 12, wherein obtaining the actual number of samples of the high frequency clock signal within the preset sampling duration comprises:
responding to the interruption of the sampling module, and obtaining the actual sampling times according to the interruption times;
alternatively, the first and second electrodes may be,
and reading the numerical value of the state register of the sampling module, and obtaining the actual sampling times according to the numerical value.
14. The apparatus according to claim 12 or 13, wherein the actual sampling times of the high-frequency clock signal within the preset sampling duration are specifically:
and acquiring the actual sampling times of the high-frequency clock signal within the preset sampling duration through a counting register.
15. A timer, comprising: a timing calibration device according to any one of claims 10 to 14.
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| CN112419628A (en) * | 2020-11-20 | 2021-02-26 | 深圳市捷诚技术服务有限公司 | RTC (real time clock) calibration method and device, computer readable medium and POS (point of sale) machine |
| CN113805463A (en) * | 2021-09-08 | 2021-12-17 | 珠海格力电器股份有限公司 | Method for calibrating timing time of air conditioner |
| CN114138056A (en) * | 2021-11-04 | 2022-03-04 | 珠海格力节能环保制冷技术研究中心有限公司 | Display terminal clock calibration method and device and display terminal |
| CN114860323A (en) * | 2022-05-20 | 2022-08-05 | 重庆御芯微信息技术有限公司 | Low-power-consumption accurate timing awakening method and device |
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| CN112419628A (en) * | 2020-11-20 | 2021-02-26 | 深圳市捷诚技术服务有限公司 | RTC (real time clock) calibration method and device, computer readable medium and POS (point of sale) machine |
| CN113805463A (en) * | 2021-09-08 | 2021-12-17 | 珠海格力电器股份有限公司 | Method for calibrating timing time of air conditioner |
| CN114138056A (en) * | 2021-11-04 | 2022-03-04 | 珠海格力节能环保制冷技术研究中心有限公司 | Display terminal clock calibration method and device and display terminal |
| CN114138056B (en) * | 2021-11-04 | 2024-05-17 | 珠海格力节能环保制冷技术研究中心有限公司 | Display terminal clock calibration method and device and display terminal |
| CN114860323A (en) * | 2022-05-20 | 2022-08-05 | 重庆御芯微信息技术有限公司 | Low-power-consumption accurate timing awakening method and device |
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