CN114860323A - Low-power-consumption accurate timing awakening method and device - Google Patents

Low-power-consumption accurate timing awakening method and device Download PDF

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CN114860323A
CN114860323A CN202210550456.XA CN202210550456A CN114860323A CN 114860323 A CN114860323 A CN 114860323A CN 202210550456 A CN202210550456 A CN 202210550456A CN 114860323 A CN114860323 A CN 114860323A
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frequency clock
timing
low
time
clock
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段文亮
祝顺宇
黎光洁
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Chongqing Yuxin Micro Information Technology Co ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/4401—Bootstrapping
    • G06F9/4418—Suspend and resume; Hibernate and awake
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/14—Time supervision arrangements, e.g. real time clock
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/324—Power saving characterised by the action undertaken by lowering clock frequency
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

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Abstract

The invention discloses a low-power consumption accurate timing awakening method and device. The method comprises the steps of firstly calibrating an unknown low-frequency clock under the current working condition, and then respectively calculating the required low-frequency clock timing time and high-frequency clock timing time according to the set sleep time, wherein the complete timing period number of the low-frequency clock which can be closest to the set sleep time is taken, and the complete timing period number of the high-frequency clock which can oscillate is taken as the rest time. After the system enters the sleep mode, the low-frequency clock is used for timing, the low-frequency clock is stopped and started after the set timing time is reached, and the wake-up is executed after the high-frequency clock reaches the set timing time. The invention adopts the low-frequency clock with low power consumption to realize the precision close to the timing of adopting the high-frequency clock, and can ensure that the system is always kept in a very low power consumption state when in dormancy.

Description

Low-power-consumption accurate timing awakening method and device
Technical Field
The invention relates to the field of microcontroller control, in particular to a method and a device for accurately waking up a microcontroller system when the microcontroller system enters a low-power-consumption sleep state.
Background
In a long-time idle state, a microcontroller system usually enters a low-power-consumption sleep state in order to save energy, most of modules and a high-frequency working clock are in a closed state at the moment, and only a low-frequency clock module is kept in a working state; when the preset time is reached or other awakening events occur, the microcontroller can rapidly enter a normal working state.
In the prior art, a low-frequency clock counter is generally adopted to complete a timing wake-up function in a low-power consumption mode, and the method has the biggest problem that the timing precision of a low-frequency clock is very low, so that the requirement of an application scene needing accurate time wake-up cannot be met.
In order to save cost, the precision of a low-speed clock provided in a microcontroller system is generally poor, and under different working conditions, the cycle deviation of each clock period caused by frequency deviation is very large relative to the cycle deviation of a high-frequency system clock, and the cycle deviation and the high-frequency system clock are not in the same order of magnitude, but the problem is particularly serious in a microcontroller system only providing an RC clock source.
Therefore, in general, the sleep wake-up timing in the current microcontroller system is not accurate enough, and it is impossible to use a high frequency clock for timing wake-up in order to realize low power consumption sleep. The invention considers that the precision of the high-frequency clock can be used for assisting the low-frequency clock to realize precise timing, thereby not only improving the timing precision, but also meeting the requirements of low power consumption.
Disclosure of Invention
The invention aims to: in order to solve the existing problems, a low-power-consumption accurate timing wake-up method is provided, so that in a system sleep stage, the low-frequency clock with low precision (low power consumption) reaches or approaches the timing precision of the high-frequency clock, and thus the low-power-consumption accurate timing wake-up of a microcontroller system is realized.
The technical scheme adopted by the invention is as follows:
a low-power consumption accurate timing wake-up method comprises the following steps:
calibrating a low-frequency clock;
respectively calculating the timing time of a low-frequency clock and the timing time of a high-frequency clock according to the set sleep time, and timing, wherein the sum of the timing time duration of the low-frequency clock and the timing time duration of the high-frequency clock is equal to or approximately equal to the set sleep time;
and performing awakening when the timing reaches the sum of the timing duration of the low-frequency clock and the high-frequency clock.
According to the method, the calibrated low-frequency clock is used for sleep timing, and the high-frequency clock is used for assisting in timing the remaining time, so that the timing accuracy is improved. Since the timing still mainly uses the low-frequency clock, the timing wake-up process is still in a low power consumption state as a whole.
Further, the low frequency clock is calibrated by using a high frequency clock.
Furthermore, when timing, a low-frequency clock is used for timing, and then a high-frequency clock is used for timing.
Further, the low frequency clock is set to perform timing with the maximum number of complete timing cycles in the set sleep time, and the high frequency clock is set to perform timing with the maximum number of complete timing cycles in the rest sleep time.
Further, the sum of the timing durations of the low-frequency clock and the high-frequency clock is equal to or approximately equal to the set sleep time, and the method includes:
the difference between the sum of the timing duration of the low-frequency clock and the high-frequency clock and the set sleep time does not exceed the timing period of one high-frequency clock, and the timing period numbers of the low-frequency clock and the high-frequency clock are both natural numbers.
In order to achieve the above object, the present invention further provides a low power consumption precise timing wake-up device, which includes a low frequency clock calibration unit, a timing setting unit, a timing unit and a wake-up unit, which are connected in sequence, wherein:
the low frequency clock calibration unit is configured to: the low frequency clock is calibrated.
The timing setting unit is configured to: receiving the set sleep time, and respectively calculating the timing time of the low-frequency clock and the high-frequency clock according to the set sleep time, wherein the sum of the timing duration of the low-frequency clock and the timing duration of the high-frequency clock is equal to or approximately equal to the set sleep time.
The timing unit is configured to: sequentially timing according to the calculated timing time of the low-frequency clock and the timing time of the high-frequency clock; the sequential execution is to execute the timing of one clock first and then execute the timing of the other clock, and the two timings are continuous.
The wake-up unit is configured to: and performing awakening when the timing unit finishes timing.
Further, the low frequency clock calibration unit calibrates the low frequency clock using the high frequency clock.
Further, the timing unit performs low frequency clock timing first and then performs high frequency clock timing.
Further, the timing setting unit performs timing setting on the low-frequency clock by using the maximum number of complete timing cycles that the low-frequency clock can execute in the set sleep time, and performs timing setting on the high-frequency clock by using the maximum number of complete timing cycles that the high-frequency clock can execute in the remaining sleep time.
Further, the difference between the sum of the timing durations of the low-frequency clock and the high-frequency clock calculated by the timing setting unit and the set sleep time does not exceed a timing period of one high-frequency clock, and the timing periods of the low-frequency clock and the high-frequency clock calculated by the timing setting unit are both natural numbers.
In summary, due to the adoption of the technical scheme, the invention has the beneficial effects that:
the invention obtains relatively accurate low-frequency clock frequency information by dynamically calibrating the system low-frequency clock before entering the sleep every time, and then divides the timing awakening time into a low-frequency timing (counting) part and a high-frequency timing (counting) part, thereby realizing the effect of approximately and completely using the high-frequency clock with high precision by using the low-frequency clock with low power consumption.
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The invention will now be described, by way of example, with reference to the accompanying drawings, in which:
FIG. 1 is a flow chart of a low power consumption precise timing wake-up method of the present invention.
FIG. 2 is a timing diagram of a phase of calibrating a low frequency clock.
Fig. 3 is a timing diagram of a sleep wake-up phase.
Fig. 4 is a flowchart of a preferred embodiment of the low power consumption accurate timing wake-up method of the present invention.
Detailed Description
All of the features disclosed in this specification, or all of the steps in any method or process so disclosed, may be combined in any combination, except combinations of features and/or steps that are mutually exclusive.
Any feature disclosed in this specification (including any accompanying claims, abstract) may be replaced by alternative features serving equivalent or similar purposes, unless expressly stated otherwise. That is, unless expressly stated otherwise, each feature is only an example of a generic series of equivalent or similar features.
Example one
As shown in fig. 1, the present embodiment provides a low power consumption precise timing wake-up method, including:
and S1, calibrating the low-frequency clock.
The calibrated low frequency clock is the frequency of the calibrated low frequency clock.
The low frequency clock may be calibrated by a pulse train of known duration and number/frequency of pulses, which may be preconfigured, with each calibration being invoked.
In some embodiments, the low-frequency clock may be assumed to be stable for a considerable period of time, with a fixed unknown frequency deviation, so that the high-frequency clock may be used to calibrate the current low-frequency clock before the system goes to sleep.
Specifically, as shown in fig. 2, in the low frequency clock calibration, it is assumed that the high frequency clock frequency is f 0 Unknown frequency of low frequency clock to be calibrated under current operating conditionsA rate of f x The calibration duration is N low frequency clock cycles (i.e., timing cycles). Assuming that the count value of the high-frequency clock counter is a in the calibration time, the relationship between the high-frequency clock and the low-frequency clock under the current working condition can be derived, as shown in formula (1).
Figure BDA0003654885610000051
Thus, the unknown low-frequency clock frequency f under the current working condition can be known x Comprises the following steps:
Figure BDA0003654885610000052
thereby enabling calibration of the low frequency clock. Calibration of the low frequency clock is performed each time the system goes to sleep.
And S2, respectively calculating the timing time of the low-frequency clock and the high-frequency clock according to the set sleep time and timing, wherein the sum of the timing time duration of the low-frequency clock and the timing time duration of the high-frequency clock is equal to or approximately equal to the set sleep time.
So-called approximately equal, i.e. maximally close to equal. In some embodiments, the number of the timing periods (i.e. oscillating for one period) of the low-frequency clock and the high-frequency clock are both integers, and the difference between the sum of the timing durations of the low-frequency clock and the high-frequency clock and the set sleep time does not exceed one timing period of the high-frequency clock. That is, even when the low frequency clock and the high frequency clock are used for timing, the timing cannot be exactly equal to the set sleep time (actually, the timing cannot be equal in many cases), and the difference in timing does not exceed the clock cycle of one high frequency clock.
The timing process can be understood as dividing the timing process into two parts, one part is clocked by a low-frequency clock, and the remaining part is clocked by a high-frequency clock, specifically, the low-frequency clock is used for timing first, and then the high-frequency clock is used for timing, as shown in fig. 3. The low frequency clock timing and the high frequency clock timing can be performed by timing the low frequency clock and the high frequency clock, and can also be performed by counting the low frequency clock and the high frequency clock, which is easier to be implemented in a microcontroller system.
In some embodiments, the low frequency clock is clocked for a maximum number of full clock cycles in a set sleep time, and the high frequency clock is clocked for a maximum number of full clock cycles in the remaining sleep time (i.e., the set sleep time minus the low frequency clock's clock time). As mentioned above, for the timing of waking up, the counting is mostly implemented by counting, i.e. the clock counts one cycle to perform one counting, and then one counting is added to the other counting cycle, and the subsequent process is added up, and when the counting reaches the set value, the waking up (system) is performed. In this regard, the timing of the present embodiment can be implemented as follows:
as shown in FIG. 4, in the system sleep phase, assuming the required precise timing wake-up time is T, the timing process is divided into two timing periods, one part is the timing period value B counted by the low frequency clock l A part of the timing period value B counted by a high frequency clock h As shown in formula (3), wherein B h 、B l Are all non-negative integers (natural numbers).
Figure BDA0003654885610000061
Solving equation B for equation (3) l Can then solve the set value B of the high-frequency counter h The obtained solutions are respectively shown as formulas (4) and (5)
Figure BDA0003654885610000062
Figure BDA0003654885610000063
Thereby obtaining the timing period value B of the low-frequency clock l And a value B of the timing period of the high frequency clock h 。
And a timing mode is a mode of recording time length. The frequency of the low frequency clock is calibrated, and the corresponding clock period can be known, so that the complete timing period duration of the low frequency clock closest to T can be calculated, and then the complete timing period duration of the high frequency clock closest to the rest time can be calculated.
And S3, when the timing reaches the sum of the timing duration of the low-frequency clock and the high-frequency clock, waking up.
After the system enters the sleep mode, the high-frequency clock is turned off, the system is timed by the low-frequency clock, and when the clock count value (which is realized by adopting a counter and counts one in one clock period) reaches a set timing period value B l When the high-frequency clock is started, the low-frequency clock is stopped to time, then the high-frequency clock is continuously used for finishing the timing of the rest sleep time, and the clock count value of the high-frequency clock reaches a set timing period value B h Then, a wake-up signal is generated to wake up the microcontroller system. In fact, the high frequency clock may be set to be clocked first, and then clocked by the low frequency clock, which is also applicable to the subsequent device embodiments.
Of course, the timing process may also be implemented without counting, or may be implemented directly by accumulating time, and the above counting is converted into time. The method comprises the steps of timing a low-frequency clock, starting the high-frequency clock when the timing reaches a set time length (realized by adopting a timer and calculated by a clock counter and a single timing period time length), stopping the timing of the low-frequency clock, finishing the timing of the rest sleep time by the high-frequency clock subsequently, and generating a wake-up signal when the timing reaches a set value.
Example two
The embodiment provides a low-power consumption accurate timing awakening device which comprises a low-frequency clock calibration unit, a timing setting unit, a timing unit and an awakening unit, wherein the units are sequentially connected in the sequence.
The low frequency clock calibration unit is configured to calibrate the low frequency clock.
Referring to embodiment one, for calibration of the low frequency clock, the low frequency clock may be calibrated by pre-configuring a pulse sequence with a known duration and number/frequency of pulses. In some embodiments, the current low frequency clock is calibrated with the high frequency clock before the system goes to sleep:
in low frequency clock calibration, assume a high frequency clock frequency of f 0 The unknown frequency of the low-frequency clock to be calibrated under the current working condition is f x The calibration duration is N low frequency clock cycles (i.e., timing cycles). Assuming that the count value of the high-frequency clock counter is a in the calibration time, the relationship between the high-frequency clock and the low-frequency clock under the current working condition can be derived, as shown in formula (1).
Figure BDA0003654885610000071
Thus, the unknown low-frequency clock frequency f under the current working condition can be known x Comprises the following steps:
Figure BDA0003654885610000081
thereby enabling calibration of the low frequency clock.
The timing setting unit is configured to receive a set sleep time, and calculate timing times of the low-frequency clock and the high-frequency clock respectively according to the set sleep time, wherein the sum of timing durations of the low-frequency clock and the high-frequency clock is equal to or approximately equal to the set sleep time.
In some embodiments, the difference between the sum of the timing durations of the low-frequency clock and the high-frequency clock calculated by the timing setting unit and the set sleep time does not exceed a timing period of one high-frequency clock, and the timing periods of the low-frequency clock and the high-frequency clock calculated by the timing setting unit are both natural numbers.
The timing process is divided into two parts, and the timing setting unit respectively sets the timing parameters of the low-frequency clock and the high-frequency clock. The timing setting unit may set to perform the low frequency clock timing first and then perform the high frequency clock timing. If the counting mode is adopted for timing, firstly setting the timing period number of the low-frequency clock, and then setting the timing period number of the high-frequency clock; if the timing is carried out in a time length counting mode, the timing time length of the low-frequency clock is set firstly, and then the timing time length of the high-frequency clock is set.
In some embodiments, the timing setting unit performs timing setting on the low frequency clock by the maximum number of complete timing cycles that the low frequency clock can perform in the set sleep time, and performs timing setting on the high frequency clock by the maximum number of complete timing cycles that the high frequency clock can perform in the rest sleep time. Taking the example by way of counting, in the system sleep stage, assuming the required precise timing wake-up time is T, the timing process is decomposed into two timing cycles, and one part is the timing cycle value B counted by the low frequency clock l A part of the timing period value B counted by a high frequency clock h As shown in formula (3), wherein B h 、B l Are all non-negative integers (natural numbers).
Figure BDA0003654885610000082
Solving equation B for equation (3) l Can then solve the set value B of the high-frequency counter h The obtained solutions are respectively shown as formulas (4) and (5)
Figure BDA0003654885610000091
Figure BDA0003654885610000092
Thereby obtaining the timing period value B of the low-frequency clock l And a value B of the timing period of the high frequency clock h 。
The timing unit is configured to sequentially perform timing according to the calculated timing time of the low frequency clock and the timing time of the high frequency clock, namely, one timing is followed by the other timing after the timing of the other timing is finished.
Similarly, corresponding to the counting mode, after the system is in a sleep state, the timing unit firstly starts the low-frequency clock, closes the high-frequency clock, records the timing period number of the low-frequency clock, and when the clock count value (realized by adopting a counter, one clock period counts one) reaches the set timing period value B l Then, turning on the high-frequency clock, stopping the low-frequency clock, and continuing to finish the timing of the rest sleep time by the high-frequency clock, wherein the timing period value of the high-frequency clock is B h In the clock count value of the low frequency clock reaches B l Then, the clock count value of the high frequency clock reaches B h When it is, the timing ends.
For the above-mentioned calculation of the timing time of the low frequency clock and the high frequency clock respectively, it can be understood that the timing time of the low frequency clock and the timing time of the high frequency clock are calculated respectively. The method comprises the steps of timing a low-frequency clock, starting a high-frequency clock when the timing reaches a set time length (realized by adopting a timer and calculated by a clock counter and a single timing period time length) after a plurality of complete timing periods, stopping the timing of the low-frequency clock, and finishing the timing of the rest sleep time by the high-frequency clock subsequently, wherein the high-frequency clock also performs the timing by a plurality of natural timing periods.
The wake-up unit is configured to perform a wake-up at the end of the timing unit.
Similarly, for the counting timing mode, the wake-up unit counts the number of the generated low-frequency clock and the number of the generated high-frequency clock, and when the clock count value of the low-frequency clock reaches a set value B l And the clock count value of the high frequency clock reaches B h A wake-up signal is generated. For the timing mode of recording the time length, the awakening unit counts the timing time length of the generated low-frequency clock and the timing time length of the high-frequency clock,when the timing duration of the low-frequency clock reaches B l Corresponding time length, and the timing time length of the high-frequency clock reaches B h And generating a wake-up signal when the corresponding time length is longer.
The invention is not limited to the foregoing embodiments. The invention extends to any novel feature or any novel combination of features disclosed in this specification and any novel method or process steps or any novel combination of features disclosed.

Claims (10)

1. A low-power consumption accurate timing wake-up method is characterized by comprising the following steps:
calibrating a low-frequency clock;
respectively calculating the timing time of a low-frequency clock and the timing time of a high-frequency clock according to the set sleep time, and timing, wherein the sum of the timing time duration of the low-frequency clock and the timing time duration of the high-frequency clock is equal to or approximately equal to the set sleep time;
and performing awakening when the timing reaches the sum of the timing duration of the low-frequency clock and the high-frequency clock.
2. The low power consumption precision timed wake-up method according to claim 1, characterized in that the low frequency clock is calibrated with a high frequency clock.
3. The low power consumption precisely timed wake-up method according to claim 1, characterized in that in the timing, the low frequency clock is used for timing first, and then the high frequency clock is used for timing.
4. The low power consumption precision timed wake-up method according to claim 1, wherein the low frequency clock is timed to perform the most complete number of timing cycles within a set sleep time, and the high frequency clock is timed to perform the most complete number of timing cycles within the remaining sleep time.
5. The low-power consumption precisely timed wake-up method according to claim 1, wherein the sum of the timing durations of the low-frequency clock and the high-frequency clock is equal to or approximately equal to the set sleep time, including:
the difference between the sum of the timing duration of the low-frequency clock and the high-frequency clock and the set sleep time does not exceed the timing period of one high-frequency clock, and the timing period numbers of the low-frequency clock and the high-frequency clock are both natural numbers.
6. The utility model provides a low-power consumption accurate timing awakening device, its characterized in that, including the low frequency clock calibration unit, timing setting unit, timing unit and the awakening unit who connects gradually, wherein:
the low frequency clock calibration unit is configured to: calibrating a low-frequency clock;
the timing setting unit is configured to: receiving set sleep time, and respectively calculating the timing time of a low-frequency clock and a high-frequency clock according to the set sleep time, wherein the sum of the timing time duration of the low-frequency clock and the timing time duration of the high-frequency clock is equal to or approximately equal to the set sleep time;
the timing unit is configured to: sequentially timing according to the calculated timing time of the low-frequency clock and the timing time of the high-frequency clock;
the wake-up unit is configured to: and performing awakening when the timing unit finishes timing.
7. The low power consumption precision timed wake-up unit according to claim 6, characterized in that said low frequency clock calibration unit calibrates the low frequency clock with a high frequency clock.
8. The low power consumption precisely timed wake-up unit according to claim 6, wherein the timing unit performs low frequency clock timing before performing high frequency clock timing.
9. The low power consumption precisely timed wake-up unit according to claim 6, wherein the timing setting unit sets the low frequency clock for the maximum number of complete timing cycles that the low frequency clock can perform during the set sleep time, and sets the high frequency clock for the maximum number of complete timing cycles that the high frequency clock can perform during the remaining sleep time.
10. The low power consumption precise timing wake-up device according to claim 6, wherein the difference between the sum of the timing durations of the low frequency clock and the high frequency clock calculated by the timing setting unit and the set sleep time does not exceed a timing period of a high frequency clock, and the number of the timing periods of the low frequency clock and the high frequency clock calculated by the timing setting unit is a natural number.
CN202210550456.XA 2022-05-20 2022-05-20 Low-power-consumption accurate timing awakening method and device Pending CN114860323A (en)

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CN111669812A (en) * 2020-05-29 2020-09-15 上海橙群微电子有限公司 Low-power-consumption Bluetooth chip, equipment, dormancy awakening control method of equipment and communication system

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