CN105703749B - A kind of accurate doze output circuit of low-power consumption and method - Google Patents
A kind of accurate doze output circuit of low-power consumption and method Download PDFInfo
- Publication number
- CN105703749B CN105703749B CN201410683200.1A CN201410683200A CN105703749B CN 105703749 B CN105703749 B CN 105703749B CN 201410683200 A CN201410683200 A CN 201410683200A CN 105703749 B CN105703749 B CN 105703749B
- Authority
- CN
- China
- Prior art keywords
- clock
- timing
- circuit
- signal
- low
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Abstract
The present invention relates to a kind of accurate doze output circuits of low-power consumption, including high frequency clock source, low-frequency clock source, clock status indicating circuit, control circuit, timer, high frequency timing margin calculator, low frequency timing margin calculator, comparator, timing results decision device.Its method is to complete suspend mode timing by the automatic switchover of two timers.Circuit of the present invention is using circuit structures such as high frequency timer, low frequency timer, clock status indicating circuit, control circuit, high frequency timing margin calculator, low frequency timing margin calculators, using the method for hardware controls high frequency timer, low frequency timer, solve the disadvantage that tradition needs to switch over by processor, reduce processor resource expense, timing accuracy is improved, system power dissipation is reduced.
Description
Technical field
The present invention relates to a kind of accurate doze output circuit of low-power consumption and methods, and specifically one kind is towards on piece system
Irrespective of size chip, the doze output circuit and method that power consumption can be effectively reduced, accurate timing is provided.
Background technology
Timing problems are a very common problems in embedded system.Different embeded processors includes difference
Timing unit, the application of no system need different timing application.Common timer-type include general timer,
Input pulse length timer, output pulse timer, multi input/output timer, the timer etc. combined with function module.
It is then more varied for the timer-type of application, such as transmission timer, receive timer, doze output, it is real-time when
Clock timer etc..
Doze output is the type in timer.Ideal doze output operation principle is usually to stop in system
One timing is set before sleeping, is activated in suspend mode, system carries out dormant state later；When doze output run to it is pre-
If timing after, generate wake-up signal, system is waken up under this signal, starts to work later.Ideal suspend mode timing
Device is actually infeasible, and high-precision timing needs high-frequency clock signal, excessively high frequency to consume larger power consumption.Such as
Fruit uses relatively low timing frequency, then the precision of timing is unable to reach requirement.The solution of this problem needs processor to assist at present
Timer solves, and after suspend mode, by low-frequency runs, solves the problems, such as that power consumption is larger；Upon awakening, by high-frequency
Runs, supply the surplus of low frequency timer count.This mode solves power consumption and precision to a certain extent
The problem of, but still it is undesirable, reason has the following aspects：The participation of processor still will produce unnecessary power consumption；Processor
The uncertainty of wake-up leads to the inexactness of suspend mode timing.
Invention content
Insufficient in view of the above technology, it is an object of the invention to provide a kind of industry wireless networks towards industrial process automation
Standard technique protocol realization is used for low-power consumption, accurate doze output circuit and the method for system on chip grade chip.The circuit
Include two improvement to traditional circuit：First is the increase in the circuits such as surplus calculates, timing results are adjudicated, and processor is realized
Operation becomes hardware calculating, reduces power consumption；Second is the uncertainty for improving processor wakeup time, be can effectively improve not
The precision of dormancy timing.
The present invention solves its technical problem and uses following technical scheme：A kind of accurate doze output circuit of low-power consumption,
It is calculated including high frequency clock source, low-frequency clock source, clock status indicating circuit, control circuit, timer, high frequency timing margin
Device, low frequency timing margin calculator, comparator, timing results decision device；
The high frequency clock source exports high frequency clock to the clock end of first timer and waiting for for clock status indicating circuit
Clock end is surveyed, first timer output end is connect with the second input terminal of first comparator；Low-frequency clock source output low frequency clock is extremely
The reference clock end of the clock end and clock clock status indicating circuit of second timer；
The output clock status signal of the clock status indicating circuit is to control circuit, when first input end accesses high frequency
Clock, the second input terminal access low-frequency clock；
First input end access timing commencing signal, the second input terminal incoming clock status signal of the control circuit,
Four output ends respectively with high frequency timing margin calculator, low frequency timing margin calculator, first timer, second timer
Enable Pin connects；
The first input end of the high frequency timing margin calculator, the input terminal of low frequency timing margin calculator access and prolong
When timing value；Second timer output end and the second input terminal of high frequency timing margin calculator, second the second input terminal of comparator,
Second input terminal of third comparator connects；High frequency timing margin calculator output end connects with first comparator first input end
It connects；Two output ends of low frequency timing margin calculator respectively with the second comparator first input end, third comparator first
Input terminal connects；
First comparator, the second comparator, the output end of third comparator are defeated with three of timing results decision device respectively
Enter end connection, timing results decision device exports timing end signal and error indication signal；The output end of second comparator also with
The input terminal in high frequency clock source connects.
The clock status indicating circuit includes：Including clock division circuits, edge correct circuit, edge sense circuit and
Shift-register circuit；The clock division circuits is corrected circuit with edge and is connect；Correct circuit and Edge check in the edge
Circuit, shift-register circuit connection；The edge sense circuit is connect with shift-register circuit；
The clock division circuits is for dividing reference clock, output frequency division clock signal to Edge check electricity
Road；
The edge sense circuit accesses clock to be measured, the sub-frequency clock signal of clock division circuits output and edge amendment
The edge revise signal of circuit output carries out edge detection, output cycle reset signal to edge amendment to sub-frequency clock signal
Circuit and shift-register circuit；
Circuit access reference clock is corrected at the edge and cycle reset signal be modified to obtain edge revise signal it is defeated
Go out to edge sense circuit；
The shift-register circuit accesses high level, reference clock and cycle reset signal, carries out internal register shifting
Position and reset operation, export clock status signal.
A kind of accurate suspend mode timing method of low-power consumption, includes the following steps：
Timing starts, and control circuit generates the enabled output tremendously low frequency timing margin calculator of low frequency calculating, low frequency timing makes
It can export to second timer；Low frequency timing margin calculator be calculated two low frequencies timings to delay timing value and compares
Value, and second timer starts counting up；
When the first low frequency timing fiducial value of low frequency timing margin calculator output and the count value of the second counter are equal
When, the first low frequency comparison match signal is generated, while starting high frequency clock source；When high frequency clock source works, clock status refers to
Show that circuit evolving clock status signal is exported to control circuit；Control circuit generates high frequency and calculates more than enabled output to high frequency timing
Amount calculator, the enabled output of high frequency timing to first timer, simultaneously close off low frequency timing and enable, second timer stops meter
Number；
High frequency timing margin calculator calculates the current count value of delay timing value and second timer, obtains height
Frequency timing fiducial value, and first timer starts counting up；When the high frequency timing fiducial value of high frequency timing margin calculator output
When equal with the count value of first timer, generate high frequency and compare matched signal；
Timing results decision device exports timing end signal according to the comparison result of first comparator and the second comparator.
After the first low frequency comparison match signal enabling high frequency clock source, when high frequency clock source exception, keep low
Frequency timing is enabled, and second timer continues to count；When count value is equal with the second low frequency timing fiducial value, the second low frequency is generated
Comparison match signal；
Timing results decision device according to the comparison result of the second comparator and third comparator export timing end signal and
Error indication signal.
The low frequency timing margin calculator to delay timing value calculate and be realized by following formula：
First low frequency timing fiducial value=(when delay timing value-high frequency clock source wakeup time-high frequency timer count
Between)/low-frequency clock source the clock cycle；
Wherein, high frequency clock source wakeup time, high frequency timer count time, low-frequency clock source clock cycle are setting
Value.
The low frequency timing margin calculator, which calculates delay timing value, also to be realized by following formula
Second low frequency timing fiducial value=delay timing value/low-frequency clock source clock cycle；
Wherein, the low-frequency clock source clock cycle is setting value.
The current count value to delay timing value and second timer calculate and is realized by following formula：High frequency
Timing fiducial value=(delay timing value-second timer current count value-phase pushing figure)/high frequency clock source clock cycle；
Delay timing value is an externally input, and second timer current count value is the output of second timer.
Wherein, phase pushing figure, high frequency clock source clock cycle are setting value.
It is described to be specially according to the comparison result of first comparator and the second comparator output timing end signal：First ratio
When compared with the output result of device and the second comparator being all equal, exports and timing end signal and do not generate error indication signal.
It is described to be specially according to the comparison result of first comparator and the second comparator output timing end signal：First ratio
When compared with the output result of device and the second comparator being all equal, exports and timing end signal and do not generate error indication signal.
It is described that timing end signal and error indication letter are exported according to the comparison result of the second comparator and third comparator
Number be specially：When the output result of second comparator and third comparator is all equal, exports timing end signal and generate
Error indication signal.
The clock status indicating circuit generates clock status signal and includes the following steps：
A. clock division circuits divides reference clock to obtain sub-frequency clock signal；
B. edge sense circuit carries out edge detection to sub-frequency clock signal and obtains cycle reset signal；
C. shift-register circuit transmits high level step by step, and when clock to be measured is normal, cycle reset signal is to inside
Register resetted, shift-register circuit output keep low level；When clock exception to be measured, cycle reset signal is lost
It loses, shift-register circuit output keeps high level；
D. edge is corrected circuit and is stopped in clock to be measured and when cycle reset abnormal signal, by the reference clock negated with it is all
Phase reset signal carries out phase and generates edge revise signal；
E. clock status signal, return to step a are exported by shift-register circuit.
The invention has the advantages that and advantage：
1. circuit of the present invention is related to ultralow Consumption towards system on chip grade chip field, can provide one kind can
To meet ultralow Consumption requirement, the doze output circuit of accurate timing.
2. circuit of the present invention is using high frequency timer, low frequency timer, clock status indicating circuit, control circuit, high frequency
The circuit structures such as timing margin calculator, low frequency timing margin calculator, using hardware controls high frequency timer, low frequency timer
Method, solve the disadvantage that tradition needs to switch over by processor, reduce processor resource expense, improve timing essence
Degree, reduces system power dissipation.
3. circuit of the present invention include high frequency timing comparator, the first low frequency timing comparator, the second low frequency timing comparator,
The structures such as the circuits such as timing results judgement when high frequency clock source can be effectively prevent to fail cause that suspend mode timing can not be completed
Defect improves the reliability of timing.
4. clock status indicating circuit can effectively provide clock signal to be measured towards system-on-chip designs in the present invention
State.
It, can be with without analog circuit 5. the clock status indicating circuit of the present invention is all using Design of Digital Circuit realization
It is used in the multiple fields such as IC design or Field Programmable Logic Array design.
6. clock status indicating circuit is when using 2 frequency dividing, six triggers and two gate circuits can be used in minimum
To realize clock status instruction function, has many advantages, such as simple in structure, operation small power consumption.
Description of the drawings
Fig. 1 is the time diagram of doze output；
Fig. 2 is the exchange-column shift schematic diagram of doze output；
Fig. 3 is the structure diagram of the present invention；
Fig. 4 is a kind of clock status indicating circuit structure chart；
Fig. 5 is 2 frequency-dividing clock frequency dividing circuit structure charts of clock status indicating circuit；
Fig. 6 is the edge sense circuit structure chart of clock status indicating circuit；
Fig. 7 is that circuit structure diagram is corrected at the edge of clock status indicating circuit；
Fig. 8 is the shift-register circuit structure chart of clock status indicating circuit.
Specific implementation mode
With reference to embodiment, the present invention is described in further detail.
A kind of low-power consumption, accurate doze output circuit and method, when function module includes high frequency clock source, low frequency
Zhong Yuan, clock status indicating circuit, control circuit, timer, high frequency timing margin calculator, low frequency timing margin calculator,
Comparator, timing results judgement etc..
The effect in low-frequency clock source described in circuit of the present invention is to generate low-frequency clock.The low-frequency clock that low-frequency clock source generates
It is used for low frequency timer timing.Low-frequency clock source is always in the doze output course of work, cannot be turned off.This
Low-frequency clock in invention circuit refers generally to clock of the frequency within the scope of 10KHz to 100KHz, according to practical application, the clock
Range can be increased or reduced suitably.
Circuit of the present invention includes the identical timer of 2 structures, different according to counting clock, is referred to as high frequency timer
With low frequency timer.Circuit of the present invention includes the identical comparator of 3 structures, different according to function, is referred to as high frequency timing
Comparator, the first low frequency timing comparator, the second low frequency timing comparator.
The effect in the high frequency clock source described in circuit of the present invention is to generate high frequency clock.High frequency clock is for high frequency timer meter
When use.High frequency clock source includes enable signal, can be turned off by enable signal and enter low power consumpting state.In circuit of the present invention
Low-frequency clock refer generally to frequency in the clock of 1MHz or more, according to practical application, which can suitably increase or reduce.
The effect of low frequency timer described in circuit of the present invention is counted under low-frequency clock.In entire dormancy period,
The counting of most of the time is completed by low frequency timer.Low frequency timer, can to dormancy period counting since count frequency is relatively low
Can have fraction surplus can not accurate metering complete, the one count surplus by high frequency timer timing complete.
The effect of high frequency timer described in circuit of the present invention is counted under high frequency clock.In entire dormancy period,
The counting of most of the time is completed by low frequency timer.High frequency timer is used to that low frequency timer can not to be completed the surplus of timing
Carry out timing.
The effect of clock status indicating circuit of the present invention is that prison shows whether high frequency clock source works normally, when generation
Clock status signal；The effect of control circuit is to receive externally input timing beginning and clock status signal, carries out logic state
Judge, generates the moulds such as control high frequency timer, low frequency timer, high frequency timing margin calculator and low frequency timing margin calculator
The enable signal of block.
The effect of low frequency timing margin calculator described in circuit of the present invention is to calculate the first low frequency timing fiducial value and second
Low frequency timing fiducial value.The effect of first low frequency timing fiducial value is for waking up high frequency clock source, and the timing of the second low frequency is compared
The effect of value is to generate the second low frequency comparison match when high frequency clock source does not wake up in time.
The effect of high frequency timing margin calculator of the present invention is to calculate high frequency timing fiducial value.High frequency timing is compared
The effect of value is to generate high frequency to compare matched signal.
The effect of comparator circuit of the present invention is compared to two values, when comparison result is equal, production
Raw comparison match signal output.
The effect of timing results decision circuit of the present invention is to compare matched signal and low frequency timing instruction to high frequency
Signal is judged that judgement timing terminates and carry out error indication.
The connection relation of circuit of the present invention is：
The high frequency clock source exports high frequency clock to the clock end of first timer and waiting for for clock status indicating circuit
Clock end is surveyed, first timer output end is connect with the second input terminal of first comparator；Low-frequency clock source output low frequency clock is extremely
The reference clock end of the clock end and clock clock status indicating circuit of second timer.
The output clock status signal of the clock status indicating circuit is to control circuit, when first input end accesses high frequency
Clock, the second input terminal access low-frequency clock.
First input end access timing commencing signal, the second input terminal incoming clock status signal of the control circuit,
Four output ends respectively with high frequency timing margin calculator, low frequency timing margin calculator, first timer, second timer
Enable Pin connects.
The first input end of the high frequency timing margin calculator, the input terminal of low frequency timing margin calculator access and prolong
When timing value；Second timer output end and the second input terminal of high frequency timing margin calculator, second the second input terminal of comparator,
Second input terminal of third comparator connects.
High frequency timing margin calculator is connect with first comparator first input end；Two of low frequency timing margin calculator
Output end distinguishes the first input end connection of the second comparator, third comparator.
First comparator, the second comparator, the output end of third comparator are defeated with three of timing results decision device respectively
Enter end connection, timing results decision device exports timing end signal and error indication signal；The output end of second comparator also with
The input terminal in high frequency clock source connects.
The principles illustrated of circuit of the present invention is as follows：
The principle of doze output circuit of the present invention and method is that the timing of dormancy time is divided into two steps is complete
At as shown in Figure 1, the respectively low frequency timer count time and high frequency timer count time.The low frequency timer count time
By low-frequency clock driving low frequency timer count is completed, the high frequency timer count time drives high frequency timer meter by high frequency clock
It counts up into.
Whole system can be further described, as shown in Figure 2.When system enters dormant state, low frequency timing margin
Calculator works, and generates two timing fiducial values, respectively the first low frequency timing fiducial value and the second low frequency timing fiducial value, the
One low frequency timing fiducial value is the timing fiducial value deducted after high frequency timing margin, and the second low frequency timing fiducial value is finally to wake up
Time, there may be certain errors for the second low frequency timing fiducial value.Wherein the calculation formula of the first low frequency timing fiducial value is such as
Under：
Wherein high frequency clock source wakeup time, high frequency timer count time and low-frequency clock source clock cycle are setting
Value.High frequency clock source wakeup time is determined by high frequency clock source；The high frequency timer count time is by dormancy time and low-frequency clock
The source clock cycle, which takes the remainder, to be calculated, or increases several low-frequency clock source clock period times after remainder calculating；It is low
The frequency clock source clock cycle is determined by the period of low-frequency clock.
The calculation formula of second low frequency timing fiducial value is as follows.
Wherein the low-frequency clock source clock cycle is setting value.The low-frequency clock source clock cycle is determined by the period of low-frequency clock
It is fixed.
After entering dormant state, timing is carried out by low frequency timer first, it will be i.e. when being up to the object time, i.e. low frequency
When timer count value reaches the first low frequency timing fiducial value, the first low frequency comparison match signal is generated, which wakes up high frequency
Clock source.
Clock status circuit monitors high frequency clock source, after high frequency clock source reaches steady-working state, i.e. high frequency clock
After source generates high frequency clock, clock status signal is generated.
Under clock status signal effect, high frequency timer is started to work, and it is fixed that high frequency timing margin calculator generates high frequency
When fiducial value, while low frequency timer is stopped.The calculation formula of high frequency timing fiducial value is as follows.
Wherein low frequency timer current count value is exported to obtain by the output port of low frequency timer；Phase pushing figure and height
The frequency clock source clock cycle is setting value.Phase pushing figure is constant, and the effective time and low frequency of value and enable port are fixed
When device phase it is related, specifically determined by the design scheme of clock status indicating circuit；The high frequency clock source clock cycle is by high frequency
The period of clock determines.
When high frequency timer count reaches high frequency timing fiducial value, generates high frequency and compare matched signal；If when high frequency
Clock wakeup time is more than the corresponding timing of the second low frequency timing fiducial value, when to reach second low for the count value of low frequency timer
When frequency timing fiducial value, the second low frequency timing indication signal is generated, at this time high frequency timer and high frequency timing margin calculator etc.
Circuit does not work within this counting period.
The effect of low frequency timing margin calculator described in circuit of the present invention is to calculate the first low frequency timing fiducial value and second
Low frequency timing fiducial value.The effect of first low frequency timing fiducial value is for waking up high frequency clock source, and the timing of the second low frequency is compared
The effect of value is to generate the second low frequency comparison match signal when high frequency clock source does not wake up in time.Due to low-frequency clock source
Frequency is relatively low, therefore the second low frequency comparison match signal may have larger error；But institute is not waken up for high frequency clock source
It is still a kind of good means to save the situation for caused high frequency compares matched signal loss.
The Rule of judgment of timing results decision circuit is：First low frequency comparator must generate the first low frequency comparison match letter
Number；High frequency timing comparator generation high frequency, which compares matched signal or the second low frequency comparator, must generate the second low frequency comparison match
Signal.When the first low frequency comparison match signal and high frequency compare matched signal it is equal when, export and timing end signal and do not produce
Raw error indication signal；When the first low frequency comparison match signal and equal the second low frequency comparison match signal, output timing terminates
Signal and generate error indication signal.
The method and step of patent of the present invention is：
Started by timing commencing signal, the enabled output tremendously low frequency timing margin calculator of control circuit generation low frequency calculating,
The enabled output tremendously low frequency timer of low frequency timing；Low frequency timing margin calculator carries out being calculated first low to delay timing value
Frequency timing fiducial value and the second low frequency timing fiducial value, and low frequency timer starts counting up；
When the first low frequency timing fiducial value of low frequency timing margin calculator output and the count value of low frequency timer are equal
When, the first low frequency comparison match signal is generated, while starting high frequency clock source；When high frequency clock source works, clock status refers to
Show that circuit evolving clock status signal is exported to control circuit；Control circuit generates high frequency and calculates more than enabled output to high frequency timing
Amount calculator, the enabled output of high frequency timing to high frequency timer, simultaneously close off low frequency timing and enable, second timer stops meter
Number；
High frequency timing margin calculator calculates the current count value of delay timing value and second timer, obtains height
Frequency timing fiducial value, and high frequency timer starts counting up；When the high frequency timing fiducial value of high frequency timing margin calculator output
When equal with the count value of high frequency timer, generate high frequency and compare matched signal；
Timing results decision device exports timing according to the comparison result of high frequency timing comparator and the first low frequency comparator and ties
Beam signal.
After first low frequency comparison match signal enabling high frequency clock source, when high frequency clock source exception, keep low frequency fixed
When it is enabled, low frequency timer continues to count；When count value is equal with the second low frequency timing fiducial value, generates the second low frequency and compare
Matched signal；Timing results decision device exports timing according to the comparison result of the first low frequency comparator and the second low frequency comparator and ties
Beam signal and error indication signal.
Circuit realizes that most of part is write using verilog language in the present embodiment, can use synthesis tool
Carry out comprehensive realization；Fraction circuit is collectively constituted by internal circuit and external electronic component, such as high frequency clock source and low frequency
Clock source；The present embodiment is applied in actual chips, achieves preferable effect.
The present embodiment uses the circuit structure illustrated in invention content, specific as shown in Figure 3.When circuit structure includes high frequency
Zhong Yuan, low-frequency clock source, clock status indicating circuit, control circuit, timer 1, timer 2, high frequency timing margin calculator,
The circuits such as low frequency timing margin calculator, comparator 1, comparator 2, comparator 3, timing results judgement.
It includes input port and output port that this, which implements its outside port, and input port includes delay timing value, periodically opens
Begin；Output port terminates including timing and error indication.
The port of each function module is in this implementation：High frequency clock source includes input port E and output port C；Low frequency
Clock source includes output port C；Clock status indicating circuit includes input port CK, C and output port ST；Control circuit includes
Input port S, A and output port C1, C2, C3, C4；Timer 1 includes input port E, CK and output port C；Timer 2 packet
E containing input port, CK and output port C；High frequency timing margin calculator includes input port E, A, B and output port C；Low frequency
Timing margin calculator includes input port E, A and output port C1, C2；Comparator 1 includes input port A and B, output port
C；Comparator 2 includes input port A and B, output port C；Comparator 3 includes input port A and B, output port C；Timing is tied
Fruit judgement includes input port A1, A2 and A3, output port C1 and C2.
The connection relation of circuit is in this implementation：The input port E in high frequency clock source is exported by the C-terminal mouth of comparator 2, high
The C-terminal mouth of frequency clock source exports high frequency clock to the C-terminal mouth of the ports CK of timer 1 and clock status indicating circuit；When low frequency
CK port of the C-terminal output low frequency clock of Zhong Yuan to the ports CK of low frequency timer module and clock status indicating circuit；Clock
The ports CK of condition indication circuit are accessed by the C-terminal mouth in low-frequency clock source, and the C-terminal mouth of clock status indicating circuit is by low-frequency clock
The C-terminal mouth in source accesses, and the ports ST of clock status indicating circuit are exported to the ports A of control circuit；The ports S of control circuit by
Externally input timing commencing signal access, the output port C1 of control circuit are connected to the ends E of high frequency timing margin calculator
Mouthful, the output port C2 of control circuit is connected to the ports E of low frequency timing margin calculator, and the output port C3 of control circuit connects
The ports E of timer 2 are connected to, output port C4 is connected to the ports E of timer 1；The ports E of timer 1 are by control circuit
C4 is accessed, and the ports CK of timer 1 are accessed by the C-terminal mouth in high frequency clock source, and the C-terminal mouth of timer 1 is output to high frequency timing ratio
Compared with the ports B of device；The ports E of timer 2 are accessed by the ports C3 of control circuit, and the ports CK of timer 2 are by low-frequency clock source
The access of C-terminal mouth, the C-terminal mouth of timer 2 exports the ports B to the ports B of high frequency timing margin calculator and comparator 3；It is high
The ports E of frequency timing margin calculator are accessed by the ports C1 of control circuit, and the ports A of high frequency timing margin calculator are by outside
The delay timing value signal of input accesses, and the ports B of high frequency timing margin calculator are accessed by the C-terminal mouth of timer 2, and high frequency is fixed
The C-terminal mouth of Shi Yuliang calculators is exported to the ports A of comparator 1；The ports E of low frequency timing margin calculator are by control circuit
The ports C2 are accessed, and the delay timing value signal that the ports A of low frequency timing margin calculator are input from the outside accesses, more than low frequency timing
The ports C1 of amount calculator are exported to the ports A of comparator 2, and the ports C2 of low frequency timing margin calculator are exported to comparator 3
The ports A；The ports A of comparator 1 are accessed by the C-terminal mouth of high frequency timing margin calculator, and the ports B of comparator 1 are by timer 1
The access of C-terminal mouth, the C-terminal mouth of comparator 1 exports to the ports A1 of timing results decision circuit；The ports A of comparator 2 are by low frequency
The ports C1 of timing margin calculator are accessed, and the ports B of comparator 2 are accessed by the C-terminal mouth of low frequency timer, the C-terminal of comparator 2
Mouth is exported to the ports E of high frequency clock source；The ports A of comparator 3 are accessed by the ports C2 of low frequency timing margin calculator, are compared
The ports B of device 3 are accessed by the C-terminal mouth of low frequency timer, and the C-terminal mouth of comparator 3 exports the ports A2 adjudicated to timing results；It is fixed
When result judgement the ports A1 by comparator 1 C-terminal mouth access, timing results judgement the ports A2 connect by the C-terminal mouth of comparator 2
Enter, the ports A3 of timing results judgement are accessed by the C-terminal mouth of comparator 3, and the ports the C1 output timing of timing results judgement terminates
Signal, the ports the C2 output error indication signal of timing results judgement.
The present embodiment medium-high frequency clock source circuit realized jointly by external quartz crystal and crystal oscillator PAD, wherein crystal oscillator PAD packets
Include ena-bung function.High frequency clock source includes enabled control port E, output terminal of clock mouth C.When enabled control is effective, clock-like
State oscillation generates high frequency clock signal；When enabled control is invalid, high frequency clock source is stopped, fixed output high level or low
Level signal is in low power consumpting state.High frequency clock source generates high frequency clock signal and is exported by output terminal of clock mouth C.
Low-frequency clock source circuit is realized jointly by external quartz crystal and crystal oscillator PAD in the present embodiment, does not have shutdown work(
Energy.Low-frequency clock source includes output terminal of clock mouth C.Low-frequency clock source generates low-frequency clock signal and is exported by output terminal of clock mouth C.
Timer 1 realizes that high frequency timer function, timer 2 realize low frequency timer function in the present embodiment.Timer 1
With timer 2 circuit structure having the same, realized using general timer circuit.Its input port includes enable port
E and input end of clock mouth CK, output port include count value port C.When enable port E is effective, in each clock input port
CK it is effective along when count value add 1, and by count value port C export；When enable port E is invalid, no matter clock input port
Whether CK has saltus step, and count value is reset to 0 always, and is exported by count value port C.
It is clock status port A that control circuit, which includes input port, in the present embodiment, and timing starts port S；Output port
For 1 enable port C4 of timer, timer 2 enable port C3, low frequency timing margin calculator enable port C2 and high frequency timing
Surplus calculator enable port C1.Its behavior be when a suspend mode timing cycle starts, i.e., it is low when timing commencing signal is effective
Frequency timing margin calculator is enabled to generate an effective impulse signal.When a suspend mode timing cycle starts, more than low frequency timing
It measures calculator enable port and generates effective impulse signal, timer 2 enable port generates useful signal, 1 enable port of timer
Invalid state is exported with low frequency timer enable port.High frequency timing margin calculator is enabled after high frequency clock source is working properly
Signal generates an effective impulse, the enable signal of timer 1 is then set as effective status simultaneously and by low frequency timer
Enable signal is set as invalid state.When timing commencing signal is invalid, all output enable signals are invalid state.
The input port of low frequency timing margin calculator in the present embodiment includes delay timing value port A and enable port
E, output port include the first low frequency timing fiducial value port C1 and the second low frequency timing fiducial value port C2.Low frequency timing margin
Calculator carries out calculating the first low frequency timing fiducial value and the second low frequency timing fiducial value when enable port E is effective, enabled
When port E fails, the count value before keeping.Calculate the calculating of the first low frequency timing fiducial value and the second low frequency timing fiducial value
It is completed according to the formula in invention content.
The effect of high frequency timing margin calculator in the present embodiment is to calculate high frequency timing fiducial value.High frequency timing is compared
The effect of value is to generate high frequency to compare matched signal.High frequency timing margin calculator includes that input port is enable port E, is delayed
Timing value port A and low frequency timer count value port B, output port are high frequency timing fiducial value port C.High frequency timing margin
Calculator calculates high frequency timing when enable port E is effective, according to the value of delay timing value port A and low frequency count value port B
Fiducial value, and exported by high frequency timing fiducial value port C.The calculating of high frequency timing fiducial value is complete according to the formula in invention content
At calculating.
Comparator 1, comparator 2, comparator 3 in the present embodiment are completely identical in structure circuit, and comparator 1 completes height
Frequency timing comparator, comparator 2 completes the first low frequency timing comparator, comparator 3 completes the second low frequency timing comparator.Compare
Device circuit includes 2 port B of 1 port A of input port fiducial value and fiducial value, output comparison match port C.Comparator circuit is by group
Logical composition generates comparison match output when the ports A are equal with the value of the ports B.
Timing results decision circuit in the present embodiment is made of combinational logic.Timing results decision circuit includes input terminal
Mouth compares mating end mouth A1, the first low frequency comparison match port A2 and the second low frequency comparison match A3, output port for high frequency
Timing terminates port C1 and error indication port C2.The work behavior of timing results decision circuit is when high frequency compares mating end mouth
When A1 and the first low frequency comparison match port A2 is effective simultaneously, timing end signal, but not generation error indication signal are generated；When
When first low frequency comparison match port A2 and the second low frequency comparison match A3 is effective simultaneously, timing timing end signal is generated, together
When generation error indication signal.Due to the effect of clock status indicating circuit, height will not be generated simultaneously in the same counting period
Frequency comparison match and low frequency timing indicate, i.e., only generate a final timing and terminate batch beam.Error indication signal indicates whether
Accurate timing termination instruction is generated, when error indication signal is effective, shows that timing termination instruction may include certain mistake
Difference；When error indication signal is invalid, timing termination instruction is accurate when table.
Clock status indicating circuit adopts the following technical scheme that in the present embodiment：
Circuit, edge sense circuit and displacement are corrected in a kind of clock status indicating circuit, including clock division circuits, edge
Register circuit；The clock division circuits is corrected circuit with edge and is connect；The edge correct circuit and edge sense circuit,
Shift-register circuit connects；The edge sense circuit is connect with shift-register circuit；
The clock division circuits is for dividing reference clock, output frequency division clock signal to Edge check electricity
Road；
The edge sense circuit accesses clock to be measured, the sub-frequency clock signal of clock division circuits output and edge amendment
The edge revise signal of circuit output carries out edge detection, output cycle reset signal to edge amendment to sub-frequency clock signal
Circuit and shift-register circuit；
Circuit access reference clock is corrected at the edge and cycle reset signal be modified to obtain edge revise signal it is defeated
Go out to edge sense circuit；
The shift-register circuit accesses high level, reference clock and cycle reset signal, carries out internal register shifting
Position and reset operation, export clock status signal.
The clock division circuits includes NOT gate and register；The data terminal of the non-gate output terminal and register connects,
Output of the output end of register as clock division circuits, and the input terminal connection of NAND gate；The clock end of register accesses
Reference clock.
The edge sense circuit includes sequentially connected three registers and an XOR gate；Three registers
Clock end accesses clock to be measured, and the output end that reset terminal corrects circuit with edge is connect, the first register connected in sequence
Data terminal as edge sense circuit input and connect with the output end of clock division circuits, third register output end with it is different
Or the first input end connection of door, the second input terminal connection of the second register output end and XOR gate, the output end of XOR gate
Output as edge sense circuit.
The edge correct circuit include NOT gate and with door, the input terminal of NOT gate accesses reference clock, output end with door
First input end connection, connect with the output end of the second input terminal of door and edge sense circuit, output end is Edge check
The output of circuit.
The shift-register circuit includes multiple registers being linked in sequence, and the clock end of each register accesses ginseng
Clock is examined, reset terminal is connect with the output end of edge sense circuit, and the data terminal of first register connects high level, last
Output of the output end of a register as shift-register circuit.
A kind of clock status indicating means, includes the following steps：
A. clock division circuits divides reference clock to obtain sub-frequency clock signal；
B. edge sense circuit carries out edge detection to sub-frequency clock signal and obtains cycle reset signal；
C. shift-register circuit transmits high level step by step, and when clock to be measured is normal, cycle reset signal is to inside
Register resetted, shift-register circuit output keep low level；When clock exception to be measured, cycle reset signal is lost
It loses, shift-register circuit output keeps high level；
D. edge is corrected circuit and is stopped in clock to be measured and when cycle reset abnormal signal, by the reference clock negated with it is all
Phase reset signal carries out phase and generates edge revise signal；
E. clock status signal, return to step a are exported by shift-register circuit.
The edge detection is specially the output of the second register and third register connected in sequence when generating edge
It differs, high level is generated by XOR gate.
It is described to carry out frequency dividing to carry out N- equal duty ratio frequency dividings.
The series of register is N+1 grades or more in the shift-register circuit.
Clock status indicating circuit is realized especially by following scheme：
A kind of clock status indicating circuit, external input port include reference clock signal, clock signal to be measured, output end
Mouth includes clock status signal.
The port function of clock status indicating circuit is described as follows：Reference clock signal is to continuously generate, to generate clock
Status signal provides the clock of reference, and 32KHz, the low frequencies such as 10KHz can be used in practical applications in generally low frequency clock
Clock；Clock signal to be measured is to be clock signal under, and refers generally to high-frequency clock, in profession of the invention, should be reference clock
3 times or more of frequency；Clock status signal indicates whether clock signal to be measured works normally, if normal work, exports low electricity
Otherwise ordinary mail number generates high level signal.
The function module of clock status indicating circuit include clock division circuits, edge correct circuit, edge sense circuit,
Shift-register circuit.
The module and port connection relationship of clock status indicating circuit are as follows：The input clock of the clock division circuits
Port is inputted by reference clock signal, and output port is sub-frequency clock signal；The input clock port of edge sense circuit is by waiting for
Clock signal input is surveyed, input reseting port is inputted by the edge revise signal of edge sense circuit, and output port is multiple for the period
Position signal；The input clock port that circuit is corrected at edge is inputted by reference clock signal, and input reseting port is by Edge check electricity
The cycle reset signal on road inputs, and output port is edge revise signal；The input clock port of shift-register circuit is by joining
Clock signal input is examined, input reseting port is inputted by the cycle reset signal of edge sense circuit, and output port is clock-like
State signal.
The function of clock division circuits is to carry out N- equal duty ratios point to reference clock signal in clock status indicating circuit
Frequency obtains sub-frequency clock signal, and the effective high level and low level length of the signal are NT/2.Wherein the value range of N be 1 to
Infinity, when N values are 1, i.e., without frequency dividing.If the duty ratio of reference clock signal meets or can value close to 1, N
It is 1.
Edge sense circuit divides clock division circuits generation under clock to be measured effect in clock status indicating circuit
Frequency clock signal carries out edge detection, specifically extracts rising edge and failing edge, generates the cycle reset that the period is NT and believes
Number.
The effect that circuit is corrected at edge in clock status indicating circuit is the cycle reset letter generated to edge sense circuit
Number and reference clock signal, pass through combinational logic circuit, generate edge revise signal.
Shift-register circuit includes N+1 grades of register groups in clock status indicating circuit, in cycle reset signal and ginseng
It examines under clock effect, the operations such as is resetted and shifted, generate clock status signal.
The principles illustrated of clock status indicating circuit is as follows.
Note reference clock signal frequency is F, period T.By the relationship of frequency and clock, the product that can obtain F and T is equal to 1,
That is F is equal to 1/T.
Reference clock signal is carried out N- equal duty ratios frequency dividing to obtain effective high level and low level length being NT/2,
Period is the frequency-dividing clock of NT；When clock to be measured is effective, it is NT cycle reset signals that the period can be generated with frequency-dividing clock；
In the N+1 grade shift register groups that high level input, reference clock drive, due to the work for the cycle reset signal that the period is NT
With shift-register circuit is resetted by the period of NT so that high level be merely able to be transmitted to shift register N grades are posted
Storage is not transferred to N+1 grades of shift-register circuit, i.e. clock status signal remains low level；When to be measured
When clock invalidating signal, edge sense circuit can not generate cycle reset signal, N+1 grades of registers in shift-register circuit
It is final to generate high level instruction.
Due to the uncertainty of clock to be measured, under certain conditions, it is possible to create abnormal cycle reset signal at this time can
The influence that mistake is generated to shift-register circuit generates the clock status result of mistake.The amendment of the result can be passed through
Cycle reset signal and reversed reference clock by with gate logic, generate edge revise signal.Edge revise signal can repair
The cycle reset signal of normal anomaly, and finally generate correct clock status signal.
When using N- equal duty ratios frequency dividing, the series of shift register is N+1 or more, can protect the normal work of original circuit
Make.
The method and step of clock status indicating circuit is：
Clock division circuits carries out N- equal duty ratios to reference clock signal and divides to obtain the period as NT sub-frequency clock signals；
Edge sense circuit carries out edge detection to the sub-frequency clock signal that clock division circuits generates, and the generation period is NT
Cycle reset signal；
Shift-register circuit transmits high level step by step, and when clock to be measured is normal, cycle reset signal is to inside
Register is resetted, and shift-register circuit output keeps low level；When clock exception to be measured, cycle reset signal is lost
It loses, shift-register circuit output keeps high level.
Circuit is corrected when detecting abnormal cycle reset signal in edge, generates edge revise signal；Edge check electricity
Road carries out logic circuit processing, corrects abnormal cycle reset signal under the effect of edge revise signal.
Shift-register circuit generates clock status signal according to cycle reset signal and reference clock signal
Embodiment：
The present embodiment is a kind of mode for realizing clock status indicating circuit described in this patent, is used relatively simple
Circuit structure, the N values wherein in clock division circuits are 2, that is, the duties such as 2- frequency dividing, shift register is used to be posted using 3
Storage shift-register circuit.
Specific embodiment please refers to shown in Fig. 4, a kind of clock status indicating circuit, in structure include clock division circuits,
Circuit and shift-register circuit are corrected in edge sense circuit, edge；Outside port includes output port reference clock and to be measured
Clock, output port clock status.
Specific connection relation is that reference clock signal is connected to the clock port CK of clock division circuits, clock division electricity
The output terminal of clock mouth Q on road generates sub-frequency clock signal C1；Clock signal to be measured is connected to the clock port of edge sense circuit
CK, clock division circuits generate the data port D that sub-frequency clock signal C1 is connected to edge sense circuit, and circuit production is corrected at edge
Raw edge revise signal F1 is connected to the reset terminal of edge sense circuit, and the output port Q of edge sense circuit generates set letter
Number R1；
The input clock port CK that circuit is corrected at edge is inputted by reference clock signal, and input reseting port R is examined by edge
The cycle reset signal R1 inputs of slowdown monitoring circuit, output port is edge revise signal F1, is exported to the reset of edge sense circuit
Port R；
The cycle reset signal R1 that edge sense circuit generates is connected to the reseting port R of shift-register circuit, reference
Clock signal is connected to the clock port CK of shift-register circuit, the data port D connection high level of shift-register circuit
Signal, shift-register circuit export Q and generate clock status signal.
The present embodiment uses 2 frequency-dividing clock frequency dividing circuits, as shown in Figure 5.The frequency dividing circuit includes register 1 and NOT gate 1.
Its connection relation is that the input end of clock mouth CK of register 1 is inputted by the portion input port CK of clock division circuits, register 1
Data-in port D by the output port Q input of NOT gate 1, the output port Q of register 1 is output to the input port of NOT gate 1
The output port Q of A, register 1 are output to the output port Q of clock division circuits；The input port A of NOT gate 1 is by register 1
Output port Q inputs, the output port Q of NOT gate 1 are output to the input port D of register 1.
Edge sense circuit structure is as shown in Figure 6 in the present embodiment.The edge sense circuit includes register 2, register
3, register 4 and XOR gate 1 form.Its connection relation is the input port D of register 2 by edge sense circuit external input CK
The input port CK of input, register 2 is inputted by edge sense circuit external input CK, and the output port Q of register 2 is output to
The input port D of register 3；The input port CK of register 3 is inputted by edge sense circuit external input CK, register 2
Input port D is inputted by the output port Q of register 2, and the output port Q of register 3 is output to the input port D of register 4
With the input port B of XOR gate 1；The input port CK of register 4 is inputted by edge sense circuit external input CK, register 4
Input port D by the output port Q input of register 3, the output port Q of register 4 is output to the input port of XOR gate 1
A；The input port A of XOR gate 1 is by the output port Q inputs of register 4, and the output port B of XOR gate 1 is by the defeated of register 3
Exit port Q inputs, the output port Q of XOR gate 1 are output to the external output port Q of edge sense circuit.
It is as shown in Figure 7 to correct circuit structure for edge in the present embodiment.The edge correct circuit include NOT gate 1 and with 1 group of door
At.Its connection relation is that the input port A of NOT gate 1 is corrected the outside port CK inputs of circuit, the output port of NOT gate 1 by edge
Q is connected to the input port A with door 1；It is accessed by the output port Q of NOT gate 1 with the input port A of door 1, the input terminal with door 1
Mouth B is corrected the outside port R accesses of circuit by edge, and the outside port that circuit is corrected at edge is output to the output port Q of door 1
Q。
Shift-register circuit structure is as shown in Figure 8 in the present embodiment.The shift-register circuit includes register 5, posts
Storage 6 and register 7 form.Its connection relation be register 5 input port D inputted by high level signal, register 5 it is defeated
Inbound port CK is inputted by shift-register circuit external input port CK, and the output port Q of register 2 is output to register 6
Input port D；The input port CK of register 6 is inputted by shift-register circuit external input port CK, the input of register 6
Port D is inputted by the output port Q of register 5, and the output port Q of register 6 is output to the input port D of register 7；Deposit
The input port CK of device 7 is inputted by shift-register circuit external input port CK, and the input port D of register 7 is by register 6
Output port Q input, the output port Q of register 7 is output to shift-register circuit external output port Q.
The present embodiment only enumerates a kind of embodiment of this circuit, when Fractional-N frequency (N is even number) can be used in other realization methods
Clock frequency dividing circuit, correspondence use N+1 or with higher level's shift-register circuit.If the set of edge detection circuit evolving is believed
Number R1 effective widths are less than normal, and it is real that more triggers can be inserted between the register 3 in edge detection circuit and register 4
It is existing.
Claims (10)
1. a kind of accurate doze output circuit of low-power consumption, it is characterised in that：Including high frequency clock source, low-frequency clock source, when
Clock condition indication circuit, control circuit, timer, high frequency timing margin calculator, low frequency timing margin calculator, comparator,
Timing results decision device；
The high frequency clock source export high frequency clock to first timer clock end and clock status indicating circuit it is to be measured when
Zhong Duan, first timer output end are connect with the second input terminal of first comparator；Low-frequency clock source output low frequency clock is to second
The reference clock end of the clock end and clock clock status indicating circuit of timer；
The output clock status signal of the clock status indicating circuit to control circuit, first input end access high frequency clock,
Second input terminal accesses low-frequency clock；
First input end access timing commencing signal, the second input terminal incoming clock status signal of the control circuit, four
Output end respectively with high frequency timing margin calculator, low frequency timing margin calculator, first timer, second timer it is enabled
End connection；
It is fixed that the first input end of the high frequency timing margin calculator, the input terminal of low frequency timing margin calculator access delay
Duration；Second timer output end and the second input terminal of high frequency timing margin calculator, second the second input terminal of comparator, third
Second input terminal of comparator connects；High frequency timing margin calculator output end is connect with first comparator first input end；It is low
Two output ends of frequency timing margin calculator respectively with the second comparator first input end, the first input end of third comparator
Connection；
First comparator, the second comparator, third comparator output end respectively with three input terminals of timing results decision device
Connection, timing results decision device export timing end signal and error indication signal；The output end of second comparator also with high frequency
The input terminal of clock source connects.
2. the accurate doze output circuit of a kind of low-power consumption according to claim 1, it is characterised in that the clock-like
State indicating circuit includes：Circuit, edge sense circuit and shift-register circuit are corrected including clock division circuits, edge；Institute
Clock division circuits is stated to connect with edge amendment circuit；Correct circuit and edge sense circuit, shift register electricity in the edge
Road connects；The edge sense circuit is connect with shift-register circuit；
The clock division circuits is for dividing reference clock, output frequency division clock signal to edge sense circuit；
The edge sense circuit accesses clock to be measured, the sub-frequency clock signal of clock division circuits output and edge and corrects circuit
The edge revise signal of output carries out edge detection to sub-frequency clock signal, and output cycle reset signal to edge corrects circuit
And shift-register circuit；
Circuit access reference clock is corrected at the edge and cycle reset signal be modified to obtain edge revise signal export to
Edge sense circuit；
The shift-register circuit accesses high level, reference clock and cycle reset signal, carry out internal register displacement and
Operation is resetted, clock status signal is exported.
3. a kind of accurate suspend mode timing method of low-power consumption, it is characterised in that include the following steps：
Timing starts, and the enabled output tremendously low frequency timing margin calculator of control circuit generation low frequency calculating, low frequency timing enable defeated
Go out to second timer；Low frequency timing margin calculator carries out delay timing value two low frequency timing fiducial values are calculated,
And second timer starts counting up；
It is raw when the count value of the first low frequency timing fiducial value of low frequency timing margin calculator output and the second counter is equal
At the first low frequency comparison match signal, while starting high frequency clock source；When high frequency clock source works, clock status indicating circuit
Clock status signal is generated to export to control circuit；Control circuit generates high frequency and calculates enabled output to the calculating of high frequency timing margin
Device, the enabled output of high frequency timing to first timer, simultaneously close off low frequency timing and enable, second timer stops counting；
High frequency timing margin calculator calculates the current count value of delay timing value and second timer, and it is fixed to obtain high frequency
When fiducial value, and first timer starts counting up；When the high frequency timing fiducial value and the of high frequency timing margin calculator output
When the count value of one timer is equal, generates high frequency and compare matched signal；
Timing results decision device exports timing end signal according to the comparison result of first comparator and the second comparator.
4. the accurate suspend mode timing method of a kind of low-power consumption according to claim 3, it is characterised in that first low frequency
After comparison match signal enabling high frequency clock source, when high frequency clock source exception, keep low frequency timing enabled, second timer
Continue to count；When count value is equal with the second low frequency timing fiducial value, the second low frequency comparison match signal is generated；
Timing results decision device exports timing end signal and mistake according to the comparison result of the second comparator and third comparator
Indication signal.
5. the accurate suspend mode timing method of a kind of low-power consumption according to claim 3, it is characterised in that the low frequency timing
Surplus calculator to delay timing value calculate and be realized by following formula：
First low frequency timing fiducial value=(delay timing value-high frequency clock source wakeup time-high frequency timer count time)/low
The frequency clock source clock cycle；
Wherein, high frequency clock source wakeup time, high frequency timer count time, low-frequency clock source clock cycle are setting value.
6. the accurate suspend mode timing method of a kind of low-power consumption according to claim 3, it is characterised in that the low frequency timing
Surplus calculator calculates delay timing value and is also realized by following formula：
Second low frequency timing fiducial value=delay timing value/low-frequency clock source clock cycle；
Wherein, the low-frequency clock source clock cycle is setting value.
7. the accurate suspend mode timing method of a kind of low-power consumption according to claim 3, it is characterised in that described pair of delay is fixed
The current count value of duration and second timer calculate and is realized by following formula：
When high frequency timing fiducial value=(delay timing value-second timer current count value-phase pushing figure)/high frequency clock source
The clock period；
Wherein, phase pushing figure, high frequency clock source clock cycle are setting value.
8. the accurate suspend mode timing method of a kind of low-power consumption according to claim 3, it is characterised in that described according to first
The comparison result of comparator and the second comparator exports timing end signal：First comparator and the second comparator it is defeated
When to go out result all be equal, export and timing end signal and do not generate error indication signal.
9. the accurate suspend mode timing method of a kind of low-power consumption according to claim 4, it is characterised in that described according to second
The comparison result of comparator and third comparator exports timing end signal and error indication signal is specially：Second comparator and
When the output result of third comparator is all equal, exports timing end signal and generate error indication signal.
10. the accurate suspend mode timing method of a kind of low-power consumption according to claim 3, it is characterised in that the clock status
Indicating circuit generates clock status signal and includes the following steps：
A. clock division circuits divides reference clock to obtain sub-frequency clock signal；
B. edge sense circuit carries out edge detection to sub-frequency clock signal and obtains cycle reset signal；
C. shift-register circuit transmits high level step by step, and when clock to be measured is normal, cycle reset signal posts inside
Storage is resetted, and shift-register circuit output keeps low level；When clock exception to be measured, cycle reset dropout,
Shift-register circuit output keeps high level；
D. edge corrects circuit and stops in clock to be measured and when cycle reset abnormal signal, the reference clock negated is answered with the period
Position signal carries out phase and generates edge revise signal；
E. clock status signal, return to step a are exported by shift-register circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410683200.1A CN105703749B (en) | 2014-11-24 | 2014-11-24 | A kind of accurate doze output circuit of low-power consumption and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410683200.1A CN105703749B (en) | 2014-11-24 | 2014-11-24 | A kind of accurate doze output circuit of low-power consumption and method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105703749A CN105703749A (en) | 2016-06-22 |
| CN105703749B true CN105703749B (en) | 2018-07-20 |
Family
ID=56941308
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410683200.1A Active CN105703749B (en) | 2014-11-24 | 2014-11-24 | A kind of accurate doze output circuit of low-power consumption and method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105703749B (en) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106227293A (en) * | 2016-07-24 | 2016-12-14 | 泰凌微电子（上海）有限公司 | A kind of system clock |
| CN107204775B (en) * | 2017-06-02 | 2021-02-02 | 广州视源电子科技股份有限公司 | Sampling method and sampling device for analog signals |
| CN108089689A (en) * | 2017-11-17 | 2018-05-29 | 珠海慧联科技有限公司 | A kind of small-sized SoC super low-power consumptions control circuit and method |
| CN107769762A (en) * | 2017-12-07 | 2018-03-06 | 绍兴光大芯业微电子有限公司 | Extremely low power dissipation Hall switch |
| CN109634168B (en) * | 2018-12-05 | 2020-02-07 | 智恒科技股份有限公司 | Method for processing sensor pulse signal |
| WO2020124302A1 (en) * | 2018-12-17 | 2020-06-25 | 智恒科技股份有限公司 | Sensor pulse signal processing method |
| CN111162737B (en) * | 2019-09-02 | 2021-02-05 | 奉加微电子（上海）有限公司 | Working method and working system of real-time clock |
| US11734151B2 (en) | 2021-06-24 | 2023-08-22 | Advanced Micro Devices, Inc. | Precise shadowing and adjustment of on-die timers in low power states |
| CN113395754B (en) * | 2021-08-17 | 2021-11-05 | 深圳华云时空技术有限公司 | High-precision low-power-consumption time keeping method |
| CN114860323A (en) * | 2022-05-20 | 2022-08-05 | 重庆御芯微信息技术有限公司 | Low-power-consumption accurate timing awakening method and device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1451247A (en) * | 1999-11-04 | 2003-10-22 | 高通股份有限公司 | Method and apparatus for activating a high frequency clock following a sleep mode with in a mobile station operating in a slotted paging mode |
| US6725067B1 (en) * | 2000-03-24 | 2004-04-20 | International Business Machines Corporation | Method and system for restarting a reference clock of a mobile station after a sleep period with a zero mean time error |
| CN103327587A (en) * | 2013-05-29 | 2013-09-25 | 北京创毅讯联科技股份有限公司 | Method and device for controlling sleep cycle of terminal |
| CN103389644A (en) * | 2013-06-19 | 2013-11-13 | 杭州士兰微电子股份有限公司 | Timing system and timing method |
-
2014
- 2014-11-24 CN CN201410683200.1A patent/CN105703749B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1451247A (en) * | 1999-11-04 | 2003-10-22 | 高通股份有限公司 | Method and apparatus for activating a high frequency clock following a sleep mode with in a mobile station operating in a slotted paging mode |
| US6725067B1 (en) * | 2000-03-24 | 2004-04-20 | International Business Machines Corporation | Method and system for restarting a reference clock of a mobile station after a sleep period with a zero mean time error |
| CN103327587A (en) * | 2013-05-29 | 2013-09-25 | 北京创毅讯联科技股份有限公司 | Method and device for controlling sleep cycle of terminal |
| CN103389644A (en) * | 2013-06-19 | 2013-11-13 | 杭州士兰微电子股份有限公司 | Timing system and timing method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105703749A (en) | 2016-06-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105703749B (en) | A kind of accurate doze output circuit of low-power consumption and method | |
| CN103645794B (en) | Chip and method for achieving sleep mode wake-up through edge detection circuit | |
| CN103631360B (en) | A kind of chip and method for supporting sleep pattern | |
| TWI475864B (en) | Electronic device | |
| WO2015014162A1 (en) | Apparatus and method for awakening mcu of soc chip | |
| CN106487372A (en) | Device including one-wire interface and the data handling system with the device | |
| CN104597790B (en) | A kind of awakening method of serial ports controller and micro controller system based on it | |
| CN103389644B (en) | Timing system and timing method | |
| CN100538561C (en) | fractional divider system and method | |
| CN2922277Y (en) | Clock burr testing circuit | |
| WO2017197946A1 (en) | Pvtm-based, wide-voltage-range clock stretching circuit | |
| CN109947226A (en) | A kind of UART wake-up circuit of MCU chip | |
| CN103197139A (en) | Clock frequency test method and clock frequency test circuit | |
| CN104508748A (en) | Power savings apparatus and method for memory device using delay locked loop | |
| CN102890445B (en) | Multi-functional timer | |
| CN201035573Y (en) | Flash memory microcontroller | |
| US9733690B2 (en) | Communication device which decreases power comsumption by powering off unused functions when device is inactive | |
| CN104035018A (en) | Voltage self-adaptive adjustment circuit and chip | |
| CN102957426B (en) | A kind of adaptive circuit of program-controlled rotary encoder | |
| US8645742B2 (en) | Semiconductor device operating according to an operation clock and having a serial communication interface performing external communications according to a unit transfer time based on the operation clock | |
| CN108089631A (en) | A kind of clock circuit for detecting for microcontroller chip | |
| CN210222120U (en) | Equal-precision broadband frequency meter based on STM32 | |
| CN111158758B (en) | Method and device for waking up central processing unit | |
| CN105703745B (en) | A kind of clock status indicating circuit and method | |
| CN203324693U (en) | Timing system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |