CN105703745B - A kind of clock status indicating circuit and method - Google Patents
A kind of clock status indicating circuit and method Download PDFInfo
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- CN105703745B CN105703745B CN201410679855.1A CN201410679855A CN105703745B CN 105703745 B CN105703745 B CN 105703745B CN 201410679855 A CN201410679855 A CN 201410679855A CN 105703745 B CN105703745 B CN 105703745B
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Abstract
The present invention relates to a kind of clock status indicating circuits, including clock division circuits, edge amendment circuit, edge sense circuit and shift-register circuit；Circuit connection is corrected at the clock division circuits and edge；The edge amendment circuit is connect with edge sense circuit, shift-register circuit；The edge sense circuit is connect with shift-register circuit；Its method is to generate different sub-frequency clock signal and cycle reset signal, displacement and reset operation instruction clock status by shift register.For circuit of the present invention when using 2 frequency dividing, six triggers are can be used in minimum and clock status instruction function can be thus achieved in two gate circuits, have many advantages, such as that structure is simple, runs small power consumption.
Description
Technical field
The present invention relates to a kind of clock status indicating circuit and method, specifically a kind of prison for on-chip system chip
Control the whether normal circuit of clock status and method.
Background technique
As integrated circuit technique, the especially rapid development of on-chip system chip technology, chip interior are generally integrated
Multiple clock oscillator, relatively common such as resistance-capacitance type oscillator, quartz oscillator.Different clock oscillators opens
The dynamic time is different, and precision, stability are also different.Usually, resistance-capacitance type oscillator has the starting time fast, and precision is opposite
The features such as low；The features such as quartz oscillator has the starting time slow, and precision is high.On-chip system chip is in the process of working on power
In, enter working condition to reach quick start, usually first uses resistance-capacitance type oscillator as system work clock, to quartz
After crystal oscillator stablizes starting, it is switched to system work clock automatically.In order to complete clock handoff procedure, system on chip
Chip interior must have working condition of the clock status indicating circuit for real-time telltable clock.It therefore is including that multi-clock vibrates
It generally all include clock monitor circuit inside the on-chip system chip of device.Clock monitor circuit can be used in on-chip system chip
When starting or when having clock oscillator failure, switching or disablement signal are generated, guarantees the normal work of chip.
Traditional implementation method is generally taken using two timers, and respectively reference clock and detection clock is counted respectively
Number, by being compared to count value, judges loss of clock.Also some methods use single counter, and two stage latch structure is led to
The similarities and differences for crossing two stage latch value judge whether clock is lost.No matter using above any method, circuit structure is all relatively multiple
Logical resource miscellaneous, consumption is more, can bring negative effect to the power consumption of on-chip system chip.
Summary of the invention
It is insufficient in view of the above technology, the clock status indicating circuit that it is an object of the present invention to provide a kind of towards system on chip and
Method.The circuit effectively can carry out state instruction to clock signal to be measured when clock frequency to be measured is greater than reference clock,
Generate the condition indicative signal of clock to be measured.
In order to achieve the above functions, this invention takes technical solutions below: a kind of clock status indicating circuit, including
Clock division circuits, edge amendment circuit, edge sense circuit and shift-register circuit；The clock division circuits and edge
Correct circuit connection；The edge amendment circuit is connect with edge sense circuit, shift-register circuit；The Edge check electricity
Road is connect with shift-register circuit；
The clock division circuits is for dividing reference clock, output frequency division clock signal to Edge check electricity
Road；
The edge sense circuit accesses clock to be measured, the sub-frequency clock signal of clock division circuits output and edge amendment
The edge revise signal of circuit output carries out edge detection to sub-frequency clock signal, and output cycle reset signal to edge is corrected
Circuit and shift-register circuit；
Edge amendment circuit access reference clock and cycle reset signal are modified to obtain edge revise signal defeated
Out to edge sense circuit；
The shift-register circuit accesses high level, reference clock and cycle reset signal, carries out internal register shifting
Position and reset operation, export clock status signal.
The clock division circuits includes NOT gate and register；The connection of the data terminal of the non-gate output terminal and register,
Output of the output end of register as clock division circuits, and the input terminal connection of NAND gate；The clock end of register accesses
Reference clock.
The edge sense circuit includes sequentially connected three registers and an XOR gate；Three registers
Clock end accesses clock to be measured, and reset terminal is connect with the output end of edge amendment circuit, sequentially connected first register
Data terminal as edge sense circuit input and connect with the output end of clock division circuits, third register output end with it is different
Or the first input end connection of door, the second input terminal connection of the second register output end and XOR gate, the output end of XOR gate
Output as edge sense circuit.
The edge sense circuit include NOT gate and with door, the input terminal of NOT gate accesses reference clock, output end with door
First input end connection, connect with the output end of the second input terminal of door and edge sense circuit, output end is Edge check
The output of circuit.
The shift-register circuit includes the register of multiple sequential connections, and the clock end of each register accesses ginseng
Clock is examined, reset terminal is connect with the output end of edge sense circuit, and the data terminal of first register connects high level, last
Output of the output end of a register as shift-register circuit.
A kind of clock status indicating means, comprising the following steps:
A. clock division circuits divides reference clock to obtain sub-frequency clock signal；
B. edge sense circuit carries out edge detection to sub-frequency clock signal and obtains cycle reset signal；
C. shift-register circuit transmits high level step by step, and when clock to be measured is normal, cycle reset signal is to inside
Register resetted, shift-register circuit output keep low level；When clock exception to be measured, cycle reset signal is lost
It loses, shift-register circuit output keeps high level；
D. edge amendment circuit stops in clock to be measured and when cycle reset abnormal signal, by the reference clock negated with it is all
Phase reset signal carries out phase and generates edge revise signal；
E. clock status signal, return step a are exported by shift-register circuit.
The edge detection is specially the output of sequentially connected second register and third register when generating edge
It differs, high level is generated by XOR gate.
It is described to carry out frequency dividing to carry out N- equal duty ratio frequency dividing.
The series of register is N+1 grades or more in the shift-register circuit.
The invention has the following beneficial effects and advantage:
1. circuit of the present invention can effectively provide the state of clock signal to be measured towards system-on-chip designs.
It, can be in IC design without analog circuit 2. circuit of the present invention all uses Design of Digital Circuit to realize
Or the multiple fields such as Field Programmable Logic Array design use.
3. circuit of the present invention is when using 2 frequency dividing, minimum can be used six triggers and two gate circuits and can be thus achieved
Clock status indicates function, has many advantages, such as that structure is simple, runs small power consumption.
Detailed description of the invention
Fig. 1 is a kind of clock status indicating circuit structure chart of the present invention；
Fig. 2 is 2 frequency-dividing clock frequency dividing circuit structure charts；
Fig. 3 is edge sense circuit structure chart；
Fig. 4 is edge amendment circuit structure diagram；
Fig. 5 is shift-register circuit structure chart.
Specific embodiment
The present invention is described in further detail with reference to the accompanying drawings and detailed description.
A kind of clock status indicating circuit, external input port include reference clock signal, clock signal to be measured, output end
Mouth includes clock status signal.
The port function of circuit is described as follows when this hair: reference clock signal is to continuously generate, to generate clock status letter
Number the clock of reference is provided, 32KHz, the low-frequency clocks such as 10KHz can be used in practical applications in generally low frequency clock；To
Surveying clock signal is to be clock signal under, and refers generally to high-frequency clock, in profession of the invention, should be the 3 of reference clock frequency
Times or more；Clock status signal indicates whether clock signal to be measured works normally, if worked normally, exports low level signal,
Otherwise high level signal is generated.
Functional module of the invention includes clock division circuits, edge amendment circuit, edge sense circuit, shift register
Circuit.
Module and port connection relationship of the invention is as follows: the input clock port of the clock division circuits is by referring to
Clock signal input, output port are sub-frequency clock signal；The input clock port of edge sense circuit is by clock signal to be measured
Input, input reseting port are inputted by the edge revise signal of edge sense circuit, and output port is cycle reset signal；Edge
The input clock port of amendment circuit is inputted by reference clock signal, inputs reseting port by the cycle reset of edge sense circuit
Signal input, output port are edge revise signal；The input clock port of shift-register circuit is defeated by reference clock signal
Enter, input reseting port is inputted by the cycle reset signal of edge sense circuit, and output port is clock status signal.
The function of clock division circuits is to carry out N- equal duty ratio to reference clock signal to divide to obtain in the invention patent
Sub-frequency clock signal, the effective high level and low level length of the signal are NT/2.Wherein the value range of N is 1 to infinity,
When N value is 1, i.e., without frequency dividing.If the duty ratio of reference clock signal meet or close to 1, N can value be 1.
Edge sense circuit is under clock to be measured effect in the invention patent, to the frequency-dividing clock of clock division circuits generation
Signal carries out edge detection, specifically extraction rising edge and failing edge, generates the cycle reset signal that the period is NT.
The effect of edge amendment circuit is the cycle reset signal generated to edge sense circuit and ginseng in the invention patent
Clock signal is examined, by combinational logic circuit, generates edge revise signal.
Shift-register circuit includes N+1 grades of register groups in the invention patent, in cycle reset signal and reference clock
It under effect, the operation such as is resetted and is shifted, generate clock status signal.
The principles illustrated of circuit of the present invention is as follows.
Note reference clock signal frequency is F, frequency T.By the relationship of frequency and clock, the product that can obtain F and T is equal to 1,
That is F is equal to 1/T.
The available effective high level of N- equal duty ratio frequency dividing is carried out to reference clock signal and low level length is NT/2,
Period is the frequency-dividing clock of NT；When clock to be measured is effective, it is NT cycle reset signal that the period can be generated with frequency-dividing clock；?
In the N+1 grade shift register group that high level input, reference clock drive, due to the work for the cycle reset signal that the period is NT
With shift-register circuit is resetted by the period of NT, so that high level be merely able to be transmitted to shift register N grades are posted
Storage is not transferred to N+1 grades of shift-register circuit, i.e. clock status signal remains low level；When to be measured
When clock invalidating signal, edge sense circuit can not generate cycle reset signal, N+1 grades of registers in shift-register circuit
It is final to generate high level instruction.
Due to the uncertainty of clock to be measured, under certain conditions, it is possible to create abnormal cycle reset signal at this time can
The influence that mistake is generated to shift-register circuit generates the clock status result of mistake.The amendment of the result can be passed through
Cycle reset signal and reversed reference clock by with gate logic, generate edge revise signal.Edge revise signal can repair
The cycle reset signal of normal anomaly, and finally generate correct clock status signal.
When using N- equal duty ratio frequency dividing, the series of shift register is N+1 or more, can protect the normal work of original circuit
Make.
The method and step of circuit of the present invention are as follows:
Clock division circuits carries out N- equal duty ratio to reference clock signal and divides to obtain the period as NT sub-frequency clock signal；
Edge sense circuit carries out edge detection to the sub-frequency clock signal that clock division circuits generates, and the generation period is NT
Cycle reset signal；
Shift-register circuit transmits high level step by step, and when clock to be measured is normal, cycle reset signal is to inside
Register is resetted, and shift-register circuit output keeps low level；When clock exception to be measured, cycle reset signal is lost
It loses, shift-register circuit output keeps high level.
Circuit is corrected when detecting abnormal cycle reset signal in edge, generates edge revise signal；Edge check electricity
Road carries out logic circuit processing, corrects abnormal cycle reset signal under the effect of edge revise signal.
Shift-register circuit generates clock status signal according to cycle reset signal and reference clock signal
Embodiment:
The present embodiment is a kind of mode for realizing clock status indicating circuit described in this patent, is used relatively simple
Circuit structure, wherein the N value in clock division circuits is 2, i.e., using the duties such as 2- frequency dividing, shift register is posted using 3
Storage shift-register circuit.
Specific embodiment refering to Figure 1, a kind of clock status indicating circuit, include in structure clock division circuits,
Edge sense circuit, edge amendment circuit and shift-register circuit；Outside port includes output port reference clock and to be measured
Clock, output port clock status.
Specific connection relationship is that reference clock signal is connected to the clock port CK of clock division circuits, clock division electricity
The clock output port Q on road generates sub-frequency clock signal C1；Clock signal to be measured is connected to the clock port of edge sense circuit
CK, clock division circuits generate the data port D that sub-frequency clock signal C1 is connected to edge sense circuit, and edge is corrected circuit and produced
Raw edge revise signal F1 is connected to the reset terminal of edge sense circuit, and the output port Q of edge sense circuit generates set letter
Number R1；
The input clock port CK of edge amendment circuit is inputted by reference clock signal, and input reseting port R is examined by edge
The cycle reset signal R1 of slowdown monitoring circuit is inputted, and output port is edge revise signal F1, is exported to the reset of edge sense circuit
Port R；
The cycle reset signal R1 that edge sense circuit generates is connected to the reseting port R of shift-register circuit, reference
Clock signal is connected to the clock port CK of shift-register circuit, the data port D connection high level of shift-register circuit
Signal, shift-register circuit export Q and generate clock status signal.
The present embodiment uses 2 frequency-dividing clock frequency dividing circuits, as shown in Figure 2.The frequency dividing circuit includes register 1 and NOT gate 1.
Its connection relationship is that the input end of clock mouth CK of register 1 is inputted by the portion input port CK of clock division circuits, register 1
Data-in port D inputted by the output port Q of NOT gate 1, the output port Q of register 1 is output to the input port of NOT gate 1
The output port Q of A, register 1 are output to the output port Q of clock division circuits；The input port A of NOT gate 1 is by register 1
Output port Q input, the output port Q of NOT gate 1 are output to the input port D of register 1.
Edge sense circuit structure is as shown in Figure 3 in the present embodiment.The edge sense circuit includes register 2, register
3, register 4 and XOR gate 1 form.Its connection relationship is the input port D of register 2 by edge sense circuit external input CK
The input port CK of input, register 2 is inputted by edge sense circuit external input CK, and the output port Q of register 2 is output to
The input port D of register 3；The input port CK of register 3 is inputted by edge sense circuit external input CK, register 2
Input port D is inputted by the output port Q of register 2, and the output port Q of register 3 is output to the input port D of register 4
With the input port B of XOR gate 1；The input port CK of register 4 is inputted by edge sense circuit external input CK, register 4
Input port D inputted by the output port Q of register 3, the output port Q of register 4 is output to the input port of XOR gate 1
A；The input port A of XOR gate 1 is inputted by the output port Q of register 4, and the output port B of XOR gate 1 is by the defeated of register 3
Exit port Q input, the output port Q of XOR gate 1 are output to the external output port Q of edge sense circuit.
Edge amendment circuit structure is as shown in Figure 4 in the present embodiment.The edge correct circuit include NOT gate 1 and with 1 group of door
At.Its connection relationship is that the input port A of NOT gate 1 is inputted by the outside port CK that circuit is corrected at edge, the output port of NOT gate 1
Q is connected to the input port A with door 1；It is accessed with the input port A of door 1 by the output port Q of NOT gate 1, the input terminal with door 1
Mouth B is accessed by the outside port R of edge amendment circuit, and the outside port of edge amendment circuit is output to the output port Q of door 1
Q。
Shift-register circuit structure is as shown in Figure 5 in the present embodiment.The shift-register circuit includes register 5, posts
Storage 6 and register 7 form.Its connection relationship be register 5 input port D inputted by high level signal, register 5 it is defeated
Inbound port CK is inputted by shift-register circuit external input port CK, and the output port Q of register 2 is output to register 6
Input port D；The input port CK of register 6 is inputted by shift-register circuit external input port CK, the input of register 6
Port D is inputted by the output port Q of register 5, and the output port Q of register 6 is output to the input port D of register 7；Deposit
The input port CK of device 7 is inputted by shift-register circuit external input port CK, and the input port D of register 7 is by register 6
Output port Q input, the output port Q of register 7 is output to shift-register circuit external output port Q.
The present embodiment only enumerates a kind of embodiment of this circuit, when Fractional-N frequency (N is even number) can be used in other implementations
Clock frequency dividing circuit, correspondence use N+1 or with higher level's shift-register circuit.If the set of edge detection circuit evolving is believed
Number R1 effective width is less than normal, and it is real that more triggers can be inserted between the register 3 in edge detection circuit and register 4
It is existing.
Claims (9)
1. a kind of clock status indicating circuit, it is characterised in that: correct circuit, Edge check including clock division circuits, edge
Circuit and shift-register circuit；Circuit connection is corrected at the clock division circuits and edge；The edge amendment circuit and side
It is connected along detection circuit, shift-register circuit；The edge sense circuit is connect with shift-register circuit；
The clock division circuits is for dividing reference clock, output frequency division clock signal to edge sense circuit；
The edge sense circuit accesses clock to be measured, the sub-frequency clock signal of clock division circuits output and edge amendment circuit
The edge revise signal of output carries out edge detection to sub-frequency clock signal, and output cycle reset signal to edge corrects circuit
And shift-register circuit；
Edge amendment circuit access reference clock and cycle reset signal be modified to obtain edge revise signal export to
Edge sense circuit；
The shift-register circuit accesses high level, reference clock and cycle reset signal, carry out internal register displacement and
Operation is resetted, clock status signal is exported.
2. a kind of clock status indicating circuit according to claim 1, it is characterised in that the clock division circuits includes
First NOT gate and register；The connection of the data terminal of the first non-gate output terminal and register, the output end of register as when
The output of clock frequency dividing circuit, and connect with the input terminal of the first NOT gate；The clock end of register accesses reference clock.
3. a kind of clock status indicating circuit according to claim 1, it is characterised in that the edge sense circuit includes
Sequentially connected three registers and an XOR gate；The clock end of three registers accesses clock to be measured, reset terminal
It is connect with the output end of edge amendment circuit, input of the sequentially connected first register data end as edge sense circuit
And connect with the output end of clock division circuits, the first input end connection of third register output end and XOR gate, second posts
The connection of second input terminal of storage output end and XOR gate, output of the output end of XOR gate as edge sense circuit.
4. a kind of clock status indicating circuit according to claim 1, it is characterised in that correct circuit and include in the edge
Second NOT gate and with door, the input terminal of the second NOT gate accesses reference clock, and output end is connect with the first input end with door, with door
The second input terminal and edge sense circuit output end connect, output end be edge correct circuit output.
5. a kind of clock status indicating circuit according to claim 1, it is characterised in that the shift-register circuit packet
The register of multiple sequential connections is included, the clock end of each register accesses reference clock, and reset terminal is electric with Edge check
The output end on road connects, and the data terminal of first register connects high level, and the output end of the last one register is posted as displacement
The output of latch circuit.
6. a kind of clock status indicating means, it is characterised in that the following steps are included:
A. clock division circuits divides reference clock to obtain sub-frequency clock signal；
B. edge sense circuit carries out edge detection to sub-frequency clock signal and obtains cycle reset signal；
C. shift-register circuit transmits high level step by step, and when clock to be measured is normal, cycle reset signal posts inside
Storage is resetted, and shift-register circuit output keeps low level；When clock exception to be measured, cycle reset dropout,
Shift-register circuit output keeps high level；
D. edge amendment circuit stops in clock to be measured and when cycle reset abnormal signal, and the reference clock negated is answered with the period
Position signal carries out phase and generates edge revise signal；
E. clock status signal, return step a are exported by shift-register circuit.
7. a kind of clock status indicating circuit according to claim 6, it is characterised in that the edge detection specifically: when
When generating edge, the output of sequentially connected second register and the output of third register are unequal, are generated by XOR gate
High level；
The edge sense circuit includes sequentially connected three registers and an XOR gate；The clock of three registers
Clock to be measured is accessed at end, and reset terminal is connect with the output end of edge amendment circuit, sequentially connected first register data
It holds the input as edge sense circuit and is connect with the output end of clock division circuits, third register output end and XOR gate
First input end connection, the second input terminal of the second register output end and XOR gate connects, the output end conduct of XOR gate
The output of edge sense circuit.
8. a kind of clock status indicating circuit according to claim 6, it is characterised in that described to carry out frequency dividing to carry out N-
Equal duty ratio frequency dividing.
9. a kind of clock status indicating circuit according to claim 8, it is characterised in that deposited in shift-register circuit
The series of device is N+1 grades or more.
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| CN201410679855.1A CN105703745B (en) | 2014-11-24 | 2014-11-24 | A kind of clock status indicating circuit and method |
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| CN201410679855.1A CN105703745B (en) | 2014-11-24 | 2014-11-24 | A kind of clock status indicating circuit and method |
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| CN105703745B true CN105703745B (en) | 2019-01-04 |
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| CN105913822B (en) | 2016-06-23 | 2018-07-17 | 京东方科技集团股份有限公司 | GOA signal judging circuits and judgment method, gate driving circuit and display device |
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|---|---|---|---|---|
| CN1571957A (en) * | 2001-08-03 | 2005-01-26 | 阿尔特拉公司 | Clock loss detection and switchover circuit |
| US20080054945A1 (en) * | 2006-08-31 | 2008-03-06 | El-Kik Tony S | Method and apparatus for loss-of-clock detection |
| WO2009076097A1 (en) * | 2007-12-06 | 2009-06-18 | Rambus Inc. | Edge-based loss-of-signal detection |
| CN102497200A (en) * | 2011-12-13 | 2012-06-13 | 东南大学 | Clock signal loss detecting circuit and clock signal loss detecting method |
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2014
- 2014-11-24 CN CN201410679855.1A patent/CN105703745B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1571957A (en) * | 2001-08-03 | 2005-01-26 | 阿尔特拉公司 | Clock loss detection and switchover circuit |
| US20080054945A1 (en) * | 2006-08-31 | 2008-03-06 | El-Kik Tony S | Method and apparatus for loss-of-clock detection |
| WO2009076097A1 (en) * | 2007-12-06 | 2009-06-18 | Rambus Inc. | Edge-based loss-of-signal detection |
| CN102497200A (en) * | 2011-12-13 | 2012-06-13 | 东南大学 | Clock signal loss detecting circuit and clock signal loss detecting method |
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