CN102111260B - Crossing-clock domain event bidirectional transmitting method and device thereof - Google Patents
Crossing-clock domain event bidirectional transmitting method and device thereof Download PDFInfo
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- CN102111260B CN102111260B CN2009102434860A CN200910243486A CN102111260B CN 102111260 B CN102111260 B CN 102111260B CN 2009102434860 A CN2009102434860 A CN 2009102434860A CN 200910243486 A CN200910243486 A CN 200910243486A CN 102111260 B CN102111260 B CN 102111260B
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Abstract
The invention provides a crossing-clock domain event bidirectional transmitting method in the design field of a multi-clock domain digital integrated circuit and a device thereof. In the method, two signal or data change detectors in different clock domains, one status indication device which is internally provided with two sub-modules and two status detectors in the different clock domains are used. After an event in any clock domain is triggered, the detectors generate pulse control signals to start up the status indication device, then corresponding clock domain sub-status modules in the status indication device generate status turning, and finally the status detectors output results in accordance with the statuses of the two sub-status modules, thus completing transmission of the event from a source clock domain to a target clock domain. Because the two status sub-modules in the status indication device are paired completely, crossing-clock domain bidirectional transmission of events can be realized by the device in the invention from the source clock domain to the target clock domain and from the target clock domain to the source clock domain without special requirements on clocks in the two clock domains.
Description
Technical field
The present invention is mainly used in the bi-directional of cross clock domain event in the multi-clock zone Design of Digital Integrated Circuit, as the transmission of interrupt requests event and response events, transmission of shared data buffer zone read-write event etc.
Background technology
In the Design of Digital Integrated Circuit field, SOC (system on a chip) (SOC) design has become topmost technology in present integrated circuit (IC) design.Increasing along with the SOC design scale, carry out dynamic simulation to asynchronous circuit and verify that the time that spends is also more and more longer, even becomes unacceptable.And for synchronous circuit, its characteristic is that the exporting change of circuit always has fixing relation (as always at rising edge clock or trailing edge, constantly changing) with clock.Therefore can use some static analysis means (as static timing analysis) to reduce to verify the workload of design sequential for synchronous circuit, greatly shorten the time of verifying.Therefore the synchronous circuit based on clock is used in a large number widely in Design of Digital Integrated Circuit.
Along with the increase of design complexities and for the consideration that reduces integrated circuit (IC) power consumption, tend to adopt a plurality of clock signals in design, the frequency of each clock signal and phase place all may be different.Circuit under generally same clock signal being driven in the art is called a clock zone., if the circuit that is operated under certain clock is output as the input that is operated in circuit under another clock, this signal is called the cross clock domain signal.If, to the dealing with improperly of cross clock domain signal, will violate because of the sequential of synchronous circuit, thereby cause circuit metastable state to occur, and then may cause logic error or function to be made mistakes in design.Because two relation and probabilities of finally leading to errors after occurring of metastable state between clock are depended in the appearance of this type of mistake, therefore often finally to show as reliability lower for such mistake, the generating function mistake, therefore be difficult to identified in this design mistake proof procedure in early days once in a while.
When needing cross clock domain to transmit event in design, also need circuit is carefully designed in addition, general transfer circuit can be wanted certain requirement to clock frequency relation or the phase relation of source clock zone and target clock zone, and can only realize unidirectional event transfer.Do not lose when the event that is passed will not appear in circuit design at that time that realize above-mentioned functions, and caused whole integrated circuit (IC) chip function to be made mistakes.
Summary of the invention
The object of the invention is to solve a kind of method of utilizing the cross clock domain event bi-directional of quantity of state, it not only can be used for the bi-directional of cross clock domain event between two clock zones, also applicable to a plurality of clock zones bi-directional of cross clock domain event between any two.
The bi-directional problem of event between two clock zones, namely two clock zones not only may be the source clock zones of transmission event but also may be the target clock zone of reception event in the different moment.By adopt the method that proposes in the present invention or device can be between the fully irrelevant clock zone of two clock frequencies, phase place the reliable bi-directional of realization event, also can complete a plurality of clock zones bi-directional of cross clock domain event between any two.Concrete technical scheme of the present invention is as follows:
(1). when being operated in event detection device in clock zone 1 and a validity event in clock zone 1 being detected, event may be an interrupt requests or to sharing a read or write event of data buffer zone.When the particular event generation being detected (as effective in interrupt request singal, or external equipment has been carried out a read or write to sharing data buffer zone), effective impulse signal of checkout gear output.
(2). two submodules in state indicating device are operated in separately clock zone 1 and 2, two submodules of clock zone use 1 Bit data (quantity of state) to represent its state.Under initial condition, the quantity of state of two submodules is set to identical; Represent two sub-module status mutual exclusions when the quantity of state of two submodules is different.
(3). after state indicating device receives the pulse signal of event detection device output in clock zone 1, at first the state of its two submodules in inside judged, if two submodules have been in the mutual exclusion state, so the event transfer before the expression is not yet completed, need to abandon the event of new generation, so submodule does not upgrade its state.If two submodules are in non-exclusive state, state indicating device upgrades the state of submodule A, and its quantity of state overturns.
(4). being operated in condition checkout gear in clock zone 2, the quantity of state of the inner submodule A of state indicating device and B to be detected different, in clock zone 2 output detections results, realization event transmission of 2 from clock zone 1 to clock zone, and pulse signal is responded in generation simultaneously, state indicating device is according to the state of responding pulse signal renewal submodule B, (its quantity of state namely overturns), make the quantity of state of submodule A and B again become identical, this moment, whole device was got back to initial condition, and once 2 event transfer is completed from clock zone 1 to clock zone.
(5). because whole device is dual structure, therefore when needs from clock zone 2 to clock zone during 1 transmission event, whole process and above-mentioned steps 1 to 4 are similar.
Description of drawings
Fig. 1 has provided each functional module and the interconnected relationship thereof that the device realized according to the method in the present invention comprises.
Fig. 2 has provided the state switching figure of submodule in the state indicating module.
Fig. 3 has provided the functional block diagram according to the designed chip of the embodiment of the present invention.
Fig. 4 has provided the key signal sequential chart according to the designed chip of the embodiment of the present invention.
Embodiment
Below in conjunction with accompanying drawing, embodiments of the invention are described.The present embodiment is implemented under the prerequisite with technical solution of the present invention, provided detailed execution mode and realized that details, protection scope of the present invention are not limited to following embodiment.
As shown in Figure 3, when the particular event of ancillary equipment occurred, the processor that needs notice to be in another clock zone carried out respective handling.Simultaneously, in other cases, when occurring, particular event on processor also need to notify the ancillary equipment that is in another clock zone to carry out respective handling.Whole process realize that details is as described below, in whole process, the sequential of key signal is as shown in Figure 4:
1. under initial situation, output event_detectA and the event_detectB of the event detection device of two clock zones all remain low level, the state of state indicating device neutron modules A is consistent with the state of submodule B, and its quantity of state stateA and stateB are low level;
2. when the particular event of ancillary equipment occurred, the event detection device in clock zone 1 produced Event triggered pulse event_detectA, and this pulse signal keeps the high level in clock (clkl) cycle in a clock zone 1;
3. under the control of Event triggered pulse, the submodule A generation state in state indicating device upgrades, and its quantity of state (stateA) overturns;
4. utilize the clock (clk2) of clock zone 2 to carry out two-stage d type flip flop sampling processing to the stateA signal and obtain stateA ', the condition checkout gear that is operated in clock zone 2 this moment is known the difference of submodule A and submodule B quantity of state by detecting stateA ' and stateB, therefore export a testing result pulse (resultB) and a response pulse (ackB);
5. under the control of responding pulse, in state indicating device, the state of submodule B is updated, its quantity of state stateB upset, this moment event from clock zone 1 to clock zone 2 event transfer complete, the state of state indicating device neutron modules A and submodule B is again identical, only this moment, quantity of state was high level, and this moment, whole circuit was got back to again initial condition, can carry out event transfer next time;
6. when particular event on processor occurred, the event detection device in clock zone 2 produced Event triggered pulse event_detectB, and similar with the event_detectA sequential, this signal also keeps the high level in clock (clk2) cycle in a clock zone 2;
7. under the control of Event triggered pulse, the submodule B generation state in state indicating device upgrades, and its quantity of state (stateB) overturns;
8. utilize the clock (clkl) of clock zone 1 to carry out two-stage d type flip flop sampling processing to the stateB signal and obtain stateB ', the condition checkout gear that is operated in clock zone 1 this moment is known the difference of submodule A and submodule B quantity of state by detecting stateB ' and stateA, therefore export a testing result pulse (resultA) and a response pulse (ackA);
9. under the control of responding pulse, the state of state indicating device neutron modules A is updated, its quantity of state stateA upset, this moment event from clock zone 2 to clock zone 1 event transfer complete, the state of state indicating device neutron modules A and submodule B is again identical, and after this whole circuit can carry out again event transfer next time;
The above has described the process of carrying out two-way event transfer by the device in the present invention between two clock zones and the concrete details that realizes.The method that proposes in the present invention and according to the device of its realization, can be applied to two-way event transfer between two frequencies, phase-independent clock zone, also applicable to a plurality of clock zones bi-directional of cross clock domain event between any two.
Claims (6)
1. device that utilizes the cross clock domain event bi-directional of quantity of state is characterized in that comprising:
Event detection device: produce the Event triggered pulse when this clock zone event occurs, effective impulse signal of event detection device output, the action of starting state indicating device;
State indicating device: when the Event triggered pulse generation of arbitrary clock zone, state indicating device upgrades the submodule state of corresponding clock zone;
Condition checkout gear: condition checkout gear compares the output of two sub-module status in state indicating device, export effective result when two sub-module status are different, and pulse control signal is responded in generation, state indicating device, according to the state of responding the corresponding submodule of pulse control signal renewal, is realized the transmission across event clock.
2. a kind of device that utilizes the cross clock domain event bi-directional of quantity of state according to claim 1, it is characterized in that described state indicating device inside comprises two submodules, the initial condition of two submodules is identical, when two sub-module status amounts are different, no longer upgrade the state of submodule.
3. a kind of device that utilizes the cross clock domain event bi-directional of quantity of state according to claim 1, it is characterized in that the submodule in described state indicating device utilizes 1 Bit data to represent the submodule state, also corresponding upset of its quantity of state after a sub-module status is updated.
4. method of utilizing the cross clock domain event bi-directional of quantity of state is characterized in that comprising following steps:
(1). be operated in an event detection device in clock zone and a validity event in this clock zone detected, effective impulse signal of event detection device output;
(2). after state indicating device receives the pulse signal of event detection device output in this clock zone, at first the state of its two submodules in inside judged, if two sub-module status amounts are different, need to abandon this validity event, the submodule state does not upgrade; If two sub-module status amounts are identical, state indicating device upgrades the state of corresponding submodule, and its quantity of state overturns;
(3). being operated in condition checkout gear in another clock zone, the quantity of state of the inner submodule of state indicating device to be detected different, clock territory output detections result at this moment, and producing simultaneously the response pulse signal, state indicating device is according to the state of responding the corresponding submodule of pulse signal renewal.
5. a kind of method of utilizing the cross clock domain event bi-directional of quantity of state as claimed in claim 4, it is characterized in that two submodules in state indicating device are operated in clock zone separately, two submodules use 1 Bit data to represent its state, under initial condition, the quantity of state of two each and every one submodules is set to identical.
6. a kind of method of utilizing the cross clock domain event bi-directional of quantity of state as claimed in claim 4, is characterized in that the method is applicable to a plurality of clock zones bi-directional of cross clock domain event between any two.
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| CN2009102434860A CN102111260B (en) | 2009-12-23 | 2009-12-23 | Crossing-clock domain event bidirectional transmitting method and device thereof |
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| CN2009102434860A CN102111260B (en) | 2009-12-23 | 2009-12-23 | Crossing-clock domain event bidirectional transmitting method and device thereof |
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Address after: 102209 Beijing, Beiqijia, the future of science and technology in the south area of China electronic network security and information technology industry base C building, Patentee after: Beijing CEC Huada Electronic Design Co., Ltd. Address before: 100102 Beijing City, Chaoyang District Lize two Road No. 2, Wangjing science and Technology Park A block five layer Patentee before: Beijing CEC Huada Electronic Design Co., Ltd. |