CN102497200A - Clock signal loss detecting circuit and clock signal loss detecting method - Google Patents
Clock signal loss detecting circuit and clock signal loss detecting method Download PDFInfo
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- CN102497200A CN102497200A CN2011104158330A CN201110415833A CN102497200A CN 102497200 A CN102497200 A CN 102497200A CN 2011104158330 A CN2011104158330 A CN 2011104158330A CN 201110415833 A CN201110415833 A CN 201110415833A CN 102497200 A CN102497200 A CN 102497200A
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Abstract
The invention discloses a clock signal loss detecting circuit and a clock signal loss detecting method. The circuit comprises a frequency dividing module, a counting module, a displacing module, a comparing module and a detecting module. The method utilizes a low-frequency clock to detect a high-frequency and includes five steps to realize a process: dividing frequencies, counting, displacing, comparing and detecting. The clock signal loss detecting circuit and the clock signal loss detecting method have the advantages that by means of detecting whether clock signals lose or not, normal operation of an integrated circuit system can be guaranteed, logical resources are saved, and overall performance of the integrated circuit system is improved. Besides, a universal solution to the design of an application specific integrated circuit multiplexed by an IP (intellectual property) module is provided, so that time for developing products is shortened, and design cost is reduced.
Description
Technical field
The present invention relates to a kind of clock signal missing detecting circuit and method, belong to electronic technology field.Through the enforcement of clock signal missing detecting circuit and method and technology scheme, can realize that loss of clock detects, avoid the operation of the system that can not keep because the master clock that Circuits System is used is lost.
Background technology
Clock signal is the reference signal of digital integrated circuit and Digital Analog Hybrid Circuits work, maybe be the inside or outside generation of Circuits System.Because crystal oscillator has very high quality factor, the clock signal great majority that IC design is at present used are all provided by crystal oscillator, and the accuracy of clock signal and stability have determined the reliability of Circuits System function.And the speed of the disappearance of clock signal and clock frequency has very big influence to the operating state of circuit, possibly cause the Circuits System can't normal running or decreased performance, therefore in the Circuits System design, needs a clock signal missing detecting circuit.
Can clock detection be divided into two types according to resource consumption and inefficacy effect: loss of clock detects and frequency offset detection.Whether the former can only lose by read clock, and the latter can make a concrete analysis of the accuracy of clock signal.In the prior art, the detection method of clock signal is normally placed counter in logical circuit, signal to be detected is carried out frequency division, obtain the signal behind the frequency division, detect with the signal of high frequency clock signal actuation counter after to frequency division.If the frequency that require to detect clock is higher than the frequency of clock to be detected, when the frequency of clock to be detected is very high, the selection that detects clock frequency will become technical bottleneck.
On the other hand, along with the deep sub-micron fabrication of integrated circuit and developing rapidly of designing technique, the complexity of chip design increases sharply, and the pressure of market competition forces the designer to shorten the design cycle to greatest extent.How to utilize forefathers' successful design experiences and design data very necessary, this just requires the designer to reuse and has designed and passed through the ip module IP (Intellectual Property) that verifies.Because IP kernel verifies that the designer can be absorbed in the design of whole system, thereby improve desin speed, make full use of existing resource, reduce cost, shorten time to market (TTM).
Summary of the invention
Goal of the invention: to the problems and shortcomings that exist in the prior art, the present invention provide a kind of simple, effectively, the circuit and the method for stable clock signal loss detection.
Technical scheme: a kind of clock signal missing detecting circuit comprises frequency division module, counting module, shift module, comparison module and detection module; The output of said frequency division module connects the input of shift module; The output of said shift module connects comparison module; Said comparison module is output as the override signal of counter; When said detection module triggers at the rising edge that detects clock, whether be 0 to judge whether clock to be detected is lost according to the count value of computing module.
Said frequency division module comprises first integrated trigger.
Said counting module comprises a counter.
Said shift module comprises second integrated trigger, the 3rd integrated trigger, the 4th integrated trigger and the 5th integrated trigger; Second integrated trigger is output as the input of the 3rd integrated trigger; The 3rd integrated trigger is output as the input of the 4th integrated trigger; The 4th integrated trigger is output as the input of the 5th integrated trigger, the two divided-frequency clock signal of the detection clock that is input as frequency division module of second integrated trigger; When the rising edge of clock to be detected triggered, the output of second integrated trigger, the 3rd integrated trigger and the 4th integrated trigger was shifted successively.
Said comparison module comprises one and door, first comparator, second comparator and the 3rd comparator; First comparator compares the output of the output of second integrated trigger and the 3rd integrated trigger; Second comparator compares the output of the output of the 3rd integrated trigger and the 4th integrated trigger, and the 3rd comparator compares the output of the output of the 4th integrated trigger and the 5th integrated trigger; The output conduct of first comparator, second comparator and the 3rd comparator and the input of door are output as the override signal of counter with door.
Said detection module comprise one or and the 6th trigger.
A kind of method that is used for above-mentioned clock signal missing detecting circuit, the clock signal missing detecting circuit receives stable detection clock and two clock signals of clock to be detected, and wherein detecting clock is low-frequency clock, and clock to be detected is a high frequency clock; Whether indicate clock to be detected to lose by detecting clock, implementation procedure is divided into five parts: frequency division part, segment count, displacing part, rating unit, test section.
Said frequency division receives and detects clock as clock pulse CP partly through first integrated trigger, and output detects the two divided-frequency clock signal of clock, and with detect clock synchronization;
Said segment count is through a counter, and after counting enabled, whether heavily loaded by the override signal control counter, override signal was 1 o'clock, and counter reloads count value, and override signal is 0 o'clock, counter counts down to 0; After the counter counts down to 0 of counter, if override signal still is 0, then counter remains 0 constantly, and counter neither resets when also not enabling, and counter remains 0;
Said displacing part comprises second integrated trigger, the 3rd integrated trigger, the 4th integrated trigger and the 5th integrated trigger; Second integrated trigger is output as the input of the 3rd integrated trigger; The 3rd integrated trigger is output as the input of the 4th integrated trigger; The 4th integrated trigger is output as the input of the 5th integrated trigger, the two divided-frequency clock signal of the detection clock that is input as frequency division module of second integrated trigger; When the rising edge of clock to be detected triggered, the output of second integrated trigger, the 3rd integrated trigger and the 4th integrated trigger was shifted successively;
Rating unit comprises one and door, first comparator, second comparator and the 3rd comparator; First comparator compares the output of the output of second integrated trigger and the 3rd integrated trigger; Second comparator compares the output of the output of the 3rd integrated trigger and the 4th integrated trigger, and the 3rd comparator compares the output of the output of the 4th integrated trigger and the 5th integrated trigger; The output conduct of first comparator, second comparator and the 3rd comparator and the input of door are output as the override signal of counter with door;
The test section comprise one or and the 6th trigger, when the rising edge that detects clock triggers, whether be 0 to judge whether clock to be detected is lost according to count value, when count value was not 0, clock signal then to be detected was lost;
System reset; The two divided-frequency clock signal that detects clock is a spacing wave; Counter O reset; First integrated trigger, second integrated trigger, the 3rd integrated trigger, the 4th integrated trigger, the 5th integrated trigger and the 6th integrated trigger zero clearing, the zero clearing of counter override signal, the zero clearing of loss of clock signal.
The override signal of said counter is by the ratio decision that detects clock frequency and clock frequency to be detected.
Whether heavily loaded comparative result by comparator determines the count value of counter; Equal the output of the 3rd integrated trigger when the output of second integrated trigger; The output of the 4th integrated trigger equals the output of the 5th integrated trigger; And the output of the 3rd integrated trigger is when being not equal to the output of the 4th integrated trigger, and override signal is 1, the counter heavy duty.
Beneficial effect: whether clock signal missing detecting circuit provided by the invention and method lose through detecting clock signal, can normal running to guarantee IC system, save logical resource, and improve the overall performance of IC system.And in the application-specific integrated circuit (ASIC) design of IP module reuse, a kind of general solution is provided, shortens the product development time, reduce design cost simultaneously.
Description of drawings
Fig. 1 is the circuit theory diagrams of embodiment of the invention clock signal missing detecting circuit;
Fig. 2 is the detection waveform figure of embodiment of the invention clock signal loss detection method.
Embodiment
Below in conjunction with accompanying drawing and specific embodiment; Further illustrate the present invention; Should understand these embodiment only be used to the present invention is described and be not used in the restriction scope of the present invention; After having read the present invention, those skilled in the art all fall within the application's accompanying claims institute restricted portion to the modification of the various equivalent form of values of the present invention.
As shown in Figure 1: the clock signal missing detecting circuit is an instance of in SoC (system on chip, SOC(system on a chip)), realizing with language.This clock signal missing detecting circuit comprises a n position integrated counter A; Six integrated triggers (promptly; The first trigger B, the second trigger C, the 3rd trigger D, the 4th trigger E, the 5th trigger F and the 6th trigger G), three integrated data comparators (that is, the first comparator H, the second comparator I, the 3rd comparator J); Import and a door K for one three, a n imports or door L.
The input stable detection clock CLKREF (low-frequency clock) from the outside, a clock CLKDET to be detected (high frequency clock), enable signal EN, reset signal RESET, the counting value of reloading CNTVALUE.
CNTVALUE＝f
CLKDET/f
CLKREF
Wherein,
The CP termination of the first trigger B is received clock CLKDET to be detected; Directly remove end RD and receive reset signal RESET; Its output
links to each other with input D, and output Q is for detecting the two divided-frequency clock signal HALF_CLKREF of clock CLKREF.
The CP termination of counter A is received clock CLKDET to be detected, directly removes end
Receive reset signal RESET, the counting Enable Pin receives enable signal EN, data input pin D
0～D
nCount pick up is thought highly of new loaded value CNTVALUE, puts several control ends synchronously
Receive override signal RELOAD.Output Q
0～Q
nWith or the door L input link to each other.The CP termination of the 6th trigger G is received and is detected clock CLKREF, directly removes end R
DReceive reset signal RESET, the output signal of input D reception or door L, output Q is loss of clock signal CLKLOSS.
The CP termination of the second trigger C, the 3rd trigger D, the 4th trigger E, the 5th trigger F is received clock CLKDET to be detected, directly removes end R
DReceive reset signal RESET; The input D of the second trigger C receives the two divided-frequency clock signal HALF_CLKREF that detects clock CLKREF; Output Q links to each other with the input of the 3rd trigger D; The output Q of the 3rd trigger D links to each other with the input of the 4th trigger E, and the output of the 4th trigger E links to each other with the input of the 5th trigger F.The second trigger C links to each other with two inputs of the first comparator H respectively with the output of the 3rd trigger D; The 3rd trigger D links to each other with two inputs of the second comparator I respectively with the output of the 4th trigger E, and the 4th trigger E links to each other with two inputs of data the 3rd comparator J respectively with the output of the 5th trigger F.
The F of the first comparator H
A=BOutput, the second comparator I's
The F of output, the 3rd comparator J
A=BOutput links to each other respectively with three inputs of door K, is counter override signal RELOAD with the output of door K.
The operation principle of foregoing circuit is: detect clock CLKREF and realize two divided-frequency through the first trigger B.The second trigger C latchs at the rising edge of the clock CLKDET to be detected currency to the two divided-frequency clock signal HALF_CLKREF that detects clock CLKREF, is output as CAPTURE1.The 3rd trigger D latchs CAPTURE1 at the rising edge of clock CLKDET to be detected, that is to say that the previous state value to HALF_CLKREF latchs, and is output as CAPTURE2.The 4th trigger E latchs CAPTURE2 at the rising edge of clock CLKDET to be detected, is output as CAPTURE3.The 5th trigger F latchs CAPTURE3 at the rising edge of clock CLKDET to be detected, is output as CAPTURE4.
When CAPTURE1 equals CAPTURE2, the F of the first comparator H
A=BBe output as 1; When CAPTURE3 equals CAPTURE4, the F of the 3rd comparator J
A=BBe output as 1; When CAPTURE2 is not equal to CAPTURE3, the second comparator I's
Be output as 1.At this moment, the value with the RELOAD signal of door K output is 1.
Counter enables, and override signal RELOAD is 1 o'clock, at the rising edge of clock CLKDET to be detected data CNTVALUE is inserted output Q
0～Q
n, the counter heavy duty; Override signal is 0 o'clock, counter counts down to 0.After the counter counts down to 0, if override signal still is 0, then count value remains 0 constant.Count value is 0 o'clock, or the output CLKLOSS that door L is output as 0, the six trigger G is 0; Count value is not 0 o'clock, or the output CLKLOSS that door L is output as 1, the six trigger G is 1, explains that clock signal to be detected loses.
Fig. 2 has described the detection waveform figure of clock signal missing detecting circuit, and count value DETCNT is 0 when supposing beginning, and CLKLOSS is 0.With the aid of pictures from left to right, that first changes is clock signal clk DET, CLKREF and HALF_CLKREF, all is to become 1 from 0.Through a CLKDET cycle, CAPTURE1 becomes 1, and CAPTURE2, CAPTURE3, CAPTURE4 still are 0.Through a CLKDET cycle, CAPTURE2 becomes 1 again, and CAPTURE3, CAPTURE4 still are 0.Satisfy CAPTURE1 and equal CAPTURE2 this moment, and CAPTURE3 equals CAPTURE4, and CAPTURE2 is not equal to the condition of CAPTURE3, and the RELOAD signal becomes 1, the counter heavy duty, and count value is CNTVALUE.Through a CLKDET cycle, CAPTURE3 becomes 1 again, and then RELOAD becomes 0, counter counts down.Pass through CNTVALUE-1 CLKDET clock cycle again, counter is decremented to 0.That the next one changes is CLKREF and HALF_CLKREF, and CLKREF becomes 1 from 0, and HALF_CLKREF becomes 0 from 1.When the rising edge that detects clock CLKREF triggered, CLKLOSS still was 0.If clock CLKDET to be detected loses in this section process, when second CLKREF triggered, counter just can not be decremented to 0.DETCNT is not equal to 0, so CLKLOSS equals 1.
A kind of method that is used for above-mentioned clock signal missing detecting circuit; The clock signal missing detecting circuit receives stable detection clock CLKREF and two clock signals of clock CLKDET to be detected; Wherein detecting clock CLKREF is low-frequency clock, and clock CLKDET to be detected is a high frequency clock; Indicate clock CLKDET to be detected whether to lose by detecting clock CLKREF.
Frequency division partly passes through the first integrated trigger B, receives to detect clock CLKREF as clock pulse CP, and output detects the two divided-frequency clock signal HALF_CLKREF of clock, and synchronous with detection clock CLKREF;
Segment count, the CP termination of counter A is received clock CLKDET to be detected, directly removes end
Receive reset signal RESET, the counting Enable Pin receives enable signal EN, data input pin D
0～D
nCount pick up is thought highly of new loaded value CNTVALUE, puts several control ends synchronously
Receive override signal RELOAD.Output Q
0～Q
nWith or the door L input link to each other.The CP termination of the 6th trigger G is received and is detected clock CLKREF, directly removes end R
DReceive reset signal RESET, the output signal of input D reception or door L, output Q is loss of clock signal CLKLOSS.
Displacing part, the CP termination of the second trigger C, the 3rd trigger D, the 4th trigger E, the 5th trigger F is received clock CLKDET to be detected, directly removes end R
DReceive reset signal RESET; The input D of the second trigger C receives the two divided-frequency clock signal HALF_CLKREF that detects clock CLKREF; Output Q links to each other with the input of the 3rd trigger D; The output Q of the 3rd trigger D links to each other with the input of the 4th trigger E, and the output of the 4th trigger E links to each other with the input of trigger.The 3rd trigger D links to each other with two inputs of the first comparator H respectively with the output of the 4th trigger E; The 4th trigger E links to each other with two inputs of the second comparator I respectively with the output of the 5th trigger F, and the 4th trigger E links to each other with two inputs of data the 3rd comparator J respectively with the output of the 5th trigger F.
Rating unit, the F of the first comparator H
A=BOutput, the second comparator I's
The F of output, the 3rd comparator J
A=BOutput links to each other respectively with three inputs of door K, is counter override signal RELOAD with the output of door K.
Whether the test section comprises one or a L and the 6th trigger G, when the rising edge that detects clock CLKREF triggers, be 0 to judge whether clock CLKDET to be detected loses according to count value, when count value is not 0, and clock CLKDET dropout then to be detected.
Claims (10)
1. a clock signal missing detecting circuit is characterized in that: comprise frequency division module, counting module, shift module, comparison module and detection module; The output of said frequency division module connects the input of shift module; The output of said shift module connects comparison module; Said comparison module is output as the override signal of counter; When said detection module triggers at the rising edge that detects clock, whether be 0 to judge whether clock to be detected is lost according to the count value of computing module.
2. clock signal missing detecting circuit as claimed in claim 1 is characterized in that: said frequency division module comprises first integrated trigger.
3. clock signal missing detecting circuit as claimed in claim 1 is characterized in that: said counting module comprises a counter.
4. clock signal missing detecting circuit as claimed in claim 1 is characterized in that: said shift module comprises second integrated trigger, the 3rd integrated trigger, the 4th integrated trigger and the 5th integrated trigger; Second integrated trigger is output as the input of the 3rd integrated trigger; The 3rd integrated trigger is output as the input of the 4th integrated trigger; The 4th integrated trigger is output as the input of the 5th integrated trigger, the two divided-frequency clock signal of the detection clock that is input as frequency division module of second integrated trigger; When the rising edge of clock to be detected triggered, the output of second integrated trigger, the 3rd integrated trigger and the 4th integrated trigger was shifted successively.
5. clock signal missing detecting circuit as claimed in claim 1 is characterized in that: said comparison module comprises one and door, first comparator, second comparator and the 3rd comparator; First comparator compares the output of the output of second integrated trigger and the 3rd integrated trigger; Second comparator compares the output of the output of the 3rd integrated trigger and the 4th integrated trigger, and the 3rd comparator compares the output of the output of the 4th integrated trigger and the 5th integrated trigger; The output conduct of first comparator, second comparator and the 3rd comparator and the input of door are output as the override signal of counter with door.
6. clock signal missing detecting circuit as claimed in claim 1 is characterized in that: said detection module comprise one or and the 6th trigger.
7. method that is used for like each described clock signal missing detecting circuit of claim 1-6; It is characterized in that; The clock signal missing detecting circuit receives stable detection clock and two clock signals of clock to be detected; Wherein detecting clock is low-frequency clock, and clock to be detected is a high frequency clock; Whether indicate clock to be detected to lose by detecting clock, implementation procedure is divided into five parts: frequency division part, segment count, displacing part, rating unit, test section.
8. clock signal loss detection method as claimed in claim 7 is characterized in that: said frequency division receives and detects clock as clock pulse CP partly through first integrated trigger, and output detects the two divided-frequency clock signal of clock, and with detect clock synchronization;
Said segment count is through a counter, and after counting enabled, whether heavily loaded by the override signal control counter, override signal was 1 o'clock, and counter reloads count value, and override signal is 0 o'clock, counter counts down to 0; After the counter counts down to 0 of counter, if override signal still is 0, then counter remains 0 constantly, and counter neither resets when also not enabling, and counter remains 0;
Said displacing part comprises second integrated trigger, the 3rd integrated trigger, the 4th integrated trigger and the 5th integrated trigger; Second integrated trigger is output as the input of the 3rd integrated trigger; The 3rd integrated trigger is output as the input of the 4th integrated trigger; The 4th integrated trigger is output as the input of the 5th integrated trigger, the two divided-frequency clock signal of the detection clock that is input as frequency division module of second integrated trigger; When the rising edge of clock to be detected triggered, the output of second integrated trigger, the 3rd integrated trigger and the 4th integrated trigger was shifted successively;
Rating unit comprises one and door, first comparator, second comparator and the 3rd comparator; First comparator compares the output of the output of second integrated trigger and the 3rd integrated trigger; Second comparator compares the output of the output of the 3rd integrated trigger and the 4th integrated trigger, and the 3rd comparator compares the output of the output of the 4th integrated trigger and the 5th integrated trigger; The output conduct of first comparator, second comparator and the 3rd comparator and the input of door are output as the override signal of counter with door;
The test section comprise one or and the 6th trigger, when the rising edge that detects clock triggers, whether be 0 to judge whether clock to be detected is lost according to count value, when count value was not 0, clock signal then to be detected was lost;
System reset; The two divided-frequency clock signal that detects clock is a spacing wave; Counter O reset; First integrated trigger, second integrated trigger, the 3rd integrated trigger, the 4th integrated trigger, the 5th integrated trigger and the 6th integrated trigger zero clearing, the zero clearing of counter override signal, the zero clearing of loss of clock signal.
9. clock signal loss detection method as claimed in claim 8 is characterized in that: the override signal of said counter is by the ratio decision that detects clock frequency and clock frequency to be detected.
10. clock signal loss detection method as claimed in claim 8 is characterized in that: whether heavily loaded comparative result by comparator determines the count value of counter; Equal the output of the 3rd integrated trigger when the output of second integrated trigger; The output of the 4th integrated trigger equals the output of the 5th integrated trigger; And the output of the 3rd integrated trigger is when being not equal to the output of the 4th integrated trigger, and override signal is 1, the counter heavy duty.
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| CN201110415833.0A CN102497200B (en) | 2011-12-13 | 2011-12-13 | Clock signal loss detecting circuit and clock signal loss detecting method |
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|---|---|---|---|
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Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105337607A (en) * | 2014-06-30 | 2016-02-17 | 澜起科技（上海）有限公司 | Clock signal loss detection device and method |
| CN105703745A (en) * | 2014-11-24 | 2016-06-22 | 中国科学院沈阳自动化研究所 | Clock state indicating circuit and method |
| CN104380606B (en) * | 2012-06-14 | 2017-04-26 | 阿海珐有限公司 | Digital sensing circuit for a secondary clock signal to be monitored for clock failure with the aid of a primary clock signal |
| WO2018058915A1 (en) * | 2016-09-28 | 2018-04-05 | 深圳市中兴微电子技术有限公司 | Clock signal loss detection device |
| CN108563283A (en) * | 2017-12-25 | 2018-09-21 | 中国航空工业集团公司洛阳电光设备研究所 | A kind of device of real time clock monitoring and system wake-up |
| CN109412581A (en) * | 2017-08-18 | 2019-03-01 | 杭州晶华微电子有限公司 | A kind of clock failure of oscillation detection circuit |
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| CN110350914A (en) * | 2019-06-18 | 2019-10-18 | 芯翼信息科技(上海)有限公司 | A kind of system on chip |
| CN110445492A (en) * | 2019-09-09 | 2019-11-12 | Oppo广东移动通信有限公司 | Cross clock domain frequency-dividing clock protects circuit, frequency dividing circuit, method and terminal device |
| CN112345820A (en) * | 2020-01-07 | 2021-02-09 | 成都华微电子科技有限公司 | High-speed serial signal loss detection circuit |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1302047A (en) * | 1999-12-29 | 2001-07-04 | 上海贝尔有限公司 | Clock signal pulse missing detecting circuit |
| CN1474508A (en) * | 2003-07-02 | 2004-02-11 | 西安大唐电信有限公司 | High frequency clock pulse loss monitoring detection circuit with low frequency clock |
| US7996749B2 (en) * | 2007-07-03 | 2011-08-09 | Altera Corporation | Signal loss detector for high-speed serial interface of a programmable logic device |
| CN202364199U (en) * | 2011-12-13 | 2012-08-01 | 东南大学 | Detection circuit for clock signal loss |
-
2011
- 2011-12-13 CN CN201110415833.0A patent/CN102497200B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1302047A (en) * | 1999-12-29 | 2001-07-04 | 上海贝尔有限公司 | Clock signal pulse missing detecting circuit |
| CN1474508A (en) * | 2003-07-02 | 2004-02-11 | 西安大唐电信有限公司 | High frequency clock pulse loss monitoring detection circuit with low frequency clock |
| US7996749B2 (en) * | 2007-07-03 | 2011-08-09 | Altera Corporation | Signal loss detector for high-speed serial interface of a programmable logic device |
| CN202364199U (en) * | 2011-12-13 | 2012-08-01 | 东南大学 | Detection circuit for clock signal loss |
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| CN104380606B (en) * | 2012-06-14 | 2017-04-26 | 阿海珐有限公司 | Digital sensing circuit for a secondary clock signal to be monitored for clock failure with the aid of a primary clock signal |
| CN105337607B (en) * | 2014-06-30 | 2019-05-17 | 澜起科技股份有限公司 | Device and method for clock signal loss detection |
| CN105337607A (en) * | 2014-06-30 | 2016-02-17 | 澜起科技（上海）有限公司 | Clock signal loss detection device and method |
| CN105703745A (en) * | 2014-11-24 | 2016-06-22 | 中国科学院沈阳自动化研究所 | Clock state indicating circuit and method |
| CN105703745B (en) * | 2014-11-24 | 2019-01-04 | 中国科学院沈阳自动化研究所 | A kind of clock status indicating circuit and method |
| WO2018058915A1 (en) * | 2016-09-28 | 2018-04-05 | 深圳市中兴微电子技术有限公司 | Clock signal loss detection device |
| CN109412581A (en) * | 2017-08-18 | 2019-03-01 | 杭州晶华微电子有限公司 | A kind of clock failure of oscillation detection circuit |
| CN108563283A (en) * | 2017-12-25 | 2018-09-21 | 中国航空工业集团公司洛阳电光设备研究所 | A kind of device of real time clock monitoring and system wake-up |
| CN108563283B (en) * | 2017-12-25 | 2021-05-18 | 中国航空工业集团公司洛阳电光设备研究所 | Real-time clock monitoring and system awakening device |
| CN109613336A (en) * | 2018-12-07 | 2019-04-12 | 中国电子科技集团公司第四十研究所 | A kind of random length FFT multimode signal frequency-domain analysis device and method |
| CN109613336B (en) * | 2018-12-07 | 2020-12-01 | 中国电子科技集团公司第四十一研究所 | Frequency domain analysis device and method for FFT (fast Fourier transform) multimode signals with any length |
| CN110350914A (en) * | 2019-06-18 | 2019-10-18 | 芯翼信息科技(上海)有限公司 | A kind of system on chip |
| CN110350914B (en) * | 2019-06-18 | 2023-07-07 | 芯翼信息科技(上海)有限公司 | System on chip |
| CN110445492A (en) * | 2019-09-09 | 2019-11-12 | Oppo广东移动通信有限公司 | Cross clock domain frequency-dividing clock protects circuit, frequency dividing circuit, method and terminal device |
| CN110445492B (en) * | 2019-09-09 | 2023-04-07 | Oppo广东移动通信有限公司 | Cross-clock-domain frequency division clock protection circuit, frequency division circuit, method and terminal equipment |
| CN112345820A (en) * | 2020-01-07 | 2021-02-09 | 成都华微电子科技有限公司 | High-speed serial signal loss detection circuit |
| CN112345820B (en) * | 2020-01-07 | 2023-08-18 | 成都华微电子科技股份有限公司 | High-speed serial signal loss detection circuit |
| CN116015255A (en) * | 2022-12-30 | 2023-04-25 | 成都电科星拓科技有限公司 | Clock seamless switching circuit supporting automatic switching loss |
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