JP2009219021A - Data recovery circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data recovery circuit with more reduced current consumption than a prior art one. <P>SOLUTION: Disclosed is the data recovery circuit for restoring serial data subjected to serial transfer by oversampling. The circuit includes: a multiphase clock generation part 2 for generating multiphase clocks; a multiphase clock control part 1000 for interrupting partial clocks among multiphase clocks; an oversampling part 1 for sampling serial data based on clocks not interrupted by the multiphase clock control part 1000; a symbol data restoration part 3 for restoring the serial data based on the sampling data sampled by the oversampling part 1. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a data recovery circuit for restoring serially transferred data.

  In recent years, USB (Universal Serial Bus), Serial ATA (Advanced Technology Attachment), IEEE1394, 1G / 10G Ethernet (registered trademark), InfiniBand to meet the demands of high-capacity and high-speed data transmission between devices, boards, and chips Various high-speed interface standards such as RapidIO, Fiber Channel, and PCI Express have been proposed and put into practical use. However, the trend toward higher speed and higher capacity is expected to increase in the future.

  Many of these interface standards employ a serial transfer method, and data is transmitted at a predetermined frequency. The transmitted data is superimposed with a clock of that frequency (embedded clock), and the data receiving unit detects this clock from the received data and restores the received data based on the detected clock signal.

  A circuit that performs these restoration operations is called a clock data recovery (hereinafter referred to simply as “CDR”) circuit. In a conventional CDR circuit, a PLL (Phase Locked Loop) circuit is generally used, and an oscillation signal (clock) of a VCO (Voltage Controlled Oscillator) included in the PLL is controlled to be synchronized with the phase of received data and used as a reproduction clock. It is done.

  The received data is accurately restored by latching the received data on the basis of the reproduction clock. However, when the data transfer speed is increased and, for example, an order exceeding Gbps, the oscillation frequency of the VCO also exceeds the GHz order. Therefore, in a CDR circuit incorporating such a VCO, the chip size increases and the power consumption increases. Negative factors such as cost and cost increase will increase.

  In addition, since the wiring delay cannot be ignored due to the increase in the data transfer speed, it is necessary to pay sufficient attention to the element arrangement and the wiring layout, and the design becomes more difficult. In addition, since the wiring delay greatly depends on the device characteristics to be used, it becomes necessary to redesign the layout for each process (or until the circuit is redesigned), which reduces the circuit reusability and development. The period is increased.

  As a solution to such a problem, an oversampling CDR circuit has been proposed (see, for example, Non-Patent Document 1).

  FIG. 24 is a configuration diagram of a conventional CDR circuit. As shown in FIG. 24, in the CDR circuit, the multiphase clock generation unit 900 is configured by a PLL, a DLL (Delayed Locked Loop), etc., and has a phase difference of equal intervals shifted from the reference clock (RefCLK) by a predetermined phase. Generate a multiphase clock.

  A flip-flop (hereinafter referred to as “F / F”) circuit 901 inputs input data (Data) in common to the data terminals, and receives each clock (CLK1 to CLKN) of the multiphase clock supplied from the multiphase clock generation unit 900. ) Are input to the clock terminals, and input data is captured at the rising edge (or falling edge) of each clock. That is, the data output from the F / F circuit 901 is obtained by sampling the input data with a clock whose phase is gradually shifted.

  A digital PLL (hereinafter referred to as “DPLL”) 902 detects an inversion timing at which logic is inverted from a bit string supplied from the F / F circuit 901, and a clock having a phase synchronized with the timing is included in the multiphase clock. And restored as a recovered clock (RecCLK).

  Further, the DPLL 902 selects and outputs data taken in with a clock having a predetermined phase difference (for example, opposite phase) from the reproduction clock (RecCLK) as reproduction data (RecData). When selecting the reproduction clock (RecCLK), the DPLL 902 detects the data inversion timing by smoothing it with a filter.

  A subsequent signal processing unit (not shown) operates based on the reproduction clock (RecCLK). Since such a circuit configuration can be configured by a digital circuit other than the multiphase clock generation unit 900, it is relatively easy to implement. However, if the phase difference between the clocks of the multiphase clock generated by the multiphase clock generation unit 900 is not equal, the CDR circuit may malfunction.

  FIG. 25 is a diagram illustrating an example of a problem when the phase differences of the multiphase clocks are not equal. In FIG. 25, the multiphase clock output from the multiphase clock generation unit 900 is described as having four phases.

  First, it is assumed that the phase of CLK2 is delayed by Δ from the ideal state, CLK2 is selected as the reproduction clock (RecCLK), and the signal processing unit processes each data in synchronization with CLK2.

  If CLK1 is selected as the reproduction clock (RecCLK) at time Tsw, the period (T ′) of the reproduction clock is further shortened by Δ in addition to the original phase difference, and therefore the time for setting up the F / F in the signal processing unit (Tsu ′) cannot be secured sufficiently, and the CDR circuit may malfunction.

  This is because, for example, even if the output phase of the multiphase clock generator 900 is designed so that the phase differences of the clocks of the multiphase clock are equally spaced, the clocks up to the output end of the recovered clock (RecCLK) The CDR circuit may malfunction due to the influence of skew (for example, due to wiring or a load). Furthermore, this skew becomes more prominent as the data transfer speed increases. Therefore, it becomes necessary to adjust the delay amount of the multiphase clock in each part, and it is not easy to realize, so that the above-mentioned problems have not been solved.

  In addition, there is a multiphase clock generator 900 that performs phase adjustment using a phase interpolator (see, for example, Patent Document 1).

  However, if a circuit such as a phase interpolator is provided, it will be possible to output multiphase clocks with equally spaced phase differences, but this will increase the number of devices and ignore wiring delays associated with higher speeds. Can not.

  As a method of avoiding this wiring delay, a method of matching the phases of the multiphase clocks at the respective inputs can be considered. However, this method realizes an oversampling CDR circuit that operates at an oversampling frequency higher than the frequency of the clock included in the transfer data (in the example of FIG. 25, four times the frequency of the clock included in the transfer data). Have the same difficulty.

  Therefore, in a device using a conventional CDR circuit using an analog PLL or an oversampling CDR circuit that recovers a clock from input data and performs signal processing based on the recovered clock, the transfer speed is increased. As a result, the difficulty of designing the CDR portion increases, so the development period increases and its realization becomes increasingly difficult.

  As a CDR circuit for solving these problems, data serially transferred in synchronization with a clock having a frequency f1 is oversampled by a multiphase clock generated by shifting the clock having a frequency f2 by a predetermined phase and sampled data. Even if the data transfer rate is high, the sampling unit for acquiring the data and the data recovery unit for detecting the f1 / f2 bits on the average from the acquired sampling data and recovering the received data are provided. In addition, since data recovery processing can be performed at a clock frequency that is a fraction of the data transfer rate, it can easily cope with system speedup, as well as jitter of transferred data and polyphase used during oversampling. Some were less susceptible to non-uniform clock phase spacing (examples) If, see Patent Document 2).

In addition, when a data edge is detected at a position that exceeds a certain reference value from the phase information reproduced by the DPLL, the eye opening of the data is obtained by bringing the data edge position closer to the phase information reproduced by the DPLL. Some of them are corrected so as to spread (see, for example, Patent Document 3).
B. Kim et. al. "A 30-MHz Hybrid Analog / Digtal Clock Recovery Circuit in 2-um CMOS", IEEE JSSC, December 1990, pp1385-1394 JP 2002-190724 A JP 2005-192192 A Japanese Patent Application No. 2007-243903

  However, in Patent Document 2 and Patent Document 3, data that is serially transferred in synchronization with a clock having a frequency f1 is oversampled by a multiphase clock generated by shifting the clock having a frequency f2 by a predetermined phase. Then, since the configuration is such that the data oversampled by the parallelizing unit is collectively output as data synchronized with one clock, there is a problem that power consumption increases.

  For example, when 8 times oversampling is performed by using a multiphase clock obtained by shifting the clock of frequency 1.25 GHz by 50 ps for data serially transferred in synchronization with a clock of frequency 2.5 GHz, 8 bits × 2 UI = 16 bits of data must be sampled simultaneously. Here, the UI is a Unit Interval, which is a period of 400 ps for serial data synchronized with a 2.5 MHz clock.

  As shown in FIG. 26, the conventional oversampling unit 201 uses the 16-phase multi-phase clocks ck0 to ck15 supplied from the multi-phase clock generation unit 202 to input serial data (Data) F / F0 to F / Sampling is performed by F15.

  After that, the data synchronized with each of the clocks ck0 to ck15 is finally output by the symbol data restoration unit 203 as data synchronized with one clock (here, ck0) by the parallelizing unit 205.

  In the parallelization unit 205, as shown in FIG. 27, among the data Q0 to Q15 synchronized with each of the multiphase clocks ck0 to ck15, the data Q0 to Q7 are represented as data QQ [0: 7] synchronized with ck0. The data Q8 to Q15 are respectively latched by the F / F as data QQ [8:15] synchronized with ck8.

  Thereafter, QQ [0: 7] and QQ [8:15] are respectively latched by the F / F as data OVS [0:15] synchronized with ck0. Accordingly, 16 × 2 = 32 F / Fs are arranged in the parallelization unit 205, and as many as 48 F / Fs are arranged in the oversampling unit 1 as a whole.

  As described above, the conventional data recovery circuit has a problem that the current consumption increases because it is necessary to operate many F / Fs at high speed.

  An object of the present invention is to provide a data recovery circuit capable of reducing current consumption as compared with a conventional data recovery circuit.

  A data recovery circuit according to the present invention is a data recovery circuit that restores serially transferred serial data by oversampling, and a multiphase clock generation unit that generates a multiphase clock, and a part of the multiphase clock A multi-phase clock control unit that stops the clock of the multi-phase clock, a sampling unit that samples the serial data based on a clock that is not stopped by the multi-phase clock control unit, and a sampling data sampled by the sampling unit And a data restoration unit for restoring the serial data.

  With this configuration, the data recovery circuit of the present invention stops the clock supplied to the latch circuit that latches each bit of the oversampling data that is not required for data recovery, and therefore consumes less current than the conventional data recovery circuit. Can be reduced.

  The multiphase clock control unit may determine a clock to be stopped based on phase information extracted from the serial data.

  With this configuration, the data recovery circuit of the present invention stops sampling of bits that are not necessary for data recovery according to the phase information of the input data, and therefore can select appropriate bits that are necessary for data recovery.

  The clock to be stopped may be determined based on the phase information extracted from the serial data and a predetermined set value.

  With this configuration, the data recovery circuit of the present invention stops the sampling of bits that are not required for data recovery according to the phase information and set value of the input data, and therefore can select appropriate bits required for data recovery. It is possible to make optimum settings in the system.

  The data recovery circuit of the present invention is a data recovery circuit that restores serially transferred serial data by oversampling, and includes a multiphase clock generation unit that generates a multiphase clock, and the multiphase clock A multi-phase clock selection unit for selecting a part of the clock; a sampling unit for sampling the serial data based on a part of the clock selected by the multi-phase clock selection unit; and a sampling sampled by the sampling unit And a data restoring unit that restores the serial data based on the data.

  With this configuration, the data recovery circuit of the present invention can reduce the number of latch circuits that latch each bit of oversampling data that is not required for data recovery, and therefore reduces current consumption compared to a conventional data recovery circuit. be able to.

  Note that the multi-phase clock selection unit may select a clock based on phase information extracted from the serial data.

  With this configuration, the data recovery circuit of the present invention performs oversampling by outputting a clock required for bits required for data recovery in accordance with the phase information of the input data, so that an appropriate bit required for data recovery is set. You can choose.

  The clock may be selected based on the phase information extracted from the serial data and a predetermined set value.

  With this configuration, since the data recovery circuit of the present invention stops sampling of bits that are not required for data recovery according to the phase information of the input data, it is possible to select an appropriate bit required for data recovery, and the system Can be used to make optimal settings.

  Further, the data recovery method of the present invention includes a multiphase clock generation step for generating a multiphase clock in a data recovery circuit that restores serially transferred serial data by oversampling, and a part of the multiphase clock. A multi-phase clock control step for stopping the clock, a sampling step for sampling the serial data based on the multi-phase clock obtained in the multi-phase clock control step, and a sampling data sampled in the sampling step. And a data restoring step for restoring the serial data.

  Therefore, the data recovery method according to the present invention stops the clock supplied to the latch circuit that latches each bit of the oversampled data that is not necessary for data recovery. Therefore, the data recovery circuit consumes less data than the conventional data recovery method. Current can be reduced.

  Further, the data recovery method of the present invention includes a multiphase clock generation step for generating a multiphase clock in a data recovery circuit that restores serially transferred serial data by oversampling, and a part of the multiphase clock. A multi-phase clock selection step for selecting the clock of the multi-phase clock, a sampling step for sampling the serial data based on a part of the clocks selected in the multi-phase clock selection step, and the sampling data sampled in the sampling step. And a data restoring step for restoring the serial data.

  Therefore, the data recovery method of the present invention can reduce the latch circuit that latches each bit of the oversampled data that is not required for data recovery from the data recovery circuit, and therefore the data recovery compared with the conventional data recovery method. The current consumption of the circuit can be reduced.

  The present invention can provide a data recovery circuit capable of reducing current consumption as compared with a conventional data recovery circuit.

  Hereinafter, embodiments of the data recovery circuit of the present invention will be described.

(First embodiment)
FIG. 1 is a schematic configuration diagram showing a physical layer unit of a serial transfer unit to which the first embodiment of the data recovery circuit of the present invention is applied. The physical layer unit 100 illustrated in FIG. 1 includes a transmission unit 101 that transmits data and a reception unit 102 that receives data.

  When data is transmitted / received using this serial transfer unit, the physical layer unit 120 having the same function as the physical layer unit 100 and having one set of transmission unit 122 and reception unit 121 is connected to the transmission paths 106 and 107. And arranged to face each other.

  The physical layer unit 100 includes a PLL 113 that generates a clock having a frequency fa from the reference clock RefCLK1, and the physical layer unit 120 includes a PLL 123 that generates a clock having a frequency fb from the reference clock RefCLK2. The physical layer units 100 and 120 operate based on clocks generated by the PLLs 113 and 123, respectively, having frequencies fa and fb, respectively. In the following description, each set of the transmission unit and the reception unit of the physical layer units 100 and 120 is referred to as a “port”.

  Serial transfer of data is performed point-to-point between ports. The transmission paths 106 and 107 in the present embodiment constitute a full-duplex line that can be performed simultaneously by separate transmission paths for transmission and reception, but are not necessarily a full-duplex line. The data recovery circuit of the present invention can be applied even in the case of a double line. The transmission paths 106 and 107 are each configured by two lines, but may be configured by radio.

  The transmission unit 101 includes an encoder unit 103 that performs encoding according to a predetermined conversion rule for transmission data Dtx supplied from an upper layer, a serializer 104 that serially converts data encoded by the encoder unit 103, And a transmission output unit 105 that transmits the serially converted data to the transmission path 106.

  Data on the transmission path 106 is transmitted as a differential signal. The encoder unit 103 performs 8B / 10B conversion on the transmission data Dtx. The 8B / 10B conversion is a conversion from 8-bit data to 10-bit data (hereinafter referred to as “symbol data”), and is a 1-bit special code for control (called a K code (or K character)). DtxK) is added to the 8-bit data.

  The PLL 113 divides the transfer clock BCLK defined in each standard and the transfer clock BCLK by 10 based on the supplied reference clock RefCLK1 (when the encoder unit 103 performs 8B / 10B conversion). A clock PCLK for internal operation is generated. For example, when data transfer is performed at 2.5 Gbps, the PLL 113 generates a transfer clock BCLK of 2.5 GHz and a clock PCLK of 250 MHz.

  The PLL 113 operates each unit by supplying a clock PCLK to the encoder unit 103 and supplying the clock PCLK and the transfer clock BCLK to the serializer 104. In addition, data transfer between the physical layer unit 100 and the upper layer is performed in synchronization with the clock PCLK.

  The reception unit 102 includes a reception input unit 108 that binarizes the differential signal transmitted through the transmission path 107, a DEQ 115 that performs digital processing on the data binarized by the reception input unit 108, and a reception input. A data recovery unit 109 that restores the data binarized by the unit 108, a deserializer 110 that converts the restored data into 10-bit symbol data in parallel, and an error that absorbs the frequency difference between the clocks on the transmission side and the reception side. A stick buffer 111 and a decoder 112 that performs 10B / 8B conversion of 10-bit symbol data into 8-bit data are provided.

  Also in the physical layer unit 120 facing the physical layer unit 100, the transmission unit 122 transmits data in synchronization with the transfer clock having the frequency fb generated by the PLL 123 based on the supplied reference clock RefCLK2.

  The elastic buffer 111 absorbs the frequency difference by adding or deleting a special code, for example. The allowable value of the frequency difference is determined for each interface standard. In this embodiment, the elastic buffer 111 is provided in the preceding stage of the decoder 112, but may be provided in the subsequent stage.

  In the present embodiment, the data recovery unit 109 and the deserializer 110 of the receiving unit 102 are described as constituting the data recovery circuit of the present invention, but the configuration of the data recovery circuit of the present invention is not limited. In addition, other configurations and functions of the physical layer unit 100 can be arbitrarily changed in combination with the first embodiment of the data recovery circuit.

  In addition, the physical layer unit 100 according to the present embodiment generates the multiphase clock supplied to the data recovery unit 109 or the clock PCLK supplied to the elastic buffer 111 or the like by the PLL 113, but the clock PCLK or transfer clock generated by the PLL 113 is also used. BCLK is also supplied to the transmission unit 101 such as the serializer 104 and the encoder unit 103, and the PLL 113 is shared. This is because the opposing physical layer units 100 and 120 are operated by clocks generated from independent reference clocks RefCLK1 and RefCLK2, respectively.

  FIG. 2 is a block diagram showing a first embodiment of the data recovery circuit of the present invention. As shown in FIG. 2, the data recovery circuit according to the first embodiment includes an oversampling unit 1, a multiphase clock generation unit 2, a multiphase clock control unit 1000, and a symbol data restoration unit 3. .

  Here, a part of the oversampling unit 1 and the symbol data restoration unit 3 constitutes the data recovery unit 109 shown in FIG. 1, and another part of the symbol data restoration unit 3 constitutes the deserializer 110 shown in FIG. is doing.

  Further, the multiphase clock generator 2 constitutes a part of the PLL 113 shown in FIG. The deserializer 110 is not necessarily provided in the data recovery circuit, and may be provided separately.

  In the present embodiment, the oversampling unit 1 constitutes a sampling unit in the present invention, and the symbol data restoration unit 3 constitutes a data restoration unit in the present invention.

  The multi-phase clock generation unit 2 shifts a clock having a predetermined frequency generated from the reference clock RefCLK by a predetermined phase, and generates a multi-phase clock having substantially equal phase differences. In the present embodiment, the multiphase clock generator 2 has multiphase clocks tck0 to tck15 having a frequency f2 that is about ½ of the transfer clock BCLK whose cycle UI is determined and a phase difference of, for example, 1/8 UI. Generate.

  For example, when the data transfer rate is 2.5 Gbps (UI is 400 ps), the multi-phase clock generator 2 generates 16 clocks with a cycle of 800 ps (frequency is 1.25 GHz) and a phase difference of 50 ps each. Generate.

  Note that the frequency f2 of the multiphase clock does not need to be ½ of the frequency of the transfer clock BCLK, may be ¼ of the frequency of the transfer clock BCLK, or may be the same as the frequency of the transfer clock BCLK. For example, the multiphase clock generation unit 2 may generate 32 clocks having a frequency f2 of 1/4 of the frequency of the transfer clock BCLK as a multiphase clock.

  Furthermore, the phase difference of the multiphase clocks generated by the multiphase clock generation unit 2 need not be limited to 1/8 UI of the cycle UI of the transfer clock BCLK. In addition, the data recovery circuit of the present embodiment is configured to include the multiphase clock generation unit 2, but the multiphase clock generation unit 2 may be configured separately from the data recovery circuit.

  The multiphase clock control unit 1000 includes clocks ck0 to ck15 respectively corresponding to the multiphase clocks tck0 to tck15 generated by the multiphase clock generation unit 2, pck0 having the same phase as the clock tck0, and pck8 having the same phase as the ck8. Is output.

  The multi-phase clock control unit 1000 outputs a selection signal Sel output from a selection signal generation unit 7 (to be described later) constituting the symbol data restoration unit 3 and a data selection unit 6 (to be described later) constituting the symbol data restoration unit 3. Of the clocks ck0 to ck15 excluding the clocks pck0 and pck8 based on the delayed selection signal dSel to be performed and the control signal Ctl representing the value set in the register (not shown) as the optimum value for the mounting state of the data recovery circuit Stop the clock.

  In the present embodiment, the control signal Ctl is represented by 2 bits and the selection signal Sel is represented by 3 bits. However, the number of bits representing the control signal Ctl and the selection signal Sel is limited. It is not a thing.

  Specifically, the multiphase clock control unit 1000 includes a clock selection unit 1001, selectors 1010 to 1025, and buffer circuits 1020 and 1021, as shown in FIG.

  The clock selection unit 1001 outputs switching signals s0 to s15 according to the control signal Ctl, the selection signal Sel, and the delay selection signal dSel to the selectors 1010 to 1025 based on the selection table shown in FIG.

  For example, in FIG. 4, when the control signal Ctl [1: 0] = 0, the clock selection unit 1001 does not stop any of the clocks tck0 to tck15 regardless of the values of the selection signal Sel and the delay selection signal dSel. The switching signals s0 to s15 are output.

  In addition, when the control signal Ctl [1: 0] = 1 and the selection signal Sel [2: 0] = 1, the clock selection unit 1001 performs the clocks tck0, tck2, and tck8 regardless of the value of the delay selection signal dSel. Then, the switching signals s0 to s15 are output so that the tck10 is stopped and the other clocks are not stopped.

  Further, the clock selection unit 1001 performs clocks tck6 and tck8 when the control signal Ctl [1: 0] = 1, the selection signal Sel [2: 0] = 7, and the delay selection signal dSel [2: 0] = 0. The switching signals s0 to s15 are output so as to stop tck14 and not stop other clocks.

  In FIG. 3, the selector 1010 receives a clock tck0 at one input terminal and “0” (Low) at the other input terminal. According to the switching signal s0 output from the clock selection unit 1001, One of the clock tck0 and “0” is output as the clock ck0.

  In the present embodiment, the selector 1010 selects “0” (Low) when the switching signal s0 is “0” (Low), and selects the clock tck0 when it is “1” (High).

  Similarly to the selector 1010, the clocks tck 1 to tck 15 are input to one of the selectors 1011 to 1025, and “0” (Low) is input to the other input terminal and output from the clock selection unit 1001. In response to the switching signals s1 to s15, one of the clocks tck1 to tck15 or “0” is output as each of the clocks ck1 to ck15.

  The buffer circuit 1020 has substantially the same delay amount as the selector 1010, delays the input clock tck0, and outputs a clock pck0 having substantially the same phase as the clock ck0 output when the clock tck0 is selected by the selector 1010. To do.

  The buffer circuit 1021 has substantially the same delay amount as the selector 1018, delays the input clock tck8, and outputs a clock pck8 having substantially the same phase as the clock ck8 output when the clock tck8 is selected by the selector 1018. To do.

  In FIG. 2, the oversampling unit 1 takes in the received data Data using the multiphase clocks ck0 to ck15 supplied from the multiphase clock control unit 1000 and outputs the oversampled data OVSD to the symbol data restoration unit 3.

  The symbol data restoring unit 3 restores 10-bit symbol data SYM from the oversampled data OVSD and generates a symbol clock SYMCLK, and has a data recovery function and a deserializer function. Note that the symbol data restoration unit 3 operates with one of the multiphase clocks (pck0 is illustrated in the figure).

  As described above, if a multiphase clock set to a frequency f2 lower than the frequency f1 of the transfer clock BCLK is used for the data recovery circuit, the oscillation frequency of the multiphase clock generation unit 2 can be lowered, thereby increasing the speed. Easy to handle.

  Next, the detail of each part is demonstrated.

  The oversampling unit 1 and an F / F circuit 4 including 16 F / Fs (F / F0 to F / F15) and a parallel output that outputs input data in synchronization with one clock (for example, pck0). And a bit complementing unit 800 that complements data bits.

  In F / F0 to F / F15, reception data Data is commonly input to the data terminals, and F / F0 to F / F15 fetch the reception data Data at the timing when the multiphase clocks ck0 to ck15 rise, Q0 to Q15 are output respectively.

  The parallelization unit 5 has, for example, a two-stage F / F, and after Q0 to Q15 are once latched into outputs Q0 to Q7 and outputs Q8 to Q15, they are combined and output Q0 to Q15. Is output, for example, oversampled data TOVSD synchronized with one clock of the multiphase clock (here, pck0).

  Here, since a part of the clocks ck0 to ck15 input to F / F0 to F / F15 is stopped, it is necessary to complement bits Q0 to Q15 output from the F / F where the clock is stopped. . Therefore, the bit complementation unit 800 performs bit complementation according to the selection signal Sel input from the selection signal generation unit 7.

  In FIG. 4, when the control signal Ctl [1: 0] = 3 and the selection signal Sel [2: 0] = 2, the bit sampled by the symbol data restoration unit 3 is 1 in “0010001000100010”. Standing bit. Here, it is assumed that the bit sequence is “b0, b1,..., B15” from the left. The bit complementing unit 800 complements the surrounding bits with the bit in which 1 is set.

  For example, when the control signal Ctl [1: 0] = 3 and the selection signal Sel [2: 0] = 2, the bit complementing unit 800 shows each bit of the oversampled data TOVSD [15: 0] as follows. OVSD [15: 0] complemented as described above is output.

OVSD [0] = TOVSD [2]
OVSD [1] = TOVSD [2]
OVSD [2] = TOVSD [2]
OVSD [3] = TOVSD [2]
OVSD [4] = TOVSD [2]
OVSD [5] = TOVSD [2]
OVSD [6] = TOVSD [6]
OVSD [7] = TOVSD [10]
OVSD [8] = TOVSD [10]
OVSD [9] = TOVSD [10]
OVSD [10] = TOVSD [10]
OVSD [11] = TOVSD [10]
OVSD [12] = TOVSD [10]
OVSD [13] = TOVSD [10]
OVSD [14] = TOVSD [14]
OVSD [15] = (next) TOVSD [2]

  Note that (next) TOVSD [2] means b2 of TOVSD input with a delay of one clock. Even when the control signal Ctl and the selection signal Sel are in other combinations, the bit complementing unit 800 sets each bit of the oversampled data TOVSD [15: 0] based on the selection table shown in FIG. The complemented OVSD [15: 0] is output.

  FIG. 5 is a diagram illustrating an example of a signal waveform of each main signal of the oversampling unit 1. In FIG. 5, (a) is a waveform example of the received data Data, (b) is a data transfer clock (which actually does not exist in the oversampling unit 1, but is described for convenience of explanation), (c−). 0) to (c-15) are multiphase clocks ck0 to ck15, and (d-0) to (d-15) are taken into F / F0 to F / F15 by the multiphase clock, and F / F0 to F Data Q0 to Q15, (e-0), and (e-1) respectively output from / F15 are data Q0 to Q5, data Q8 to Q15, and (f) that are once taken in by the parallelizing unit 5. The oversampled data OVSD output from the conversion unit 5 is shown.

  In FIG. 5, when the control signal Ctl input to the multiphase clock control unit 1000 is 0, that is, when all the clocks ck0 to ck15 are not stopped, the signals of the main signals of the oversampling unit 1 The waveform is shown.

  When the control signal Ctl input to the multiphase clock controller 1000 is other than 0, one of the clocks s0 to s15 is stopped according to the value of the selection signal Sel as shown in FIG. The

  The periods of the multiphase clocks ck0 to ck15 shown in (c-0) to (c-15) are set to twice (2UI) the period (UI) of the data transfer clock shown in (b). The phases of the clocks ck0 to ck15 are shifted so that the phase differences between adjacent clocks are equally spaced.

  The black circles attached to the reception data Data shown in (a) are the sampling points of the multiphase clocks ck0 to ck15, and the output data of the F / F0 to F / F15 captured by the multiphase clocks ck0 to ck15. Q0 to Q15 change from (d-0) to (d-15). In FIG. 5, the left side of the bit string is LSB, which represents a sample point that is fast in time.

  The parallelizing unit 5 once fetches Q0 to Q7 at the clock pck0, outputs QQ [0: 7] as shown in (e-0), fetches Q8 to Q15 at the clock pck8, and (e-1) QQ [8:15] is output as shown in FIG.

  Then, the parallelization unit 5 takes in QQ [0: 7] and QQ [8:15] at the next clock pck0 and synchronizes them in parallel, and, as shown in (f), oversampled data OVSD [0:15]. Is output.

  As described above, the parallelization unit 5 captures Q0 to Q7 with the clock pck0, captures Q8 to Q15 with the clock pck8, and then captures Q0 to Q15 with the next clock pck0. This is because the setup time of the parallelizing unit 5 for Q15 and Q14 is insufficient and the data cannot be normally captured.

  Here, in the present embodiment, the data acquisition in the parallelization unit 5 is set to two stages as described above, but the number of stages may be further increased so that the data can be acquired more stably.

  In general, the reception data Data rises or falls at a timing that is so-called jitter that fluctuates randomly or due to various factors as indicated by the hatched portion (a) in FIG.

  For this reason, sampling data near the timing at which data transitions may fluctuate and cannot be accurately restored. However, according to the present embodiment, such a problem can also be solved as shown by being surrounded by a broken line in FIG.

  Next, the configuration and operation of the symbol data restoring unit 3 that restores received data from oversampled data OVSD will be described.

  In FIG. 2, the symbol data restoration unit 3 includes a data selection unit 6, a selection signal generation unit 7, a deserializer 8, and a comma detection unit 9, and restores 10-bit symbol data SYM from the oversampled data OVSD. At the same time, a symbol clock SYMCLK whose phase is adjusted is generated.

  In the present embodiment, the oversampled data OVSD is 16-bit data in which 2 bits of transfer data are sampled with an 8-phase clock. Therefore, the symbol data restoration unit 3 may select and output data (bits) taken in with a clock having a predetermined phase from the 16-bit oversampling data OVSD.

  However, the transfer clock included in the data transmitted from the transmitting unit 122 of the opposing physical layer unit 120 and the multiphase clocks (clocks ck0 to ck15) used for sampling in the receiving unit 102 of the physical layer unit 100 have exactly the same frequency. If the frequency of the multi-phase clock is a natural fraction of the frequency of the transfer clock, the phase at which the symbol data restoration unit 3 captures the oversampling data OVSD may remain fixed.

  However, since the multi-phase clock and the transfer clock usually have a frequency difference within a certain range, the symbol data restoration unit 3 gradually shifts the capture phase. Therefore, it is sometimes necessary to selectively output one or three pieces of data.

  For example, if the frequency difference between the multi-phase clock and the transfer clock is 0.1% (1000 ppm), a shift of 1 bit occurs with respect to 1000 bits of transfer data, and 500 cycles of the clock pck0 used for oversampling. Once, one or three pieces of data are output.

  The selection signal generator 7 generates a selection signal Sel that indicates the bit capture phase of the oversampled data OVSD.

  The data selection unit 6 selectively selects 1 to 3 restored data (d0, d1, d2) from the oversampled data OVSD output from the oversampling unit 1 according to the selection signal Sel output from the selection signal generation unit 7. Output to. Further, the data selection unit 6 also outputs status signals S0 and S1 indicating the valid portion of the restored data.

  The comma detection unit 9 detects a comma code called a comma as a special code inserted into the transfer data at a predetermined interval, and outputs a comma detection signal Det.

  Based on the comma detection signal Det, the deserializer 8 performs parallel conversion of 1 to 3 restoration data (d0, d1, d2) supplied from the data selection unit 6 into 10-bit symbol data SYM. The deserializer 8 also generates a symbol clock SYMCLK.

  FIG. 6 is a diagram illustrating a configuration example of the selection signal generation unit 7. In FIG. 6, the selection signal generation unit 7 includes both edge detection units 20 and a DPLL 566, and is configured to operate based on the clock pck0 supplied from the multiphase clock control unit 1000.

  Both edge detectors 20 detect both rising and falling edges from the bit string of oversampled data OVSD, and output edge data RxEdge indicating the edge positions.

  Specifically, the both-edge detection unit 20 calculates an exclusive OR of the oversampled data OVSD [0:15] and the data dOVSD [0:15] obtained by delaying the oversampled data OVSD by one phase difference. .

  Note that dOVSD [0:15] is obtained by dOVSD [0:15] = {pOVSD [15], OVSD [0:14]} if OVSD [15] one clock before is expressed as pOVSD [15]. Can do.

  The DPLL 566 includes a comparison unit 21, a loop filter 562, and a digital VCO 563, and outputs 6-bit phase data (phase information in the present invention) St representing a phase synchronized with the phase of the input edge data RxEdge.

  The comparison unit 21 compares the phase of the edge of the edge data RxEdge with the phase data St output from the digital VCO 563, and outputs the phase difference data PDDat.

  The configuration of the comparison unit 21 is shown in FIG. 7, the comparison unit 21 includes first phase difference detection units 530a and 530c, second phase difference detection units 530b and 530d, clip circuits 531a to 531d, and an addition circuit 532.

  The first phase difference detection unit 530a is the 0th to 3rd bits of the oversampling data OVSD, and the second phase difference detection unit 530b is the 4th to 7th bits of the oversampling data OVSD, the first phase difference detection unit 530c is provided for the 8th to 11th bits of the oversampling data OVSD, and the second phase difference detector 530d is provided for the 12th to 15th bits of the oversampling data OVSD.

  Since the pulse width of the signal received by the comparison unit 21 may be narrowed due to various jitters, there may be a plurality of data edges within a time corresponding to 1 UI. Even in such a case, the comparison unit 21 is configured as described above so that each of the phase difference detection units 530a to 530d does not detect two or more data edges.

  In the present embodiment, it is assumed that the shortest pulse width of the received signal at the time of oversampling is 1/2 UI or more, and edge detection is performed for each 1/2 UI. When there is a possibility that the pulse width of the received signal of the system actually used may be further narrowed, it can be dealt with by further dividing the phase detection unit.

  Each of the phase difference detection units 530a to 530d sets 0 when no edge exists in the 4-bit portion of the input edge data RxEdge, and when there is an edge, the first phase difference detection units 530a and 530c perform FIG. The second phase difference detectors 530b and 530d output signals representing the phase difference from the phase data St output from the digital VCO 563 as shown in FIG.

  Each of the clipping circuits 531a to 531d clips the input data with the prescribed value for phase correction. For example, when clipping at ± 8, each of the clipping circuits 531a to 531d outputs the input data as it is when the value of the input data is -8 or more and 8 or less, outputs 8 when it exceeds 8, and less than -8 Sometimes -8 is output. The same applies to each of the clipping circuits 531a to 531d when clipping input data with other values.

  The adder circuit 532 adds the outputs of the clip circuits 531a to 531d and outputs the result as phase difference data PDDat. Thus, the phase difference data PDDat obtained by adding the phase difference data of each 4-bit portion of the edge data RxEdge after clipping is output from the comparison unit 21.

  In FIG. 6, the phase difference data PDDat output from the comparison unit 21 is input to the loop filter 562. The loop filter 562 is a filter that determines the loop characteristics of the DPLL 566, and outputs the data VCOIN obtained by smoothing the phase difference data PDDat output from the comparison unit 21 to the digital VCO 563. By changing the characteristic of the loop filter 562, the characteristic of the DPLL 566 can be changed.

  FIG. 10 shows an example of the loop filter 562. In FIG. 10, the loop filter 562 includes multipliers 570 and 571, adders 572 and 575, a limit circuit 573, and an F / F 574.

  Multipliers 570 and 571 are multipliers having fixed magnifications a and b, respectively, and multiply the input phase difference data PDDat by a fixed number. By adopting a configuration in which the magnifications a and b of the multipliers 570 and 571 can be set by a register (not shown), the characteristics of the DPLL 566 can be changed.

  Further, the adder 572, the limit circuit 573, and the F / F 574 constitute an integrator. The limit circuit 573 is a circuit that limits the output to the maximum value or the minimum value when an overflow or underflow occurs in the adder 572.

  In FIG. 6, a digital VCO 563 corresponds to an analog PLL VCO and outputs phase data St. In this embodiment, the digital VCO 563 outputs data with 6 bits (64 values). In this case, 1 LSB of the phase data St output from the digital VCO 563 corresponds to a phase of 1/64 cycle (1/64 UI).

  FIG. 11 shows a configuration example of the digital VCO 563. In FIG. 11, the digital VCO 563 includes an adder 580 and an F / F 581. The adder 580 constitutes an integrator by adding the input data VCOIN and the feedback data from the F / F 581. The digital VCO 563 outputs the upper 6 bits among the bits held by the F / F 581 as the phase data St of the digital VCO 563.

  With this configuration, the digital VCO 563 integrates the data obtained by smoothing the phase difference data PDDat output from the comparison unit 21 by the loop filter 562. Therefore, the phase data St output from the digital VCO 563 represents a phase. .

  Here, as the number of bits of the phase data St is increased, the phase represented by one bit of the phase data St is reduced, and the accuracy of the phase that can be expressed by the digital VCO 563 with the phase data St is increased.

  The phase data St output from the digital VCO 563 is returned to the comparison unit 21, and feedback control is performed by the comparison unit 21, the loop filter 562, and the digital VCO 563.

  For this reason, the phase data St follows the phase of the edge data RxEdge. In this embodiment, the selection signal Sel output from the DPLL 566 is composed of the upper 3 bits of the phase data St.

  In FIG. 2, the data selection unit 6 restores the restored data d0, d1, d2 by using the oversampling data OVSD output from the oversampling unit 1 and the selection signal Sel, and a status signal indicating an effective portion of the restored data S0 and S1 are output.

  FIG. 12 shows the configuration of the data selection unit 6. As illustrated in FIG. 12, the data selection unit 6 includes an F / F 700, a data generation unit 701, and a data state signal generation unit 702. The F / F 700 generates a delay selection signal dSel obtained by delaying the input selection signal Sel by one clock.

  The data generation unit 701 generates restored data d0, d1, and d2 from the input oversampling data OVSD, the selection signal Sel, and the delay selection signal dSel. FIG. 13 shows the relationship between the input signal and output signal of the data generation unit 701.

  The data status signal generation unit 702 generates status signals S0 and S1 indicating valid portions of data output from the data generation unit 701. FIG. 14 shows the relationship between the input signal and output signal of the data state signal generation unit 702.

  FIG. 15 is a diagram illustrating a configuration example of the deserializer 8. As shown in FIG. 15, the deserializer 8 includes a shift register 36 to which restored data d0, d1, and d2 are input, a symbol conversion unit 37, and a symbol synchronization control unit 38. The shift register 36 sequentially holds the restored data d0, d1, and d2 according to the status signals S0 and S1, and outputs the held restored data as parallel data PData.

  FIG. 16 is a diagram illustrating a detailed configuration example of the shift register 36 included in the deserializer 8. The shift register 36 shown in FIG. 16 includes F / Fs 40 (0) to (11) and multiplexers 41 (1) to (11). In addition, in FIG. 16, the illustration of those subsequent to F / F 40 (5) is omitted.

  F / Fs 40 (0) to (11) are connected in cascade to form a shift register. The multiplexers 41 (1) to (11) select restored data d0, d1, and d2 to be input to the F / Fs 40 (0) to (11), respectively, according to the status signals S0 and S1.

  Each of the multiplexers 41 (1) to (11) corresponds to a 3-bit shift, 2-bit shift, and 1-bit shift from the top among the three inputs of the restored data d1, d0, and d2, and {S1, S0} = {0,1}, the bottom input to perform 1-bit shift, and {S1, S0} = {1,1}, the top input to perform 3-bit shift, etc. In this case, since the 2-bit shift is performed, the middle input is selected and output.

  Further, the F / Fs 40 (0) to (11) output the outputs Q0 to Q11 as parallel data PData [0:11]. As a result, the data restored by 1 to 3 is converted in parallel.

  In FIG. 2, the comma detection unit 9 detects whether or not a predetermined comma code pattern is included in the parallel data PData output from the deserializer 8, and a detection signal Det representing the detection result is detected. The detected position signal DetPos (for example, the number of LSB bits of the detected comma code pattern) is output to the deserializer 8.

  Note that the comma code in the 8B / 10B conversion is “00111111010” or “1100000101” when the left side is FRB (First Received Bit). Here, “0011111001” or “1100010001” may be detected as another code having an attribute indicating a symbol delimiter.

  For example, when PData [11: 0] is “100111110101”, since PData [10: 1] matches the comma code, “H” is detected as the detection signal Det, and 1 is detected from the comma detection unit 9 as the detection position signal DetPos. Is output.

  FIG. 17 is a signal waveform diagram illustrating the symbol synchronization control unit 38 and the symbol conversion unit 37 shown in FIG. In FIG. 17, PData [11] is a bit (FRB) received first, and PData [0] is a bit (LRB) received last.

  (A) is the clock ck0, (b) is PData [11: 0], (c) is the detection signal Det, (d) is the detection position signal DetPos, (e-0), (e- 1) shows status signals S0 ′ and S1 ′ (where S0 ′ and S1 ′ are signals obtained by delaying S0 and S1 by one clock, respectively), and (g) shows one clock of parallel data PData. The delayed dPData, (h) is the symbol clock SYMCLK (the same signal as the latch enable signal LE), (i) is the symbol position signal LEPos indicating the symbol effective position of the parallel data PData, (j) is 10 bits Symbol data SYM signal is represented.

  When the comma code pattern COM is detected in the parallel data PData shown in (b) (the underlined portion of the enlarged view), the detection signal Det shown in (c) from the comma detection unit 9 and the detection shown in (d) A position signal DetPos is output.

  The symbol synchronization control unit 38 has a built-in counter, and uses the detection signal Det as a start signal and the detection position signal DetPos as a count initial value, and starts counting. This counter is counted by the number of 1 to 3 restored data input to the deserializer 8.

  That is, the symbol synchronization control unit 38 performs counting based on the status signals S0 ′ and S1 ′, and outputs a latch enable signal LE shown in (h) (LE) every time the count value accumulates 10 bits (one symbol). To “H”) and set the count value to −10.

  At the same time, the symbol synchronization control unit 38 outputs a count value as the symbol position signal LEPos shown in (i) indicating the effective position of the parallel data PData. The status signal is counted by using S0 ′ and S1 ′ shown in (e-1) and (e-2), respectively, which are delayed by the processing time in each block (one clock in this example).

  The symbol synchronization control unit 38 advances the count by 1 when {S1 ′, S0 ′} is {0, 1}, and advances the count by 3 when {S1 ′, S0 ′} is {1, 1}. In other cases, the count is advanced by two.

  The symbol conversion unit 37 delays the parallel data PData by one clock from the dPData shown in (g), and the 10-bit symbol shown in (j) according to the symbol position signal LEPos when the latch enable signal LE is “H”. Data SYM [0: 9] is taken out.

  Therefore, if the symbol position signal LEPos is 0, 1, or 2, dPData [9: 0] [10: 1] [11: 2] is extracted. If the symbol position signal LEPos is 3 or more, the data is extracted at the previous clock, so there is no data to be extracted here.

  The symbol synchronization control unit 38 outputs the same signal as the latch enable signal LE as the symbol clock SYMCLK. In this way, 10-bit symbol data SYM can be restored in synchronization with the symbol clock SYMCLK.

  The cycle of the symbol clock SYMCLK is normally 5 clocks (clock 0) (10 clocks for transfer), but it is 4 clocks or 6 clocks depending on the frequency difference between the transmitting side and the receiving side. May be. This difference is absorbed by the elastic buffer 111 described with reference to FIG.

  FIG. 18 is a diagram illustrating a configuration example of the PLL 113. The PLL 113 shown in FIG. 18 includes frequency dividers 50 and 58, a phase frequency comparator 51, a low-pass filter 52, a voltage control oscillator 53, and a frequency divider circuit 55, and a transfer clock from the reference clock RefCLK. BCLK, internal operation clock PCLK, and multiphase clocks ck0 to ck15 are generated.

  The voltage controlled oscillator 53 is configured by a ring oscillator to which four stages of differential buffers 54a to 54d are connected, generates 8-phase clocks c0 to c7, and outputs one of them as a transfer clock BCLK.

  The frequency divider 50 divides the transfer clock BCLK by 10 and feeds it back to the phase frequency comparator 51. The phase frequency comparator 51 performs phase comparison between the reference clock RefCLK and the output of the frequency divider 50, and drives an inherent charge pump based on this phase difference information.

  The low pass filter 52 smoothes the charge pump output and supplies the control voltage Vc to the voltage controlled oscillator 53. The differential buffers 54a to 54d in the voltage controlled oscillator 53 perform the phase synchronization control by changing the delay amount according to the control voltage Vc. For example, when a clock of 250 MHz is supplied as the reference clock RefCLK, the voltage controlled oscillator 53 generates a transfer clock BCLK of 2.5 GHz.

  The frequency divider 58 divides the transfer clock BCLK by 10 to generate the clock PCLK. The frequency dividing circuit 55 includes eight frequency dividers 56a to 56h (configured by toggle F / F or the like) 56a to 56h to which clocks c0 to c7 are input, and forward and inverted signals are output from the frequency dividing circuit 55. The

  Further, these two frequency dividers 56a to 56f are reset by the output RSTB of the reset circuit 57, and adjust the phase of each clock so as to be (c-0) ck0 to (c-15) ck15 shown in FIG. .

  That is, by dividing the 8-phase clocks c0 to c7 by 2, the 16-phase clocks ck0 to ck15 are generated by the 2-frequency dividers 56a to 56h at a frequency half that of the transfer clock BCLK.

  FIG. 19 is a diagram illustrating a relationship between a plurality of physical layer units and a PLL. The PLL 150 in FIG. 19 also serves as the multiphase clock generation unit 2 and includes a plurality of physical layer units (here, the first and second lane physical layer units 151 and 152 are shown, and the others are not shown). The transfer clock BCLK, the clock PCLK, and the multiphase clocks ck0 to ck15 are configured to be supplied in common.

  The first lane physical layer unit 151 includes a transmission unit 101-1 and a reception unit 102-1 (having the data recovery circuit of the present embodiment), and the second lane physical layer unit 152 also includes the first lane physical layer. Similarly to the unit 151, the transmission unit 101-2 and the receiving unit 102-2 (having the data recovery circuit of this embodiment) are provided.

  The reference clock RefCLK is supplied to the PLL 150, the PLL 150 supplies the transfer clock BCLK and the clock PCLK to each of the transmission units 101-1 and 101-2, and the multiphase clock ck0 to each of the reception units 102-1 and 102-2. Supply ~ ck15. Thus, the PLL 150 can be shared by a plurality of physical layer units.

  As described above, the data recovery circuit according to the present embodiment stops the clock supplied to the F / F corresponding to the bit of the oversampling data OVSD that is not necessary for data recovery, and therefore is compared with the conventional data recovery circuit. Thus, current consumption can be reduced.

  In addition, when the data recovery circuit of the present embodiment is made into an LSI, it is not necessary to use an expensive package as a countermeasure against heat generation, or to use a large number of power supply pads to supply a large amount of current to the circuit.

  Furthermore, since the LSI chip size is determined by the relationship between the pad spacing and the number of pads that must be secured, when the data recovery circuit of this embodiment is implemented as an LSI, the chip size can be suppressed, and the cost can be reduced. be able to.

  In addition, the data recovery circuit according to the present embodiment easily changes from oversampling with 16 phases at a frequency of 1/2 of the transfer clock BCLK to oversampling with 32 phases at a frequency of 1/4 of the transfer clock BCLK, for example. By further lowering the operating frequency, the transfer data rate can be further increased.

  In addition, since the data recovery circuit of this embodiment can restore data using a clock that is not synchronized with the received data, the generation of the multiphase clock can be shared with the generation of the transfer clock BCLK, and the chip size Can be suppressed.

(Second Embodiment)
A second embodiment of the data recovery circuit of the present invention is shown in FIG. In the present embodiment, the same components as those in the first embodiment of the data recovery circuit of the present invention are denoted by the same reference numerals, and description thereof is omitted.

  In FIG. 20, the data recovery circuit of this embodiment includes an oversampling unit 2001, a multiphase clock generation unit 2, a multiphase clock selection unit 2000, and a symbol data restoration unit 3.

  The multiphase clock selection unit 2000 selects and outputs a clock used for data sampling from among the multiphase clocks tck0 to tck15 generated by the multiphase clock generation unit 2. Note that the multiphase clock selection unit 2000 outputs the clocks pck0 and pck8, similarly to the multiphase clock control unit 1000 described in the first embodiment of the data recovery circuit of the present invention.

  Specifically, the multiphase clock selection unit 2000 always selects tck0 as the clock cka. Further, the multiphase clock selection unit 2000 generates clocks tck0 to tck15 corresponding to clocks c0 to c15 in which 1 is set when the control signal Ctl [1: 0] = 3 in the selection table shown in FIG. The clocks ckb to cke are selected respectively.

  That is, when the selection signal Sel = 0, the multiphase clock selection unit 2000 selects tck0 as ckb, selects tck4 as ckc, selects tck8 as ckd, and selects tck12 as cke.

  When the selection signal Sel = 1, the multiphase clock selection unit 2000 selects tck1 as ckb, selects tck5 as ckc, selects tck9 as ckd, and selects tck13 as cke.

  When the selection signal Sel = 2, the multiphase clock selection unit 2000 selects tck2 as ckb, selects tck6 as ckc, selects tck10 as ckd, and selects tck14 as cke.

  When the selection signal Sel = 3, the multiphase clock selection unit 2000 selects tck3 as ckb, selects tck7 as ckc, selects tck11 as ckd, and selects tck15 as cke.

  In addition, when the selection signal Sel = 4, the multiphase clock selection unit 2000 selects tck0 as ckb, selects tck4 as ckc, selects tck8 as ckd, and selects tck12 as cke.

  In addition, when the selection signal Sel = 5, the multiphase clock selection unit 2000 selects tck1 as ckb, selects tck5 as ckc, selects tck9 as ckd, and selects tck13 as cke.

  Further, when the selection signal Sel = 6, the multi-phase clock selection unit 2000 selects tck2 as ckb, selects tck6 as ckc, selects tck10 as ckd, and selects tck14 as cke.

  Further, when the selection signal Sel = 7, the multiphase clock selection unit 2000 selects tck3 as ckb, selects tck7 as ckc, selects tck11 as ckd, and selects tck15 as cke.

  In this embodiment, the multi-phase clock selection unit 2000 selects the clock to be output as described above so as to simplify the configuration. However, the selection signal Sel = 7 and the delay selection signal dSel = 0 are selected. Only in some cases five clocks are required. Therefore, the multiphase clock selection unit 2000 may stop the clock cka when the selection signal Sel = 7 and the delay selection signal dSel = 0 are not satisfied.

  Further, when the selection signal Sel = 0 and the delay selection signal dSel = 7, the multi-phase clock selection unit 2000 may stop the clocks cka and ckb because only three clocks are required.

  The oversampling unit 2001 has an F / F circuit 2002 including five F / Fs (F / Fa to F / Fe) and a parallel output unit that outputs input data in synchronization with one clock (for example, pck0). A conversion unit 2003, a bit mapping unit 2004 that performs bit mapping of data, and a bit complementing unit 800.

  Each of the F / Fa to F / Fe included in the F / F circuit 2002 samples serial transmission data (Data) at the timing of an input clock.

  The parallelizing unit 2003 outputs 5-bit data POVSD obtained by synchronizing the input bit data (Qa to Qe) with one clock (in this example, pck0).

  As shown in FIG. 21, the parallelizing unit 2003 includes F / Fs 2010a to 2010e and 2011a to 2011e, and among these F / Fs, pck0 is input to the F / Fs 2010a to 2010c and 2011a to 2011e. Fck F8 is input to F / F 2010d to 2010e.

  Further, bit data Qa to Qe are input to the F / Fs 2010a to 2010e, respectively. Output data of the F / Fs 2010a to 2010e are input to the F / Fs 2011a to 2010e, respectively.

  As described above, the output data Qa to Qe of the F / Fs 2011a to 2011e constitute 5-bit data POVSD.

  The bit mapping unit 2004 performs mapping for outputting the 5-bit data POVSD output by the parallelizing unit 2003 as 16-bit data TOVSD as in the first embodiment of the present invention.

  When the selection signal Sel = 2, the input / output data relationship of the bit mapping unit 2004 is as shown in FIG. For example, the bit mapping unit 2004 converts each bit “00110” of POVSD (POVSD [0], POVSD [1], POVSD [2], POVSD [3], POVSD [4] from the left side) into 16-bit data TOVSD. Map to the actual sampling location.

  That is, in FIG. 22, the bit mapping unit 2004 sets POVSD [0] to TOVSD [0], POVSD [1] to TOVSD [2], POVSD [2] to TOVSD [6], and POVSD [3]. Is mapped to TOVSD [10] and POVSD [4] is mapped to TOVSD [14].

  The bit mapping unit 2004 maps “0” to these bits, although there is no problem with any value other than the above TOVSD bits. The TOVSD is input to the bit complementing unit 800 and output as data OVSD in which the bits are complemented.

  In this embodiment, since the oversampling unit 2001 can obtain the same oversampling data OVSD as the oversampling unit 1 of the first embodiment, the symbol data restoration unit 3 is the same as that of the first embodiment. A configuration can be used.

  FIG. 23 is a diagram illustrating an example of a signal waveform of each main signal of the oversampling unit 2001. In FIG. 23, (a) is a waveform example of the received data Data, (b) is a data transfer clock (which actually does not exist in the oversampling unit 2001, but is described for convenience of explanation), (c−). a) to (ce) are multiphase clocks cka to cke, (da) to (de) are taken into F / Fa to F / Fe by the multiphase clock, and F / Fa to F Data Qa to Qe, (e-0), and (e-1) respectively output from / Fe are data PQQ [0: 2] (F / F2010a to F / F2010c) once taken into the parallelizing unit 2003. Data PQQ [3: 4] (corresponding to outputs of F / F2010d to F / F2010e) and (f-0) are oversampled data POVSD output from the parallelizing unit 2003, (g-0) ) Bitmappi It represents oversampled data TOVSD mapped by grayed portion 2004.

  FIG. 23 shows signal waveforms of main signals of the oversampling unit 2001 when the selection signal Sel input to the multiphase clock generation unit 2001 is 2.

  The cycles of the multiphase clocks ck0 to ck15 shown in (c-a) to (ce) are set to twice (2UI) the cycle (UI) of the data transfer clock shown in (b). The phases of ck0 to ck15 are shifted so that the phase differences between adjacent clocks are equally spaced.

  The black circles of the received data Data shown in (a) are the sampling points of the multiphase clocks ck0 to ck15, and the output data Qa to Qe of each F / Fa to F / Fe captured by the multiphase clocks ck0 to ck15. Changes from (d-a) to (d-e). In FIG. 23, the left side of the bit string is LSB, which represents a sample point that is fast in time.

  The parallelizing unit 2003 once fetches Qa to Qc at the clock pck0, outputs PQQ [0: 2] as shown in (e-0), fetches Qd to Qe at the clock pck8, (e-1) PQQ [3: 4] is output as shown in FIG.

  Then, the parallelizing unit 2003 captures PQQ [0: 2] and PQQ [3: 4] at the next clock pck0 and performs parallel synchronization, and as shown in (f-0), the oversampled data POVSD [0: 4] is output.

  As described above, the oversampling unit 2001 of this embodiment can reduce the number of F / Fs from 48 to 15 compared to the oversampling unit 1 of the first embodiment. Therefore, current consumption can be greatly reduced, and the circuit scale can be reduced.

  In this embodiment, the bit mapping unit 2004 is configured so that the data format of the data OVSD output by the bit mapping unit 2004 matches the first embodiment, but the bit mapping unit 2004 is changed from the configuration of the oversampling unit 2001. May be omitted, and the symbol data restoration unit 3 may map each bit.

  FIG. 20 shows a configuration corresponding to the case where the number of bits sampled by the oversampling unit 2001 is 3 to 5 bits (corresponding to the case of the control signal Ctl = 3 in FIG. 4), and an F / F circuit. 2002 requires 5 F / Fs.

  In the selection table shown in FIG. 4, when the control signal Ctl = 2, the number of bits to be sampled is 7 to 9 bits, so the F / F circuit 2002 needs 9 F / Fs. Therefore, 18 F / Fs are required for the parallelizing unit 2003.

  Therefore, in the present embodiment, the number of F / Fs is set to 5 in order to perform sampling per 2 UI, but in FIG. 4, nine F / Fs corresponding to the control signal Ctl = 2 are represented by the F / F circuit 2002. The multi-phase clock selection unit 2000 may output nine multi-phase clocks and stop each clock according to the control signal Ctl signal.

It is a block diagram which shows the physical layer part of the serial transfer part to which 1st Embodiment of the data recovery circuit of this invention is applied. 1 is a block diagram showing a first embodiment of a data recovery circuit of the present invention. It is a block diagram which shows the multiphase clock control part which comprises 1st Embodiment of the data recovery circuit of this invention. It is a conceptual diagram which shows the selection table which the multiphase clock control part which comprises 1st Embodiment of the data recovery circuit of this invention refers. It is a timing chart which shows an example of each main signal of the oversampling part which comprises 1st Embodiment of the data recovery circuit of this invention. It is a block diagram which shows the selection signal production | generation part which comprises 1st Embodiment of the data recovery circuit of this invention. It is a block diagram which shows the comparison part which comprises the selection signal production | generation part shown in FIG. It is a graph which shows the characteristic of the 1st phase difference detection part which comprises the comparison part shown in FIG. It is a graph which shows the characteristic of the 2nd phase difference detection part which comprises the comparison part shown in FIG. It is a block diagram which shows the loop filter which comprises the selection signal production | generation part shown in FIG. FIG. 7 is a block diagram showing a digital VCO constituting the selection signal generation unit shown in FIG. 6. It is a block diagram which shows the data selection part which comprises 1st Embodiment of the data recovery circuit of this invention. It is a figure which shows the relationship between the input signal and output signal of a data generation part which comprises the data selection part shown in FIG. It is a figure which shows the relationship between the input signal and output signal of the data state signal generation part which comprises the data selection part shown in FIG. It is a block diagram which shows the deserializer which comprises 1st Embodiment of the data recovery circuit of this invention. It is a block diagram which shows the shift register which comprises the deserializer shown in FIG. 16 is a timing chart for explaining operations of a symbol synchronization control unit and a symbol conversion unit that constitute the deserializer illustrated in FIG. 15. It is a block diagram which shows PLL which comprises the physical layer part shown in FIG. It is a block diagram at the time of providing one PLL with respect to a some physical layer part. It is a block diagram which shows 2nd Embodiment of the data recovery circuit of this invention. It is a block diagram which shows the parallelization part which comprises 2nd Embodiment of the data recovery circuit of this invention. It is a conceptual diagram for demonstrating the mapping by the bit mapping part which comprises 2nd Embodiment of the data recovery circuit of this invention. It is a timing chart which shows an example of each main signal of the oversampling part which comprises 2nd Embodiment of the data recovery circuit of this invention. It is a block diagram of a CDR circuit used conventionally. FIG. 25 is a timing chart illustrating an example of a problem in the case where the phase differences between the multiphase clocks are not equal in the CDR circuit illustrated in FIG. 24. It is a block diagram which shows the conventional data recovery circuit. It is a timing chart which shows an example of each main signal of the oversampling part which comprises the conventional data recovery circuit.

Explanation of symbols

1, 201, 2001 Oversampling unit (sampling unit)
2, 202, 900 Multiphase clock generation unit 3, 203 Symbol data recovery unit (data recovery unit)
4, 901, 2002 F / F circuit 5, 205, 2003 Parallelization unit 6 Data selection unit 7 Selection signal generation unit 8, 110 Deserializer 9 Comma detection unit 20 Both edge detection unit 21 Comparison unit 36 Shift register 37 Symbol conversion unit 38 Symbol synchronization controller 40, 574, 581, 700, 2010a to 2010e, 2011a to 2011e F / F
41 Multiplexer 50, 58 Frequency divider 51 Phase frequency comparator 52 Low pass filter 53 Voltage controlled oscillator 54a-54d Differential buffer 55 Frequency divider circuit 56a-56h Two frequency divider 57 Reset circuit 100, 120 Physical layer part 101, 122 Transmission Unit 102, 121 receiving unit 103 encoder unit 104 serializer 105 transmission output unit 106, 107 transmission path 108 reception input unit 109 data recovery unit 111 elastic buffer 112 decoder 113, 123, 150 PLL
115 DEQ
151 1st lane physical layer part 152 2nd lane physical layer part 530a, 530c 1st phase difference detection part 530b, 530d 2nd phase difference detection part 531a-531d Clip circuit 532 Adder circuit 562 Loop filter 563 Digital VCO
566, 902 DPLL
570 Multiplier 572, 580 Adder 573 Limit circuit 701 Data generation unit 702 Data state signal generation unit 800 Bit complement unit 1000 Multiphase clock control unit 1001 Clock selection unit 1010-1025 Selector 1020, 1021 Buffer circuit 2000 Multiphase clock selection unit 2004 Bit mapping part

Claims (8)

A data recovery circuit that restores serially transferred serial data by oversampling,
A multiphase clock generator for generating a multiphase clock;
A multiphase clock control unit for stopping a part of the multiphase clock;
A sampling unit that samples the serial data based on a clock that is not stopped by the multi-phase clock control unit;
A data recovery circuit comprising: a data restoration unit that restores the serial data based on sampling data sampled by the sampling unit.   The data recovery circuit according to claim 1, wherein the multiphase clock control unit determines a clock to be stopped based on phase information extracted from the serial data.   The data recovery circuit according to claim 1, wherein the multiphase clock control unit determines a clock to be stopped based on phase information extracted from the serial data and a predetermined set value. A data recovery circuit that restores serially transferred serial data by oversampling,
A multiphase clock generator for generating a multiphase clock;
A multiphase clock selector for selecting a part of the multiphase clock; and
A sampling unit that samples the serial data based on a part of clocks selected by the multiphase clock selection unit;
A data recovery circuit comprising: a data restoration unit that restores the serial data based on sampling data sampled by the sampling unit.   The data recovery circuit according to claim 4, wherein the multiphase clock selection unit selects a clock based on phase information extracted from the serial data.   5. The data recovery circuit according to claim 4, wherein the multiphase clock control unit selects a clock based on phase information extracted from the serial data and a predetermined set value. In the data recovery circuit to restore by oversampling the serially transferred serial data,
A multi-phase clock generation step for generating a multi-phase clock; and
A multiphase clock control step of stopping a part of the multiphase clock; and
A sampling step of sampling the serial data based on the multiphase clock obtained in the multiphase clock control step;
A data recovery method for executing a data recovery step of recovering the serial data based on the sampling data sampled in the sampling step. In the data recovery circuit to restore by oversampling the serially transferred serial data,
A multi-phase clock generation step for generating a multi-phase clock; and
A multiphase clock selection step of selecting a part of the multiphase clocks;
A sampling step of sampling the serial data based on a part of the clocks selected in the multiphase clock selection step;
A data recovery method for executing a data recovery step of recovering the serial data based on the sampling data sampled in the sampling step.

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