JP2010016545A - Multi-phase clock generation circuit, over-sampling circuit, and phase shift circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a multi-phase clock generation circuit which suppresses the increase of current consumption while generating multi-phase clocks with smaller phase differences, and to provide an over-sampling circuit. <P>SOLUTION: The multi-phase clock generation circuit includes: a delay amount control part 11 which includes a pair of input/output terminals, a phase comparator 13 for detecting a phase difference between outputs of two delay lines for generating delays corresponding to a biased voltage at delay control terminals, and an averaging filter 14 for averaging an output of the phase comparator 13 and has a reference voltage connected to one delay control terminal thereof and has an output of the averaging filter 14 connected to the other delay control terminal thereof and performs such control as to give a prescribed phase difference between outputs of respective delay lines; and a clock delay part 20 which includes a plurality of delay lines 21 having the same number of delay elements connected in series, wherein respective delay lines 21 are different by combination of the number of delay elements 22 to which the reference voltage is connected, and the number of delay elements to which the output voltage of the averaging filter 14 is connected. The multi-phase clock generation circuit generates a multi-phase clock with a prescribed phase difference. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a multi-phase clock generation circuit for generating a clock having a predetermined phase difference, a phase shift circuit, and an oversampling circuit including these.

In recent years, many high-speed interface standards have been proposed and put into practical use in order to satisfy large capacity and high-speed data transmission between devices, boards, and chips. Many of these interface standards employ a serial transmission method. In serial transmission, data is transmitted based on a predetermined frequency. A clock of that frequency is superimposed on the transmitted data, and the data receiving unit extracts this clock from the received data and restores the received data based on the extracted clock signal. A circuit that performs these restoration operations is called a clock data recovery (CDR) circuit.
In a conventional CDR circuit, a PLL (Phase Locked Loop) circuit is generally used, and an oscillation clock of a VCO (Voltage Controlled Oscillator) in the PLL circuit is controlled to be synchronized with a phase of received data, and is extracted as a reproduction clock. . The received data is accurately restored by latching the received data on the basis of the recovered clock.
However, as the data rate increases, the VCO transmission frequency also increases, and a CDR circuit incorporating such a VCO increases disadvantages such as an increase in chip size, an increase in current consumption, and an increase in cost. In addition, since the wiring delay cannot be ignored due to the higher speed, the element layout and the wiring delay largely depend on the characteristics of the device to be used. Therefore, it is necessary to redesign the layout for each process, and the circuit reusability is reduced. This leads to an increase in the development period.
As a solution to such a problem, an oversampling CDR circuit has been proposed (see Non-Patent Document 1).

FIG. 6 is a configuration diagram of a conventional oversampling CDR circuit.
As shown in FIG. 6, in the CDR circuit, the multiphase clock generation unit 100 is configured by a PLL, a DLL (Delay Locked Loop), etc., and has a multiphase phase difference that is shifted by a predetermined phase from the reference clock (REFCLK). Generate a clock.
The data sampling unit 101 inputs the input data (DATA) in common to the data terminals, inputs the multiphase clocks (CLK1 to CLKN) from the multiphase clock generation unit 100 to the clock terminals, and rises each clock (or Input data is captured at the falling edge. That is, the data output from the data sampling unit 101 is obtained by sampling input data with a clock having a predetermined phase shift.
The digital PLL (DPLL) 102 detects the inversion timing at which the logic is inverted from the bit string supplied from the data sampling unit 101, selects a clock having a phase synchronized with the timing from the multiphase clock, and reproduces the recovered clock (RECCLK). ) To restore. Further, data taken in with a clock having a predetermined phase difference (for example, opposite phase) from the reproduction clock (RECCLK) is selected and output as reproduction data (RECDATA). At this time, the reproduction clock is selected by smoothing the data inversion timing with a filter. With such a configuration, since the circuit other than the multiphase clock generation unit 100 can be configured with a digital circuit, the implementation is relatively easy. However, the multiphase clocks used in this circuit configuration have a problem of mutual phase difference, and may malfunction if the phase differences are not equally spaced.
As a solution to such a problem, a data recovery circuit has been proposed in which data is accurately restored with an independent clock having a frequency equal to or lower than that of the clock included in the data included in the input data (see Patent Document 1). ).

FIG. 7 is a diagram for explaining the data recovery circuit of Patent Document 1. In FIG.
In FIG. 7, the data recovery circuit proposed in Patent Document 1 includes a multiphase clock generation unit 203, an oversampling unit 206, and a symbol data restoration unit 207.
The multiphase clock generation unit 203 shifts a clock having a predetermined frequency generated from the reference clock REFCLK by a predetermined phase, and generates a multiphase clock having substantially equal phase phases.
The oversampling unit 206 takes in the reception data Data using the multiphase clocks CK0 to CK11 supplied from the multiphase clock generation unit 203 and outputs oversampling data OVSD. The oversampling unit 206 includes an oversampling flip-flop 204 and a parallelizing unit 205 that outputs input data in synchronization with one clock (for example, CK0).
The symbol data restoration unit 207 includes a data selection unit 208, a DES (deserializer) 209, a selection signal generation unit 210, and a comma detection unit 211, restores the symbol data SYM from the oversampling data OVSD, and generates a symbol clock SYMCLK.
That is, the selection signal generation unit 210 instructs the capture phase of the oversampling data OVSD, and the data selection unit 208 outputs the restoration data from the oversampling data OVSD in accordance with the support from the selection signal generation unit 210. The comma detection unit 211 detects a comma code inserted into the transfer data at a predetermined interval, and outputs a comma detection signal.
Further, the deserializer 209 converts the restored data supplied from the data selection unit 6 into the symbol data SYM in parallel based on the comma detection signal, and also generates the symbol clock SYMCLK.
JP 2005-192192 A B. Kim et. Al. "A 30-MHz Hybrid Analog / Digital Clock Recovery Circuit in 2-um CMOS" IEEE, JSSC, December 1990, pp.1385-1394

In such a data recovery circuit, it is necessary to increase the number of oversampling in order to further improve the data recovery accuracy. However, the generation of the multiphase clock necessary for increasing the number of oversampling has the following problems. The following describes problems related to the generation of multiphase clocks.
The multiphase clock is generally generated by a circuit called DLL (Delay Locked Loop).

FIG. 8 is a diagram illustrating an example of a DLL that generates an eight-phase delay.
As shown in FIG. 8, the DLL includes a delay generation unit 300 including a delay element 303, a phase detector (PD) 301, and an averaging filter 302 such as a low pass filter (Low Pass Filter: LPF). The
First, a reference clock generated by a PLL (Phase Locked Loop) is input to the delay generation unit 300.
The phase comparator 301 detects the phase difference between the reference clock and the output of the delay generation unit 300 and locks it with a predetermined phase difference. For example, if a 2.5 GHz reference clock having a period of 400 ps (picoseconds) is input, an 8-phase clock having a phase difference of 50 ps that is 1/8 of 400 ps is generated.
In the DLL circuit described above, when the number of phases of the multiphase clock is increased in order to increase the number of oversampling, it can be dealt with by increasing the number of delay elements 303 constituting the delay line (delay generation unit) 300. The minimum value is determined by the minimum time for the reference clock to pass through the delay element 303. This time is a parameter that greatly depends on the transistor manufacturing process, and there is a limit for each technology. As an example, a minimum line width of 90 nanometers process technology is 30 picoseconds or more.

FIG. 9 is a diagram illustrating an example of the delay element 303 included in the delay generation unit 300. FIG. 9A is a block diagram, and FIG. 9B is an example of a circuit diagram.
The delay time of the delay element 303 is determined by the CNT voltage. As the CNT voltage increases, the current flowing through the delay element increases, the time for charging / discharging the next stage load decreases, and the delay time decreases. Conversely, when the CNT voltage decreases, the current flowing through the delay element decreases, the time for charging / discharging the next stage load increases, and the delay time increases. Further, as described above, when the CNT voltage is increased, the through current flowing through the delay element is increased, so that current consumption is inevitably increased.
In view of the above problems, the present invention provides a multiphase clock generation circuit that suppresses an increase in current consumption while generating a multiphase clock with a smaller phase difference and an oversampling circuit using the multiphase clock generation circuit. For the purpose.

  In order to solve the above-described problem, the invention according to claim 1 includes a pair of input / output terminals and a delay amount control terminal, and provides a delay amount corresponding to a voltage biased to the delay amount control terminal. Two delay lines formed by connecting a plurality of delay elements to be generated in series, a phase comparator for detecting a phase difference between outputs of the two delay lines, and averaging for averaging the outputs of the phase comparators A reference voltage is connected to the delay amount control terminal of the delay element that constitutes one delay line of the two delay lines, and the delay amount of the delay element that constitutes the other delay line By connecting the output of the averaging filter to the control terminal, a delay amount control unit that controls the output of each delay line to have a predetermined phase difference, and a plurality and the same number of the delay elements are connected in series. Multiple configured A combination of the number of delay elements each having an extension line and the reference voltage in each delay line being connected to the delay amount control terminal and the number of delay elements having the output voltage of the averaging filter connected to the delay amount control terminal And a multi-phase clock generation circuit that generates a multi-phase clock having a predetermined phase difference by inputting a reference clock to each delay line of the clock delay unit. .

The invention according to claim 2, a plurality input and output terminals of the pair, and a delay amount control terminal, a delay element for generating a delay amount in accordance with a bias voltage to the delay control terminal A plurality of delay lines configured in series, a plurality of phase comparators for detecting a phase difference between one delay line and the other delay lines among the plurality of delay lines, and each phase comparator A plurality of averaging filters for averaging the outputs of the delay elements, wherein a reference voltage is connected to the delay amount control terminal of the delay element constituting one delay line of the plurality of delay lines, and each of the other delays A delay amount control unit for controlling the output of each delay line to have a predetermined phase difference by connecting the output of each averaging filter to the delay amount control terminal of the delay element constituting the line; Connect the same number of delay elements directly A plurality of delay lines connected to each other, and the number of the delay elements connected to the delay amount control terminal for the reference voltage in each delay line and the output voltage of the averaging filter are connected to the delay amount control terminal A clock delay unit having a different combination of the number of delay elements, and a multi-phase clock having a predetermined phase difference is generated by inputting a reference clock to each delay line of the clock delay unit. Features a phase clock generation circuit.

According to a third aspect of the present invention, there is provided an oversampling circuit that performs oversampling using a clock generated by the multiphase clock generation circuit according to the first or second aspect.
According to a fourth aspect of the present invention, there are provided a plurality of delay elements each including a pair of input / output terminals and a delay amount control terminal and generating a delay amount corresponding to a voltage biased to the delay amount control terminal. Two delay lines configured in series, a phase comparator for detecting a phase difference between outputs of the two delay lines, and an averaging filter for averaging the outputs of the phase comparators, A reference voltage is connected to the delay amount control terminal of the delay element constituting one of the two delay lines, and the averaging is performed on the delay amount control terminal of the delay element constituting the other delay line. A plurality of delays configured by connecting a delay amount control unit for controlling the output of each delay line to have a predetermined phase difference by connecting the output of the filter and a plurality of the same number of the delay elements connected in series Each with a line Phase shift with different combinations of the number of delay elements connected to the delay amount control terminal for the reference voltage in the extension line and the number of delay elements connected to the delay amount control terminal for the output voltage of the averaging filter And a phase shift circuit for generating a serial data pattern having a predetermined phase difference by inputting a serial data pattern to each delay line of the phase shift unit.

According to a fifth aspect of the present invention, a plurality of delay elements each including a pair of input / output terminals and a delay amount control terminal and generating a delay amount corresponding to a voltage biased at the delay amount control terminal are provided. A plurality of delay lines configured in series, a plurality of phase comparators for detecting a phase difference between one delay line and the other delay lines among the plurality of delay lines, and each phase comparator A plurality of averaging filters for averaging the outputs of the delay elements, wherein a reference voltage is connected to the delay amount control terminal of the delay element constituting one delay line of the plurality of delay lines, and each of the other delays A delay amount control unit for controlling the output of each delay line to have a predetermined phase difference by connecting the output of each averaging filter to the delay amount control terminal of the delay element constituting the line; Connect the same number of delay elements directly A plurality of delay lines connected to each other, the number of the delay elements connecting the reference voltage in each delay line to the delay amount control terminal, and the output voltage of the averaging filter to the delay amount control terminal A phase shift unit having different combinations of the number of connected delay elements, and a serial data pattern is input to each delay line of the phase shift unit to generate a serial data pattern having a predetermined phase difference Features a phase shift circuit.
According to a sixth aspect of the present invention, there is provided an oversampling circuit that performs oversampling using a polyphase serial data pattern generated by using the phase shift circuit according to the fourth or fifth aspect.

With such a configuration, in the multiphase clock generation circuit of the present invention, the predetermined phase difference of the multiphase clock does not depend on the phase difference of the delay elements of the multiphase clock generation circuit. Compared to the above, it is possible to easily realize a minute phase difference. In addition, the multiphase clock generation circuit of the present invention does not require high-speed operation of the delay element, so that current consumption can be suppressed compared to a conventional circuit that requires high-speed operation to generate a minute phase difference. Is possible.
Further, in the phase shift circuit of the present invention, since the predetermined phase difference of the phase shift circuit does not depend on the phase difference of the delay element of the phase shift circuit, a minute phase difference can be easily realized compared to the delay time of the delay element alone. Is possible. In addition, the phase shift circuit according to the present invention does not require a high-speed operation of the delay element, so that the current consumption can be suppressed as compared with a conventional circuit that requires a high-speed operation to generate a minute phase difference. It is.

The best mode for carrying out the present invention will be described below with reference to the drawings.
[First Embodiment]
FIG. 1 is a diagram showing an oversampling data recovery circuit including a multiphase clock generation circuit according to a first embodiment of the present invention.
As shown in FIG. 1, the data recovery circuit including the multiphase clock generation circuit according to the first embodiment of the present invention includes a multiphase clock generation unit (multiphase clock generation circuit) 10, an oversampling unit 30, and symbol data restoration. The unit 40 is configured.
The multiphase clock generation unit 10 includes a delay amount control unit 11 and a clock delay unit 20, and receives reference clocks REFCLKP and REFCLKM and a reference bias VREF and has a predetermined phase difference (25 picoseconds in the present embodiment). A 16-phase clock CK [0:15] is output.
Here, the reference clocks REFCLKP and REFCLKM are forward and inversion clocks (phase difference is 200 picoseconds) having a frequency of 2.5 GHz and a phase difference of 180 °.
In the present embodiment, the delay amount control unit 11 includes two delay lines 12, a phase comparator 13, and an averaging filter 14 each configured by connecting four delay elements 15 in series.

As will be described in detail later, the delay amount control unit 11 uses two delay lines 12 to generate a bias that generates a predetermined delay amount.
The oversampling unit 30 takes in the received data Data using the multiphase clocks CK0 to CK15 supplied from the multiphase clock generation unit 10 and outputs oversampling data OVSD [0:15].
More specifically, the oversampling unit 30 includes a sampling FF (flip-flop) unit 31 and a parallelizing unit 32. The sampling FF unit 31 samples the reception data Data at the rising (or falling) timing of the multiphase clocks CK <b> 0 to CK <b> 15 having equal phase differences generated by the multiphase clock generation unit 10. The output of the sampling FF unit 31 has a phase difference generated by the multiphase clock generation unit 10.
The paralleling unit 32 outputs data D0 to D15 input with a phase difference as parallel data synchronized with one clock.
In this embodiment, the paralleling unit 32 adjusts and outputs only the timing without changing the data rate and bus width of the input data D0 to D15. However, the bus width is increased immediately before or after the parallelizing unit 32. It is also possible to output to the symbol data restoration unit 40 after performing serial / parallel conversion to lower the data rate.
In addition, the symbol data restoration unit 40 generates symbol data SYM and a symbol clock SYMCLK from the oversampling data OVSD.

Next, a mechanism of delay generation in the delay amount control unit will be described in detail.
FIG. 2 is a diagram illustrating an example of a delay element constituting the delay line.
FIG. 2A is a block diagram, and FIG. 2B and FIG. 2C are examples of circuit diagrams.
Each delay element 15 generates a phase difference (delay) between the input terminal IN and the output terminal OUT in accordance with the voltage input to the delay amount control terminal CNT.
Returning to FIG. 1, the reference voltage VREF is connected to the delay amount control terminal CNT of one delay line 12-1 of the two delay lines 12 constituting the delay amount control unit 11, and the other delay line 12-2 is connected. The delay amount control terminal CNT is connected to a voltage DLYB obtained by averaging the comparison results obtained by inputting the outputs of the two delay lines to the phase comparator 13 by the averaging filter 14.

FIG. 3 is a diagram illustrating an operation process until DLYB is locked in the delay amount control unit 11.
The operation until the delay amount of the delay amount control unit 11 is determined will be described with reference to FIG. In the operation start state (I), DLYB is charged to the power supply voltage. In a state where DLYB is charged to the power supply voltage, the delay element 15 to which the lock voltage DLYB is connected to the delay amount control terminal CNT is in a state where the delay amount is the smallest. If the reference voltage VREF is a power supply voltage, the phase difference between the outputs of the two delay lines 12 of the delay amount control unit 11 is 0 ° immediately after the operation is started. After the start of the operation (II), when the delay amount of the delay line (delay line 2 in the figure) to which DLYB is biased becomes large and the phase difference between the two delay lines 12 becomes 90 ° (100 picoseconds) (III ) Locks the voltage of DLYB.
Since the difference in time passing through the delay line 12 is 100 picoseconds, the difference in delay time between the delay element 15 to which the reference voltage VREF is biased and the delay element 15 to which the lock voltage DLYB is biased is 4 minutes of 100 picoseconds. 1 of 25 picoseconds.
In this embodiment, since a clock with a frequency of 2.5 GHz is input, an analog multiplier (not shown) capable of high-speed operation is used, and the averaging filter 14 uses a first-order low-pass filter, but does not require high-speed operation. The system is not limited to this, and a phase comparator using a general exclusive OR (XOR) gate can also be used.
In the embodiment of the present invention, the number of delay elements 15 constituting each delay line 12 is four. However, in order to obtain a smaller phase difference, the total number of delay elements constituting the delay line can be increased.

Returning to FIG. 1, the clock delay unit 20 will be described next.
The clock delay unit 20 includes 16 delay lines 21. In the present embodiment, each delay line 21 is configured by connecting eight delay elements 22 in series. The delay line 21 of the clock delay unit 20 is designed with the same load using the same delay element as the delay line 12 of the delay amount control unit 11, but the number of stages for connecting the delay elements in series is different. Further, since the delay line 21 of the clock delay unit 20 and the delay line 12 of the delay amount control unit 11 are required to have the same electrical characteristics, they are designed with the same layout.
The configuration of the 16 delay lines 21 of the clock delay unit 20 is the same, but the number of delay elements 22 biased to the reference voltage VREF and the lock voltage DLYB is different in each delay line.
Table 1 below shows each clock, the delay line 21 that generates them, the number of eight delay elements 22 constituting the delay line 21, the number biased to the reference voltage VREF, the number biased to the lock voltage DLYB, and the delay. Summarize time. However, the delay time is set to X picoseconds of the delay element biased with the reference voltage VREF.
[Table 1]

For example, in the delay line 21 that generates CK0, all the eight delay elements 22 that are configured are biased to the reference voltage VREF, so that the delay time of the input and output of the delay line 21 is 8 × picoseconds.
In the delay line 21 that generates CK1, seven delay elements 22 out of the eight delay elements 22 are biased to the reference voltage VREF, and one delay element 22 is biased to the lock voltage DLYB. The time is 8X + 25 picoseconds. Therefore, the phase difference between adjacent clocks is 25 picoseconds. Similarly, the phase difference between adjacent clocks of CK2 to CK15 is 25 picoseconds.
In the data recovery circuit including the multiphase clock generation circuit 10 of the present embodiment, high-precision oversampling can be realized with a 16-phase multiphase clock having a minute phase difference of 25 ps.
Further, a predetermined phase difference (here, 25 picoseconds) does not become the delay time of the delay element. That is, it is possible to realize a minute phase difference compared to the delay time of the delay element alone. That is, since the predetermined phase difference of the multiphase clock and the delay time of one stage of the delay element are independent, it is possible to generate a multiphase clock with a smaller phase difference.
In addition, since it is not necessary to operate the delay element at high speed, the current consumption of the delay element can be suppressed as compared with the conventional circuit.
In the present embodiment, a data recovery circuit for serial data with a reference clock of 2.5 GHz and a data rate of 5 Gbps is assumed as an example, but the reference clock and data rate are not limited to this, and any reference clock and data rate are used. Can adapt to

[Second Embodiment]
FIG. 4 is a diagram showing an oversampling data recovery circuit including a multiphase clock generation circuit according to the second embodiment of the present invention.
In addition, the same code | symbol is attached | subjected and demonstrated to the same component as embodiment of 1st Embodiment.
The multiphase clock generation circuit of the present embodiment includes a multiphase clock generation unit 10a, an oversampling unit 30, and a symbol data restoration unit 40.
In this embodiment, the parallelizing unit 32 adjusts and outputs only the timing without changing the data rate and bus width of the input data D0 to D15. However, as in the first embodiment, the parallelizing unit 32 The data may be output to the symbol data restoration unit 40 after serial / parallel conversion is performed to increase the bus width immediately before or immediately after to reduce the data rate.
The multiphase clock generation unit 10a includes a delay amount control unit 11a and a clock delay unit 20a. The multiphase clock generator 10a receives the reference clocks REFCLKP and REFCLKM and the reference bias VREF, and outputs a 16-phase clock CK [0:15] having a predetermined phase difference (25 picoseconds in this embodiment).
The reference clocks REFCLKP and REFCLKM are forward and inversion clocks (phase difference is 200 picoseconds) having a frequency of 2.5 GHz and a phase difference of 180 °.

The delay amount control unit 11a according to the present embodiment includes three delay lines 12 (12-1, 12-2, 12-3), two phase comparators 13, and two averaging filters 14. The delay amount control unit 11 uses the three delay lines 12 to generate two types of biases (DLYB1, DLYB2) that generate two types of delay amounts.
Similar to the principle described in the first embodiment, the phase difference between the delay line 12-1 to which the reference voltage VREF is biased and the delay line 12-2 to which the lock voltage DLYB1 is biased is 90 ° (100 picoseconds). ), The lock voltage DLYB1 is locked. Further, the lock voltage DLYB2 is locked so that the phase difference between the delay line 12-2 to which the lock voltage DLYB1 is biased and the delay line 12-3 to which the lock voltage DLYB2 is biased is also 90 ° (100 picoseconds). . The difference in delay time between the delay element 15 to which the reference voltage VREF is biased and the delay element 15 to which the lock voltage DLYB1 is biased is one-fourth of 100 picoseconds, which is 25 picoseconds. Similarly, the delay time difference between the delay element 15 to which the lock voltage DLYB1 is biased and the delay element 15 to which the lock voltage DLYB2 is biased is a quarter of 100 picoseconds, and thus is 25 picoseconds.

Therefore, if the delay time of the delay element 15 to which the reference voltage VREF is biased is X picoseconds, the delay time of the delay element 15 to which the lock voltage DLYB1 is biased is X + 25 picoseconds, and the lock voltage DLYB2 is further biased. The delay time of the delay element 15 is X + 50 picoseconds.
In this embodiment, since a clock with a frequency of 2.5 GHz is input, an analog multiplier (not shown) capable of high-speed operation is used, and each averaging filter 14 uses a first-order low-pass filter, but high-speed operation is required. In a system that does not, this is not the case, and a phase comparator using a general exclusive OR (XOR) gate can also be used.
In the embodiment of the present invention, the number of delay elements 15 constituting each delay line 12 is four, but in order to obtain a smaller phase difference, the total number of delay elements 15 constituting the delay line 12 is increased. it can.

Next, the clock delay unit 20a of this embodiment will be described. In the present embodiment, the clock delay unit is composed of 16 delay lines 21a. The reference bias VREF and the two biases generated by the delay amount control unit 11 and the lock voltages DLYB1 and DLYB2 are input to the clock delay unit 20a. Each delay line 21a is configured by connecting four delay elements 22 in series. The delay line 21a of the clock delay unit 20a is designed with the same load using the same delay element as the delay line of the delay amount control unit 11a. Further, since the delay line 21a of the clock delay unit 20a and the delay line 12 of the delay amount control unit 11 are required to have the same electrical characteristics, they are designed with the same layout.
The configuration of the 16 delay lines 12a of the clock delay unit 20a is the same, but the number of delay elements biased to the reference voltage VREF and the lock voltages DLYB1 and DLYB2 in each delay line is different.
Table 2 below shows the number of the four delay elements 22 constituting each clock and the delay line 21a that generates each clock, the number biased to the reference voltage VREF, the number biased to the lock voltage DLYB1, and the bias to the lock voltage DLYB2. Summarize the number and delay time. However, the delay time is set to X picoseconds of the delay element biased with the reference voltage VREF.
[Table 2]

For example, in the delay line 21a for generating CK0, the four delay elements 22 constituting the CK0 are biased to the reference voltage VREF, so that the delay time of the input and output of the delay line 21 is 4 × picoseconds. In the delay line 21 that generates CK1, three of the four delay elements are biased to the reference voltage VREF, and one delay element 22 is biased to the lock voltage DLYB1, so that the delay time of the delay line 21a Is 4X + 25 picoseconds. Therefore, the phase difference between adjacent clocks is 25 picoseconds. In the delay line 21a for generating CK2, three delay elements 22 out of four delay elements 22 are biased to the reference voltage VREF, and one delay element is biased to the lock voltage DLYB2, so that the delay of the delay line 21a. The time is 4X + 50 picoseconds. Therefore, adjacent clocks have a phase difference of 25 picoseconds.
In the data recovery circuit including the multiphase clock generation circuit of this embodiment, high-precision oversampling can be realized with a 16-phase multiphase clock having a minute phase difference of 25 ps.
In the multiphase clock generation circuit of this embodiment, a predetermined phase difference (here, 25 picoseconds) does not become the delay time of the delay element. That is, it is possible to realize a minute phase difference compared to the delay time of the delay element alone. That is, since the predetermined phase difference of the multiphase clock and the delay time of one stage of the delay element are independent, it is possible to generate a multiphase clock with a smaller phase difference.
Further, since it is not necessary to operate the delay element at high speed, current consumption of the delay element can be suppressed as compared with the conventional circuit.
In the present embodiment, a data recovery circuit for serial data with a reference clock of 2.5 GHz and a data rate of 5 Gbps is assumed as an example, but the reference clock and data rate are not limited to this, and any reference clock and data rate are used. Can adapt to

[Third Embodiment]
FIG. 5 is a diagram showing an oversampling data recovery circuit including a phase shift circuit according to a third embodiment of the present invention.
The configuration of the data recovery circuit including the third embodiment of the present invention includes a delay amount control unit 50, a phase shift unit 60, an oversampling unit 70, and a symbol data restoration unit 80.
The delay amount control unit 50 includes two delay lines 51 each including a delay element 52, and includes a phase comparator 53 and an averaging filter 54 that compare the phases of the delay line outputs. The configuration is the same as that of the quantity control unit 11.
Further, the oversampling unit 70 takes in the multiphase data s [0: 7] by the two supplied clocks REFCCK and REFCKM, and outputs the oversampling data OVSD [0:15].
The oversampling unit 70 is composed of a sampling FF unit 71 composed of FF0 to FF15 and a parallelizing unit 72, for example.
The sampling FF unit 71 samples the reception data Data having a phase difference of equal intervals generated by the phase shift unit 60 at the rising (or falling) timing of the reference clocks REFCLKP and REFCKM. The output of the sampling FF unit 71 has a phase difference generated by the phase shift unit 60.
The parallelizing unit 72 outputs data D0 to D15 input with a phase difference as parallel data synchronized with one clock.
In addition, the symbol data restoration unit 80 generates symbol data SYM and a symbol clock SYMCLK from the oversampling data OVSD.

In the first and second embodiments, the paralleling unit 32 adjusts and outputs only the timing without changing the data rate and bus width of the input data D0 to 15; It is also possible to output to the symbol data restoration unit 80 after performing serial-parallel conversion to increase the width and reduce the data rate.
In the delay amount control unit 50, the phase difference between the delay line 51 to which the reference voltage VREF is biased and the delay line 51 to which the lock voltage DLYB is biased is 90 ° (similar to the principle described in the first embodiment). The lock voltage DLYB is locked so as to be 100 picoseconds). The difference in delay time between the delay element 52 to which the reference voltage VREF is biased and the delay element 52 to which the lock voltage DLYB is biased is one-fourth of 100 picoseconds, which is 25 picoseconds.
In this embodiment, since a clock with a frequency of 2.5 GHz is input, an analog multiplier (not shown) capable of high-speed operation is used, and the averaging filter 54 uses a first-order low-pass filter, but does not require high-speed operation. The system is not limited to this, and a phase comparator using a general exclusive OR (XOR) gate can also be used.
In this embodiment, the number of delay elements 52 constituting the delay line 51 is four. However, in order to obtain a smaller phase difference, the total number of delay elements 52 constituting the delay line 51 can be increased.

Next, the phase shift unit 60 which is the main configuration of the present embodiment will be described. The phase shift unit 60 includes eight delay lines 61. The reference bias VREF and the lock bias DLUYB generated by the delay amount control unit 50 are input. Each delay line 61 is configured by connecting eight delay elements 62 in series. The delay line 61 of the phase shift unit 60 is designed with the same load using the same delay element as the delay line 61 of the delay amount control unit 50. Further, since the delay line 61 of the phase shift unit 60 and the delay line 51 of the delay amount control unit 50 are required to have the same electrical characteristics, they are designed with the same layout.
The configuration of the eight delay lines 61 of the phase shift unit 60 is the same, but the number of delay elements 62 biased to the reference voltage VREF and the lock voltage DLYB in each delay line 61 is different.
Table 3 below summarizes the number biased to VREF, the number biased to DLYB, and the delay time among the eight delay elements constituting each data s [0: 7] and the delay line that generates the data s [0: 7]. However, the delay time is set to X picoseconds of the delay element 62 biased with the reference voltage VREF.
[Table 3]

For example, in the delay line 61 that generates S0, the eight delay elements 62 constituting the delay line 61 are all biased to the reference voltage VREF, so that the delay time of the input and output of the delay line 61 is 8 × picoseconds. On the other hand, in the delay line 61 that generates S1, seven delay elements out of the eight delay elements 62 are biased to the reference voltage VREF, and one delay element is biased to the lock voltage DLYB. The output delay time is 8X + 25 picoseconds. Therefore, the phase difference between adjacent data is 25 picoseconds.
In the data recovery circuit including the phase shift circuit of this embodiment, high-precision oversampling can be realized with an 8-phase multiphase clock having a minute phase difference of 25 picoseconds.
In the phase shift circuit of this embodiment, a predetermined phase difference (here, 25 picoseconds) does not become the delay time of the delay element. That is, it is possible to realize a minute phase difference compared to the delay time of the delay element alone.
That is, since the resolution of the phase shift circuit and the delay time of one stage of the delay element are independent, a phase shift circuit with a smaller phase difference can be generated.
Further, since it is not necessary to operate the delay element at high speed, current consumption of the delay element can be suppressed as compared with the conventional circuit.

In the present embodiment, a data recovery circuit for serial data with a reference clock of 2.5 GHz and a data rate of 5 Gbps is assumed as an example, but the reference clock and data rate are not limited to this, and any reference clock and data rate are used. Can adapt to
In the present embodiment, the delay amount control unit 50 is configured to include two delay lines 51, one phase comparator 53, and one averaging filter 54. However, as in the case of the second embodiment. In addition, for example, the number of delay lines 51 may be three, and in this case, two phase comparators 53 and two averaging filters 54 may be provided to generate a bias that generates two or more types of delay amounts.
Even with this configuration, since the resolution of the phase shift circuit and the delay time of one stage of the delay element are independent, a phase shift circuit with a smaller phase difference can be generated. Further, since it is not necessary to operate the delay element at high speed, an increase in current consumption can be suppressed.

1 is a diagram illustrating an oversampling data recovery circuit including a multiphase clock generation circuit according to a first embodiment of the present invention. FIG. 4 is a diagram illustrating an example of a delay element 15. The figure which shows the operation | movement process until DLYB locks in the delay amount control part 11. FIG. The figure which shows the oversampling data recovery circuit containing the multiphase clock generation circuit which is the 2nd Embodiment of this invention. The figure which shows the oversampling data recovery circuit containing the phase shift circuit which is the 3rd Embodiment of this invention. The block diagram of the oversampling CDR circuit conventionally used. 2 is a diagram for explaining a data recovery circuit of Patent Document 1. FIG. The figure which shows an example of DLL which generates the delay of 8 phases. The figure which shows an example of the delay element 303 which comprises the delay production | generation part 300 of FIG.

Explanation of symbols

  10 multiphase clock generation unit, 10a multiphase clock generation unit, 11 delay amount control unit, 11a delay amount control unit, 12 delay line, 12a delay line, 13 phase comparator, 14 averaging filter, 15 delay element, 20 clock Delay unit, 20a clock delay unit, 21 delay line, 21a delay line, 22 delay element, 30 oversampling unit, 31 sampling FF unit, 32 parallelization unit, 40 symbol data restoration unit, 50 delay amount control unit, 51 delay line , 52 delay element, 53 phase comparator, 54 averaging filter, 60 phase shift unit, 61 delay line, 62 delay element, 70 oversampling unit, 71 sampling FF unit, 72 parallelization unit, 80 symbol data restoration unit, 100 Multi-phase clock generator, 101 data samples , 203 multi-phase clock generation unit, 204 flip-flop, 205 parallelization unit, 206 oversampling unit, 207 symbol data restoration unit, 208 data selection unit, 209 deserializer, 210 selection signal generation unit, 211 comma detection unit, 300 Delay generator, 301 phase comparator, 303 delay element

Claims (6)

Two delay lines comprising a pair of input / output terminals and a delay amount control terminal, wherein a plurality of delay elements are connected in series to generate a delay amount corresponding to a voltage biased to the delay amount control terminal. A phase comparator that detects a phase difference between the outputs of the two delay lines, and an averaging filter that averages the outputs of the phase comparators, and one of the two delay lines is Each delay line is configured such that a reference voltage is connected to the delay amount control terminal of the delay element constituting the delay element, and an output of the averaging filter is connected to the delay amount control terminal of the delay element constituting the other delay line. A delay amount control unit that controls the output of the signal to have a predetermined phase difference;
A plurality of delay lines configured by connecting a plurality of the same number of the delay elements in series, and the number of the delay elements connected to the delay amount control terminal in each delay line and the averaging filter A clock delay unit having a different combination of the number of delay elements connected to the delay amount control terminal of an output voltage; and
And a multi-phase clock generating circuit that generates a multi-phase clock having a predetermined phase difference by inputting a reference clock to each delay line of the clock delay unit. A plurality of delay lines comprising a pair of input / output terminals and a delay amount control terminal, wherein a plurality of delay elements are connected in series to generate a delay amount corresponding to a voltage biased to the delay amount control terminal. A plurality of phase comparators that detect a phase difference between one delay line and the other delay lines, and a plurality of averaging filters that average the outputs of the phase comparators. The delay amount of the delay element constituting each other delay line is connected to a reference voltage to the delay amount control terminal of the delay element constituting one delay line of the plurality of delay lines. A delay amount control unit for controlling the output of each delay line to have a predetermined phase difference by connecting the output of each averaging filter to the control terminal;
A plurality of delay lines configured by connecting a plurality of the same number of the delay elements in series, and the number of the delay elements connected to the delay amount control terminal in each delay line and the averaging filter A clock delay unit having a different combination of the number of delay elements connected to the delay amount control terminal of an output voltage; and
And a multi-phase clock generating circuit that generates a multi-phase clock having a predetermined phase difference by inputting a reference clock to each delay line of the clock delay unit.   3. An oversampling circuit that performs oversampling using a clock generated by the multiphase clock generation circuit according to claim 1. Two delay lines comprising a pair of input / output terminals and a delay amount control terminal, wherein a plurality of delay elements are connected in series to generate a delay amount corresponding to a voltage biased to the delay amount control terminal. And a phase comparator that detects a phase difference between outputs of the two delay lines, and an averaging filter that averages the outputs of the phase comparator,
A reference voltage is connected to the delay amount control terminal of the delay element constituting one delay line of the two delay lines, and the average is connected to the delay amount control terminal of the delay element constituting the other delay line. A delay amount control unit for controlling the output of each delay line to have a predetermined phase difference by connecting the output of the activation filter;
A plurality of delay lines configured by connecting a plurality of the same number of the delay elements in series, and the number of the delay elements connected to the delay amount control terminal in each delay line and the averaging filter A phase shift unit having different combinations of the number of delay elements connected to the delay amount control terminal of the output voltage;
With
A phase shift circuit, wherein a serial data pattern is input to each delay line of the phase shift unit to generate a serial data pattern having a predetermined phase difference. A plurality of delay lines comprising a pair of input / output terminals and a delay amount control terminal, wherein a plurality of delay elements are connected in series to generate a delay amount corresponding to a voltage biased to the delay amount control terminal. A plurality of phase comparators that detect a phase difference between one delay line and the other delay lines, and a plurality of averaging filters that average the outputs of the phase comparators. The delay amount of the delay element constituting each other delay line is connected to a reference voltage to the delay amount control terminal of the delay element constituting one delay line of the plurality of delay lines. A delay amount control unit for controlling the output of each delay line to have a predetermined phase difference by connecting the output of each averaging filter to the control terminal;
A plurality of delay lines configured by connecting a plurality of the same number of delay elements in series, the number of the delay elements having the reference voltage in each delay line connected to the delay amount control terminal, and the averaging filter A phase shift unit having a different combination of the number of delay elements connected to the delay amount control terminal.
With
A phase shift circuit, wherein a serial data pattern is input to each delay line of the phase shift unit to generate a serial data pattern having a predetermined phase difference.   6. An oversampling circuit that performs oversampling using a multiphase serial data pattern generated by using the phase shift circuit according to claim 4 or 5.

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