CN105703749A - Low-power consumption and accurate sleep timer circuit and method - Google Patents
Low-power consumption and accurate sleep timer circuit and method Download PDFInfo
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Abstract
The invention relates to a low-power consumption and accurate sleep timer circuit. The low-power consumption and accurate sleep timer includes a high-frequency clock source, a low-frequency clock source, a clock state indicating circuit, a control circuit, timers, a high-frequency timing margin calculator, a low-frequency timing margin calculator, comparators and a timer result decision device. According to a low-power consumption and accurate sleep timing method, sleep timing is completed by means of automatic switching of two timers. According to the circuit of the invention, circuit structures such as the high-frequency clock source, the low-frequency clock source, the clock state indicating circuit, the control circuit, the high-frequency timing margin calculator and the low-frequency timing margin calculator are adopted; and according to the method, hardware is utilized to control the high-frequency timing margin calculator and the low-frequency timing margin calculator. With the circuit and method adopted, a detect that switching is carried out by means of a processor in the prior art can be eliminated, the resource overhead of the processor can be decreased, timing accuracy can be improved, and power consumption of a system can be decreased.
Description
Technical field
The present invention relates to a kind of accurate doze output circuit of low-power consumption and method, specifically a kind of towards SOC(system on a chip) level chip, it is possible to effectively reduce power consumption, the doze output circuit that accurate timing is provided and method。
Background technology
Timing problems is a very common problem in embedded system。Different flush bonding processors comprises different timing units, no system applies the timing application that needs are different。The intervalometer etc. that common timer-type includes general intervalometer, input pulse length intervalometer, output pulse timer, multi input/output timer are combined with functional module。Timer-type for application is then more varied, such as transmission timer, receives intervalometer, doze output, Real-time clock timer etc.。
Doze output is a kind of type in intervalometer。Desirable doze output operation principle is usually before system dormancy and arranges a timing, be activated when dormancy, and system carries out resting state afterwards；After doze output runs to default timing, producing wake-up signal, system is waken up under this signal, starts working afterwards。Desirable doze output is actually infeasible, and high-precision timing needs altofrequency clock signal, the power consumption that too high frequency consumption is bigger。If using relatively low timing frequency, then the precision of timing is unable to reach requirement。The solution of this problem at present needs processor accessory timer to solve, and after dormancy, by low-frequency runs, solves the problem that power consumption is bigger；Upon awakening, by high-frequency runs, the surplus of low frequency timer count is supplied。This mode to some extent solves the problem of power consumption and precision, but still undesirable, and reason has the following aspects: the participation of processor still can produce unnecessary power consumption；The uncertainty that processor wakes up causes the inexactness of dormancy timing。
Summary of the invention
For above-mentioned technical deficiency, it is an object of the invention to provide a kind of industry wireless network standard technique protocol realization towards industrial process automation, for the low-power consumption of SOC(system on a chip) level chip, accurate doze output circuit and method。Traditional circuit is comprised two improvement by this circuit: first is the increase in the circuit such as surplus calculating, timing results judgement, the computing that processor realizes is become hardware and calculates, reduce power consumption；Second is the uncertainty improving processor wakeup time, it is possible to be effectively improved the precision of dormancy timing。
This invention address that its technical problem by the following technical solutions: a kind of accurate doze output circuit of low-power consumption, including high frequency clock source, low-frequency clock source, clock status indicating circuit, control circuit, intervalometer, high frequency timing margin computer, low frequency timing margin computer, comparator, timing results decision device；
Described high frequency clock source exports the clock end to be measured of the high frequency clock clock end to first timer and clock status indicating circuit, first timer outfan and first comparator the second input and connects；The reference clock end of the low-frequency clock source output low frequency clock clock end to second timer and clock clock status indicating circuit；
The output clock status signal of described clock status indicating circuit is to control circuit, and first input end accesses high frequency clock, the second input accesses low-frequency clock；
The first input end of described control circuit accesses timing commencing signal, the second input incoming clock status signal, four outfans respectively with high frequency timing margin computer, low frequency timing margin computer, first timer, second timer Enable Pin be connected；
The first input end of described high frequency timing margin computer, low frequency timing margin computer the equal access delay timing value of input；Second timer outfan and high frequency timing margin computer the second input, second comparator the second input, the 3rd comparator the second input be connected；High frequency timing margin computer outfan and the first comparator first input end connect；Two outfans of low frequency timing margin computer are connected with the first input end of the second comparator first input end, the 3rd comparator respectively；
First comparator, the second comparator, the 3rd comparator outfan be connected with three inputs of timing results decision device respectively, timing results decision device output timing end signal and error indication signal；The outfan of the second comparator is also connected with the input in high frequency clock source。
Described clock status indicating circuit includes: include clock division circuits, edge correction circuit, edge sense circuit and shift-register circuit；Described clock division circuits is connected with edge correction circuit；Described edge correction circuit is connected with edge sense circuit, shift-register circuit；Described edge sense circuit is connected with shift-register circuit；
Described clock division circuits is for dividing reference clock, and output frequency division clock signal is to edge sense circuit；
Described edge sense circuit access clock to be measured, clock division circuits output sub-frequency clock signal and edge correction circuit output edge correction signal, sub-frequency clock signal carries out edge detection, and output cycle reset signal is to edge correction circuit and shift-register circuit；
Described edge correction circuit accesses reference clock and cycle reset signal is modified obtaining edge correction signal and exports to edge sense circuit；
Described shift-register circuit accesses high level, reference clock and cycle reset signal, carries out internal register displacement and reset operation, exports clock status signal。
A kind of accurate dormancy timing method of low-power consumption, comprises the following steps:
Timing starts, and control circuit produces low frequency calculating enable output tremendously low frequency timing margin computer, low frequency timing enables and exports to second timer；Delay timing value is calculated obtaining two low frequency timing fiducial values by low frequency timing margin computer, and second timer starts counting up；
When the first low frequency timing fiducial value of low frequency timing margin computer output and the count value of the second enumerator are equal, generate the first low frequency comparison match signal, start high frequency clock source simultaneously；When high frequency clock source works, clock status indicating circuit generates clock status signal and exports to control circuit；Control circuit generates high frequency calculating enable output tremendously high frequency timing margin computer, high frequency timing enables and exports to first timer, simultaneously closes off low frequency and regularly enables, and second timer stops counting；
The current count value of delay timing value and second timer is calculated by high frequency timing margin computer, obtains high frequency timing fiducial value, and first timer starts counting up；When the high frequency timing fiducial value of high frequency timing margin computer output and the count value of first timer are equal, generate high-frequency ratio relatively matched signal；
Timing results decision device exports timing end signal according to the comparative result of the first comparator and the second comparator。
After described first low frequency comparison match signal enabling high frequency clock source, when high frequency clock source exception, keeping low frequency timing to enable, second timer continues counting；When count value is equal with the second low frequency timing fiducial value, generate the second low frequency comparison match signal；
Timing results decision device exports timing end signal and error indication signal according to the comparative result of the second comparator and the 3rd comparator。
Delay timing value is calculated being realized by below equation by described low frequency timing margin computer:
First low frequency timing fiducial value=(delay timing value-high frequency clock source wakeup time-high frequency timer count time)/low-frequency clock source clock cycle；
Wherein, high frequency clock source wakeup time, high frequency timer count time, low-frequency clock source clock cycle are setting value。
Delay timing value is calculated realizing also by below equation by described low frequency timing margin computer
Second low frequency timing fiducial value=delay timing value/low-frequency clock source clock cycle；
Wherein, the low-frequency clock source clock cycle is setting value。
The described current count value to delay timing value and second timer is calculated being realized by below equation: high frequency timing fiducial value=(delay timing value-second timer current count value-phase pushing figure)/high frequency clock source clock cycle；Delay timing value is an externally input, and second timer current count value is the output of second timer。
Wherein, phase pushing figure, high frequency clock source clock cycle are setting value。
The described comparative result according to the first comparator and the second comparator exports timing end signal particularly as follows: when the output result of the first comparator and the second comparator is all equal, exports timing end signal and do not produce error indication signal。
The described comparative result according to the first comparator and the second comparator exports timing end signal particularly as follows: when the output result of the first comparator and the second comparator is all equal, exports timing end signal and do not produce error indication signal。
The described comparative result according to the second comparator and the 3rd comparator exports timing end signal and error indication signal particularly as follows: when the output result of the second comparator and the 3rd comparator is all equal, exports timing end signal and produce error indication signal。
Described clock status indicating circuit generates clock status signal and comprises the following steps:
A. reference clock is carried out frequency dividing and obtains sub-frequency clock signal by clock division circuits；
B. sub-frequency clock signal is carried out edge detection and obtains cycle reset signal by edge sense circuit；
C. high level is transmitted by shift-register circuit step by step, and when clock to be measured is normal, internal depositor is resetted by cycle reset signal, and shift-register circuit output keeps low level；When clock exception to be measured, cycle reset dropout, shift-register circuit output keeps high level；
D. correction circuit in edge is when clock to be measured stopping and cycle reset abnormal signal, the reference clock negated and cycle reset signal is carried out and generates edge correction signal；
E. exported clock status signal by shift-register circuit, return step a。
The invention have the advantages that and advantage:
1. circuit of the present invention is towards SOC(system on a chip) level chip field, relates to ultralow Consumption, it is provided that one can meet ultralow Consumption requirement, the doze output circuit of accurate timing。
2. circuit of the present invention adopts the circuit structures such as high frequency intervalometer, low frequency intervalometer, clock status indicating circuit, control circuit, high frequency timing margin computer, low frequency timing margin computer, the method adopting hardware controls high frequency intervalometer, low frequency intervalometer, solve the shortcoming that tradition needs to switch over by processor, decrease processor resource expense, improve timing accuracy, reduce system power dissipation。
3. circuit of the present invention includes the structures such as circuit such as high frequency timing comparator, the first low frequency timing comparator, the second low frequency timing comparator, timing results judgement, when can effectively prevent high frequency clock source to lose efficacy, cause the defect that cannot complete dormancy timing, improve the reliability of timing。
4. in the present invention clock status indicating circuit towards system-on-chip designs, it is possible to the effective state that clock signal to be measured is provided。
5. the clock status indicating circuit of the present invention all adopts Design of Digital Circuit to realize, it does not have analog circuit, it is possible to adopt in multiple fields such as IC design or field programmable logic array designs。
6. clock status indicating circuit is when adopting 2 frequency dividing, and most I adopts six triggers and two gate circuits namely can realize clock status deictic function, has simple in construction, runs the advantages such as power consumption is little。
Accompanying drawing explanation
Fig. 1 is the time diagram of doze output；
Fig. 2 is the exchange-column shift schematic diagram of doze output；
Fig. 3 is the structured flowchart of the present invention；
Fig. 4 is a kind of clock status indicating circuit structure chart；
Fig. 5 is 2 frequency-dividing clock frequency dividing circuit structure charts of clock status indicating circuit；
Fig. 6 is the edge sense circuit structure chart of clock status indicating circuit；
Fig. 7 is the edge correction circuit structure diagram of clock status indicating circuit；
Fig. 8 is the shift-register circuit structure chart of clock status indicating circuit。
Detailed description of the invention
Below in conjunction with embodiment, the present invention is described in further detail。
A kind of low-power consumption, accurate doze output circuit and method, its functional module includes high frequency clock source, low-frequency clock source, clock status indicating circuit, control circuit, intervalometer, high frequency timing margin computer, low frequency timing margin computer, comparator, timing results judgement etc.。
The effect in low-frequency clock source described in circuit of the present invention is to generate low-frequency clock。The low-frequency clock that low-frequency clock source generates uses for low frequency intervalometer timing。Low-frequency clock source is always in doze output work process, it is impossible to be turned off。Low-frequency clock in circuit of the present invention refers generally to frequency clock in 10KHz to 100KHz scope, and according to practical application, this clock ranges can suitably increase or reduce。
Circuit of the present invention comprises 2 identical intervalometers of structure, different according to counting clock, is called high frequency intervalometer and low frequency intervalometer。Circuit of the present invention comprises 3 identical comparators of structure, different according to function, is called high frequency timing comparator, the first low frequency timing comparator, the second low frequency timing comparator。
The effect in the high frequency clock source described in circuit of the present invention is to produce high frequency clock。High frequency clock is for high frequency intervalometer timing。High frequency clock source comprises enable signal, it is possible to turn off entrance low power consumpting state by enabling signal。Low-frequency clock in circuit of the present invention refers generally to the frequency clock at more than 1MHz, and according to practical application, this clock ranges can suitably increase or reduce。
The effect of low frequency intervalometer described in circuit of the present invention is to count under low-frequency clock。In whole dormancy period, the counting of most of the time is completed by low frequency intervalometer。Low frequency intervalometer is relatively low due to count frequency, and dormancy period counting be there may be fraction surplus cannot complete by accurate metering, and this one count surplus is completed by high frequency intervalometer timing。
The effect of high frequency intervalometer described in circuit of the present invention is to count under high frequency clock。In whole dormancy period, the counting of most of the time is completed by low frequency intervalometer。High frequency intervalometer carries out timing for the surplus that low frequency intervalometer cannot complete timing。
The effect of clock status indicating circuit of the present invention is that prison shows high frequency clock source whether normal operation, produces clock status signal；The effect of control circuit is that the timing receiving externally input starts and clock status signal, carries out logic state judgement, generates the enable signal controlling the modules such as high frequency intervalometer, low frequency intervalometer, high frequency timing margin computer and low frequency timing margin computer。
The effect of low frequency timing margin computer described in circuit of the present invention is to calculate the first low frequency timing fiducial value and the second low frequency timing fiducial value。The effect of the first low frequency timing fiducial value is for waking high frequency clock source up, and the effect of the second low frequency timing fiducial value is when high frequency clock source is not waken up in time, produces the second low frequency comparison match。
The effect of high frequency timing margin computer of the present invention is to calculate high frequency timing fiducial value。The effect of high frequency timing fiducial value is to generate high-frequency ratio relatively matched signal。
The effect of comparator circuit of the present invention is that two numerical value are compared, and when comparative result is equal, produces the output of comparison match signal。
The effect of timing results decision circuit of the present invention is that high-frequency ratio relatively matched signal and low frequency timing indication signal are judged, judgement timing terminates and carries out mistake instruction。
The annexation of circuit of the present invention is:
Described high frequency clock source exports the clock end to be measured of the high frequency clock clock end to first timer and clock status indicating circuit, first timer outfan and first comparator the second input and connects；The reference clock end of the low-frequency clock source output low frequency clock clock end to second timer and clock clock status indicating circuit。
The output clock status signal of described clock status indicating circuit is to control circuit, and first input end accesses high frequency clock, the second input accesses low-frequency clock。
The first input end of described control circuit accesses timing commencing signal, the second input incoming clock status signal, four outfans respectively with high frequency timing margin computer, low frequency timing margin computer, first timer, second timer Enable Pin be connected。
The first input end of described high frequency timing margin computer, low frequency timing margin computer the equal access delay timing value of input；Second timer outfan and high frequency timing margin computer the second input, second comparator the second input, the 3rd comparator the second input be connected。
High frequency timing margin computer and the first comparator first input end connect；The second comparators distinguished by two outfans of low frequency timing margin computer, the first input end of the 3rd comparator connects。
First comparator, the second comparator, the 3rd comparator outfan be connected with three inputs of timing results decision device respectively, timing results decision device output timing end signal and error indication signal；The outfan of the second comparator is also connected with the input in high frequency clock source。
The principles illustrated of circuit of the present invention is as follows:
Doze output circuit of the present invention and side's ratio juris are that the timing of dormancy time is divided into two steps complete, as it is shown in figure 1, respectively low frequency timer count time and high frequency timer count time。The low frequency timer count time is driven low frequency timer count to complete by low-frequency clock, the high frequency timer count time is driven high frequency timer count to complete by high frequency clock。
Whole system can further describe, as shown in Figure 2。When system enters resting state, low frequency timing margin computer works, produce two timing fiducial values, respectively the first low frequency timing fiducial value and the second low frequency timing fiducial value, first low frequency timing fiducial value is the timing fiducial value after deduction high frequency timing margin, second low frequency timing fiducial value is final wakeup time, and the second low frequency timing fiducial value would be likely to occur certain error。Wherein the computing formula of the first low frequency timing fiducial value is as follows:
Wherein high frequency clock source wakeup time, high frequency timer count time and low-frequency clock source clock cycle are setting value。High frequency clock source wakeup time is determined by high frequency clock source；The high frequency timer count time is made remainder number by dormancy time and low-frequency clock source clock cycle and calculates, or increases several low-frequency clock source clock period time after remainder calculates；The low-frequency clock source clock cycle was determined by the cycle of low-frequency clock。
The computing formula of the second low frequency timing fiducial value is as follows。
Wherein the low-frequency clock source clock cycle is setting value。The low-frequency clock source clock cycle was determined by the cycle of low-frequency clock。
After entering resting state, first being carried out timing by low frequency intervalometer, when namely will be up to the object time, when namely low frequency timer count value reaches the first low frequency timing fiducial value, generate the first low frequency comparison match signal, this signal wakes high frequency clock source up。
Clock status circuit monitors high frequency clock source, after high frequency clock source reaches steady-working state, after namely high frequency clock source produces high frequency clock, produces clock status signal。
Under clock status signal effect, high frequency intervalometer is started working, and high frequency timing margin computer generates high frequency timing fiducial value, and low frequency intervalometer quits work simultaneously。The computing formula of high frequency timing fiducial value is as follows。
Its medium and low frequency intervalometer current count value is exported by the output port of low frequency intervalometer and obtains；Phase pushing figure and high frequency clock source clock cycle are setting value。Phase pushing figure is constant, and its value is relevant to the phase place of the effective time of enable port Yu low frequency intervalometer, is specifically determined by the design of clock status indicating circuit；The high frequency clock source clock cycle was determined by the cycle of high frequency clock。
When high frequency timer count reaches high frequency timing fiducial value, produce high-frequency ratio relatively matched signal；If the timing that high frequency clock wakeup time is corresponding more than the second low frequency timing fiducial value, when the count value of low frequency intervalometer reaches the second low frequency timing fiducial value, producing the second low frequency timing indication signal, now the circuit such as high frequency intervalometer and high frequency timing margin computer does not work within this count cycle。
The effect of low frequency timing margin computer described in circuit of the present invention is to calculate the first low frequency timing fiducial value and the second low frequency timing fiducial value。The effect of the first low frequency timing fiducial value is for waking high frequency clock source up, and the effect of the second low frequency timing fiducial value is when high frequency clock source is not waken up in time, produces the second low frequency comparison match signal。Owing to the frequency in low-frequency clock source is relatively low, therefore the second low frequency comparison match signal is likely to there is bigger error；But high frequency clock source is not waken up for the high-frequency ratio relatively matched signal loss caused, be still a kind of good means to save the situation。
The Rule of judgment of timing results decision circuit is: the first low frequency comparison apparatus must produce the first low frequency comparison match signal；High frequency timing comparator produces high-frequency ratio relatively matched signal or the second low frequency comparison apparatus must produce the second low frequency comparison match signal。When the first low frequency comparison match signal and high-frequency ratio are equal compared with matched signal, export timing end signal and do not produce error indication signal；When first low frequency comparison match signal and the second low frequency comparison match signal are equal, export timing end signal and produce error indication signal。
The method step of patent of the present invention is:
Being started by timing commencing signal, control circuit produces low frequency calculating enable output tremendously low frequency timing margin computer, low frequency timing enables and exports tremendously low frequency intervalometer；Delay timing value is calculated obtaining the first low frequency timing fiducial value and the second low frequency timing fiducial value by low frequency timing margin computer, and low frequency intervalometer starts counting up；
When the first low frequency timing fiducial value of low frequency timing margin computer output and the count value of low frequency intervalometer are equal, generate the first low frequency comparison match signal, start high frequency clock source simultaneously；When high frequency clock source works, clock status indicating circuit generates clock status signal and exports to control circuit；Control circuit generates high frequency calculating enable output tremendously high frequency timing margin computer, high frequency timing enables and exports tremendously high frequency intervalometer, simultaneously closes off low frequency and regularly enables, and second timer stops counting；
The current count value of delay timing value and second timer is calculated by high frequency timing margin computer, obtains high frequency timing fiducial value, and high frequency intervalometer starts counting up；When the high frequency timing fiducial value of high frequency timing margin computer output and the count value of high frequency intervalometer are equal, generate high-frequency ratio relatively matched signal；
Timing results decision device exports timing end signal according to the comparative result of the low frequency comparison apparatus of high frequency timing comparator and first。
After first low frequency comparison match signal enabling high frequency clock source, when high frequency clock source exception, keeping low frequency timing to enable, low frequency intervalometer continues counting；When count value is equal with the second low frequency timing fiducial value, generate the second low frequency comparison match signal；Timing results decision device exports timing end signal and error indication signal according to the comparative result of the first low frequency comparison apparatus and the second low frequency comparison apparatus。
In the present embodiment, circuit realiration major part part uses verilog language to write, it is possible to use synthesis tool comprehensively realizes；Fraction circuit is collectively constituted by internal circuit and external electronic component, such as high frequency clock source and low-frequency clock source；The present embodiment is applied in actual chips, achieves good effect。
The present embodiment adopts the circuit structure illustrated in summary of the invention, specifically as shown in Figure 3。Circuit structure includes the circuit such as high frequency clock source, low-frequency clock source, clock status indicating circuit, control circuit, intervalometer 1, timer 2, high frequency timing margin computer, low frequency timing margin computer, comparator 1, comparator 2, comparator 3, timing results judgement。
This is implemented its outside port and includes input port and output port, and input port includes delay timing value, timing starts；Output port includes timing to be terminated and mistake instruction。
In this enforcement, the port of each functional module is: high frequency clock source includes input port E and output port C；Low-frequency clock source includes output port C；Clock status indicating circuit comprises input port CK, C and output port ST；Control circuit comprises input port S, A and output port C1, C2, C3, C4；Intervalometer 1 comprises input port E, CK and output port C；Timer 2 comprises input port E, CK and output port C；High frequency timing margin computer includes input port E, A, B and output port C；Low frequency timing margin computer includes input port E, A and output port C1, C2；Comparator 1 comprises input port A and B, output port C；Comparator 2 comprises input port A and B, output port C；Comparator 3 comprises input port A and B, output port C；Timing results judgement includes input port A1, A2 and A3, output port C1 and C2。
In this enforcement, the annexation of circuit is: the input port E in high frequency clock source is exported by the C port of comparator 2, and the C port in high frequency clock source exports the C port of the high frequency clock CK port to intervalometer 1 and clock status indicating circuit；The CK port of the C end output low frequency clock in the low-frequency clock source CK port to low frequency timer module and clock status indicating circuit；The CK port of clock status indicating circuit is accessed by the C port in low-frequency clock source, and the C port of clock status indicating circuit is accessed by the C port in low-frequency clock source, and the ST port of clock status indicating circuit exports the A port to control circuit；The S port of control circuit is accessed by the timing commencing signal of externally input, the output port C1 of control circuit is connected to the E port of high frequency timing margin computer, the output port C2 of control circuit is connected to the E port of low frequency timing margin computer, the output port C3 of control circuit is connected to the E port of timer 2, and output port C4 is connected to the E port of intervalometer 1；The E port of intervalometer 1 is accessed by the C4 of control circuit, and the CK port of intervalometer 1 is accessed by the C port in high frequency clock source, and the C port of intervalometer 1 exports the B port of high frequency timing comparator；The E port of timer 2 is accessed by the C3 port of control circuit, and the CK port of timer 2 is accessed by the C port in low-frequency clock source, and the C port of timer 2 exports the B port of tremendously high frequency timing margin computer and the B port of comparator 3；The E port of high frequency timing margin computer is accessed by the C1 port of control circuit, the A port of high frequency timing margin computer is accessed by the delay timing value signal of externally input, the B port of high frequency timing margin computer is accessed by the C port of timer 2, and the C port of high frequency timing margin computer exports the A port to comparator 1；The E port of low frequency timing margin computer is accessed by the C2 port of control circuit, the A port of low frequency timing margin computer is accessed by the delay timing value signal of externally input, the C1 port output of low frequency timing margin computer is to the A port of comparator 2, and the C2 port of low frequency timing margin computer exports the A port to comparator 3；The A port of comparator 1 is accessed by the C port of high frequency timing margin computer, and the B port of comparator 1 is accessed by the C port of intervalometer 1, and the C port of comparator 1 exports the A1 port to timing results decision circuit；The A port of comparator 2 is accessed by the C1 port of low frequency timing margin computer, and the B port of comparator 2 is accessed by the C port of low frequency intervalometer, the E port of the C port output tremendously high frequency clock source of comparator 2；The A port of comparator 3 is accessed by the C2 port of low frequency timing margin computer, and the B port of comparator 3 is accessed by the C port of low frequency intervalometer, the A2 port that the C port output of comparator 3 is adjudicated to timing results；The A1 port of timing results judgement is accessed by the C port of comparator 1, the A2 port of timing results judgement is accessed by the C port of comparator 2, the A3 port of timing results judgement is accessed by the C port of comparator 3, the C1 port output timing end signal of timing results judgement, the C2 port output error indication signal of timing results judgement。
The present embodiment medium-high frequency clock source circuit is realized with crystal oscillator PAD jointly by external quartz crystal, and wherein crystal oscillator PAD includes ena-bung function。High frequency clock source comprises enable and controls port E, output terminal of clock mouth C。When enabling control and being effective, clock status vibration produces high frequency clock signal；When enabling control and being invalid, high frequency clock source quits work, and fixes output high level or low level signal, is in low power consumpting state。High frequency clock source produces high frequency clock signal and is exported by output terminal of clock mouth C。
The present embodiment medium and low frequency clock source circuit is realized with crystal oscillator PAD jointly by external quartz crystal, does not have turn-off function。Low-frequency clock source comprises output terminal of clock mouth C。Low-frequency clock source produces low-frequency clock signal and is exported by output terminal of clock mouth C。
In the present embodiment, intervalometer 1 realizes high frequency timer function, and timer 2 realizes low frequency timer function。Intervalometer 1 and timer 2 have identical circuit structure, adopt general timer circuit to realize。Its input port comprises enable port E and input end of clock mouth CK, and output port includes count value port C。When enable port E is effective, each clock input port CK effective along time count value add 1, and by count value port C output；When enable port E is invalid, no matter whether clock input port CK has saltus step, and count value is reset to 0 all the time, and is exported by count value port C。
In the present embodiment, control circuit includes input port is clock status port A, and timing starts port S；Output port is intervalometer 1 enable port C4, timer 2 enable port C3, low frequency timing margin computer enable port C2 and high frequency timing margin computer enable port C1。Its behavior is when a dormancy timing cycle starts, and when namely timing commencing signal is effective, low frequency timing margin computer enables and produces an effective impulse signal。When a dormancy timing cycle starts, low frequency timing margin computer enable port produces effective impulse signal, and timer 2 enable port produces useful signal, intervalometer 1 enable port and low frequency intervalometer enable port output disarmed state。After high frequency clock source is working properly, high frequency timing margin computer enables signal and produces an effective impulse, is then set to effective status and the enable signal of low frequency intervalometer is set to disarmed state by the signal that enables of intervalometer 1 simultaneously。When timing commencing signal is invalid, all outputs enable signal and are disarmed state。
The input port of the low frequency timing margin computer in the present embodiment includes delay timing value port A and enable port E, and output port includes the first low frequency timing fiducial value port C1 and the second low frequency timing fiducial value port C2。Low frequency timing margin computer is calculated the first low frequency timing fiducial value and the second low frequency timing fiducial value when enable port E is effective, when enable port E lost efficacy, and the count value before maintenance。The calculating calculating the first low frequency timing fiducial value and the second low frequency timing fiducial value completes according to the formula in summary of the invention。
The effect of the high frequency timing margin computer in the present embodiment is to calculate high frequency timing fiducial value。The effect of high frequency timing fiducial value is to generate high-frequency ratio relatively matched signal。It is enable port E, delay timing value port A and low frequency timer count value port B that high frequency timing margin computer comprises input port, and output port is high frequency timing fiducial value port C。High frequency timing margin computer, when enable port E is effective, calculates high frequency timing fiducial value according to the value of delay timing value port A and low frequency count value port B, and by high frequency timing fiducial value port C output。Calculating of high frequency timing fiducial value completes to calculate according to the formula in summary of the invention。
Comparator 1 in the present embodiment, comparator 2, comparator 3 are completely identical in structure circuit, and comparator 1 completes high frequency timing comparator, and comparator 2 completes the first low frequency timing comparator, comparator 3 completes the second low frequency timing comparator。Comparator circuit comprises input port fiducial value 1 port A and fiducial value 2 port B, exports comparison match port C。Comparator circuit is made up of combination logic, when A port is equal with the value of B port, produces comparison match output。
Timing results decision circuit in the present embodiment is made up of combination logic。It is that high-frequency ratio relatively mates port A1, the first low frequency comparison match port A2 and the second low frequency comparison match A3 that timing results decision circuit includes input port, and output port terminates port C1 and mistake instruction port C2 for timing。The work behavior of timing results decision circuit be when high-frequency ratio relatively mate port A1 and the first low frequency comparison match port A2 simultaneously effectively time, produce timing end signal, but not generation error indication signal；When the first low frequency comparison match port A2 and the second low frequency comparison match A3 is simultaneously effective, produces timing timing end signal, be simultaneously generated error indication signal。Due to the effect of clock status indicating circuit, high frequency comparison match and low frequency timing instruction will not be produced in the same count cycle simultaneously, namely only produce a final timing and terminate batch bundle。Error indication signal indicates whether to produce accurate timing termination instruction, when error indication signal is effective, it was shown that timing termination instruction is likely to comprise certain error；When error indication signal is invalid, during table, timing termination instruction is accurate。
In the present embodiment, clock status indicating circuit adopts the following technical scheme that
A kind of clock status indicating circuit, including clock division circuits, edge correction circuit, edge sense circuit and shift-register circuit；Described clock division circuits is connected with edge correction circuit；Described edge correction circuit is connected with edge sense circuit, shift-register circuit；Described edge sense circuit is connected with shift-register circuit；
Described clock division circuits is for dividing reference clock, and output frequency division clock signal is to edge sense circuit；
Described edge sense circuit access clock to be measured, clock division circuits output sub-frequency clock signal and edge correction circuit output edge correction signal, sub-frequency clock signal carries out edge detection, and output cycle reset signal is to edge correction circuit and shift-register circuit；
Described edge correction circuit accesses reference clock and cycle reset signal is modified obtaining edge correction signal and exports to edge sense circuit；
Described shift-register circuit accesses high level, reference clock and cycle reset signal, carries out internal register displacement and reset operation, exports clock status signal。
Described clock division circuits includes not gate and depositor；Described non-gate output terminal is connected with the data terminal of depositor, and the outfan of depositor is as the output of clock division circuits, and the input of NAND gate connects；The clock of depositor terminates into reference clock。
Described edge sense circuit includes three depositors being sequentially connected with and an XOR gate；The clock end of described three depositors all accesses clock to be measured, reset terminal is all connected with the outfan of edge correction circuit, the the first register data end being sequentially connected with is as the input of edge sense circuit and is connected with the outfan of clock division circuits, 3rd depositor outfan is connected with the first input end of XOR gate, second depositor outfan is connected with the second input of XOR gate, and the outfan of XOR gate is as the output of edge sense circuit。
Described edge sense circuit include not gate and with door, the input of not gate accesses reference clock, and outfan is connected with the first input end with door, is connected with the outfan of edge sense circuit with the second input of door, and outfan is the output of edge sense circuit。
Described shift-register circuit includes multiple depositor being linked in sequence, the clock end of each depositor all accesses reference clock, reset terminal is all connected with the outfan of edge sense circuit, the data terminal of first depositor connects high level, and the outfan of last depositor is as the output of shift-register circuit。
A kind of clock status indicating means, comprises the following steps:
A. reference clock is carried out frequency dividing and obtains sub-frequency clock signal by clock division circuits；
B. sub-frequency clock signal is carried out edge detection and obtains cycle reset signal by edge sense circuit；
C. high level is transmitted by shift-register circuit step by step, and when clock to be measured is normal, internal depositor is resetted by cycle reset signal, and shift-register circuit output keeps low level；When clock exception to be measured, cycle reset dropout, shift-register circuit output keeps high level；
D. correction circuit in edge is when clock to be measured stopping and cycle reset abnormal signal, the reference clock negated and cycle reset signal is carried out and generates edge correction signal；
E. exported clock status signal by shift-register circuit, return step a。
Described edge detection is specially when producing edge, and the second depositor being sequentially connected with and the output of the 3rd depositor not etc., do not produce high level by XOR gate。
The described frequency dividing that carries out is for carrying out N-equal duty ratio frequency dividing。
In described shift-register circuit, the progression of depositor is more than N+1 level。
Clock status indicating circuit realizes especially by below scheme:
A kind of clock status indicating circuit, external input port includes reference clock signal, clock signal to be measured, output port include clock status signal。
The port function of clock status indicating circuit describes as follows: reference clock signal is to continuously generate, and provides the clock of reference for producing clock status signal, is generally low frequency clock, in actual applications, can adopt the low-frequency clocks such as 32KHz, 10KHz；Clock signal to be measured, for being clock signal under, refers generally to altofrequency clock, in specialty of the present invention, should be more than the 3 of reference clock frequency times；Clock status signal indicates clock signal to be measured whether normal operation, if normal operation, output low level signal, otherwise generates high level signal。
The functional module of clock status indicating circuit includes clock division circuits, edge correction circuit, edge sense circuit, shift-register circuit。
Module and the port connection relationship of clock status indicating circuit are as follows: the input clock port of described clock division circuits is inputted by reference clock signal, and output port is sub-frequency clock signal；The input clock port of edge sense circuit is inputted by clock signal to be measured, and input reseting port is inputted by the edge correction signal of edge sense circuit, and output port is cycle reset signal；The input clock port of edge correction circuit is inputted by reference clock signal, and input reseting port is inputted by the cycle reset signal of edge sense circuit, and output port is edge correction signal；The input clock port of shift-register circuit is inputted by reference clock signal, and input reseting port is inputted by the cycle reset signal of edge sense circuit, and output port is clock status signal。
In clock status indicating circuit, the function of clock division circuits is reference clock signal to carry out N-equal duty ratio frequency dividing obtain sub-frequency clock signal, and effective high level of this signal and low level length are NT/2。Wherein the span of N is 1 to infinity, when N value is 1, does not namely divide。If the dutycycle of reference clock signal meets or can value be 1 close to 1, N。
In clock status indicating circuit, edge sense circuit is under clock effect to be measured, and the sub-frequency clock signal that clock division circuits is generated carries out edge detection, extracts rising edge and trailing edge specifically, and the generation cycle is the cycle reset signal of NT。
In clock status indicating circuit, the effect of edge correction circuit is cycle reset signal and reference clock signal that edge sense circuit is produced, by combinational logic circuit, produces edge correction signal。
In clock status indicating circuit, shift-register circuit comprises N+1 level Parasites Fauna, under cycle reset signal and reference clock effect, carries out resetting and the operation such as displacement, generates clock status signal。
The principles illustrated of clock status indicating circuit is as follows。
Note reference clock signal frequency is F, and frequency is T。By the relation of frequency and clock, can obtaining the product of F and T equal to 1, namely F is equal to 1/T。
Reference clock signal carrying out N-equal duty ratio frequency dividing and can obtain effective high level and low level length is NT/2, the cycle is the frequency-dividing clock of NT；When clock to be measured is effective, can generate the cycle with frequency-dividing clock is NT cycle reset signal；In the N+1 level shift register group that high level input, reference clock drive, effect due to cycle reset signal that the cycle is NT, shift-register circuit resetted with NT for the cycle, high level is made to be merely able to be delivered to the N level depositor of shift register, being not transferred to the N+1 level of shift-register circuit, namely clock status signal remains low level；When disabling clock signals to be measured, edge sense circuit cannot generate cycle reset signal, and the N+1 level depositor in shift-register circuit finally produces high level instruction。
Due to the uncertainty of clock to be measured, under certain conditions, it is possible to create abnormal cycle reset signal, now shift-register circuit can be produced the impact of mistake, produce the clock status result of mistake。For the correction of this result can pass through cycle reset signal and reverse reference clock by with gate logic, produce edge correction signal。Correction signal in edge can revise abnormal cycle reset signal, and finally produces correct clock status signal。
When adopt N-equal duty ratio frequency dividing time, the progression of shift register be N+1 or more than, original normal circuit operation can be protected。
The method step of clock status indicating circuit is:
Reference clock signal is carried out N-equal duty ratio frequency dividing by clock division circuits, and to obtain the cycle be NT sub-frequency clock signal；
The sub-frequency clock signal that clock division circuits is generated by edge sense circuit carries out edge detection, and the generation cycle is the cycle reset signal of NT；
High level is transmitted by shift-register circuit step by step, and when clock to be measured is normal, internal depositor is resetted by cycle reset signal, and shift-register circuit output keeps low level；When clock exception to be measured, cycle reset dropout, shift-register circuit output keeps high level。
Correction circuit in edge, when abnormal cycle reset signal being detected, generates edge correction signal；Edge sense circuit, under edge correction signal function, carries out logic circuit process, revises abnormal cycle reset signal。
Shift-register circuit, according to cycle reset signal and reference clock signal, produces clock status signal
Embodiment:
The present embodiment is a kind of mode realizing clock status indicating circuit described in this patent, have employed relatively simple circuit structure, wherein the N value in clock division circuits is 2, namely adopts the duty frequency dividings such as 2-, and shift register adopts 3 bit register shift-register circuits。
Specific embodiment refers to shown in Fig. 4, a kind of clock status indicating circuit, and structure includes clock division circuits, edge sense circuit, edge correction circuit and shift-register circuit；Outside port includes output port reference clock and clock to be measured, output port clock status。
Concrete annexation is, reference clock signal is connected to the clock port CK of clock division circuits, and the output terminal of clock mouth Q of clock division circuits produces sub-frequency clock signal C1；Clock signal to be measured is connected to the clock port CK of edge sense circuit, clock division circuits produces sub-frequency clock signal C1 and is connected to the FPDP D of edge sense circuit, correction circuit in edge produces edge correction signal F1 and is connected to the reset terminal of edge sense circuit, and the output port Q of edge sense circuit generates set signal R1；
The input clock port CK of edge correction circuit is inputted by reference clock signal, and input reseting port R is inputted by the cycle reset signal R1 of edge sense circuit, and output port is edge correction signal F1, exports the reseting port R to edge sense circuit；
The cycle reset signal R1 that edge sense circuit generates is connected to the reseting port R of shift-register circuit, reference clock signal is connected to the clock port CK of shift-register circuit, the FPDP D of shift-register circuit connects high level signal, and shift-register circuit output Q produces clock status signal。
The present embodiment adopts 2 frequency-dividing clock frequency dividing circuits, as shown in Figure 5。This frequency dividing circuit includes depositor 1 and not gate 1。The input end of clock mouth CK that its annexation is depositor 1 is inputted by the portion input port CK of clock division circuits, the data-in port D of depositor 1 is inputted by the output port Q of not gate 1, the output port Q of depositor 1 exports the input port A of not gate 1, and the output port Q of depositor 1 exports the output port Q of clock division circuits；The input port A of not gate 1 is inputted by the output port Q of depositor 1, and the output port Q of not gate 1 exports the input port D of depositor 1。
In the present embodiment, edge sense circuit structure is as shown in Figure 6。This edge sense circuit comprises depositor 2, depositor 3, depositor 4 and XOR gate 1 and forms。The input port D that its annexation is depositor 2 is inputted by edge sense circuit externally input CK, and the input port CK of depositor 2 is inputted by edge sense circuit externally input CK, and the output port Q of depositor 2 exports the input port D of depositor 3；The input port CK of depositor 3 is inputted by edge sense circuit externally input CK, and the input port D of depositor 2 is inputted by the output port Q of depositor 2, and the output port Q of depositor 3 exports the input port D of depositor 4 and the input port B of XOR gate 1；The input port CK of depositor 4 is inputted by edge sense circuit externally input CK, and the input port D of depositor 4 is inputted by the output port Q of depositor 3, and the output port Q of depositor 4 exports the input port A of XOR gate 1；The input port A of XOR gate 1 is inputted by the output port Q of depositor 4, and the output port B of XOR gate 1 is inputted by the output port Q of depositor 3, and the output port Q of XOR gate 1 exports the external output port Q of edge sense circuit。
In the present embodiment, edge correction circuit structure is as shown in Figure 7。This edge correction circuit comprises not gate 1 and forms with door 1。The input port A that its annexation is not gate 1 is inputted by the outside port CK of edge correction circuit, and the output port Q of not gate 1 is connected to the input port A with door 1；Accessed by the output port Q of not gate 1 with the input port A of door 1, accessed by the outside port R of edge correction circuit with the input port B of door 1, with the outside port Q that the output port Q of door 1 exports edge correction circuit。
In the present embodiment, shift-register circuit structure is as shown in Figure 8。This shift-register circuit comprises depositor 5, depositor 6 and depositor 7 and forms。The input port D that its annexation is depositor 5 is inputted by high level signal, and the input port CK of depositor 5 is inputted by shift-register circuit external input port CK, and the output port Q of depositor 2 exports the input port D of depositor 6；The input port CK of depositor 6 is inputted by shift-register circuit external input port CK, and the input port D of depositor 6 is inputted by the output port Q of depositor 5, and the output port Q of depositor 6 exports the input port D of depositor 7；The input port CK of depositor 7 is inputted by shift-register circuit external input port CK, and the input port D of depositor 7 is inputted by the output port Q of depositor 6, and the output port Q of depositor 7 exports shift-register circuit external output port Q。
The present embodiment only enumerates a kind of embodiment of this circuit, and other implementation can adopt Fractional-N frequency (N is even number) clock division circuits, corresponding employing N+1 or higher level shift-register circuit。If the set signal R1 effective width of edge detection circuit evolving is less than normal, the realization of more trigger can be inserted between depositor 3 and the depositor 4 in edge detection circuit。
Claims (10)
1. the accurate doze output circuit of low-power consumption, it is characterised in that: include high frequency clock source, low-frequency clock source, clock status indicating circuit, control circuit, intervalometer, high frequency timing margin computer, low frequency timing margin computer, comparator, timing results decision device；
Described high frequency clock source exports the clock end to be measured of the high frequency clock clock end to first timer and clock status indicating circuit, first timer outfan and first comparator the second input and connects；The reference clock end of the low-frequency clock source output low frequency clock clock end to second timer and clock clock status indicating circuit；
The output clock status signal of described clock status indicating circuit is to control circuit, and first input end accesses high frequency clock, the second input accesses low-frequency clock；
The first input end of described control circuit accesses timing commencing signal, the second input incoming clock status signal, four outfans respectively with high frequency timing margin computer, low frequency timing margin computer, first timer, second timer Enable Pin be connected；
The first input end of described high frequency timing margin computer, low frequency timing margin computer the equal access delay timing value of input；Second timer outfan and high frequency timing margin computer the second input, second comparator the second input, the 3rd comparator the second input be connected；High frequency timing margin computer outfan and the first comparator first input end connect；Two outfans of low frequency timing margin computer are connected with the first input end of the second comparator first input end, the 3rd comparator respectively；
First comparator, the second comparator, the 3rd comparator outfan be connected with three inputs of timing results decision device respectively, timing results decision device output timing end signal and error indication signal；The outfan of the second comparator is also connected with the input in high frequency clock source。
2. a kind of accurate doze output circuit of low-power consumption according to claim 1, it is characterised in that described clock status indicating circuit includes: include clock division circuits, edge correction circuit, edge sense circuit and shift-register circuit；Described clock division circuits is connected with edge correction circuit；Described edge correction circuit is connected with edge sense circuit, shift-register circuit；Described edge sense circuit is connected with shift-register circuit；
Described clock division circuits is for dividing reference clock, and output frequency division clock signal is to edge sense circuit；
Described edge sense circuit access clock to be measured, clock division circuits output sub-frequency clock signal and edge correction circuit output edge correction signal, sub-frequency clock signal carries out edge detection, and output cycle reset signal is to edge correction circuit and shift-register circuit；
Described edge correction circuit accesses reference clock and cycle reset signal is modified obtaining edge correction signal and exports to edge sense circuit；
Described shift-register circuit accesses high level, reference clock and cycle reset signal, carries out internal register displacement and reset operation, exports clock status signal。
3. the accurate dormancy timing method of low-power consumption, it is characterised in that comprise the following steps:
Timing starts, and control circuit produces low frequency calculating enable output tremendously low frequency timing margin computer, low frequency timing enables and exports to second timer；Delay timing value is calculated obtaining two low frequency timing fiducial values by low frequency timing margin computer, and second timer starts counting up；
When the first low frequency timing fiducial value of low frequency timing margin computer output and the count value of the second enumerator are equal, generate the first low frequency comparison match signal, start high frequency clock source simultaneously；When high frequency clock source works, clock status indicating circuit generates clock status signal and exports to control circuit；Control circuit generates high frequency calculating enable output tremendously high frequency timing margin computer, high frequency timing enables and exports to first timer, simultaneously closes off low frequency and regularly enables, and second timer stops counting；
The current count value of delay timing value and second timer is calculated by high frequency timing margin computer, obtains high frequency timing fiducial value, and first timer starts counting up；When the high frequency timing fiducial value of high frequency timing margin computer output and the count value of first timer are equal, generate high-frequency ratio relatively matched signal；
Timing results decision device exports timing end signal according to the comparative result of the first comparator and the second comparator。
4. a kind of accurate dormancy timing method of low-power consumption according to claim 3, it is characterised in that after described first low frequency comparison match signal enabling high frequency clock source, when high frequency clock source exception, keeps low frequency timing to enable, and second timer continues counting；When count value is equal with the second low frequency timing fiducial value, generate the second low frequency comparison match signal；
Timing results decision device exports timing end signal and error indication signal according to the comparative result of the second comparator and the 3rd comparator。
5. a kind of accurate dormancy timing method of low-power consumption according to claim 3, it is characterised in that delay timing value is calculated being realized by below equation by described low frequency timing margin computer:
First low frequency timing fiducial value=(delay timing value-high frequency clock source wakeup time-high frequency timer count time)/low-frequency clock source clock cycle；
Wherein, high frequency clock source wakeup time, high frequency timer count time, low-frequency clock source clock cycle are setting value。
6. a kind of accurate dormancy timing method of low-power consumption according to claim 3, it is characterised in that delay timing value is calculated realizing also by below equation by described low frequency timing margin computer
Second low frequency timing fiducial value=delay timing value/low-frequency clock source clock cycle；
Wherein, the low-frequency clock source clock cycle is setting value。
7. a kind of accurate dormancy timing method of low-power consumption according to claim 3, it is characterised in that the described current count value to delay timing value and second timer is calculated being realized by below equation:
High frequency timing fiducial value=(delay timing value-second timer current count value-phase pushing figure)/high frequency clock source clock cycle；
Wherein, phase pushing figure, high frequency clock source clock cycle are setting value。8. a kind of accurate dormancy timing method of low-power consumption according to claim 3, it is characterized in that the described comparative result according to the first comparator and the second comparator exports timing end signal particularly as follows: when the output result of the first comparator and the second comparator is all equal, exports timing end signal and do not produce error indication signal。
8. a kind of accurate dormancy timing method of low-power consumption according to claim 3, it is characterized in that the described comparative result according to the first comparator and the second comparator exports timing end signal particularly as follows: when the output result of the first comparator and the second comparator is all equal, exports timing end signal and do not produce error indication signal。
9. a kind of accurate dormancy timing method of low-power consumption according to claim 4, it is characterized in that the described comparative result according to the second comparator and the 3rd comparator exports timing end signal and error indication signal particularly as follows: when the output result of the second comparator and the 3rd comparator is all equal, exports timing end signal and produce error indication signal。
10. a kind of accurate dormancy timing method of low-power consumption according to claim 3, it is characterised in that described clock status indicating circuit generates clock status signal and comprises the following steps:
A. reference clock is carried out frequency dividing and obtains sub-frequency clock signal by clock division circuits；
B. sub-frequency clock signal is carried out edge detection and obtains cycle reset signal by edge sense circuit；
C. high level is transmitted by shift-register circuit step by step, and when clock to be measured is normal, internal depositor is resetted by cycle reset signal, and shift-register circuit output keeps low level；When clock exception to be measured, cycle reset dropout, shift-register circuit output keeps high level；
D. correction circuit in edge is when clock to be measured stopping and cycle reset abnormal signal, the reference clock negated and cycle reset signal is carried out and generates edge correction signal；
E. exported clock status signal by shift-register circuit, return step a。
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