CN106227293A - A kind of system clock - Google Patents
A kind of system clock Download PDFInfo
- Publication number
- CN106227293A CN106227293A CN201610585645.5A CN201610585645A CN106227293A CN 106227293 A CN106227293 A CN 106227293A CN 201610585645 A CN201610585645 A CN 201610585645A CN 106227293 A CN106227293 A CN 106227293A
- Authority
- CN
- China
- Prior art keywords
- timer
- count value
- frequency
- value
- system clock
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/08—Clock generators with changeable or programmable clock frequency
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/324—Power saving characterised by the action undertaken by lowering clock frequency
Abstract
The present invention relates to integrated circuit fields, disclose a kind of system clock.In the present invention, a kind of system clock, including: first timer and second timer, the precision of first timer is higher than second timer；Second timer keeping count, second timer institute count value is the first count value；First timer counts when system is in communications status, and first timer institute count value is the second count value；Wherein, second timer, when the first count value reaches predetermined value, wakes up system up；The first current count value, when system is waken up, according to frequency and the frequency of second timer of first timer, is converted to the first conversion value by first timer；And using the first conversion value as the second current count value, continue counting.Embodiment of the present invention achieves the raising of clock accuracy, limits system power dissipation simultaneously, reduces cost.
Description
Technical field
The present invention relates to integrated circuit fields, particularly to a kind of system clock.
Background technology
We refer to clock system by usually said system clock, and it is by agitator, timing wake-up device, frequency divider etc.
Composition.System clock is the pulse of a system, processor under the driving of system clock, completion system perform instruction, outward
If parts are under the driving of system clock, complete data and send, receive, the work such as analogue signal and digital signal conversion, therefore,
System clock normal operation can play vital effect for a system.
In radio network technique field, the application of low-power consumption bluetooth or zigbee, the communication node of system can be carried out
Twice communication, first under the pattern of low-power consumption, system enters sleep state, then wakes up at an identical time point, enters
Row communicates again, and the most each communication node has a system clock to obtain the time.
Agitator relatively common in system clock in prior art is crystal oscillator, is called for short " crystal oscillator ", and typically
Only one of which low precision 32K crystal oscillator carrys out timing as intervalometer, but the timing accuracy of the crystal oscillator of 32K is 33us, timing accuracy
Poor.Therefore, system needs a high-precision intervalometer to replace low precision 32K crystal oscillator intervalometer, but this may result in and is
Under system duty, power consumption is excessive, thus cisco unity malfunction.
Further, since crystal oscillator is an external devices, relatively costly.
Summary of the invention
The purpose of embodiment of the present invention is to provide a kind of system clock so that the precision of system clock is carried significantly
Height, limits the power consumption of system simultaneously, reduces cost.
For solving above-mentioned technical problem, embodiments of the present invention provide a kind of system clock, including: first timer
And second timer, the precision of first timer is higher than second timer；
Second timer keeping count, second timer institute count value is the first count value；First timer is at system
Counting when communications status, first timer institute count value is the second count value；
Wherein, second timer, when the first count value reaches predetermined value, wakes up system up；
First timer is when system is waken up, according to frequency and the frequency of second timer of first timer, and ought
The first front count value is converted to the first conversion value；And using the first conversion value as the second current count value, continue counting.
In terms of existing technologies, service precision is higher than the first timer of second timer to embodiment of the present invention,
Effectively raise the precision of system clock, first timer timing under system is in communications status, and utilize second to determine
Time device institute count value conversion value so that in the case of first timer is the most idle, it is also possible to obtain and wake up up
The current count value of rear system, thus improve the precision of system clock, and maintain the low-power consumption of system clock.Additionally, by
Count value in first timer keeps continuous on a timeline, calling of software of being more convenient for.
It addition, enumerator, for obtaining the frequency ratio of first timer and second timer；It is additionally operable to calculate first fixed
Time device upper once system is waken up time the second count value；Processor, for when system enters sleep state, utilizing high-precision
Spend the second count value and frequency ratio that counter counts calculates, calculate predetermined value.Further define second timer to exist
The method being calibrated when first timer does not works so that while keeping low-power consumption, improves the precision of system clock.
It addition, enumerator is for when system is in communications status, it is thus achieved that first timer and the frequency of second timer
Ratio.Limit the acquisition methods of frequency ratio further so that frequency ratio more meets actual value.
It addition, the count value that enumerator is in utilizing scheduled duration, it is thus achieved that first timer and the frequency of second timer
Rate ratio.Limit the acquisition methods of frequency ratio further so that the acquisition of frequency ratio more fast and flexible.
It addition, enumerator is when system is in sleep state, stop counting.Thus save power consumption further.
It addition, second timer is at predetermined instant, according to frequency and the frequency of second timer of first timer, ought
Front second count value is converted to the second conversion value, and using the second conversion value as the first current count value, continues counting.Enter one
Step limits the calibration steps of second timer so that system clock accuracy is higher.
Accompanying drawing explanation
Fig. 1 is the working-flow figure of a kind of system clock according to first embodiment of the invention；
Fig. 2 is the structural representation of a kind of system clock according to first embodiment of the invention；
Fig. 3 is the structural representation of a kind of system clock according to fifth embodiment of the invention.
Detailed description of the invention
For making the object, technical solutions and advantages of the present invention clearer, below in conjunction with the accompanying drawing each reality to the present invention
The mode of executing is explained in detail.But, it will be understood by those skilled in the art that in each embodiment of the present invention,
In order to make reader be more fully understood that, the application proposes many ins and outs.But, even if there is no these ins and outs and base
Many variations and amendment in following embodiment, it is also possible to realize the application technical scheme required for protection.
First embodiment of the present invention relates to a kind of system clock.This system clock includes: first timer and second
Intervalometer, the precision of first timer is higher than second timer.Wherein, second timer keeping count, second timer is counted
Numerical value is the first count value；First timer counts when system is in communications status, and first timer institute count value is second
Count value；Wherein, second timer, when the first count value reaches predetermined value, wakes up system up；First timer is at system quilt
When waking up up, according to frequency and the frequency of second timer of first timer, the first current count value is converted to first turn
Change value；And using the first conversion value as the second current count value, continue counting.
Each mode of operation of native system clock is described below with Fig. 1:
Step 101: judge whether system is in communications status.
Specifically, it is judged that whether the system of system clock is in communications status, if it is judged that be yes, then step is entered
In rapid 103, otherwise enter in step 102.
It is noted that second timer is low precision intervalometer, it is possible to use 32KHz intervalometer realizes, RC vibrates
Device is chip internal device, and cost is relatively low.And first timer is high-resolution timer, its frequency can be more than or equal to
8MHz.High-precision timer signal can obtain from pll clock frequency dividing, and the source of PLL is that high-frequency crystal oscillator frequency multiplication obtains,
General high-frequency crystal oscillator is all greater than 10MHz, and uses the crystal oscillator of 16MHz in present embodiment.
System can be according to the count value of system clock, every certain time length, outwardly sends signal.If system clock
System is in communications status, then enter step 103, otherwise, enter in step 102, continue executing with next step.
Step 102: obtain the first count value.
Specifically, in system, second timer keeping count, second timer institute count value is the first count value,
When system is not in communications status, owing to second timer is in communication or not under concentric in system, all can persistently count
Number, therefore, first obtains the first count value of second timer.
Step 103: judge whether system will enter sleep state.
Specifically: if system will enter sleep state, then enter in step 104, otherwise, repeat this behaviour
Make.Under system is in communications status, works a period of time, complete after needing operation to be performed, or system is in communication
Under state, free time length is more than a default duration, such as 5 seconds, then can be transmitted into the instruction of sleep, and system is receiving
To when entering SLEEP instruction, it is judged that system is for will enter sleep state, and otherwise, whether duplicate detection system is sleep to be entered
State.
Step 104: obtain first timer and the frequency ratio of second timer.
Specifically, when system is in communications status, it is thus achieved that first timer and the frequency ratio of second timer, permissible
The frequency values obtained is made to more conform to actual value.Such as, in a communication state, the frequency values of first timer is system
32MHz, the frequency values of second timer is 32KHz, then the frequency ratio of first timer and second timer is 1000.
Step 105: calculate first timer upper once system is waken up time the second count value.
Specifically, first timer counts when system is in communications status, and first timer institute count value is second
Count value, say, that first timer, when system is in and does not communicates, also can be in idle state, be in system
During communications status, can calculate first timer upper once system is waken up time the second count value, namely first is fixed
Time the device counter starting value when next time starts working.
In particular, the time point that system is waken up next time is preset according to communication standard, such as the first time
System is to work at 10s, communicates, and second time is to work at 20s, communicates, and third time is to work at 30s, leads to
Letter, by that analogy.
It should be noted that step 104 and step 105 do not have strict logical order, step 104 and step 105 to perform
The priority of order, will not cause any impact to the result of present embodiment, although present embodiment first carries out in step 104
Content, then perform the content in step 105, vice versa.Further, step 104 and step 105 enter sleep state in system
Moment performs.
Step 106: calculate predetermined value.
Specifically, predetermined value is according to the first timer got in step 104 and described second timer
The first timer calculated in frequency ratio, and step 105 upper once system is waken up time the second count value, calculate
Draw.
Such as, in step 104, it is thus achieved that first timer and the frequency ratio of second timer be 1000, step 105
In, the first timer gone out of calculating upper once system is waken up time the second count value be 100, then going out of can calculating is pre-
Fixed number value is 100000.
Step 107: system enters sleep state.
Specifically, at first timer after one section of duration, system enters sleep state, first in this condition
Intervalometer is in off position, and now, second timer is in running order.After entering dormant system, enter step
In rapid 102, obtain the first count value.
Step 108: judge whether the first count value reaches default value.
Specifically, in step 106, it is in communications status in system, when i.e. first timer is in running order, calculates
Drawing predetermined value, be in sleep state in system, namely first timer is in non-duty, and second timer continues
Work, when the first count value got is equal to predetermined value, enters in step 109, otherwise, enters in step 102, again
Obtain the first count value, and carry out again the judgement in 108 steps, until judged result is yes, enter next step.
It is noted that owing to system clock is waken up at Preset Time, so default value is also required to continue
Arranging, as predetermined system clock 10s, 20s after the power-up wake up, then during 5s sleep, default value is provided that corresponding 10s
Numerical value, system, when 15s sleeps, is provided that the numerical value of corresponding 20s, by that analogy.
Step 109: wake up system up.
If the first count value of second timer is equal with default value, then wake up system, after waking up up, first timer up
Duty is transferred to by off position.
Step 110: obtain current first count value.
Specifically, during step 109 wakes up system up, second timer keeping count, after waking up system up, obtains
Take the first count value that second timer is current.
Step 111: current first count value is converted to the first conversion value.
Specifically, first timer is when system is waken up, according to the frequency of first timer and second timer
Frequency, is converted to the first conversion value by the first current count value.Wherein, the frequency of first timer and the frequency of second timer
Rate can be obtained by system.
Such as, for first timer that frequency is 32MHz and the second timer of 32KHz, the frequency of its first timer
The frequency ratio of rate and second timer is 1000.If by the first counting of the current second timer that step 110 gets
Value is 100000, and according to the two numerical value obtained before, can calculate the first conversion value is 100.
Step 112: using the first conversion value as current second count.
Specifically, first timer is transferred to duty by off position, now the second counting of first timer
Value for entering the count value before off position, the first conversion value calculated according to second timer in step 111, by this
One conversion value is as current second count value, and continues counting.Now, system already at communications status, then enters step
In 103, it is judged that whether system has performed existing operation, is prepared to enter into sleep state.
Visible, although second timer does not works at sleep state, but after being waken up, still can be with current point in time
Due count value continues counting so that whether second timer counting continuously, is not slept by system and affected.
It should be noted that step 110 to 112 be waken up for system time operation, perform after step 112, the first timing
Device and second timer normally count.
Below with first timer for 32MHz intervalometer, as a example by second timer is 32KHz intervalometer, to this embodiment party
Formula is described briefly, and its structural representation is as shown in Figure 2.
System clock 21 includes: high-precision enumerator 211,32MHz timer 2 12,32KHz timer 2 13, synchronization module
214, control circuit 215, calibration module 216 and arithmetical unit 217.
High-precision enumerator 211, for obtaining the frequency ratio of 32MHz timer 2 12 and 32KHz timer 2 13, is additionally operable to
Calculate 32MHz timer 2 12 upper once system is waken up time the second count value, calibration module 216 by obtain high-precision meter
The count value of number device 211, carries out the calibration between 32MHz timer 2 12 and 32KHz timer 2 13, at high-precision enumerator 211
Carrying out counting and in calibration process with calibration module 216, arithmetical unit 217 carries out product plus and minus calculation.
The information such as 32KHz timer 2 13 and 32MHz timer 2 12 carry out counting, frequency mutual, 32KHz intervalometer
213 carry out the synchronized update of count value with synchronization module 214, and synchronization module 214 is by the 32KHz timer 2 13 of synchronization gain
The synchronizing information such as count value, frequency is in 32MHz timer 2 12.
Control circuit 215 is the central control system of system clock 21, can control 32KHz timer 2 13 fixed with 32MHz
Time device 212 duty, it is also possible to control synchronization module 214 synchronized update progress etc..
It is noted that in actual applications, second timer can use the intervalometer of 32bit, when intervalometer meter
Count to reach meeting Automatic Cycle after the upper limit, be equivalent to give up carry.
In terms of existing technologies, the main distinction and effect are present embodiment: service precision is higher than the second timing
The first timer of device, effectively raises the precision of system clock, first timer timing under system is in communications status,
And utilize the conversion value of second timer institute count value so that in the case of first timer is the most idle,
The current count value waking up rear system up can also be obtained, thus improve the precision of system clock, and maintain system clock
Low-power consumption.It addition, utilize RC agitator to realize low essence intervalometer, eliminate and prior art needs realize used by low essence intervalometer
Crystal oscillator, reduce external devices, reduce cost.Additionally, in present embodiment, although first timer is in sleep state not work
Make, but after being waken up, still can obtain the count value of current point in time, keep continuous counter on a timeline, software of being more convenient for
Call.
Second embodiment of the invention relates to a kind of system clock, and the second embodiment is that the first embodiment is the most excellent
Change, be in place of main optimization: in second embodiment of the invention, set up an enumerator, in utilizing scheduled duration
Count value, it is thus achieved that first timer and the frequency ratio of second timer.So that the acquisition of frequency ratio more quickly spirit
Live.
Specifically, scheduled duration can be a duration of user setup, and this duration is used for calculating the first timing
Device and the frequency ratio of second timer, wherein, the size of the frequency ratio of first timer and second timer, not by pre-
If the impact of duration value, therefore, preset duration can be obtained first timer and second timer by user setup one is convenient
The value of frequency.
It addition, in actual applications, preset duration can be set as several cycles of second timer, such as 16 week
Phase, namely utilizing counter records when second timer 16 cycles of work, the count value of first timer is how many.
Such as, preset duration is set to 1 second, and in this preset duration, the first timer count value got is 8, the
Two timer count values are 7000, then calculate first timer and the ratio of second timer frequency, and can obtain this ratio is
875.The frequency ratio then got may be used for further calculating.
In terms of existing technologies, the main distinction and effect are present embodiment: provide a kind of acquisition first fixed
Time device and the method for second timer frequency ratio, owing to the precision of second timer is relatively low, frequency in practice may not
Stable, theoretic frequency value and may be not equal to sometime, so utilizing newly-increased enumerator just to it will be seen that actual frequency
Ratio, can make the acquisition more fast and flexible of frequency ratio.
Third embodiment of the present invention relates to a kind of system clock.3rd embodiment is that the first embodiment is further
Optimizing, be: in place of main optimization in third embodiment of the invention, enumerator, when system is in sleep state, stops
Counting.Thus further reduce system clock power consumption.
Specifically, enumerator, when system is in sleep state, stops counting, when system is in running order, just
Often counting.When system is waken up, enumerator can obtain the first timer under system communication status and second timer
Frequency ratio, it is also possible to calculate the second count value when first timer is waken up next time.During due to sleep state, enumerator
Count value is not used, so stopping counting also not interfering with system clock function, it is also possible to further reduce system clock
Power consumption.
Four embodiment of the invention relates to a kind of system clock, and the 4th embodiment is that the first embodiment is the most excellent
Changing, be: in place of main optimization in four embodiment of the invention, second timer is at predetermined instant, according to the first timing
The frequency of device and the frequency of second timer, be converted to current second count value the second conversion value, and make with the second conversion value
For the first current count value, continue counting.So that the precision of system clock is higher.
Specifically, predetermined instant is that entrance system enters the dormant moment, i.e. first timer entrance does not works
In the moment of state, now, the second timer frequency according to first timer and the frequency of second timer, by current second meter
Numerical value is converted to the second conversion value, and using the second conversion value as the first current count value, continues counting.
Such as, first timer frequency is 32MHz, and the frequency of second timer is 32KHz, enters not at first timer
In the moment of duty, the second count value obtaining current first timer is 10, now the first count value of second timer
May be 9900, the ratio of first timer frequency and second timer frequency by obtaining, i.e. 1000, in conjunction with current first
Second count value of intervalometer calculates further, and obtaining the second conversion value is 10000, replaces current with the second conversion value obtained
The first count value, the first count value of i.e. current second timer replaces with 10000, and second timer continues with this value
Count.Then, first timer enters off position, and second timer works on, owing to second timer is the
Before one intervalometer enters off position, being calibrated, therefore, second timer is in terms of the second conversion value obtained is carried out
Number, it is more accurate to count.
In terms of existing technologies, the main distinction and effect are present embodiment: define the school of second timer
Quasi-method, so that the precision of system clock is higher.
The step of the most various methods divides, and is intended merely to describe clear, it is achieved time can merge into a step or
Some step is split, is decomposed into multiple step, as long as comprising identical logical relation, all at the protection domain of this patent
In；To adding inessential amendment in algorithm or in flow process or introducing inessential design, but do not change its algorithm
With the core design of flow process all in the protection domain of this patent.
Fifth embodiment of the invention relates to a kind of system clock, as it is shown on figure 3, include: first timer 31, second is fixed
Time device 32, wherein, also include: enumerator 33 and processor 34.
Wherein, the precision of first timer 31 is higher than second timer 32, and the frequency of first timer 31 can be more than
Or equal to 32MHz, second timer 32 can be the RC agitator of 32KHz.
Second timer 32 keeping count, 32 count values of second timer are the first count value；First timer 31 exists
Counting when system is in communications status, 31 count values of first timer are the second count value.
Second timer 32, when the first count value reaches predetermined value, wakes up system up.
First timer 31 is when system is waken up, according to frequency and the frequency of second timer 32 of first timer 31
Rate, is converted to the first conversion value by the first current count value；And using the first conversion value as the second current count value, continue
Counting.
Enumerator 33 is for obtaining first timer 31 and the frequency ratio of second timer 32；It is additionally operable to calculate first fixed
Time device 31 upper once system is waken up time the second count value.
Processor 34 for when system enters sleep state, utilizes the second count value and frequency that enumerator 33 calculates
Ratio, calculates predetermined value.
Enumerator 33 is additionally operable to when system is in communications status, it is thus achieved that first timer 31 and the frequency of second timer 32
Rate ratio.
In terms of existing technologies, the main distinction and effect are present embodiment: service precision is higher than the second timing
The first timer of device, effectively raises the precision of system clock, first timer timing under system is in communications status,
And utilize the conversion value of second timer institute count value so that in the case of first timer is the most idle,
The current count value waking up rear system up can also be obtained, thus improve the precision of system clock, and maintain system clock
Low-power consumption.
It is seen that, present embodiment is the system embodiment corresponding with the first embodiment, and present embodiment can be with
First embodiment is worked in coordination enforcement.The relevant technical details mentioned in first embodiment the most still has
Effect, in order to reduce repetition, repeats no more here.Correspondingly, the relevant technical details mentioned in present embodiment is also applicable in
In first embodiment.
It is noted that each module involved in present embodiment is logic module, in actual applications, one
Individual logical block can be a physical location, it is also possible to be a part for a physical location, it is also possible to multiple physics lists
The combination of unit realizes.Additionally, for the innovative part highlighting the present invention, will be with solution institute of the present invention in present embodiment
The unit that the technical problem relation of proposition is the closest introduces, but this is not intended that in present embodiment the list that there is not other
Unit.
It will be appreciated by those skilled in the art that all or part of step realizing in above-described embodiment method can be by
Program instructs relevant hardware and completes, and this program is stored in a storage medium, including some instructions with so that one
Individual equipment (can be single-chip microcomputer, chip etc.) or processor (processor) perform method described in each embodiment of the application
All or part of step.And aforesaid storage medium includes: USB flash disk, portable hard drive, read only memory (ROM, Read-Only
Memory), random access memory (RAM, Random Access Memory), magnetic disc or CD etc. are various can store journey
The medium of sequence code.
It will be understood by those skilled in the art that the respective embodiments described above are to realize the specific embodiment of the present invention,
And in actual applications, can to it, various changes can be made in the form and details, without departing from the spirit and scope of the present invention.
Claims (10)
1. a system clock, it is characterised in that including: first timer and second timer, the essence of described first timer
Degree is higher than described second timer；
Described second timer keeping count, described second timer institute count value is the first count value；Described first timer
Counting when described system is in communications status, described first timer institute count value is the second count value；
Wherein, described second timer, when described first count value reaches predetermined value, wakes up described system up；
Described first timer is when described system is waken up, according to frequency and the described second timer of described first timer
Frequency, current described first count value is converted to the first conversion value；And using described first conversion value as current
Two count values, continue counting.
System clock the most according to claim 1, it is characterised in that also include:
Enumerator, for obtaining described first timer and the frequency ratio of described second timer；It is additionally operable to calculate described
One intervalometer upper once system is waken up time the second count value；
Processor, for when described system enters sleep state, utilizes the second counting that described high-resolution counter calculates
Value and described frequency ratio, calculate described predetermined value.
System clock the most according to claim 2, it is characterised in that described enumerator is for being in communication in described system
During state, it is thus achieved that described first timer and the frequency ratio of described second timer.
System clock the most according to claim 2, it is characterised in that described enumerator in utilizing scheduled duration based on
Numerical value, it is thus achieved that described first timer and the frequency ratio of described second timer.
System clock the most according to claim 2, it is characterised in that described enumerator is in sleep state in described system
Time, stop counting.
System clock the most according to claim 1, it is characterised in that described second timer is at predetermined instant, according to institute
State frequency and the frequency of described second timer of first timer, presently described second count value is converted to the second conversion
Value, and using described second conversion value as the first current count value, continue counting.
System clock the most according to claim 6, it is characterised in that when described predetermined instant is for entering dormant
Carve.
System clock the most as claimed in any of claims 1 to 7, it is characterised in that described second timer utilizes
RC agitator realizes.
System clock the most according to claim 8, it is characterised in that the frequency of described RC agitator is 32KHz.
System clock the most according to claim 1, it is characterised in that the frequency of described first timer is more than or equal to
8MHz。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610585645.5A CN106227293A (en) | 2016-07-24 | 2016-07-24 | A kind of system clock |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610585645.5A CN106227293A (en) | 2016-07-24 | 2016-07-24 | A kind of system clock |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106227293A true CN106227293A (en) | 2016-12-14 |
Family
ID=57531388
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610585645.5A Pending CN106227293A (en) | 2016-07-24 | 2016-07-24 | A kind of system clock |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106227293A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107800388A (en) * | 2017-10-17 | 2018-03-13 | 广东美的制冷设备有限公司 | Control method, control device, storage medium and remote control |
| CN108650663A (en) * | 2018-03-23 | 2018-10-12 | 珠海慧联科技有限公司 | A kind of bluetooth module and its clock work method of low clock request |
| CN108934061A (en) * | 2017-05-24 | 2018-12-04 | 芯光飞株式会社 | The wireless communication device and method for having low-power mode |
| CN109765985A (en) * | 2018-12-25 | 2019-05-17 | 赛特威尔电子股份有限公司 | Single-chip microcontroller intermittence operation control method, system and device |
| CN111492571A (en) * | 2017-09-18 | 2020-08-04 | 采埃孚汽车英国有限公司 | Timer circuit for dual channel motor controller |
| CN113009899A (en) * | 2019-12-20 | 2021-06-22 | 金卡智能集团股份有限公司 | RTC (real time clock) calibration method for high-precision timing of metering instrument |
| GB2608838A (en) * | 2021-07-13 | 2023-01-18 | Nordic Semiconductor Asa | System timer with high resolution and ultra-low power operation |
| WO2023285396A1 (en) * | 2021-07-13 | 2023-01-19 | Nordic Semiconductor Asa | Synchronised multi-processor operating system timer |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1739157A (en) * | 2003-01-21 | 2006-02-22 | 三星电子株式会社 | Generate the equipment of bit clock and the method that generates this bit clock |
| CN101075146A (en) * | 2006-05-19 | 2007-11-21 | 联发科技股份有限公司 | Method and apparatus for correcting |
| CN101083503A (en) * | 2006-05-30 | 2007-12-05 | 凯明信息科技股份有限公司 | Method for maintaining accurately system synchronous information of receiving apparatus under sleeping state |
| CN103389644A (en) * | 2013-06-19 | 2013-11-13 | 杭州士兰微电子股份有限公司 | Timing system and timing method |
| CN103491623A (en) * | 2012-06-08 | 2014-01-01 | 联发科技股份有限公司 | Integrated circuit and communication method thereof |
| CN105703749A (en) * | 2014-11-24 | 2016-06-22 | 中国科学院沈阳自动化研究所 | Low-power consumption and accurate sleep timer circuit and method |
-
2016
- 2016-07-24 CN CN201610585645.5A patent/CN106227293A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1739157A (en) * | 2003-01-21 | 2006-02-22 | 三星电子株式会社 | Generate the equipment of bit clock and the method that generates this bit clock |
| CN101075146A (en) * | 2006-05-19 | 2007-11-21 | 联发科技股份有限公司 | Method and apparatus for correcting |
| CN101083503A (en) * | 2006-05-30 | 2007-12-05 | 凯明信息科技股份有限公司 | Method for maintaining accurately system synchronous information of receiving apparatus under sleeping state |
| CN103491623A (en) * | 2012-06-08 | 2014-01-01 | 联发科技股份有限公司 | Integrated circuit and communication method thereof |
| CN103389644A (en) * | 2013-06-19 | 2013-11-13 | 杭州士兰微电子股份有限公司 | Timing system and timing method |
| CN105703749A (en) * | 2014-11-24 | 2016-06-22 | 中国科学院沈阳自动化研究所 | Low-power consumption and accurate sleep timer circuit and method |
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108934061B (en) * | 2017-05-24 | 2021-07-27 | 戴乐格半导体韩国株式会社 | Wireless communication device with low power mode and method |
| CN108934061A (en) * | 2017-05-24 | 2018-12-04 | 芯光飞株式会社 | The wireless communication device and method for having low-power mode |
| CN111492571A (en) * | 2017-09-18 | 2020-08-04 | 采埃孚汽车英国有限公司 | Timer circuit for dual channel motor controller |
| CN107800388A (en) * | 2017-10-17 | 2018-03-13 | 广东美的制冷设备有限公司 | Control method, control device, storage medium and remote control |
| CN108650663A (en) * | 2018-03-23 | 2018-10-12 | 珠海慧联科技有限公司 | A kind of bluetooth module and its clock work method of low clock request |
| CN109765985A (en) * | 2018-12-25 | 2019-05-17 | 赛特威尔电子股份有限公司 | Single-chip microcontroller intermittence operation control method, system and device |
| CN109765985B (en) * | 2018-12-25 | 2022-11-22 | 赛特威尔电子股份有限公司 | Method, system and device for controlling intermittent work of single chip microcomputer |
| CN113009899A (en) * | 2019-12-20 | 2021-06-22 | 金卡智能集团股份有限公司 | RTC (real time clock) calibration method for high-precision timing of metering instrument |
| GB2608838A (en) * | 2021-07-13 | 2023-01-18 | Nordic Semiconductor Asa | System timer with high resolution and ultra-low power operation |
| WO2023285396A1 (en) * | 2021-07-13 | 2023-01-19 | Nordic Semiconductor Asa | Synchronised multi-processor operating system timer |
| WO2023285390A1 (en) * | 2021-07-13 | 2023-01-19 | Nordic Semiconductor Asa | System timer with high resolution and ultra-low power operation |
| GB2612009A (en) * | 2021-07-13 | 2023-04-26 | Nordic Semiconductor Asa | Synchronised multi-processor operating system timer |
| GB2608838B (en) * | 2021-07-13 | 2023-08-30 | Nordic Semiconductor Asa | System timer with high resolution and ultra-low power operation |
| GB2612009B (en) * | 2021-07-13 | 2023-10-18 | Nordic Semiconductor Asa | Synchronised multi-processor operating system timer |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106227293A (en) | A kind of system clock | |
| US7315956B2 (en) | Method and apparatus for timing and event processing in wireless systems | |
| CN105142210B (en) | A kind of real-time clock synchronous calibration method and sensor for wireless sense network | |
| CN109067394B (en) | On-chip clock calibration device and calibration method | |
| JP2004507812A (en) | Clock generator especially for USB devices | |
| CN102412957B (en) | High-precision synchronous clock adjusting method | |
| CN100538561C (en) | fractional divider system and method | |
| CN101959298B (en) | Method and device for calibrating slow timing clock and terminal | |
| CN105573463A (en) | Power consumption management method and device | |
| CN105703749A (en) | Low-power consumption and accurate sleep timer circuit and method | |
| CN112530056A (en) | Method for reducing power consumption of intelligent door lock, intelligent door lock and storage medium | |
| CN103389644A (en) | Timing system and timing method | |
| CN104536739A (en) | Method for arousing terminal system | |
| US20120249431A1 (en) | Electronic device with a page turning function during a sleep mode of the electronic device | |
| CN109582371B (en) | Low-power-consumption awakening method and device | |
| CN104375820A (en) | Event-driven processor and operating method thereof | |
| CN102890445B (en) | Multi-functional timer | |
| CN214480603U (en) | Bluetooth clock circuit structure | |
| CN104160354A (en) | Timebase peripheral | |
| CN113259037B (en) | Time synchronization method, medium, and apparatus based on sensor time synchronization system | |
| CN113392063B (en) | Time synchronization method, device and system | |
| CN204613603U (en) | The synchro system of clock information and air conditioner | |
| CN109799872A (en) | Improve the method, apparatus and electronic equipment of low-res real-time clock waking-up precision | |
| CN104571461A (en) | Terminal | |
| CN100405863C (en) | Method for regulating sleeping processor in mobile terminal machine process |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20161214 |
|
| RJ01 | Rejection of invention patent application after publication |