CN109067394B - On-chip clock calibration device and calibration method - Google Patents
On-chip clock calibration device and calibration method Download PDFInfo
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- CN109067394B CN109067394B CN201811031597.0A CN201811031597A CN109067394B CN 109067394 B CN109067394 B CN 109067394B CN 201811031597 A CN201811031597 A CN 201811031597A CN 109067394 B CN109067394 B CN 109067394B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/0802—Details of the phase-locked loop the loop being adapted for reducing power consumption
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
- H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
- H03L7/0992—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider comprising a counter or a frequency divider
Abstract
The invention discloses an on-chip clock calibration device and a calibration method, wherein the device comprises an RC oscillation circuit, a frequency division calibration circuit and a reference high-frequency clock source, wherein the frequency division calibration circuit comprises a timing counter, a frequency division ratio calculation module and a high-frequency clock starting module; the timing counter receives the low-frequency clock signal output by the frequency divider and intermittently outputs a starting signal to the high-frequency clock starting module; after the high-frequency clock starting module receives the starting signal, starting a reference high-frequency clock source; after the reference high-frequency clock source is started, outputting a high-frequency clock signal to the frequency division ratio calculation module; the frequency dividing ratio calculation module receives an original RC clock signal and a high-frequency clock signal, calculates a frequency dividing ratio and outputs the numerical value of the frequency dividing ratio to the frequency divider; the frequency divider divides the frequency of the original RC clock signal based on the frequency division ratio and outputs a calibrated low frequency clock signal. The method realizes the calibration of the clock frequency by using the calibration device. The invention can realize low power consumption to calibrate the low-frequency clock signal.
Description
Technical Field
The invention relates to the field of clock signal processing, in particular to an on-chip clock calibration device and an on-chip clock calibration method for realizing clock signal calibration by applying the device.
Background
Most of existing electronic devices are provided with chips such as a CPU on a circuit board, and the chips such as the CPU consume more electric energy when being in an operating state, so that the existing electronic devices often set that the chips operate in an Active mode or a Sleep mode, and the chips operate at a higher frequency and consume more electric energy when operating in the wake mode, and operate at a lower frequency and consume less electric energy when operating in the Sleep mode. Generally, when a chip needs to execute an instruction, for example, data needs to be processed, the chip enters an awake mode and is in a normal operating state, and when the chip does not need to process the data, the chip enters a sleep mode, so that electric energy consumed by the chip is saved.
Since the chip operates in the wake-up mode and the sleep mode, the operating frequencies are different, and therefore different clock frequencies need to be provided to meet the requirements of the operating frequencies of the chip in the two different modes. Furthermore, when the chip enters the sleep mode from the wake-up mode, the clock frequency needs to be accurately switched to the low frequency mode, and when the chip enters the wake-up mode from the sleep mode, the clock frequency needs to be accurately switched to the high frequency mode. In order to correctly recover the clock signal frequency after the chip enters the wake-up mode from the sleep mode, the accuracy of the low-power consumption clock is required to be high.
At present, most electronic equipment uses a low-frequency crystal oscillator to provide a sleep clock signal, and because the clock precision of the crystal oscillator is better and the power consumption is low, the crystal oscillator is widely applied to chips of communication systems such as GPS, Bluetooth and wifi as a low-power consumption clock signal source at sleep timing. With the recent rise of mobile communication and IOT devices, there is a demand for smaller device size and lower cost, so that on-chip low-power clock signal sources (such as RC oscillators) are widely used and intensively studied. However, the accuracy of the on-chip low-power-consumption clock signal source is poor, and the on-chip low-power-consumption clock signal source greatly changes along with temperature change, voltage fluctuation and process difference, so that the frequency of the on-chip low-power-consumption clock signal needs to be calibrated.
For a method for enhancing the reliability of system clock signal recovery used by a system with a sleep wake-up process, the prior art mainly solves the problem by improving the precision of a clock source, improving the tolerance of a communication system to clock signal errors or utilizing a calibration strategy.
The most direct method is to solve the problem of clock errors by improving the precision of a clock source, so that the traditional low-frequency and low-power consumption clock signal source tends to use a crystal oscillator as the clock source. However, the current method of designing a low-frequency and low-power clock source by using on-chip resources is fundamentally limited from the physical level and cannot achieve the performance equivalent to that of a crystal oscillator. For example, after the chip is manufactured, the influence of the process level deviation on the absolute value of the clock signal source frequency is reduced by using a method for adjusting the capacitance resistance, but the influence of the transistor on the voltage fluctuation and the relatively significant deviation caused by the relative temperature change of the capacitance resistance cannot be reduced. Meanwhile, the cost is increased in the factory calibration test of the chip, and the frequency of the clock signal gradually deviates from the factory calibration result along with the aging of the chip.
While reducing the clock accuracy requirement of the communication protocol can improve the tolerance of the communication system to clock errors, general communication systems comply with established protocols, such as bluetooth, wifi, etc. In the prior art, keep-alive transmission times are increased near the estimated wake-up time point of the slave device, so that the master device and the slave device are prevented from being disconnected due to the error of a clock signal. Therefore, in the prior art, the situation of connection interruption caused by overlarge clock error of other equipment is reduced by improving the compatibility of other Bluetooth equipment. However, when a device is used as a slave device, the accuracy required by the bluetooth protocol specification for the clock signal still needs to be followed, and since it cannot be guaranteed that the other bluetooth devices also use the same clock recovery method when the other bluetooth devices are used as master devices, this method is not suitable for general communication systems with clear communication protocol specifications.
Since the CPU and other chips are turned off in the sleep mode, the clock signal calibration scheme in the prior art is calibrated in the wake mode. In the sleep mode and the wake-up mode, the temperature and voltage states of the chip may change, so that the operation of calculating the low-power consumption clock in the wake-up mode may cause a large error. For example, in the solution disclosed in chinese patent application publication No. CN105873190A, when iteratively calculating the calibration factor, iteration is performed by using the actual system timing minus the recovered system timing as a calibration error, and the low power consumption clock is in the sleep mode and the wake-up mode within a span of receiving the actual system timing, which results in inaccurate calculation of the calibration error. Once the frequency values of the low-power-consumption clock signals in the sleep mode and the wake-up mode are greatly different, calibration failure can be caused, and even the chip cannot wake up at a preset time point and time synchronization of the system is carried out, so that the frequency accuracy of the clock signals after the chip wakes up is influenced.
Disclosure of Invention
The invention mainly aims to provide an on-chip clock calibration device capable of accurately calibrating a low-frequency clock signal of a chip in a sleep mode, so that the clock frequency can be continuously calibrated after a system is awakened, calibration can be carried out according to an objective regular step interval of temperature change in the process of entering the sleep state from a working state, and calibration can be periodically carried out after the system enters the sleep state.
Another object of the present invention is to provide an on-chip clock calibration method implemented by the above-mentioned on-chip clock calibration apparatus, wherein the determined frequency is output after the dynamic frequency division calibration instead of the calculated frequency value.
In order to achieve the above main object, the on-chip clock calibration apparatus provided by the present invention includes an RC oscillating circuit and a frequency division calibration circuit, wherein the frequency division calibration circuit includes a frequency divider for receiving an original RC clock signal output by the RC oscillating circuit; the device also comprises a reference high-frequency clock source, and the frequency division calibration circuit also comprises a timing counter, a frequency division ratio calculation module and a high-frequency clock starting module; the timing counter receives the low-frequency clock signal output by the frequency divider and intermittently outputs a starting signal to the high-frequency clock starting module; after the high-frequency clock starting module receives the starting signal, starting a reference high-frequency clock source; after the reference high-frequency clock source is started, outputting a high-frequency clock signal to the frequency division ratio calculation module; the frequency dividing ratio calculation module receives the original clock signal and the high-frequency clock signal, calculates the frequency dividing ratio and outputs the numerical value of the frequency dividing ratio to the frequency divider; the frequency divider divides the original RC clock signal by a decimal frequency based on a frequency division ratio and outputs a calibrated low-frequency clock signal.
According to the scheme, after the chip enters the sleep mode, the output low-frequency clock signal is calibrated by intermittently utilizing the high-frequency clock signal output by the high-frequency clock signal source, and the whole calibration process is executed when the chip is in the sleep mode, so that the problem of inaccurate calibration caused by the fact that the calibration process is executed in the wake mode can be avoided. On the other hand, since the calibration of the clock frequency is performed intermittently, not continuously, the reference high frequency clock source is not operated for a long time but operated intermittently, thereby reducing the power consumed by the reference high frequency clock source. Because the electric energy consumed by the RC oscillating circuit is low, the power consumption of the whole on-chip clock calibration device is low.
In a preferred embodiment, the timing counter counts the time of a plurality of calibration times, and outputs a start signal to the high-frequency clock start module once when each calibration time is reached.
Therefore, the time of a plurality of calibration moments is calculated by the timing counter, so that the time of each time when the calibration needs to be executed can be accurately determined.
The timing counter records the time of a plurality of calibration periods, and outputs a starting signal to the high-frequency clock starting module when each calibration period arrives in sequence; and after the last recorded calibration period time is reached, taking the last calibration period as a set period, and outputting a starting signal to the high-frequency clock starting module.
Preferably, the time of the plurality of calibration periods is the time of the plurality of calibration periods matched with the law of the chip temperature change speed in the process from the working state to the dormant state in the practical application scene.
It can be seen that the timing counter ensures accurate execution of the calibration by recording the time of a plurality of calibration periods and issuing a start signal in turn at the arrival of each calibration period.
Preferably, the timer counter is provided with a plurality of registers, each register records the number of minimum stepping time periods of one calibration period, and the period times of the plurality of calibration periods are gradually increased in sequence according to the temperature change rule after the calibration period enters the sleep mode.
Therefore, when the chip just enters the sleep mode from the wake-up mode, the original RC clock frequency of the RC oscillating circuit is higher due to the higher temperature of the chip, so that the calibration period is shorter, the temperature of the chip is gradually reduced along with the increase of the sleep time, the original RC clock frequency of the RC oscillating circuit is also reduced and kept stable, and the calibration period is longer, so that the calibration accuracy can be ensured, and the power consumption of the on-chip clock calibration device can be saved.
Optionally, the division ratio calculation module has a division circuit, and the division circuit calculates the value of the division ratio by dividing a preset value by the division calibration value.
Therefore, the frequency dividing ratio calculating module can quickly calculate the frequency dividing ratio through the preset value, so that the frequency dividing ratio is simple and quick to calculate.
The further scheme is that the frequency division calibration value is the count value of the high-frequency clock signal when the count value of the original RC clock signal meets the precision calculation requirement.
Therefore, the number of the high-frequency clock signals when the accuracy requirement of the original RC clock signal meeting the calibration accuracy requirement is calculated to be used as the divisor of the division circuit, so that the frequency division ratio can be conveniently and quickly calculated by the frequency division ratio calculation module. Because the counting values of the high-frequency clock signals corresponding to the same counting value of the original RC clock signal are different at different moments, the calculated frequency dividing ratios are different, and the calibration of the low-frequency clock signal is realized.
In order to achieve the above another object, the present invention provides a method for calibrating an on-chip clock, including: the RC oscillating circuit outputs an original RC clock signal to the frequency divider, and the frequency divider divides the frequency of the original RC clock signal based on the frequency division ratio and outputs a low-frequency clock signal; the frequency divider outputs a low-frequency clock signal to the timing counter and intermittently sends a starting signal to the high-frequency clock starting module; after the high-frequency clock starting module receives the starting signal, starting a reference high-frequency clock source; after the reference high-frequency clock source is started, outputting a high-frequency clock signal to the frequency division ratio calculation module; the frequency dividing ratio calculation module receives an original RC clock signal and a high-frequency clock signal, calculates a frequency dividing ratio and outputs the numerical value of the frequency dividing ratio to the frequency divider; the frequency divider divides the original RC clock signal by a decimal frequency based on a frequency division ratio and outputs a calibrated low-frequency clock signal.
According to the scheme, after the chip enters the sleep mode, the original RC clock signal is calibrated by intermittently utilizing the high-frequency clock signal output by the high-frequency clock signal source, the whole calibration process is executed when the chip is in the sleep mode, and the problem of inaccurate calibration caused by the fact that the calibration process is executed in the wake-up mode can be avoided. On the other hand, since the calibration of the clock frequency is performed intermittently, not continuously, the reference high frequency clock source is not operated for a long time but operated intermittently, thereby reducing the power consumed by the reference high frequency clock source. Because the electric energy consumed by the RC oscillating circuit is low, the power consumption of the whole on-chip clock calibration device is low.
Drawings
Fig. 1 is a graph of the change in frequency of an RC oscillation circuit with time and the change in temperature of the RC oscillation circuit with time.
FIG. 2 is a block diagram of an embodiment of an on-chip clock calibration apparatus according to the present invention.
Fig. 3 is a flowchart illustrating the operation of the timing counter in the embodiment of the on-chip clock calibration apparatus of the present invention.
FIG. 4 is a flowchart illustrating the operation of the high frequency clock enable module in the embodiment of the on-chip clock calibration apparatus of the present invention.
Fig. 5 is a block diagram of a frequency division ratio calculation circuit in an embodiment of the on-chip clock calibration apparatus of the present invention.
FIG. 6 is a flow chart of an embodiment of the on-chip clock calibration method of the present invention.
The invention is further explained with reference to the drawings and the embodiments.
Detailed Description
The on-chip clock calibration device is applied to an integrated circuit with chips such as a CPU (central processing unit), the CPU can work in a wake-up mode and a sleep mode, and the on-chip clock calibration device is used for generating a low-frequency clock signal used by the chips in the sleep mode. The on-chip clock calibration method of the invention applies the on-chip clock calibration device to generate a low-frequency clock signal.
On-chip clock calibration apparatus embodiment:
the on-chip clock calibration device of the embodiment is used for generating a low-frequency clock signal for the chip to use after the chip enters the sleep mode from the wake-up mode. When the chip is switched from the wake-up mode to the sleep mode, the temperature of the chip will gradually decrease, and the clock frequency of the RC oscillating circuit also decreases, and the trend of the variation relationship between the temperature, the time and the frequency of the chip is shown in fig. 1. From fig. 1, it can be seen that the chip enters the sleep mode from the wake-up mode at 0 second, the temperature of the chip gradually decreases from 60 ℃ to 38 ℃ within 25 seconds after entering the sleep mode, and the frequency of the clock signal output by the RC oscillating circuit also gradually decreases from 800 khz to 798.80 khz. The value above each dot in fig. 1 is the temperature, and the value below the dot is the frequency of the clock signal of the RC oscillation circuit. As can be seen from fig. 1, the temperature of the chip gradually decreases with the passage of time, and the frequency of the clock signal of the RC oscillation circuit also gradually levels off.
The main idea of the present embodiment is to provide a high frequency clock signal source to calibrate the low frequency clock signal obtained by frequency division, and the present embodiment uses a frequency divider to frequency-divide the original RC clock signal of the RC oscillating circuit to obtain the low frequency clock signal. Referring to fig. 2, the present embodiment has an RC oscillation circuit 10, a reference high frequency clock source 40, and a frequency division calibration circuit 70, wherein the frequency division calibration circuit 70 includes a frequency divider 20, a timing counter 30, a high frequency clock start module 50, and a frequency division ratio calculation module 60.
Since the power consumption of the RC oscillating circuit 10 is low and the power consumption of the reference high frequency clock source 40 is high, the reference high frequency clock source 40 is intermittently started in the present embodiment, that is, the calibration of the frequency of the low frequency clock signal is performed intermittently and not continuously. In this way, power consumption of the entire on-chip clock calibration apparatus can be saved. As can be seen from fig. 1, after the chip enters the sleep state from the wake-up state, the frequency of the original RC clock signal will decrease rapidly, and after a period of time, the frequency change tends to be stable, so that the calibration period is shorter within a shorter time after the chip enters the sleep mode, and the calibration period will gradually increase as the time increases, on one hand, the accuracy of the low-frequency clock signal obtained after the chip enters the sleep mode can be ensured, and on the other hand, the power consumption of the on-chip clock calibration apparatus can be further saved.
In this embodiment, the RC oscillating circuit 10 is an RC oscillating clock generating circuit, and is used to provide an original RC clock source to be frequency-divided and calibrated, and generally, the original RC clock signal is a clock signal with a higher frequency. And the reference high frequency clock source 40 is a high precision high frequency clock source, which functions to provide a reference high frequency clock signal for calibration and to provide driving for the division circuit of the division ratio calculation module 60. Since the high frequency clock signal provided by the reference high frequency clock source 40 is a clock signal for calibration, the frequency of the high frequency clock signal needs to be higher than that of the original RC clock signal, so as to realize calibration of the original RC clock signal.
The frequency of the original RC clock signal output by the RC oscillating circuit 10 varies with the temperature of the chip, i.e. the curve shown in fig. 1 varies. After receiving the original RC clock signal output by the RC oscillating circuit 10, the frequency divider 20 divides the original RC clock signal based on the frequency division ratio, thereby forming a low-frequency clock signal with a lower frequency for the CPU or other chips to use in the sleep mode.
In this embodiment, the frequency divider 20 is a random number frequency division functional module, and is configured to divide the frequency of the original RC clock signal according to the frequency division ratio output by the frequency division ratio calculating module 60 to obtain a low-frequency clock signal. Preferably, in this embodiment, the errors of the low-frequency clock signal output by the frequency divider 20 are randomly and uniformly distributed, theoretically, the frequency-division error expected value is zero, actually, the errors are determined only by the original RC clock signal and the high-frequency clock signal, and as long as the errors of the original RC clock signal and the high-frequency clock signal are within the allowable range in the calibration period, the low-frequency clock signal output by frequency division can meet the requirements.
Further, the frequency divider 20 divides the original RC clock signal by a fractional number based on the dividing ratio to output the calibrated low-frequency clock signal, for example, the dividing ratio is not an integer but a fractional number, for example, the dividing ratio is 50.5, and when the frequency divider 20 divides the frequency, the interval between 50 and 51 is used as the dividing ratio, so that the frequency of the divided low-frequency clock signal is within the allowable error range.
The timing counter 30 is used to intermittently start the reference high frequency clock source 40, so that the frequency division ratio calculating module 60 intermittently calculates the value of the frequency division ratio, and the frequency divider 20 also intermittently receives the value of the frequency division ratio, thereby calculating the frequency division ratio. As can be seen from fig. 1, when a chip such as a CPU enters a sleep mode from a wake-up mode, the temperature will decrease rapidly, the original RC clock frequency of the RC oscillating circuit 10 will also decrease rapidly, and after a certain time, the original RC clock frequency will tend to be stable. Therefore, the timer counter 30 will have a short calibration period in a short time after the chip enters the sleep mode, and the calibration period for the low frequency clock signal will gradually increase as time goes by. Therefore, the period of the timer counter 30 starting the reference high frequency clock source 40 is not fixed, but after the chip enters the sleep mode, the time of the first period is short, the subsequent calibration period gradually increases, and after a certain time, the calibration period becomes a fixed period.
In this embodiment, after the timer counter 30 receives the original RC clock signal output by the divider 20, a plurality of calibration time instants are calculated, and preferably, each calibration time instant is the end time of each calibration period. When each calibration time is reached, the timing counter 30 outputs a start signal to the high-frequency clock start module 50, after the high-frequency clock start module 50 receives the start signal, the reference high-frequency clock source 40 is started, and simultaneously, a signal is output to the frequency division ratio calculation module 60, and the frequency division ratio calculation module 60 outputs a value to the frequency divider 20, where the value is the value of the frequency division ratio calculated by the frequency division ratio calculation module 60.
In order to facilitate the calculation of the time of each calibration period, in the present embodiment, the time of a plurality of calibration periods may be recorded in the timing counter 30, for example, the time of the first calibration period, the time of the second calibration period, and the like are recorded. Since the calibration operation needs to be performed frequently in a short time after the chip enters the sleep mode, and the calibration period is gradually increased with the passage of time, the timing counter 30 needs to record the time of the previous calibration periods, and the fixed calibration period can be used for calibration after the frequency of the original RC clock period of the RC oscillating circuit 10 is stabilized.
Therefore, the timing counter 30 records the time of a plurality of calibration periods, and outputs a start signal to the high frequency clock start module 50 once when each calibration period arrives, for example, at the arrival time of each calibration period. And after the last recorded calibration period time is reached, if the chip is continuously in the sleep mode, the last calibration period is taken as a set period, and a starting signal is output to the high-frequency clock starting module. For example, the timing counter 30 records the time of the previous 10 calibration periods after the chip enters the sleep mode, and after the time of the previous 10 calibration periods, if the chip is still in the sleep mode, each subsequent calibration period is a period set by the last recorded calibration period, and when the last time of the set period is reached, the start signal is output to the high-frequency clock start module 50 once, so as to start the clock signal calibration operation once.
In order to meet the operation requirements of different chips, the timing counter 30 of the present embodiment needs to have the following functions: the change rule of the calibration period can be configured according to different chips; after the chip is awakened from the sleep mode, the calibration period of the chip is automatically switched to an initial value, so that the calibration is started from the first calibration period after the chip enters the sleep mode next time; the calibration function may be enabled and disabled, i.e., the calibration function may be enabled or disabled as desired.
Preferably, a plurality of registers are provided in the timer counter 30, and each register records the number of minimum step time periods of one calibration period. For example, in the present embodiment, the minimum step time REG _ DELT used for calibration is set, which is the greatest common divisor of the time lengths of the plurality of calibration periods. For example, after the chip enters the sleep mode, the period duration required for the first calibration period is the duration REG _ TIM0 of the minimum calibration period, and each subsequent calibration period is several times the minimum step time, so the value stored in the registers is an integer, which means that the calibration period corresponding to the current register is a multiple of the minimum step time. For example, if the first calibration period is the minimum step time, the register corresponding to the first calibration period stores a value of 1, the second calibration period is 10 times the minimum step time, the register corresponding to the second calibration period stores a value of 10, the third calibration period is 25 times the minimum step time, the register corresponding to the third calibration period stores a value of 25, and so on.
Since the timing count time is in units of up to several seconds, the time value of the timing counter 30 requires a 32-bit register to store data, and if one register is used for storing data for each time, resource waste is caused, especially when the number of calibration cycles is more densely changed, and therefore, the present embodiment provides a design scheme for saving registers.
The present embodiment sets a plurality of registers to store a plurality of preset values, where the stored values include the minimum step time REG _ DELT, the number of different cycles REG _ NUM that need to be calibrated, and the like, and also sets a plurality of registers to store the number of the differences REG _ DELT from the current calibration cycle to the next calibration cycle, that is, the time of the current calibration cycle is a value that is a multiple of the minimum step time REG _ DELT, and preferably, N +1 calibration cycle registers are used to respectively record the value of each calibration cycle that is a multiple of the minimum step time cycle, and the value stored in each calibration cycle register can be represented by REG _0 to REG _ N. In addition, a value register is needed to store the duration REG _ TIM0 of the minimum calibration period, preferably, the duration REG _ TIM0 of the minimum calibration period is a preset default value, and the time length of the first calibration period after the chip enters the sleep mode is also needed.
The operation of the timer counter 30 will now be described with reference to fig. 3. First, step S1 is executed to set the total count value as the value of the minimum calibration period, i.e. after the chip enters the sleep mode, at the initial time, the total count value REG _ SUM is set as the value of the minimum calibration period REG _ TIM 0. Preferably, the total count value REG _ SUM is stored in a register, the value of which can be erased. Then, step S2 is executed to determine whether the count value TIM _ CNT of the timer counter is equal to the total count value REG _ SUM, if yes, step S4 is executed to once send a start signal to the high frequency clock start module 50 by the timer counter 30. If the count value TIM _ CNT of the timing counter is less than the total count value REG _ SUM, step S3 is performed, the count value of the timing counter increments by one, and the process returns to perform step S2.
After step S4 is executed, it indicates that the calibration of the clock signal has been executed for one cycle, the time of the next calibration cycle needs to be calculated, and after the time length of the current cycle has elapsed, the next start signal is sent, and the sending time of the next start signal is the time when the current calibration cycle ends. Therefore, the end time of the current calibration period needs to be accurately calculated. In this embodiment, on one hand, the cycle counter is used to calculate which cycle is currently located, and on the other hand, the calibration cycle register is used to calculate how many times the time length of the current cycle is the minimum step time REG _ DELT, so as to calculate the time length of the new calibration cycle.
Therefore, immediately after the step S4 is executed, the step S5 is executed to increment the number of calibration cycles by one, that is, to increment the count value of the cycle number counter NUM by 1, and then the step S6 is executed to determine whether the value of the sequence number of the next calibration cycle register is reached. For example, if the current calibration period is the 2 nd calibration period and the sequence number of the corresponding calibration period register is 2, the number of calibration periods is incremented once when step S5 is executed, and the sequence number of the calibration period is changed to 3, so step S6 is to determine whether the count value of the current period number counter is the sequence number of one of the calibration period registers. If the count value of the current cycle count counter is the serial number of one of the calibration cycle registers, step S7 is executed to obtain the value stored in the corresponding calibration cycle register. For example, a value stored in the calibration period register with the corresponding sequence number is obtained, for example, a value REG _3 stored in the calibration period register with the sequence number 3 is obtained, for example, the value is 50.
Since the value stored in each calibration period register indicates that the time length of the calibration period is a multiple of the minimum step time REG _ DELT, after the value stored in the calibration period register is obtained (assuming that the value is N), a variable M is set, the variable M is incremented from 0, and is incremented once after each lapse of the minimum step time REG _ DELT, and when the variable M is incremented to N, indicating that the end time of the current calibration period has been reached, an enable signal may be sent.
Therefore, after step S7, step S9 is executed to increment the value of the variable M once after a minimum step time REG _ DELT, and step S10 is executed to determine whether the minimum step time period calculated value M is greater than the value N of the calibration period register, if yes, step S11 is executed, otherwise, step S9 is executed again, i.e., after a minimum step time REG _ DELT, the value of the variable M is incremented once.
In step S11, the value of the variable M is added to the value of the minimum calibration period duration REG _ TIM0 to obtain a new total count value REG _ SUM, and then the process returns to step S2 to determine whether the count value TIM _ CNT of the timer counter has counted to the new total count value REG _ SUM, and if so, a calibration calculation is enabled, that is, a start signal is sent to the high-frequency clock start module 50. It can be seen that, by determining whether the count value TIM _ CNT of the timing counter is equal to the total count value REG _ SUM, it is further determined that the current time is the time of one calibration period, thereby ensuring that the time for starting signal transmission is accurate.
In step S6, if the number of cycles is not equal to the preset number, step S8 needs to be executed to determine whether the number of cycles is greater than the maximum value, for example, the maximum number of cycles REG _ NUM stored in the register that needs to be calibrated is 10, if the current number of cycles is greater than 10, step S12 is executed to determine whether the chip is in the sleep mode, if the chip is in the sleep mode, step S13 is executed to obtain the value stored in the last calibration cycle register, step S9 is executed, if the chip is not in the sleep mode, which indicates that the chip has been awakened, the calibration operation of the low frequency clock is directly exited, and the high frequency operation is used. If the current cycle count is not greater than the maximum cycle count in step S8, the process returns to step S5, and the cycle count counter is incremented, i.e., jumps to the next calibration cycle.
It can be seen that the timing counter 30 does not frequently transmit the start signal, but intermittently transmits the start signal, and the transmission time of the start signal is implemented by the values stored in the plurality of registers in combination with the count values of the plurality of counters, so as to periodically transmit the start signal to the high frequency clock start module 50.
The operation of the high frequency clock enable module 50 is described below with reference to fig. 4. First, step S21 is executed to determine whether a start signal is received, if yes, step S22 is executed to turn on the power of the reference high frequency clock source 40, and step S23 is executed to set parameters required when the reference high frequency clock source 40 operates, and step S24 is executed to turn on the reference high frequency clock source 40, at which time the reference high frequency clock source 40 is started and operated. However, the reference high frequency clock source 40 does not enter the stable operating state immediately after the start, that is, the reference high frequency clock source 40 needs to output the high frequency clock signal with stable frequency after a certain time, so that the step S25 needs to be executed to determine whether the stable operating time of the reference high frequency clock source is reached, if yes, the step S26 is executed, otherwise, the waiting is continued until the reference high frequency clock source 40 enters the stable operating state.
In step S26, after the reference high-frequency clock source 40 enters the stable operating state, the buffer of the reference high-frequency clock source 40 is opened, and data is obtained from the buffer of the reference high-frequency clock source 40, that is, the high-frequency clock signal of the reference high-frequency clock source 40 is output to the frequency division ratio calculation module 60. Then, step S27 is executed to determine whether the clock signal calibration operation is finished, if the clock signal calibration operation of the current period is finished, step S28 is executed to turn off the reference high frequency clock source 40 and turn off the power supply of the reference high frequency clock source, so as to ensure that the reference high frequency clock source 40 is not in the operating state for a long time, but is in the operating state for a period of time after receiving the start signal, and immediately stops operating after one time of calibration is finished, thereby avoiding a large amount of power consumption caused by the long-time operation of the reference high frequency clock source 40.
The high-frequency clock signal output by the reference high-frequency clock source 40 is used to calibrate the frequency of the low-frequency clock signal, and specifically, the high-frequency clock signal output by the reference high-frequency clock source 40 is output to the frequency division ratio calculation module 60. The operation of the frequency division ratio calculation module 60 will be described with reference to fig. 5. The main function of the division ratio calculation block 60 is to calculate a parameter required by the frequency divider 20, i.e., a division ratio. In this embodiment, the frequency division ratio is not fixed, but a specific numerical value of the frequency division ratio is determined according to the frequency of the original RC clock signal of the RC oscillation circuit 10 and the frequency of the high-frequency clock signal.
Referring to fig. 5, the division ratio calculation block 60 includes a register 61, a division circuit 62, a high-frequency clock cycle counter 63, a high-frequency clock cycle register 64, and an original RC clock cycle counter 65.
The register 61 is used to store a dividend of the division circuit 62, the Value of the dividend is a preset Value, and the calculation process of the Value is described below assuming that the Value is Value.
Assume that the maximum frequency of the original RC clock signal of the RC oscillation circuit 10 is fmaxrcMHz, error accuracy Dppm (D parts per million), high frequency clock frequency fdcxoAnd (4) MHz. The frequency maximum error of the original RC clock signal of the RC oscillating circuit 10 is 1/f by high frequency crystal oscillatordcxoIf the requirement for calibrating the accuracy of the original RC clock signal needs to be met, the calculation accuracy error must be smaller than the error of the original RC clock signal, assuming that the number of cycles of N original RC clock signals is needed to calculate the original RC clock signal meeting the accuracy requirement, and the number of cycles of the corresponding high-frequency clock signal is N, equations 1 and 2 can be derived:
Also, the relationship between the frequency of the original RC clock signal and the frequency of the high frequency clock signal may be represented using equation 3.
Suppose that the low-frequency clock frequency of the frequency-divided output of the frequency divider 20 is floscAnd MHz, when the frequency dividing ratio of the frequency of the low-frequency clock signal and the frequency of the original RC clock signal meets the requirement of the formula 4, the frequency dividing calculation precision of the low-frequency clock signal when all the frequencies are changed can be met.
When ">" of equation 2 is taken as "=", the Value to be held by the reference register 61 is:
Wherein the parameter n, the maximum frequency f of the original RC clock signalmaxrcError accuracy D and divided low frequency clock frequency floscAre all known numbers. Therefore, the frequency division ratio can be calculated by knowing the count value N of the high-frequency clock signal within the duration of N original RC clock signals. From equation 5, the Value is N times the frequency dividing ratio, i.e. the original clock frequency fdcxoWith a low frequency clock frequency floscIs N times the ratio of (a).
The division circuit 62 is a shift division circuit, and preferably, the division circuit 62 is driven by a high-frequency clock signal, so that the operation speed of the division circuit 62 is increased, and the calibration time is shortened. When the high frequency clock is turned off after the calibration calculation is completed, the division circuit 62 does not work, thereby saving the power consumption of the whole frequency division ratio calculation module 60.
The original RC clock period counter 65 is used to count the number of original RC clock signals of the RC oscillation circuit 10, and therefore the original RC clock period counter 65 receives the original RC clock signals and counts the number of the original RC clock signals. Since the frequency dividing ratio is calculated by determining the number N of cycles of the corresponding high-frequency clock signal after calculating the number N of cycles of the original RC clock signal that meets the requirement of the calibration accuracy, the number N of cycles of the original RC clock signal that meets the requirement of the calibration accuracy is preset, the count value of the counter is incremented once after the original RC clock cycle counter 65 receives one pulse of the original RC clock signal, and a signal is output to the high-frequency clock cycle counter 63 when the count value reaches N.
The high frequency clock period counter 63 is used to count the number of periods of the high frequency clock signal of the reference high frequency clock source 40, i.e. to start counting when the original RC clock period counter 65 starts counting, and to stop counting when receiving the signal sent by the original RC clock period counter 65, and the count value is the number N of periods of the high frequency clock signal corresponding to N periods of the original RC clock signal.
The high-frequency clock cycle register 64 is used to store the count value of the high-frequency clock cycle counter 63, i.e., store the count value N, and send the count value N to the division circuit 62. Therefore, the division circuit 62 calculates the numerical Value of the frequency division ratio using Value as the dividend and the high-frequency clock cycle register 64 as the divisor and outputs the Value divider 20.
Preferably, each time the calibration is started, the high frequency clock cycle counter 63 and the original RC clock cycle counter 65 are cleared to their respective counts, i.e., the previous counts are cleared to avoid affecting the accuracy of the technique.
Because the frequency of the original RC clock signal is continuously reduced along with the time that the chip enters the sleep mode, the time length of N original RC clock signal cycles satisfying the requirement of calibration accuracy is changed, and the frequency of the high-frequency clock signal is stable, so that the number N of cycles of the corresponding high-frequency clock signal is also changed within the time length of N original RC clock signals within different time periods, and thus, the calculated frequency division ratio is not fixed, but changes along with the change of time, thereby satisfying the requirement of frequency calibration of the low-frequency clock signal.
The embodiment of the on-chip clock calibration method comprises the following steps:
the working flow of the on-chip clock calibration method of the present invention is described below with reference to fig. 6. First, step S31 is executed, the RC oscillating circuit outputs an original RC clock signal, and then step S32 is executed, the frequency divider divides the original RC clock signal based on a preset frequency division ratio to form a low frequency clock signal. Preferably, the frequency divider prestores a default frequency dividing ratio, which can be determined according to the frequency of the original RC clock signal output by the RC oscillating circuit when the chip just enters the sleep mode.
Then, step S33 is executed, the frequency divider outputs the divided low-frequency clock signal to the timer counter, and the timer counter executes step S34 to determine whether a calibration time is reached, if yes, step S35 is executed, otherwise, the timer continues to wait. In this embodiment, the timer counter sets the memories to store a plurality of values, respectively, including storing the number of minimum stepping time periods between each calibration period and the previous calibration period, and also storing the minimum stepping time length, so as to calculate the end time of each calibration period. Therefore, step S34 is to calculate the end time of each calibration period.
When the end time of one calibration period is reached, step S35 is executed, the timing counter sends a start signal to the high-frequency clock start module, the high-frequency clock start module executes step S36, starts the reference high-frequency clock source, for example, turns on the power supply of the reference high-frequency clock source, and outputs the high-frequency clock signal to the frequency division ratio calculation module after the frequency of the high-frequency clock signal of the reference high-frequency clock source is stabilized.
Next, step S37 is executed, in which the frequency division ratio calculation module calculates the numerical value of the frequency division ratio, for example, using a preset value stored in one register as a dividend, calculates the number N of cycles of the high frequency clock signal corresponding to the time of N original RC clock frequency cycles satisfying the calibration accuracy requirement, calculates the specific numerical value of the frequency division ratio used by the frequency divider using N as a divisor, and sends the numerical value of the frequency division ratio to the frequency divider. Because the frequency dividing ratio calculated by the frequency dividing ratio calculating module is not fixed but is reduced along with the reduction of the frequency of the original RC clock signal, the frequency divider determines the low-frequency clock signal after frequency division by using the frequency dividing ratio calculated by the frequency dividing ratio calculating module, the frequency stability of the low-frequency clock signal can be ensured as much as possible, and the stability of the working frequency of the chip in the sleep mode is met.
Then, step S38 is executed, the frequency divider divides the frequency of the original RC clock signal by the frequency division ratio calculated by the frequency division ratio calculation module to obtain a new low-frequency clock signal, and step S39 is finally executed to determine whether the chip exits from the sleep mode, if so, the low-frequency clock signal is not calibrated, but the clock signal used by the chip in the wake-up mode is provided. If the chip is still in the sleep mode, the process returns to step S33, and the time of the next calibration cycle is counted again by the timer counter. Preferably, the timing counter determines the time length of several calibration periods, for example, the time length of 10 calibration periods, and after the time length of the last calibration period is reached, the chip is still in the sleep mode, and the time length of the last calibration period is continuously used as the set calibration period to calibrate the frequency of the clock chip.
Of course, the above-mentioned solution is only a preferred embodiment of the present invention, and the practical application may also have more changes, for example, the specific manner of the calibration period calculation, the specific configuration of the frequency division ratio calculation module, and the like, which do not affect the implementation of the present invention, and should also be included in the protection scope of the present invention.
Claims (7)
1. The on-chip clock calibration device comprises an RC oscillating circuit and a frequency division calibration circuit, wherein the frequency division calibration circuit comprises a frequency divider for receiving an original RC clock signal output by the RC oscillating circuit;
the method is characterized in that:
the device also comprises a reference high-frequency clock source, and the frequency division calibration circuit also comprises a timing counter, a frequency division ratio calculation module and a high-frequency clock starting module;
the timing counter receives the low-frequency clock signal output by the frequency divider and intermittently outputs a starting signal to the high-frequency clock starting module;
after the high-frequency clock starting module receives the starting signal, starting the reference high-frequency clock source;
after the reference high-frequency clock source is started, outputting a high-frequency clock signal to the frequency dividing ratio calculation module;
the frequency dividing ratio calculation module receives the original RC clock signal and the high-frequency clock signal, calculates a frequency dividing ratio and outputs the numerical value of the frequency dividing ratio to the frequency divider;
the frequency divider divides the original RC clock signal by decimal frequency based on the frequency division ratio and outputs a calibrated low-frequency clock signal;
the timing counter calculates the time of a plurality of calibration moments, and outputs a starting signal to the high-frequency clock starting module once when each calibration moment is reached;
the timing counter records the time of a plurality of calibration periods and outputs a starting signal to the high-frequency clock starting module when each calibration period arrives in sequence;
and after the last recorded calibration period time is reached, taking the last calibration period as a set period, and outputting a cycle starting signal to the high-frequency clock starting module.
2. The on-chip clock calibration apparatus of claim 1, wherein:
the timing counter is provided with a plurality of registers, each register recording the number of minimum stepping time periods of one calibration period.
3. The on-chip clock calibration apparatus of claim 2, wherein:
the cycle time of the plurality of calibration periods is gradually increased in sequence.
4. The on-chip clock calibration apparatus according to any one of claims 1 to 3, wherein:
the frequency dividing ratio calculating module is provided with a dividing circuit which divides a preset value by a frequency dividing calibration value to calculate and obtain a numerical value of the frequency dividing ratio.
5. The on-chip clock calibration apparatus of claim 4, wherein:
and the frequency division calibration value is the count value of the high-frequency clock signal when the count value of the original RC clock signal meets the precision calculation requirement.
6. An on-chip clock calibration method, comprising:
the RC oscillating circuit outputs an original RC clock signal to a frequency divider, and the frequency divider divides the frequency of the original RC clock signal based on a frequency division ratio and outputs a low-frequency clock signal;
the method is characterized in that:
the frequency divider outputs the low-frequency clock signal to a timing counter and intermittently sends a start signal to a high-frequency clock start module: the timing counter calculates the time of a plurality of calibration moments, and outputs a starting signal to the high-frequency clock starting module once when each calibration moment is reached;
after the high-frequency clock starting module receives the starting signal, a reference high-frequency clock source is started;
after the reference high-frequency clock source is started, outputting a high-frequency clock signal to the frequency dividing ratio calculation module;
the frequency dividing ratio calculation module receives the original RC clock signal and the high-frequency clock signal, calculates a frequency dividing ratio and outputs the numerical value of the frequency dividing ratio to the frequency divider;
the frequency divider divides the original RC clock signal by decimal frequency based on the frequency division ratio and outputs a calibrated low-frequency clock signal;
the timing counter records the time of a plurality of calibration periods and outputs a starting signal to the high-frequency clock starting module when each calibration period arrives in sequence;
and after the last recorded calibration period time is reached, taking the last calibration period as a set period, and outputting a cycle starting signal to the high-frequency clock starting module.
7. The method of on-chip clock calibration of claim 6, wherein:
and the frequency division ratio calculation module divides a preset value by a frequency division calibration value to calculate and obtain a numerical value of the frequency division ratio, wherein the frequency division calibration value is the counting value of the high-frequency clock signal when the counting value of the low-frequency clock signal meets the precision calculation requirement.
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