CN109067394A - On piece clock calibrating device and calibration method - Google Patents
On piece clock calibrating device and calibration method Download PDFInfo
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- CN109067394A CN109067394A CN201811031597.0A CN201811031597A CN109067394A CN 109067394 A CN109067394 A CN 109067394A CN 201811031597 A CN201811031597 A CN 201811031597A CN 109067394 A CN109067394 A CN 109067394A
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- 230000006266 hibernation Effects 0.000 description 4
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/0802—Details of the phase-locked loop the loop being adapted for reducing power consumption
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
- H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
- H03L7/0992—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider comprising a counter or a frequency divider
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Abstract
The present invention discloses a kind of on piece clock calibrating device and calibration method, which includes RC oscillating circuit, frequency dividing calibration circuit and benchmark high frequency clock source, and frequency dividing calibration circuit includes timer conter, frequency dividing ratio computing module and high frequency clock starting module；Timer conter receives the low-frequency clock signal of frequency divider output, and intermittent to high frequency clock starting module output enabling signal；After high frequency clock starting module receives enabling signal, start benchmark high frequency clock source；High frequency clock signal is exported to frequency dividing ratio computing module after the starting of benchmark high frequency clock source；Frequency dividing ratio computing module receives original RC clock signal and high frequency clock signal, and calculates frequency dividing ratio, and the numerical value of frequency dividing ratio is exported to frequency divider；Frequency divider divides original RC clock signal based on frequency dividing ratio and exports the low-frequency clock signal after calibration.This method realizes the calibration of clock frequency using above-mentioned calibrating installation.The present invention can be realized calibrating to low-frequency clock signal for low-power consumption.
Description
Technical field
The present invention relates to clock signal process field more particularly to a kind of on piece clock calibrating device and apply this dress
Set the on piece clock correcting method for realizing clock signal calibration.
Background technique
The chips such as CPU are arranged in existing electronic equipment on circuit boards mostly, when in running order due to chips such as CPU
The electric energy of consumption is more, and therefore, chip operation is often arranged in wake-up (Active) mode or suspend mode in present electronic equipment
(Sleep) mode, in the wake mode, with the work of higher frequency, and the electric energy consumed is more for chip operation, and in suspend mode
Under mode, with the work of lower frequency, the electric energy of consumption is less.In general, when chip needs to be implemented instruction, such as need logarithm
When according to being handled, awakening mode will be entered, be in normal operating conditions, it, will when chip does not need to handle data
Into suspend mode, to save electric energy consumed by chip.
Since chip operation is in awakening mode and suspend mode, working frequency is different, it is therefore desirable to be provided not
With clock frequency to meet the requirement of working frequency of the chip under two kinds of different modes.Also, work as chip from awakening mode
When into suspend mode, need that clock frequency is accurately switched to low frequency mode, and when chip enters wake-up from suspend mode
After mode, need frequency error factor to high frequency mode accurately.It, can after entering awakening mode from suspend mode for chip
The recovery for correctly carrying out clock signal frequency, has higher requirement to the precision of low power consuming clock.
Currently, most of electronic equipment provides sleep clock signal using low frequency crystal oscillator, due to crystal oscillator
Clock accuracy it is preferable and low in energy consumption, so the communication systems such as GPS, bluetooth, wifi chip suspend mode timing be used as low function
It consumes signal source of clock and is widely applied.Recently as the rise of mobile communication and IOT equipment, have to the volume of equipment smaller
Requirement, have lower expectation to cost, thus on piece low power consuming clock signal source (such as RC oscillator) be widely used and
Primary study.But the precision of on piece low power consuming clock signal source is poor, with the difference of temperature change, voltage fluctuation and technique
And there is large change, it is therefore desirable to calibrate to the frequency of on piece low power consuming clock signal.
Method for enhancing the reliability that clock signal of system restores used in the system with dormancy awakening process,
The prior art is mainly to pass through improve the precision of clock source, improve communication system to the tolerance or utilization of clock signal errors
Strategy is calibrated to solve.
Solve the problems, such as that clocking error is method the most direct by the method for improving the precision of clock source, so traditional
Low frequency and low power consumption signal source of clock is all inclined to using crystal oscillator as clock source.But it is set of today using Resources on Chip
The method of meter low frequency and low power consumption clock source receives basic limitation from physical layer, is unable to reach comparable with crystal oscillator
Performance.For example, the deviation for being reduced technique level using the method to capacitance resistance adjustment believes clock after chip manufacturing
The influence of number source frequency absolute value, but the relative temperature variation of capacitance resistance cannot be reduced and bring relatively significant deviation with
And influence of the voltage fluctuation to transistor.Cost is increased in chip factory adjustment test simultaneously, and with chip aging clock
The frequency of signal can also be gradually deviated from the result of factory adjustment.
And the tolerance that communication system can be improved to clocking error in requirement of the communication protocol to clock accuracy is reduced, still
General communication system is communicated in accordance with set agreement, such as bluetooth, wifi.Existing technology is in estimation from setting
Standby wakeup time point nearby increases keep-alive transmission number, is avoided with this because of master-slave equipment lost contact caused by the error of clock signal
The case where.Therefore, the prior art is to be reduced by improving the compatibility to remaining bluetooth equipment because other equipment clock misses
The case where disconnecting caused by difference is excessive.But Bluetooth protocol specification pair is still followed when a certain equipment is used as from equipment
Clock signal permissible accuracy because it cannot be guaranteed that remaining bluetooth equipment that identical clock is also used when as main equipment is extensive
Compound method, so this method is less applicable in the general communication system for having clear Communications Protocol Specification.
Since in the hibernation mode, the chips such as CPU can be closed, so in the prior art, by clock signal calibration
Scheme is all to be calibrated in the wake mode.And under suspend mode and awakening mode, the temperature and voltage status of chip have
Variation, so causing the operation calculated in the wake mode low power consuming clock that can all bring biggish error.For example,
In scheme disclosed in the Chinese invention patent application of Publication No. CN105873190A, when iterating to calculate calibration factor, utilize
The timing that real system timing subtracts recovery is iterated as calibration error, and at one of reception real system timing
I.e. can be in suspend mode also has the time for being in awakening mode to low power consuming clock in span, and which results in calibration error calculating
Inaccuracy.When being in suspend mode and awakening mode low power consuming clock signal frequency value difference is larger, school will lead to
Quasi- failure, even resulting in chip cannot wake up at preset time point to set time with timing, call out to influence chip
The frequency accuracy of clock signal after waking up.
Summary of the invention
The main object of the present invention be to provide it is a kind of can accurately to chip low-frequency clock signal in the hibernation mode into
Row calibration on piece clock calibrating device, in order to after system is waken up clock frequency it is lasting calibrate, from work shape
State can calibrate during entering dormant state according to the objective law ladder interval of temperature change, and enter suspend mode shape
It is periodically calibrated after state.
It is a further object of the present invention to provide a kind of on piece clock alignments realized using clock calibrating device in sheet above
Method exports after dynamic frequency dividing calibration and determines frequency rather than frequency calculated value.
In order to realize above-mentioned main purpose, on piece clock calibrating device provided by the invention, including RC oscillating circuit with
And frequency dividing calibration circuit, frequency dividing calibration circuit include the frequency divider for receiving the original RC clock signal of RC oscillating circuit output；Its
In, which further includes benchmark high frequency clock source, frequency dividing calibration circuit further include timer conter, frequency dividing ratio computing module and
High frequency clock starting module；Timer conter receives the low-frequency clock signal of frequency divider output, and it is intermittent to high frequency when
Clock starting module exports enabling signal；After high frequency clock starting module receives enabling signal, start benchmark high frequency clock source；Benchmark
High frequency clock signal is exported to frequency dividing ratio computing module after the starting of high frequency clock source；Frequency dividing ratio computing module receives original clock letter
Number and high frequency clock signal, and calculate frequency dividing ratio, the numerical value of frequency dividing ratio exported to frequency divider；Frequency divider is based on frequency dividing ratio pair
Original RC clock signal carries out fractional frequency division and exports the low-frequency clock signal after calibration.
By above scheme as it can be seen that the present invention is after chip enters suspend mode, a high frequency is utilized by intermittent
The high frequency clock signal of signal source of clock output calibrates the low-frequency clock signal of output, and entire calibration process is in chip
It is executed under suspend mode, it in this way can be to avoid calibration process executes in the wake mode and causes calibration is inaccurate to ask
Topic.On the other hand, since the calibration of clock frequency is intermittent execution, rather than lasting execution, such benchmark high frequency
Clock source is not to work long hours, but intermittent work, to reduce the electric energy of benchmark high frequency clock source consumption.Due to
The electric energy of RC oscillating circuit consumption is very low, therefore the power consumption of entire on piece clock calibrating device is very low.
One Preferable scheme is that, timer conter calculate it is multiple calibration the moment times, and reach each school
When punctual quarter, one-shot signal is exported to high frequency clock starting module.
It can be seen that the time at multiple calibration moment is calculated by timer conter, it is every so as to accurately determine
At the time of once needing to be implemented calibration.
Further embodiment is that timer conter records the time of multiple calibration cycles, and successively in each calibration
When period reaches, one-shot signal is exported to high frequency clock starting module；Reach the last one calibration cycle recorded
It is the setting period with the last one calibration cycle after time, exports enabling signal to high frequency clock starting module.
Preferably, the time of multiple calibration cycles is and the process in practical application scene from working condition to dormant state
The time for multiple calibration cycles that the rule of middle chip temperature changing speed matches.
As it can be seen that timer conter is reached by recording time of multiple calibration cycles, and successively in each calibration cycle
When issue enabling signal, it can be ensured that the accurate execution of calibration.
Further scheme is that timer conter is provided with multiple registers, and each register records a calibration week
The quantity of the minimum step time cycle of phase, it is preferred that the cycle time of multiple calibration cycles becomes according to temperature after entering suspend mode
Law successively gradually increases.
It can be seen that when chip just enters suspend mode from awakening mode, since the temperature of chip is higher, RC oscillation
The original RC clock frequency of circuit is higher, therefore calibration cycle is shorter, and with the increase of dormancy time, the temperature of chip is gradually
It reduces, the original RC clock frequency of RC oscillating circuit also decreases and keep stable, and calibration cycle will grow longer, in this way can be with
Ensure the accuracy calibrated, and the power consumption of on piece clock calibrating device can be saved.
Optional scheme is, frequency dividing ratio computing module has a division circuit, division circuit using a preset value divided by point
Frequency calibration value calculates the numerical value for obtaining frequency dividing ratio.
It can be seen that frequency dividing ratio computing module can quickly calculate frequency dividing ratio by preset value, so that frequency dividing ratio
It calculates simple, quick.
Further embodiment is, when frequency dividing calibration value is that the count value of original RC clock signal meets accuracy computation requirement,
The count value of high frequency clock signal.
As it can be seen that high frequency clock signal when by calculating the required precision for meeting the original RC clock signal of calibration accuracy requirement
Number can be convenient frequency dividing ratio computing module as the divisor of division circuit and quickly calculate frequency dividing ratio.Due to when different
It inscribes, the count value of the corresponding high frequency clock signal of count value of identical original RC clock signal is not identical, calculates in this way
The frequency dividing ratio come is not also just identical, to realize the calibration to low-frequency clock signal.
To realize above-mentioned another object, on piece clock correcting method provided by the invention include: RC oscillating circuit to point
Frequency device exports original RC clock signal, and frequency divider is based on frequency dividing ratio and divide simultaneously output low frequency clock to original RC clock signal
Signal；Also, frequency divider is to timer conter output low frequency clock signal, and intermittent sends out to high frequency clock starting module
Send enabling signal；After high frequency clock starting module receives enabling signal, start benchmark high frequency clock source；It opens in benchmark high frequency clock source
High frequency clock signal is exported to frequency dividing ratio computing module after dynamic；Frequency dividing ratio computing module receives original RC clock signal and high frequency
Clock signal, and frequency dividing ratio is calculated, the numerical value of frequency dividing ratio is exported to frequency divider；Frequency divider is based on frequency dividing ratio to original RC clock
Signal carries out fractional frequency division and exports the low-frequency clock signal after calibration.
By above scheme as it can be seen that the present invention is after chip enters suspend mode, a high frequency is utilized by intermittent
The high frequency clock signal of signal source of clock output calibrates original RC clock signal, and entire calibration process is in chip
It is executed under suspend mode, it on the one hand can be to avoid calibration process executes in the wake mode and causes calibration is inaccurate to ask
Topic.On the other hand, since the calibration of clock frequency is intermittent execution, rather than lasting execution, such benchmark high frequency
Clock source is not to work long hours, but intermittent work, to reduce the electric energy of benchmark high frequency clock source consumption.Due to
The electric energy of RC oscillating circuit consumption is very low, therefore the power consumption of entire on piece clock calibrating device is very low.
Detailed description of the invention
Fig. 1 is the song that the frequency of RC oscillating circuit is changed over time with the variation of time and the temperature of RC oscillating circuit
Line chart.
Fig. 2 is the structural block diagram of on piece clock calibrating device embodiment of the present invention.
Fig. 3 is the work flow diagram of timer conter on piece clock calibrating device embodiment of the present invention.
Fig. 4 is the work flow diagram of on piece clock calibrating device embodiment medium-high frequency clock starting module of the present invention.
Fig. 5 is the structural block diagram of frequency dividing ratio counting circuit on piece clock calibrating device embodiment of the present invention.
Fig. 6 is the flow chart of on piece clock correcting method embodiment of the present invention.
The invention will be further described with reference to the accompanying drawings and embodiments.
Specific embodiment
On piece clock calibrating device of the invention, which is applied, to be had on the integrated circuits of chips such as CPU, and CPU can work
In awakening mode and suspend mode, on piece clock calibrating device for generate chip in the hibernation mode used in low frequency when
Clock signal.On piece clock correcting method of the invention generates low-frequency clock signal using above-mentioned on piece clock calibrating device.
On piece clock calibrating device embodiment:
The on piece clock calibrating device of the present embodiment is used for after chip enters suspend mode from awakening mode, when generating low frequency
Clock signal is used for chip.After chip is switched to suspend mode by awakening mode, the temperature of chip will be reduced gradually, and
The clock frequency of RC oscillating circuit also decreases, and the variation relation trend of the temperature of chip, time and frequency is as shown in Figure 1.
It can be seen from figure 1 that chip entered suspend mode from awakening mode at 0 second, and in 25 seconds upon entering a sleep mode, the temperature of chip
Degree is gradually decrease to 38 DEG C from 60 DEG C, and the frequency of the clock signal of RC oscillating circuit output is also gradually decrease to from 800K hertz
798.80K hertz.Numerical value in Fig. 1 above each dot is temperature, and the numerical value below dot is the clock of RC oscillating circuit
The frequency of signal.It will be seen from figure 1 that over time, the temperature of chip gradually decreases, and the clock of RC oscillating circuit
The frequency of signal also gradually tends to be steady.
The central scope of the present embodiment is that one high frequency clock signal source of setting is come to frequency dividing low-frequency clock obtained letter
It number is calibrated, and the present embodiment carries out frequency dividing using original RC clock signal of the frequency divider to RC oscillating circuit and obtains low frequency
Clock signal.Referring to fig. 2, the present embodiment has RC oscillating circuit 10, benchmark high frequency clock source 40 and frequency dividing calibration circuit 70,
Wherein, frequency dividing calibration circuit 70 includes that frequency divider 20, timer conter 30, high frequency clock starting module 50 and frequency dividing ratio calculate
Module 60.
Since the power consumption of RC oscillating circuit 10 is very low, and the power consumption in benchmark high frequency clock source 40 is higher, therefore, the present embodiment
It is intermittent starting benchmark high frequency clock source 40, that is, the calibration of frequency of low-frequency clock signal is intermittent progress
, it is not lasting progress.In this way, the power consumption of entire on piece clock calibrating device can be saved.From fig. 1, it can be seen that due to core
After piece enters dormant state from wake-up states, the frequency of original RC clock signal be will fall rapidly upon, and when by one section
Between after, frequency variation tends to be steady, therefore, within the short period after chip enters suspend mode, calibration cycle is shorter, with
The time increase, calibration cycle will gradually increase, and on the one hand can ensure that chip enters after suspend mode, when the low frequency of acquisition
On the other hand the accuracy of clock signal can further save the power consumption of on piece clock calibrating device.
In the present embodiment, RC oscillating circuit 10 is RC running clock generation circuit, and effect is to provide calibration to be divided
Original RC clock source, in general, original RC clock signal is the clock signal with upper frequency.And benchmark high frequency clock source
40 be a High-precision high-frequency clock source, and effect is to provide for school reference of reference high frequency clock signal, and is frequency dividing ratio
The division circuit of computing module 60 provides driving.Since the high frequency clock signal that benchmark high frequency clock source 40 provides is for calibrating
Clock signal, therefore the frequency of high frequency clock signal needs the frequency higher than original RC clock signal, to realize to original
The calibration of RC clock signal.
The frequency for the original RC clock signal that RC oscillating circuit 10 exports changes with the temperature change of chip, i.e., such as Fig. 1
Shown in curvilinear motion.After frequency divider 20 receives the original RC clock signal that RC oscillating circuit 10 exports, it is based on frequency dividing ratio pair
Original RC clock signal is divided, to form the lower low-frequency clock signal of frequency so that the chips such as CPU are in suspend mode
Lower use.
In the present embodiment, frequency divider 20 is a random number division function module, and effect is to calculate mould according to frequency dividing ratio
The frequency dividing ratio that block 60 exports divides original RC clock signal, obtains low-frequency clock signal.Preferably, in the present embodiment,
The error for the low-frequency clock signal that frequency divider 20 exports is to be uniformly distributed at random, and theoretically, frequency dividing error desired value is zero, practical
On, error only is determined by original RC clock signal and high frequency clock signal, if in calibration cycle, original RC clock signal with
Within the allowable range, then the low-frequency clock signal for dividing output can then be met the requirements the error of high frequency clock signal.
Further, frequency divider 20 is based on frequency dividing ratio and carries out fractional frequency division to original RC clock signal, to export calibration
Low-frequency clock signal afterwards, for example, frequency dividing ratio is not an integer, but a decimal, such as frequency dividing ratio is 50.5, then divides
When frequency device 20 is divided, interval is used 50 and 51 as frequency dividing ratio, so that the low-frequency clock signal after frequency dividing
Frequency is in the error range of permission.
Timer conter 30 is used for intermittent starting benchmark high frequency clock source 40, in this way, between frequency dividing ratio computing module 60
The numerical value for calculating frequency dividing ratio of having a rest property, frequency divider 20 is also the intermittent numerical value for receiving frequency dividing ratio, to calculate point
Frequency ratio.From fig. 1, it can be seen that temperature will reduce rapidly after the chips such as CPU enter suspend mode from awakening mode, RC oscillation
The original RC clock frequency of circuit 10 also reduces rapidly therewith, and after certain time, original RC clock frequency will
It tends towards stability.Therefore, timer conter 30 will be after chip enters suspend mode, within a short period of time, and calibration cycle is shorter,
Over time, the calibration cycle of low-frequency clock signal is gradually increased.Therefore, timer conter 30 starts benchmark high frequency
The period of clock source 40 is not fixed, but after chip enters suspend mode, the time of a cycle is shorter, subsequent
Calibration cycle will gradually increase, and after some period of time, calibration cycle will become the fixed period.
It is more by calculating after timer conter 30 receives the original RC clock signal that frequency divider 20 exports in the present embodiment
The time at a calibration moment, it is preferred that the time at each calibration moment is the end time of each calibration cycle.It reaches
When each calibration moment, timer conter 30 exports enabling signal to high frequency clock starting module 50, and high frequency clock starts mould
After block 50 receives enabling signal, start benchmark high frequency clock source 40, while to 60 output signal of frequency dividing ratio computing module, dividing
Frequency ratio computing module 60 will export a numerical value to frequency divider 20, which is exactly the frequency dividing calculated of frequency dividing ratio computing module 60
The numerical value of ratio.
The time of each calibration cycle for ease of calculation in the present embodiment, can recorde more in timer conter 30
Time of a calibration cycle, such as time, the time of second calibration cycle of first calibration cycle of record etc..Due in core
Piece entered in the short period after suspend mode, calibration operation need it is frequent carry out, and calibration cycle is pushing away at any time
What shifting gradually increased, therefore, timer conter 30 needs to record the time of several calibration cycles of front, when RC oscillating circuit 10
The original RC clock cycle frequency tend towards stability after, fixed calibration cycle can be used and calibrated.
Therefore, timer conter 30 records the time of multiple calibration cycles, and successively when each calibration cycle reaches,
Such as in each calibration cycle arrival time, one-shot signal is exported to high frequency clock starting module 50.Also, it reaches
After the last one the calibration cycle time recorded, if fruit chip keeps suspend mode, then with the last one calibration week
Phase is the setting period, exports enabling signal to high frequency clock starting module.Stop for example, timer conter 30 has recorded chip entrance
The time of 10 calibration cycles before sleep mode is later, after the time of 10 calibration cycles in front, such as fruit chip
Still in suspend mode, then it is the period set that subsequent each calibration cycle, which is all with the last one calibration cycle recorded,
In each last moment for reaching the setting period, one-shot signal is exported to high frequency clock starting module 50, to start
Clock signal calibration operation.
In order to adapt to the job requirement of different chips, the timer conter 30 of the present embodiment needs with the following functions:
Calibration cycle changing rule can be configured according to different chips；In chip after suspend mode wake-up, calibration cycle automatically switches
It will be calibrated since first calibration cycle after entering suspend mode next time to initial value；Can enable and
Calibration function is closed, that is, can according to need the function of starting calibration or close calibration function.
Preferably, multiple registers are provided in timer conter 30, each register records a calibration cycle most
The quantity of small stepping time cycle.For example, the minimum step time REG_DELT that setting calibration uses in the present embodiment, the time
The greatest common divisor of the time span of multiple calibration cycles.For example, chip enters after suspend mode, first calibration cycle institute
The cycle duration needed is the duration REG_TIM0 of minimum calibration cycle, each later calibration cycle is the minimum step time
Several times, the numerical value therefore, in multiple registers stored is an integer, which means actual registers
Corresponding calibration cycle is the multiple of minimum step time.For example, first calibration cycle is the minimum step time, then first
The numerical value of calibration cycle corresponding registers storage is exactly 1, and the second calibration cycle is 10 times of minimum step time, then and second
The numerical value of the corresponding register storage of a calibration cycle is exactly 10, and third calibration cycle is 25 times of minimum step time, then and the
The numerical value of the corresponding register storage of three calibration cycles is exactly 25, is so analogized.
Since the timer counter time is as unit of being up to the several seconds, the time value of timer conter 30 needs 32bit
Register carry out storing data, if carrying out storing data using a register to each time, it will cause the wasting of resources,
It is especially become apparent from when calibration cycle number comparatively dense changes, therefore, the present embodiment provides a kind of design sides for saving register
Case.
Multiple registers are arranged to store multiple preset numerical value in the present embodiment, and the numerical value stored includes most small step
Into time REG_DELT, need different cycles number REG_NUM for calibrating etc., and also set up multiple registers for store from
The number for the REG_DELT that the current alignment period differs to next calibration cycle, the i.e. time in current alignment period are most small steps
Into the numerical value of the multiple of time REG_DELT, it is preferred that record each calibration week respectively using N+1 calibration cycle register
Phase is the numerical value of the multiple of minimum step time cycle, and REG_ can be used in the numerical value of each calibration cycle registers storage
0 to REG_N indicates.In addition it is also necessary to one register of numerical value is used to store the duration REG_TIM0 of minimum calibration cycle, it is excellent
Choosing, the duration REG_TIM0 of minimum calibration cycle is a preset default value, after which enters suspend mode, the
The time span of one calibration cycle.
The workflow of timer conter 30 is introduced below with reference to Fig. 3.Firstly, executing step S1, setting total count value is
The numerical value of minimum calibration cycle, i.e., after chip enters suspend mode, under initial time, set total count value REG_SUM as
The numerical value of minimum calibration cycle REG_TIM0.Preferably, total count value REG_SUM is stored in a register, the deposit
The numerical value of device can be erasable.Then, step S2 is executed, judges whether the count value TIM_CNT of timer conter is equal to total
Numerical value REG_SUM, if so, executing step S4, timer conter 30 sends one-shot signal to high frequency clock starting module 50.
If the count value TIM_CNT of timer conter is less than total count value REG_SUM, S3, the meter of timer conter are thened follow the steps
Numerical value is primary from increasing, and returns to step S2.
After executing step S4, indicates that the calibration of clock signal has executed the calibration of a cycle, need to calculate next
The time of calibration cycle, and after the time span by current period, enabling signal next time is retransmited, next time
Enabling signal sending time at the time of be current alignment end cycle.Therefore, it is necessary to accurately calculate the current alignment period
End time.In the present embodiment, which when on the one hand calculating the period being currently located by number of cycles counter in period, separately
On the one hand, the time span that current period is calculated by calibration cycle register is the number of minimum step time REG_DELT
Again, the time span of new calibration cycle is thus calculated.
Therefore after executing step S4, step S5 is executed at once, the quasi-periodic number of high-ranking officers is primary from increasing, that is, the period
The count value of a counter NUM adds 1, then executes step S6, judges whether the sequence for reaching next calibration cycle register
Number numerical value.For example, current calibration cycle is the 2nd calibration cycle, the serial number of corresponding calibration cycle register is 2, then
When executing step S5, the quasi-periodic number of high-ranking officers is primary from increasing, then the serial number of calibration cycle becomes 3, and therefore, step S6 is judgement
The count value of current period counter whether be one of calibration cycle register serial number.If current period number
The count value of counter is the serial number of one of calibration cycle register, thens follow the steps S7, obtains corresponding calibration cycle
The numerical value of registers storage.For example, obtaining the numerical value of the calibration cycle registers storage of corresponding serial number, such as obtain serial number
For 3 calibration cycle registers store up numerical value REG_3, such as the numerical value be 50.
What is indicated due to the numerical value of each calibration cycle registers storage be the time span of the calibration cycle is most
Therefore the multiple of small stepping time REG_DELT obtains the numerical value (assuming that the numerical value is N) of calibration cycle registers storage
After, set a variable M, variable M since 0 from increasing, and it is every by one minimum step time REG_DELT after oneself
Increase primary, when variable M is from increasing N, expression has arrived at the finish time in current alignment period, can send one-shot and believe
Number.
Therefore, after executing step S7, step S9, after a minimum step time REG_DELT, variable M are executed
Numerical value it is primary from increasing, then execute step S10, judge whether minimum step time cycle calculated value M posts greater than calibration cycle
The numerical value of N of storage, if so, otherwise executing step S11 returns to step S9, i.e., using a minimum step time REG_
After DELT, the numerical value of variable M is primary from increasing.
In step S11, the numerical value of variable M is added with the numerical value of minimum calibration cycle duration REG_TIM0, is obtained new
Total count value REG_SUM, then returns to step S2, judges whether the count value TIM_CNT of timer conter has counted
To new total count value REG_SUM, calculated if so, then enabling primary calibration, i.e. transmission one-shot signal to high frequency clock opens
Dynamic model block 50.As it can be seen that by judge the count value TIM_CNT and total count value REG_SUM of timer conter it is whether equal come into
At the time of one step is a calibration cycle at the time of determining current, so that it is guaranteed that enabling signal is accurate at the time of transmission.
In step S6, if number of cycles is not equal to preset number, step S8 is needed to be implemented, judges number of cycles
Whether be greater than maximum value, for example, the maximum number of cycles REG_NUM that calibrates of needs of registers storage is 10, then if
Current number of cycles has been to then follow the steps S12 more than 10, judges whether chip is in suspend mode, such as in not
Sleep mode thens follow the steps S13, obtains the numerical value of the last one calibration cycle registers storage, and executes step S9, if
Not in suspend mode, indicates that chip has waken up, then directly exit the calibration of low-frequency clock, use higher frequency
Work.If in step S8, current number of cycles is not more than maximum number of cycles, then S5, period are returned to step
Counter is primary from increasing, that is, jumps to next calibration cycle.
As it can be seen that timer conter 30 is not frequent transmission enabling signal, but intermittent transmission enabling signal, and
And the numerical value that is stored up by multiple registers of the sending time of enabling signal and in conjunction with the count value of multiple counters come real
It is existing, so that timing sends enabling signal to high frequency clock starting module 50.
The workflow of high frequency clock starting module 50 is introduced below with reference to Fig. 4.Firstly, executing step S21, judge whether
Enabling signal is received, if so, executing step S22, opens the power supply in benchmark high frequency clock source 40, and execute step S23, if
Required parameter when benchmark high frequency clock source 40 works is set, and executes step S24, opens benchmark high frequency clock source 40, this
When, benchmark high frequency clock source 40 starts and works.But benchmark high frequency clock source 40 is not that starting immediately enters stabilization later
Working condition, i.e., benchmark high frequency clock source 40 need by after a certain period of time could output frequency it is stable high frequency clock letter
Number, therefore, it is necessary to execute step S25, judge whether to reach the benchmark high frequency clock source stable working time, if so, executing step
Otherwise rapid S26 is continued waiting for, until benchmark high frequency clock source 40 enters stable working condition.
In step S26, after benchmark high frequency clock source 40 enters steady-working state, benchmark high frequency clock source 40 is opened
Buffer, data are obtained from the buffer in benchmark high frequency clock source 40, i.e., by the high frequency clock in benchmark high frequency clock source 40
Signal is exported to frequency dividing ratio computing module 60.Then, step S27 is executed, judges whether the work of clock signal calibration terminates, such as
The clock signal calibration of fruit current period terminates, and thens follow the steps S28, closes benchmark high frequency clock source 40, and close
The power supply in benchmark high frequency clock source, so that it is guaranteed that benchmark high frequency clock source 40 is not in running order for a long time, but only
Have and receive in running order in enabling signal later a period of time, and after primary calibration terminates, stops at once
Work, avoids consuming a large amount of electric energy due to benchmark high frequency clock source 40 works long hours.
The high frequency clock signal that the high clock source 40 of benchmark exports is for calibrating the frequency of low-frequency clock signal, specifically
, the high frequency clock letter output that benchmark high frequency clock source 40 exports to frequency dividing ratio computing module 60.It is divided below with reference to Fig. 5 introduction
Than the working principle of computing module 60.The major function of frequency dividing ratio computing module 60 is parameter required for calculating frequency divider 20,
That is frequency dividing ratio.In the present embodiment, frequency dividing ratio is not fixed, but according to the original RC clock signal of RC oscillating circuit 10
Frequency and the frequency of high frequency clock signal determine the specific value of frequency dividing ratio.
Participate in Fig. 5, frequency dividing ratio computing module 60 include register 61, division circuit 62, high frequency clock cycles counter 63,
High frequency clock cycles register 64 and original RC clock cycle counter 65.
Wherein, register 61 is used to store the dividend of division circuit 62, and the numerical value of dividend is one preset
Numerical value, it is assumed that the reckoning process of numerical value Value is described below in numerical value Value.
Assuming that the maximum frequency of the original RC clock signal of RC oscillating circuit 10 is fmaxrcMHz, error precision are Dppm (hundred
Ten thousand/D), high frequency clock frequency is fdcxoMHz.By high frequency crystal oscillator come in terms of RC oscillating circuit 10 original RC clock letter
Number frequency worst error be 1/fdcxo, if desired meet the required precision for calibrating original RC clock signal, then necessarily require to count
Calculate the error that trueness error is less than original RC clock signal itself, it is assumed that need the number of cycles of n original RC clock signals
The original RC clock signal for meeting required precision can be calculated, and the periodicity of corresponding high frequency clock signal is N, it can
Derive formula 1 and formula 2:
(formula 1)
(formula 2)
Also, the expression of formula 3 can be used in the relationship between the frequency of original RC clock signal and the frequency of high frequency clock signal.
(formula 3)
Assuming that the low-frequency clock frequency of the frequency dividing output of frequency divider 20 is floscMHz, the then frequency of low-frequency clock signal and original RC
The frequency dividing ratio of the frequency of clock signal is when meeting the requirement of formula 4, it can when meeting low-frequency clock signal all frequencies variation
Color seperation grating precision.
(formula 4)
When " > " of formula 2 is taken as "=", then join the value Value to be saved of register 61 are as follows:
(formula 5)
Wherein, parameter n, original RC clock signal maximum frequency fmaxrc, error precision D and frequency dividing after low-frequency clock frequency flosc
It is all datum.Therefore only it is to be understood that in the duration of n original RC clock signal high frequency clock signal count value N, Ji Keji
Calculation obtains frequency dividing ratio.From formula 5 it is found that Value value is N times of frequency dividing ratio, that is, original clock frequency fdcxoWith low-frequency clock
Frequency floscN times of ratio.
Division circuit 62 is a shift division circuit, it is preferred that division circuit 62 is driven by high frequency clock signal, thus
Accelerate the arithmetic speed of division circuit 62, shortens prover time.High frequency clock is closed after the completion of calibration calculates, division circuit 62
Also it does not just work, to save the power consumption of entire frequency dividing ratio computing module 60.
Original RC clock cycle counter 65 is used to calculate the number of the original RC clock signal of RC oscillating circuit 10, therefore
Original RC clock cycle counter 65 receives former RC beginning clock signal, and calculates the number of original RC clock signal.Due to this
Embodiment is after meeting the number of cycles of a original RC clock signal of n of calibration accuracy requirement by calculating, to determine corresponding
Therefore the number of cycles N of high frequency clock signal, presets to calculate frequency dividing ratio and meets the original of calibration accuracy requirement
The number n of RC clock signal period, original RC clock cycle counter 65 receive a pulse of original RC clock signal with
Afterwards, the count value of counter is primary from increasing, and when count value reaches n, exports and believe to high frequency clock cycles counter 63
Number.
Number of cycles of the high frequency clock cycles counter 63 for the high frequency clock signal in calculating benchmark high frequency clock source 40,
It namely starts counting when original RC clock cycle counter 65 starts counting, and is counted receiving the original RC clock cycle
Stop counting when the signal that number device 65 is sent, when which is exactly the n period of original RC clock signal when corresponding high frequency
The number of cycles N of clock signal.
High frequency clock cycles register 64 is used to store the count value of high frequency clock cycles counter 63, i.e. stored count value
N, and count value N is sent to division circuit 62.Therefore, division circuit 62 uses Value as dividend, when using high frequency
Clock period register 64 is used as divisor, calculates the numerical value of frequency dividing ratio and output valve frequency divider 20.
Preferably, when calibration starts every time, high frequency clock cycles counter 63 and original RC clock cycle counter 65 are all
Count value need to be reset, that is, count value before is reset, to avoid the accuracy of influence technique.
Since the frequency of original RC clock signal is constantly reduced as the time that chip enters suspend mode lengthens, because
This, the time span for meeting n original RC clock signal periods of calibration accuracy requirement is variation, and high frequency clock signal
Frequency be it is stable, therefore, in different time period, in the cycle time length of n original RC clock signal, corresponding high frequency
The number of cycles N of clock signal is also variation, in this way, the frequency dividing ratio calculated is also not fixed, but with the time
Variation and change, to meet the requirement to the frequency calibration of low-frequency clock signal.
On piece clock correcting method embodiment:
The workflow of on piece clock correcting method of the invention is introduced below with reference to Fig. 6.Firstly, step S31 is executed, RC oscillation
Then circuit output one original RC clock signal executes step S32, frequency divider is based on a preset frequency dividing ratio to original
RC clock signal is divided, and a low-frequency clock signal is formed.Preferably, the frequency dividing of a default is stored in advance in frequency divider
Than, the frequency dividing ratio can according to chip just into suspend mode when the output of RC oscillating circuit original RC clock signal frequency it is true
It is fixed.
Then, step S33 is executed, frequency divider is to the low-frequency clock signal after timer conter output frequency division, timer counter
Device executes step S34, judges whether otherwise reach a calibration moment, continues waiting for if so, thening follow the steps S35.This reality
It applies in example, timer conter sets multiple memories and stores multiple numerical value respectively, including stores each calibration cycle and upper one
The quantity of the minimum step time cycle at a calibration cycle interval, and minimum step time span is also stored, to calculate
The end time of each calibration cycle.Therefore, step S34 is in the finish time for calculating each calibration cycle.
When the finish time for reaching a calibration cycle, S35 is thened follow the steps, timer conter starts mould to high frequency clock
Block sends enabling signal, and high frequency clock starting module executes step S36, starts benchmark high frequency clock source, such as opens benchmark height
The power supply of frequency clock source, and after the high frequency clock signal frequency stabilization in benchmark high frequency clock source, mould is calculated to frequency dividing ratio
Block exports high frequency clock signal.
Then, step S37 is executed, frequency dividing ratio computing module calculates the numerical value of frequency dividing ratio, such as uses a register institute
The preset value of storage calculates n original RC clock frequency periods for meeting calibration accuracy requirement as dividend
Time corresponding high frequency clock signal number of cycles N, use N as divisor, calculate frequency dividing ratio used in frequency divider
Specific value, and the numerical value of frequency dividing ratio is sent to frequency divider.Not due to frequency dividing ratio computing module frequency dividing ratio calculated
It is fixed, but reduces as the frequency of original RC clock signal reduces, therefore, frequency divider application frequency dividing ratio computing module
Frequency dividing ratio calculated come determine frequency dividing after low-frequency clock signal, can guarantee that the frequency of low-frequency clock signal is steady as far as possible
It is fixed, meet the stabilization of chip working frequency in the hibernation mode.
Then, step S38 is executed, frequency divider the calculated frequency dividing ratio of application frequency dividing ratio computing module is to original RC clock signal
It is divided, to obtain new low-frequency clock signal, finally executes step S39, judge whether chip exits suspend mode, such as
It is then no longer to be calibrated to low-frequency clock signal, and be to provide chip used clock signal in the wake mode.If
Chip then returns to step S33 still in suspend mode, again by timer conter calculate next calibration cycle when
Between.Preferably, timer conter determines the time span of several calibration cycles, such as the time span of 10 calibration cycles, and
And after reaching the last one calibration cycle time span, chip then continues to use the last one school still in suspend mode
Quasi-periodic time span determines regularly to calibrate the frequency of clock chip as the calibration cycle of setting.
Certainly, above-mentioned scheme is the preferred embodiment of the invention, and practical application is that can also have more variations,
For example, concrete mode, the change of specific composition of frequency dividing ratio computing module etc. that calibration cycle used calculates, these change not
Implementation of the invention is influenced, also should include within the scope of the present invention.
Claims (10)
1. on piece clock calibrating device, including RC oscillating circuit and frequency dividing calibration circuit, the frequency dividing calibration circuit includes connecing
Receive the frequency divider of the original RC clock signal of the RC oscillating circuit output；
It is characterized by:
The device further includes benchmark high frequency clock source, and the frequency dividing calibration circuit further includes timer conter, frequency dividing ratio calculating mould
Block and high frequency clock starting module；
The timer conter receives the low-frequency clock signal of the frequency divider output, and intermittent to the high frequency clock
Starting module exports enabling signal；
After the high frequency clock starting module receives the enabling signal, start benchmark high frequency clock source；
High frequency clock signal is exported to the frequency dividing ratio computing module after the starting of benchmark high frequency clock source；
The frequency dividing ratio computing module receives the original RC clock signal and the high frequency clock signal, and calculates frequency dividing
Than exporting the numerical value of the frequency dividing ratio to the frequency divider；
The frequency divider carries out fractional frequency division to the original RC clock signal based on the frequency dividing ratio and exports low after calibrating
Frequency clock signal.
2. on piece clock calibrating device according to claim 1, it is characterised in that:
The timer conter calculates the time at multiple calibration moment, and when reaching each described calibration moment, to institute
State high frequency clock starting module output one-shot signal.
3. on piece clock calibrating device according to claim 2, it is characterised in that:
The timer conter records the time of multiple calibration cycles, and successively when each calibration cycle reaches, to
The high frequency clock starting module exports enabling signal；
It is setting week with calibration cycle described in the last one after reaching the calibration cycle time that the last one is recorded
Phase exports cycle start signal to the high frequency clock starting module.
4. on piece clock calibrating device according to claim 3, it is characterised in that:
The timer conter is provided with multiple registers, and each register records the most small step of a calibration cycle
Into the quantity of time cycle.
5. on piece clock calibrating device according to claim 3, it is characterised in that:
The cycle time of multiple calibration cycles successively gradually increases.
6. on piece clock calibrating device according to any one of claims 1 to 5, it is characterised in that:
The frequency dividing ratio computing module has division circuit, and the division circuit is using a preset value divided by frequency dividing calibration value meter
Calculate the numerical value for obtaining the frequency dividing ratio.
7. on piece clock calibrating device according to claim 6, it is characterised in that:
When the frequency dividing calibration value is that the count value of the original RC clock signal meets accuracy computation requirement, the high frequency clock
The count value of signal.
8. on piece clock correcting method, comprising:
RC oscillating circuit exports original RC clock signal to frequency divider, and the frequency divider is based on frequency dividing ratio to the original RC clock
Signal divide and output low frequency clock signal；
It is characterized by:
The frequency divider exports the low-frequency clock signal to timer conter, and intermittent to high frequency clock starting module
Send enabling signal；
After the high frequency clock starting module receives the enabling signal, start benchmark high frequency clock source；
High frequency clock signal is exported to the frequency dividing ratio computing module after the starting of benchmark high frequency clock source；
The frequency dividing ratio computing module receives the original RC clock signal and the high frequency clock signal, and calculates frequency dividing
Than exporting the numerical value of the frequency dividing ratio to the frequency divider；
The frequency divider carries out fractional frequency division to the original RC clock signal based on the frequency dividing ratio and exports low after calibrating
Frequency clock signal.
9. on piece clock correcting method according to claim 8, it is characterised in that:
The timer conter it is intermittent to high frequency clock starting module output enabling signal include: the timer conter meter
The time at multiple calibration moment is calculated, and when reaching each described calibration moment, it is defeated to the high frequency clock starting module
One-shot signal out.
10. on piece clock correcting method according to claim 8 or claim 9, it is characterised in that:
The frequency dividing ratio computing module calculates the numerical value for obtaining the frequency dividing ratio using a preset value divided by frequency dividing calibration value,
In, when the frequency dividing calibration value is that the count value of the low-frequency clock signal meets accuracy computation requirement, the high frequency clock letter
Number count value.
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| CN110308762A (en) * | 2019-06-21 | 2019-10-08 | 广芯微电子（广州）股份有限公司 | A kind of clock frequency calibration method of chip interior clock source |
| CN110324026A (en) * | 2019-06-21 | 2019-10-11 | 广芯微电子（广州）股份有限公司 | A kind of clock frequency detection method of chip interior clock source |
| CN112230711A (en) * | 2020-09-25 | 2021-01-15 | 紫光展锐(重庆)科技有限公司 | Calibration device, calibration method and computer-readable storage medium |
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