CN103901942A - Clock precision calibration method and device for terminal - Google Patents
Clock precision calibration method and device for terminal Download PDFInfo
- Publication number
- CN103901942A CN103901942A CN201210586902.9A CN201210586902A CN103901942A CN 103901942 A CN103901942 A CN 103901942A CN 201210586902 A CN201210586902 A CN 201210586902A CN 103901942 A CN103901942 A CN 103901942A
- Authority
- CN
- China
- Prior art keywords
- clock
- ratio
- terminal
- timing offset
- factor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
The invention relates to terminals, and discloses a clock precision calibration method and device for a terminal. The method comprises the steps of obtaining the time duration from closing of a rapid clock to working of a slow clock, and the timing deviation of the time duration, conducting calculation to obtain the timing deviation proportion according to the time duration and the timing deviation, conducting amortized computation on the timing deviation proportion to correct proportionality coefficients of the slow clock and the rapid clock, and completing calibration of the precision of the slow clock. The aim of calibrating the slow clock is achieved by measuring the timing deviation of the slow clock in the working time duration and correcting the proportionality coefficients of the slow clock and the rapid clock according to the timing deviation, therefore, the precision of the slow clock is calibrated, dependency on the hardware is reduced, the accuracy is improved, power consumption is reduced, the timing deviation is corrected in time, and the receiving performance of the terminal can be further improved.
Description
Technical field
The present invention relates to terminal, particularly for calibration steps and the device of the clock accuracy of terminal.
Background technology
During existing terminal realizes; conventionally can use the crystalline substance of a 26M to shake as system clock; produce timing more accurately, but because terminal is not duty constantly, therefore conventionally can use the slow clock of a 32K; carry out timing controlled when sleep under IDLE; because being brilliant shake, 26M clock produces, so insensitive to temperature variation, more accurate; 32K clock is comparatively responsive to temperature variation, and therefore 32K clock will often calibrate to prevent its accuracy generation deviation.
Such way at present, although saved to a great extent power consumption, but in the process of 32K clock alignment, because employing is the method for hardware calibration, so still need to use 26M clock to count, and under usual condition, because do hardware calibration before, follow-up flow process can further be optimized, by adopting the method for software calibration little deviation, further reduce the dependence of calibration to hardware, more save thereby realize power consumption.
Summary of the invention
The calibration steps and the device that the object of the present invention is to provide a kind of clock accuracy for terminal, make the calibration to clock accuracy, reduces the dependence to hardware, improve accuracy, reduce power consumption, revise in time timing offset, thereby can further promote terminal receptivity.
For solving the problems of the technologies described above, embodiments of the present invention provide a kind of calibration steps of the clock accuracy for terminal, described terminal has fast clock and slow clock, and the clock frequency of described fast clock is greater than the clock frequency of described slow clock, and described fast clock is accurately; Comprise following steps:
A. obtain described fast clock and close, the time span T of described slow clock onset, and timing offset Δ T in described T time span;
B. according to described Δ T and described T, calculate timing offset ratio Δ R;
C. read the scale-up factor of described slow clock and described fast clock; Wherein, the initial value of described scale-up factor obtains by hardware calibration;
D. the described scale-up factor reading is deducted to described timing offset ratio, obtain new scale-up factor, complete the calibration to slow clock accuracy.
Embodiments of the present invention also provide a kind of calibrating installation of the clock accuracy for terminal, described terminal has fast clock and slow clock, and the clock frequency of described fast clock is greater than the clock frequency of described slow clock, described fast clock is accurately, comprises: duration acquisition module, timing offset acquisition module, timing offset ratio computing module, scale-up factor acquisition module, clock alignment module;
Described duration acquisition module is used for obtaining described fast clock closes, the time span T of described slow clock onset;
Described timing offset acquisition module is for obtaining the timing offset Δ T in described T time span;
Described timing offset ratio computing module, for according to described Δ T and described T, calculates timing offset ratio Δ R;
Described scale-up factor acquisition module is for reading the scale-up factor of described slow clock and described fast clock; Wherein, the initial value of described scale-up factor obtains by hardware calibration;
Described clock alignment module, for the described scale-up factor reading is deducted to described timing offset ratio, obtains new scale-up factor, completes the calibration to slow clock accuracy.
Embodiment of the present invention in terms of existing technologies, is closed by obtaining fast clock, the time span of slow clock onset, and timing offset in this time span; And calculate accordingly timing offset ratio; The conversion of timing offset ratio is revised the scale-up factor of slow clock and fast clock, completed the calibration to slow clock accuracy.Due to by measuring the timing offset in onset time section, and according to the scale-up factor of the slow clock of this timing offset correction and fast clock, reach the object of the slow clock of calibration, therefore, make the calibration to slow clock accuracy, reduce the dependence to hardware, improve accuracy, reduce power consumption, revise in time timing offset, thereby can further promote terminal receptivity.
In addition, in described steps A, comprise following sub-step:
In each terminal, after sleep state is waken up, described terminal is received paging, and obtains the length length of one's sleep, as described T; Wherein, described terminal described fast clock within the sleep state time period is closed, described slow clock onset;
The reception data of receiving paging are carried out to channel estimating, obtain the timing offset amount in the length length of one's sleep, as described Δ T.
Because terminal is within the sleep state time period, fast clock is closed, slow clock onset, and the length of one's sleep, length was easy to obtain, and all can go to receive paging after each terminal is waken up, can calculate timing offset in length of one's sleep length according to receiving data, therefore, obtain length and the timing offset that produces in the time period thereof the length of one's sleep, can further make the calibration to slow clock accuracy, reduce dependence to hardware.
In addition, can pass through directly to calculate the ratio of described Δ T and described T, and using described ratio as described Δ R, thereby obtaining timing offset ratio, computing method are simple, reduce clock accuracy and calibrate the lasting time, thereby further reduce power consumption.
In addition, can also calculate timing offset ratio by following three kinds of modes:
The first: the size of more described Δ T and default threshold value; If described Δ T is less than or equal to default threshold value, calculate the ratio of described Δ T and described T, and using described ratio as described Δ R; If described Δ T is greater than default threshold value, calculate the ratio of described default threshold value and described T, and using described ratio as described Δ R.
The second: the average of calculating default number Δ T; Calculate the average of the T that described default number Δ T is corresponding; Calculate the ratio of the average of described Δ T and the average of described T, using described ratio as described Δ R.
The third: according to the variation tendency of default number Δ T, determine adjusted value; Calculate the ratio of described adjusted value and described T, using described ratio as described Δ R.
By above-mentioned three kinds of computing method, can obtain timing offset ratio comparatively accurately, thereby ensure the robustness of clock accuracy calibration.
Brief description of the drawings
Fig. 1 is according to the process flow diagram of the calibration steps of the clock accuracy for terminal of first embodiment of the invention;
Fig. 2 is the calibration structure schematic diagram according to the clock accuracy for terminal of third embodiment of the invention.
Embodiment
For making the object, technical solutions and advantages of the present invention clearer, below in conjunction with accompanying drawing, the embodiments of the present invention are explained in detail.But, persons of ordinary skill in the art may appreciate that in the each embodiment of the present invention, in order to make reader understand the application better, many ins and outs are proposed.But, even without these ins and outs and the many variations based on following embodiment and amendment, also can realize the each claim of the application technical scheme required for protection.
The first embodiment of the present invention relates to a kind of calibration steps of the clock accuracy for terminal, and the method is applicable to following situation: terminal has fast clock and slow clock, and the clock frequency of fast clock is greater than the clock frequency of slow clock, and fast clock is accurately.Such as, typical fast clock be operate on normal manipulation mode 2G clock (for example: 26MHz, be called for short " 26M clock ") or 3G clock (for example: 30.72MHz), typical slow clock is the 2G clock (for example: 32.768KHz, abbreviation " 32K clock ") that operates on sleep pattern.The flow process of present embodiment as shown in Figure 1, specifically comprises following steps:
Specifically, in each terminal, after sleep state is waken up, terminal is received paging, and obtains the length length of one's sleep, as T; Wherein, terminal fast clock within the sleep state time period is closed, slow clock onset; The reception data of receiving paging are carried out to channel estimating, obtain the timing offset amount in the length length of one's sleep, as Δ T.Because terminal is within the sleep state time period, fast clock is closed, slow clock onset, and the length of one's sleep, length was easy to obtain, and all can go to receive paging after each terminal is waken up, can calculate the timing offset in length of one's sleep length according to receiving data, therefore, obtain length and the timing offset that produces in the time period thereof the length of one's sleep, can further make the calibration to slow clock accuracy, reduce dependence to hardware.
Be 26M clock with fast clock below, slow clock is that 32K clock is that example is specifically described.Terminal, in sleeping, is to save power consumption, conventionally can carry out with chip internal low rate clock the control of timing, the setting regularly of sleep of the normally used 32K of being clock.Because the inaccuracy of 32K clock, it is along with the deviation that temperature variation causes is larger, so in using 32K clock, have some restrictions, such as needs carry out the calibration of 32K clock according to certain condition.The calibration here, the main method adopting is at present hardware calibration, respectively 32K clock and 26M clock are counted respectively at the appointed time, carry out certain association to name a person for a particular job both count results of time, can obtain corresponding X.y the 26M clock of a 32K clock, X is integral part, and y is fraction part.Because 26M clock is accurately, so obtaining after 32K clock and 26M clock proportionate relationship, think that 32K clock is also accurately.
Enter when sleep in terminal, the duration of sleep as required, calculate need N accurately 26M clock as digit, then by this digit according to the proportionate relationship after above-mentioned calibration, be converted to K 32K clock and J 26M clock, wherein:
j=N-K × X.y,
represent downward rounding operation.
In the process using, along with the variation of temperature, can there is certain variation in 32K clock, and just no longer can mate with calibration result before this time, therefore needs to do calibration again.
Relatively slow the interval that consideration temperature variations is waken up with respect to terminal sleep now, terminal is generally slept maximum duration at the lower 2.56s of being of long evolving system (LTE), lower in time division multiple access (TDMA)-synchro system (TD-S) is 2.56s, lower in global system for mobile communications (GSM) is 2.2s, under normal circumstances, during this period of time in temperature variation can difference too not large.
Under idle condition IDLE, each software wakes up after terminal, and terminal all can go to receive paging, can calculate timing offset according to receiving data.And timing offset is generally introduced by so several aspects:
Because the error that 32K clock is introduced, magnitude may be at 10ppm magnitude (ppm:part per million, 1,000,000/), and because the mobile error of introducing calculate according to maximum 500km/h, the ratio 0.46*10 of the light velocity relatively
-6, that is to say that magnitude is less than 1ppm, therefore, can think that the principal element that timing offset is introduced is 32K clock.
In view of conclusions, can obtain the method for present embodiment: by calibration 32K clock, improve the precision of 32K clock.
For the calibration of 32K clock, above-mentioned hardware calibration method be by again to mark 26M clock, accurately represent the time of current 32K clock according to the counting situation of 26M clock.But since timing offset when having obtained sleep awakening here just can utilize this timing offset correction 32K clock accuracy, concrete grammar is as follows:
1. obtain and be waken up terminal sleep time span T before.
2. by the channel estimating of carrying out receiving data, obtain the timing offset amount Δ T of current terminal.
3. calculate the departure calculating after sleep awakening
herein, due to
magnitude very little, be about parts per million (ppm), therefore can by Δ R amplify 10
6doubly,
calculate and storage to facilitate.
4. read 32K clock and 26M clock scale-up factor R
32k/26M, a 32K clock represents R
32k/26Mindividual 26M clock, the initial value of this parameter need to obtain by hardware calibration, such as just start time, fixedly does, and specific practice, referring to related hardware calibration steps, does not repeat them here.R
32k/26Mintegral part be designated as R
32k/26M_int, fraction part is designated as R
32k/26M_floor, conventional Parameter storage method is to use the register of 32, high 16 storage integer-bit, and low 16 storage decimal places, that is:
R
32k/26M＝R
32k/26M_int<<16+R
32k/26M_floor；
In formula, << represents to left shift operation.Computing method are below carried out as basis taking this kind of storage mode.
5. the departure of 1 unit value representative of integral part deviation is 1 26M clock of deviation in each 32K clock,
in order to be consistent with the magnitude of Δ ppm, need to amplify 10
6doubly,
fraction part represents different precision according to its figure place, represents fraction part with 16 the most frequently used 2 system method for expressing, and departure corresponding to the unit deviation value of each fraction part is:
equally, in order to be consistent with the magnitude of Δ ppm, and amplified 10
6, obtain
6. the Δ ppm estimating is before converted parameters R
32k/26Mmodify, amending method is as two formula are listed below:
That is:
Finally gather and obtain:
In formula, mod represents complementation computing.
7. by R
32k/26Mbe updated to
complete the correction to 32K clock.
Compared with prior art, present embodiment is closed by obtaining fast clock, the time span of slow clock onset, and timing offset in this time span; And calculate accordingly timing offset ratio; The conversion of timing offset ratio is revised the scale-up factor of slow clock and fast clock, completed the calibration to slow clock accuracy.Due to by measuring the timing offset of slow clock in onset time section, and according to the scale-up factor of the slow clock of this timing offset correction and fast clock, reach the object of the slow clock of calibration, therefore, make the calibration to slow clock accuracy, reduce the dependence to hardware, improve accuracy, reduce power consumption, revise in time timing offset, thereby can further promote terminal receptivity.
The second embodiment of the present invention relates to a kind of calibration steps of the clock accuracy for terminal.The second embodiment has done further improvement on the first embodiment basis, main improvements are: in the second embodiment, can pass through statistical method, obtain the timing offset ratio of slow clock comparatively accurately, thereby ensure the robustness of clock accuracy calibration.
The computation process of describing for the first embodiment, in actual environment because the impact of some labile factors, as temperature changes repeatedly, multi-path influence and measured deviation etc., causing the adjustment amount in the calibration of slow clock may not be complete, therefore in the process of specific implementation, the measured deviation that need to introduce a variety of causes considers, and obtains measured value comparatively accurately.These class methods have more, such as by multiple averaging, or the method such as observation trend, be the familiar method of industry.Obtaining comparatively accurately after measurement result, can be according to maximum adjustment amount restriction, or the strategy such as trend adjustment, the robustness ensureing to realize when.
Specifically, can calculate by following three kinds of modes the timing offset ratio of slow clock:
The first: the relatively size of Δ T and default threshold value; If Δ T is less than or equal to default threshold value, calculate the ratio of Δ T and T, and using ratio as Δ R; If Δ T is greater than default threshold value, calculate default threshold value and the ratio of T, and using ratio as Δ R.Threshold value herein can make to add up by experiment the empirical value obtaining, such as, using the average of Δ T all values in a day as threshold value.
The second: the average of calculating default number Δ T; Calculate the average of the T that default number Δ T is corresponding; Calculate the ratio of the average of Δ T and the average of T, using ratio as Δ R.Arithmetic mean be in statistics for eliminating the common method of measuring error, calculate simple.
The third: according to the variation tendency of default number Δ T, determine adjusted value; The ratio of calculate adjusting values and T, using ratio as Δ R.Direction and state estimating that trend adjustment strategy changes according to sustainable development within the long term, its concrete mensuration adopts existing method, does not repeat them here.
To sum up, in realizing, take measured deviation etc. into consideration, method is more, but thought is still unified, uses timing estimate deviation amendment 32K clock alignment value out, thereby reaches saving hardware calibration, the object of Hoisting System performance.
The step of the whole bag of tricks is divided above, just in order being described clearly, can to merge into a step or some step is split while realization, is decomposed into multiple steps, as long as comprise identical logical relation, all in the protection domain of this patent; To adding inessential amendment in algorithm or in flow process or introducing inessential design, but the core design that does not change its algorithm and flow process is all in the protection domain of this patent.
Third embodiment of the invention relates to a kind of calibrating installation of the clock accuracy for terminal, as shown in Figure 2, comprises: duration acquisition module, timing offset acquisition module, timing offset ratio computing module, scale-up factor acquisition module, clock alignment module.
Wherein, duration acquisition module is used for obtaining fast clock closes, the time span T of slow clock onset; Specifically, duration acquisition module after sleep state is waken up, obtains the length length of one's sleep, as T in each terminal; Wherein, terminal fast clock within the sleep state time period is closed, slow clock onset.
Timing offset acquisition module is for obtaining the timing offset Δ T of slow clock in T time span; After terminal is received paging, the reception data of receiving paging are carried out to channel estimating, obtain the timing offset amount in the length length of one's sleep, as Δ T.
Timing offset ratio computing module, for according to Δ T and T, calculates timing offset ratio Δ R; Can directly calculate the ratio of Δ T and T, and using ratio as Δ R.
Scale-up factor acquisition module is for reading the scale-up factor of slow clock and fast clock; Wherein, the initial value of scale-up factor obtains by hardware calibration.
Clock alignment module, for the scale-up factor reading is deducted to timing offset ratio, obtains new scale-up factor, completes the calibration to slow clock accuracy.
In addition, what deserves to be explained is, terminal has fast clock and slow clock, and the clock frequency of fast clock is greater than the clock frequency of slow clock, and fast clock is accurately.Taking the clock frequency of fast clock as 26 megahertz MHz, it is example that the clock frequency of slow clock is 32768 hertz:
The calibrating installation of clock accuracy also comprises: the register of 32, and for storing the scale-up factor R of slow clock and fast clock
32k/26M, wherein, high 16 storage integral part R
32k/26M_int, low 16 storage fraction part R
32k/26M_floor.
Clock alignment module further comprises: graduation of whole numbers of units departure calculating sub module, decimal unit deviation amount calculating sub module, integer are adjusted submodule, decimal is adjusted submodule, merged submodule.
Graduation of whole numbers of units departure calculating sub module is for the corresponding departure of unit deviation value of computes integer part
Decimal unit deviation amount calculating sub module is for calculating the corresponding departure of unit deviation value of fraction part
Integer adjusts submodule and decimal adjustment submodule is used for according to Δ R, and the integral part of comparative example coefficient and fraction part are adjusted respectively:
Wherein,
with
respectively integral part and the fraction part after adjusting;
represent downward rounding operation;
Merge submodule for the integral part after adjusting and fraction part are merged, obtain new scale-up factor:
Wherein,
for new scale-up factor; << represents to left shift operation.
Be not difficult to find, present embodiment is the system embodiment corresponding with the first embodiment, present embodiment can with the enforcement of working in coordination of the first embodiment.The correlation technique details of mentioning in the first embodiment is still effective in the present embodiment, in order to reduce repetition, repeats no more here.Correspondingly, the correlation technique details of mentioning in present embodiment also can be applicable in the first embodiment.
It is worth mentioning that, each module involved in present embodiment is logic module, and in actual applications, a logical block can be a physical location, can be also a part for a physical location, can also realize with the combination of multiple physical locations.In addition, for outstanding innovation part of the present invention, in present embodiment, the unit not too close with solving technical matters relation proposed by the invention do not introduced, but this does not show not exist in present embodiment other unit.
Four embodiment of the invention relates to a kind of calibrating installation of the clock accuracy for terminal.The 4th embodiment has done further improvement on the 3rd embodiment basis, main improvements are: in the 4th embodiment, can pass through statistical method, obtain the timing offset ratio of slow clock comparatively accurately, thereby ensure the robustness of clock accuracy calibration.
Specifically, timing offset ratio computing module further comprises: comparison sub-module, the first ratio calculation submodule; Wherein, comparison sub-module is for the size of Δ T relatively and default threshold value; When the first ratio calculation submodule judges that in comparison sub-module Δ T is less than or equal to default threshold value, calculate the ratio of Δ T and T, and using this ratio as Δ R; And in the time that comparison sub-module judges that Δ T is greater than default threshold value, calculate default threshold value and the ratio of T, and using this ratio as Δ R.
Or timing offset ratio computing module further comprises: deviation mean value computation submodule, sleep duration mean value computation submodule, the second ratio calculation submodule; Wherein, deviation mean value computation submodule is for calculating the average of default number Δ T; Sleep duration mean value computation submodule is for calculating the average of the T that default number Δ T is corresponding; The second ratio calculation submodule is for calculating the ratio of the average of Δ T and the average of T, using this ratio as Δ R.
Or timing offset ratio computing module further comprises: trend is observed submodule, the 3rd ratio calculation submodule; Wherein, trend is observed submodule for according to the variation tendency of default number Δ T, determines adjusted value; The 3rd ratio calculation submodule is for the ratio of calculate adjusting values and T, using this ratio as Δ R.
Because the second embodiment is mutually corresponding with present embodiment, therefore present embodiment can with the enforcement of working in coordination of the second embodiment.The correlation technique details of mentioning in the second embodiment is still effective in the present embodiment, and the technique effect that can reach in the second embodiment can be realized in the present embodiment too, in order to reduce repetition, repeats no more here.Correspondingly, the correlation technique details of mentioning in present embodiment also can be applicable in the second embodiment.
Persons of ordinary skill in the art may appreciate that the respective embodiments described above are to realize specific embodiments of the invention, and in actual applications, can do various changes to it in the form and details, and without departing from the spirit and scope of the present invention.
Claims (14)
1. for a calibration steps for the clock accuracy of terminal, described terminal has fast clock and slow clock, and the clock frequency of described fast clock is greater than the clock frequency of described slow clock, and described fast clock is accurately, it is characterized in that, comprises following steps:
A. obtain described fast clock and close, the time span T of described slow clock onset, and timing offset Δ T in described T time span;
B. according to described Δ T and described T, calculate timing offset ratio Δ R;
C. read the scale-up factor of described slow clock and described fast clock; Wherein, the initial value of described scale-up factor obtains by hardware calibration;
D. the described scale-up factor reading is deducted to described timing offset ratio, obtain new scale-up factor, complete the calibration to slow clock accuracy.
2. the calibration steps of the clock accuracy for terminal according to claim 1, is characterized in that, in described steps A, comprises following sub-step:
In each terminal, after sleep state is waken up, described terminal is received paging, and obtains the length length of one's sleep, as described T; Wherein, described terminal described fast clock within the sleep state time period is closed, described slow clock onset;
The reception data of receiving paging are carried out to channel estimating, obtain the timing offset amount in the length length of one's sleep, as described Δ T.
3. the calibration steps of the clock accuracy for terminal according to claim 1, is characterized in that, in described step B, comprises following sub-step:
Calculate the ratio of described Δ T and described T, and using described ratio as described Δ R.
4. the calibration steps of the clock accuracy for terminal according to claim 1, is characterized in that, in described step B, comprises following sub-step:
The size of more described Δ T and default threshold value;
If described Δ T is less than or equal to default threshold value, calculate the ratio of described Δ T and described T, and using described ratio as described Δ R;
If described Δ T is greater than default threshold value, calculate the ratio of described default threshold value and described T, and using described ratio as described Δ R.
5. the calibration steps of the clock accuracy for terminal according to claim 1, is characterized in that, in described step B, comprises following sub-step:
Calculate the average of default number Δ T;
Calculate the average of the T that described default number Δ T is corresponding;
Calculate the ratio of the average of described Δ T and the average of described T, using described ratio as described Δ R.
6. the calibration steps of the clock accuracy for terminal according to claim 1, is characterized in that, in described step B, comprises following sub-step:
According to the variation tendency of default number Δ T, determine adjusted value;
Calculate the ratio of described adjusted value and described T, using described ratio as described Δ R.
7. according to the calibration steps of the clock accuracy for terminal described in claim 1 to 6 any one, it is characterized in that, the clock frequency of described fast clock is 26 megahertzes, and the clock frequency of described slow clock is 32768 hertz; The scale-up factor R of described slow clock and described fast clock
32k/26Mby the register-stored of 32, wherein, high 16 storage integral part R
32k/26M_int, low 16 storage fraction part R
32k/26M_floor;
In described step D, comprise following sub-step:
The corresponding departure of unit deviation value of computes integer part
Calculate the corresponding departure of unit deviation value of fraction part
According to described Δ R, the integral part to described scale-up factor and fraction part are adjusted respectively:
Wherein,
with
respectively integral part and the fraction part after adjusting;
represent downward rounding operation;
Integral part after described adjustment and fraction part are merged, obtain new scale-up factor:
Wherein,
for new scale-up factor; << represents to left shift operation.
8. the calibrating installation for the clock accuracy of terminal, described terminal has fast clock and slow clock, and the clock frequency of described fast clock is greater than the clock frequency of described slow clock, described fast clock is accurately, it is characterized in that, comprise: duration acquisition module, timing offset acquisition module, timing offset ratio computing module, scale-up factor acquisition module, clock alignment module;
Described duration acquisition module is used for obtaining described fast clock closes, the time span T of described slow clock onset;
Described timing offset acquisition module is for obtaining the timing offset Δ T in described T time span;
Described timing offset ratio computing module, for according to described Δ T and described T, calculates timing offset ratio Δ R;
Described scale-up factor acquisition module is for reading the scale-up factor of described slow clock and described fast clock; Wherein, the initial value of described scale-up factor obtains by hardware calibration;
Described clock alignment module, for the described scale-up factor reading is deducted to described timing offset ratio, obtains new scale-up factor, completes the calibration to slow clock accuracy.
9. the calibrating installation of the clock accuracy for terminal according to claim 8, is characterized in that, described duration acquisition module after sleep state is waken up, obtains the length length of one's sleep, as described T in each terminal; Wherein, described terminal described fast clock within the sleep state time period is closed, described slow clock onset;
Described timing offset acquisition module, after described terminal is received paging, carries out channel estimating to the reception data of receiving paging, obtains timing departure in the length length of one's sleep, as described Δ T.
10. the calibrating installation of the clock accuracy for terminal according to claim 8, is characterized in that, described timing offset ratio computing module calculates the ratio of described Δ T and described T, and using described ratio as described Δ R.
The calibrating installation of 11. clock accuracies for terminal according to claim 8, is characterized in that, described timing offset ratio computing module comprises: comparison sub-module, the first ratio calculation submodule;
Described comparison sub-module is for the size of more described Δ T and default threshold value;
Described the first ratio calculation submodule, in the time that described comparison sub-module judges that described Δ T is less than or equal to default threshold value, calculates the ratio of described Δ T and described T, and using described ratio as described Δ R; And in the time that described comparison sub-module judges that described Δ T is greater than default threshold value, calculate the ratio of described default threshold value and described T, and using described ratio as described Δ R.
The calibrating installation of 12. clock accuracies for terminal according to claim 8, is characterized in that, described timing offset ratio computing module comprises: deviation mean value computation submodule, sleep duration mean value computation submodule, the second ratio calculation submodule;
Described deviation mean value computation submodule is for calculating the average of default number Δ T;
Described sleep duration mean value computation submodule is for calculating the average of the T that described default number Δ T is corresponding;
Described the second ratio calculation submodule is for calculating the ratio of the average of described Δ T and the average of described T, using described ratio as described Δ R.
The calibrating installation of 13. clock accuracies for terminal according to claim 8, is characterized in that, described timing offset ratio computing module comprises: trend is observed submodule, the 3rd ratio calculation submodule;
Described trend is observed submodule for according to the variation tendency of default number Δ T, determines adjusted value;
Described the 3rd ratio calculation submodule is for calculating the ratio of described adjusted value and described T, using described ratio as described Δ R.
The calibrating installation of the clock accuracy for terminal described in 14. according to Claim 8 to 13 any one, is characterized in that, the clock frequency of described fast clock is 26 megahertzes, and the clock frequency of described slow clock is 32768 hertz;
Also comprise: the register of 32, for storing the scale-up factor R of described slow clock and described fast clock
32k/26M, wherein, high 16 storage integral part R
32k/26M_int, low 16 storage fraction part R
32k/26M_floor;
Described clock alignment module comprises: graduation of whole numbers of units departure calculating sub module, decimal unit deviation amount calculating sub module, integer are adjusted submodule, decimal is adjusted submodule, merged submodule;
Described graduation of whole numbers of units departure calculating sub module is for the corresponding departure of unit deviation value of computes integer part
Described decimal unit deviation amount calculating sub module is for calculating the corresponding departure of unit deviation value of fraction part
Described integer adjusts submodule and described decimal adjustment submodule is used for according to described Δ R, and the integral part to described scale-up factor and fraction part are adjusted respectively:
Wherein,
with
respectively integral part and the fraction part after adjusting;
represent downward rounding operation;
Described merging submodule, for the integral part after described adjustment and fraction part are merged, obtains new scale-up factor:
Wherein,
for new scale-up factor; << represents to left shift operation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210586902.9A CN103901942B (en) | 2012-12-28 | 2012-12-28 | For the calibration method and device of the clock accuracy of terminal |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210586902.9A CN103901942B (en) | 2012-12-28 | 2012-12-28 | For the calibration method and device of the clock accuracy of terminal |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103901942A true CN103901942A (en) | 2014-07-02 |
| CN103901942B CN103901942B (en) | 2017-07-04 |
Family
ID=50993327
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210586902.9A Active CN103901942B (en) | 2012-12-28 | 2012-12-28 | For the calibration method and device of the clock accuracy of terminal |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103901942B (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105578586A (en) * | 2014-10-17 | 2016-05-11 | 联芯科技有限公司 | Synchronous timing device and method |
| CN105897394A (en) * | 2016-06-16 | 2016-08-24 | 桥弘数控科技（上海）有限公司 | Method and device for synchronous adjustment of clocks |
| CN107800388A (en) * | 2017-10-17 | 2018-03-13 | 广东美的制冷设备有限公司 | Control method, control device, storage medium and remote control |
| CN109155729A (en) * | 2016-05-18 | 2019-01-04 | 日本电信电话株式会社 | Wireless communication system, wireless terminal and method for synchronizing time |
| WO2019024064A1 (en) * | 2017-08-04 | 2019-02-07 | 深圳市汇顶科技股份有限公司 | Timing method, clock device and terminal device |
| CN109799872A (en) * | 2018-12-29 | 2019-05-24 | 百富计算机技术（深圳）有限公司 | Improve the method, apparatus and electronic equipment of low-res real-time clock waking-up precision |
| CN111726450A (en) * | 2019-03-19 | 2020-09-29 | 安克创新科技股份有限公司 | Control method of intelligent express cabinet and intelligent express cabinet |
| CN114666029A (en) * | 2022-03-24 | 2022-06-24 | 维沃移动通信有限公司 | Calibration control method and device and electronic equipment |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030212531A1 (en) * | 2002-05-13 | 2003-11-13 | Kerr John S. | Synchronizing clock enablement in an electronic device |
| CN101431816A (en) * | 2008-11-19 | 2009-05-13 | 深圳华为通信技术有限公司 | Frequency difference acquiring method and terminal |
| CN101959298A (en) * | 2009-07-17 | 2011-01-26 | 联芯科技有限公司 | Method and device for calibrating slow timing clock and terminal |
| CN102540868A (en) * | 2010-12-31 | 2012-07-04 | 重庆重邮信科通信技术有限公司 | Slow clock crystal frequency compensation method and device for mobile communication terminal |
-
2012
- 2012-12-28 CN CN201210586902.9A patent/CN103901942B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030212531A1 (en) * | 2002-05-13 | 2003-11-13 | Kerr John S. | Synchronizing clock enablement in an electronic device |
| CN101431816A (en) * | 2008-11-19 | 2009-05-13 | 深圳华为通信技术有限公司 | Frequency difference acquiring method and terminal |
| CN101959298A (en) * | 2009-07-17 | 2011-01-26 | 联芯科技有限公司 | Method and device for calibrating slow timing clock and terminal |
| CN102540868A (en) * | 2010-12-31 | 2012-07-04 | 重庆重邮信科通信技术有限公司 | Slow clock crystal frequency compensation method and device for mobile communication terminal |
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105578586A (en) * | 2014-10-17 | 2016-05-11 | 联芯科技有限公司 | Synchronous timing device and method |
| CN105578586B (en) * | 2014-10-17 | 2019-05-21 | 辰芯科技有限公司 | A kind of synchronization timing device and method |
| CN109155729A (en) * | 2016-05-18 | 2019-01-04 | 日本电信电话株式会社 | Wireless communication system, wireless terminal and method for synchronizing time |
| CN109155729B (en) * | 2016-05-18 | 2022-04-05 | 日本电信电话株式会社 | Wireless communication system, wireless terminal, and time synchronization method |
| CN105897394B (en) * | 2016-06-16 | 2019-02-15 | 桥弘数控科技（上海）有限公司 | A kind of clock synchronization adjustment method and device |
| CN105897394A (en) * | 2016-06-16 | 2016-08-24 | 桥弘数控科技（上海）有限公司 | Method and device for synchronous adjustment of clocks |
| WO2019024064A1 (en) * | 2017-08-04 | 2019-02-07 | 深圳市汇顶科技股份有限公司 | Timing method, clock device and terminal device |
| US10498524B2 (en) | 2017-08-04 | 2019-12-03 | Shenzhen GOODIX Technology Co., Ltd. | Timing method, clock device and terminal device |
| CN107800388A (en) * | 2017-10-17 | 2018-03-13 | 广东美的制冷设备有限公司 | Control method, control device, storage medium and remote control |
| CN109799872A (en) * | 2018-12-29 | 2019-05-24 | 百富计算机技术（深圳）有限公司 | Improve the method, apparatus and electronic equipment of low-res real-time clock waking-up precision |
| CN111726450A (en) * | 2019-03-19 | 2020-09-29 | 安克创新科技股份有限公司 | Control method of intelligent express cabinet and intelligent express cabinet |
| CN114666029A (en) * | 2022-03-24 | 2022-06-24 | 维沃移动通信有限公司 | Calibration control method and device and electronic equipment |
| CN114666029B (en) * | 2022-03-24 | 2024-05-31 | 维沃移动通信有限公司 | Calibration control method and device and electronic equipment |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103901942B (en) | 2017-07-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103901942A (en) | Clock precision calibration method and device for terminal | |
| CN100456858C (en) | Time error compensation device and method for terminal | |
| CN103176400B (en) | Intelligent ammeter clock calibration method | |
| US8560875B2 (en) | Apparatus for clock calibrating a less precise second clock signal with a more precise first clock signal wherein the first clock signal is inactive during a sniff mode and the second clock signal is active during a sniff mode | |
| CN106026919B (en) | The punctual compensation method of crystal oscillator | |
| CN109067394B (en) | On-chip clock calibration device and calibration method | |
| WO2018151202A1 (en) | Sensing system and time stamp correction method | |
| CN107765760B (en) | RTC module clock source dynamic calibration method and RTC module clock source dynamic calibration system in instrument sleep mode | |
| CN101959298B (en) | Method and device for calibrating slow timing clock and terminal | |
| CN101930211A (en) | Clock source device based on GPS second pulse and control method thereof | |
| CN103699001B (en) | Utilize clocking method and system that constant-temperature crystal oscillator realizes | |
| CN103904998A (en) | Method and device for adjusting frequency of mobile terminal | |
| CN102129062B (en) | Electric energy small-signal measuring and calibrating method and device | |
| EP2790324A1 (en) | Method for providing a stabilized oscillator signal | |
| CN112737509B (en) | Method and system for compensating frequency drift of crystal oscillator | |
| CN109617528A (en) | It is a kind of for correcting the method and its system of active oscillator frequency | |
| EP2613177A1 (en) | Reverse frequency and time aiding | |
| CN104635193B (en) | A kind of SOC real-time clock high-accuracy compensation method of ammeter | |
| CN103024778A (en) | Method for improving real-time clock precision on wireless communication terminal | |
| JP5914718B2 (en) | Time base with oscillator, frequency division circuit and clock pulse suppression circuit | |
| CN112737574B (en) | Timing calibration method and related device for clock source in chip | |
| CN203086445U (en) | Novel microwave atomic clock system | |
| US8344817B2 (en) | Compensating DFLL with error averaging | |
| CN107748831A (en) | The compensation method of instrument timing error and its system | |
| JP4952406B2 (en) | Time correction method, microcomputer internal clock, electronic control unit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20191118 Address after: 1-1-609-a, North Zone, financial and Trade Center, No. 6865, Asia Road, Tianjin Free Trade Zone (Dongjiang Free Trade Port Area), 300450 Patentee after: Huiyi finance leasing (Tianjin) Co., Ltd Address before: 201206 No. 1258 Mingyue Road, Shanghai, Pudong New Area Patentee before: Leadcore Technology Co., Ltd. |
|
| TR01 | Transfer of patent right | ||
| EE01 | Entry into force of recordation of patent licensing contract |
Application publication date: 20140702 Assignee: Leadcore Technology Co., Ltd. Assignor: Huiyi finance leasing (Tianjin) Co., Ltd Contract record no.: X2020990000002 Denomination of invention: Clock precision calibration method and device for terminal Granted publication date: 20170704 License type: Exclusive License Record date: 20200103 |
|
| EE01 | Entry into force of recordation of patent licensing contract | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20220324 Address after: 201206 Ming Yue Road, Pudong New Area, Shanghai, No. 1258 Patentee after: LEADCORE TECHNOLOGY Co.,Ltd. Address before: 300450 Tianjin pilot free trade zone (Dongjiang Bonded Port Area), 1-1-609-a, north area of financial and Trade Center, No. 6865, Asia Road Patentee before: Huiyi finance leasing (Tianjin) Co.,Ltd. |
|
| TR01 | Transfer of patent right |