CN101959298B - Method and device for calibrating slow timing clock and terminal - Google Patents
Method and device for calibrating slow timing clock and terminal Download PDFInfo
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- CN101959298B CN101959298B CN200910055012.3A CN200910055012A CN101959298B CN 101959298 B CN101959298 B CN 101959298B CN 200910055012 A CN200910055012 A CN 200910055012A CN 101959298 B CN101959298 B CN 101959298B
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
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Abstract
Embodiment of the invention discloses a method and a device for calibrating a slow timing clock and a terminal and relates to the technical field of telecommunication. The method and the device are invented for solving the problem that the mobile phone terminal cannot enter a sleep state in time and therefore shortens the sleep time of the mobile phone terminal and increases the power consumption thereof in the prior art. The method for calibrating the slow timing clock comprises the following steps of: obtaining a high speed clock signal and a slow clock signal, wherein the high speed clock signal is more than 13MHz; and calibrating the timing of the slow timing clock according to the high speed clock signal. In the embodiment of the invention, the power consumption of the mobile phone terminal can be greatly reduced and the clock precision can be improved.
Description
Technical field
The present invention relates to technical field of telecommunications, particularly relate to one timer clock collimation technique at a slow speed.
Background technology
At present, mobile phone terminal carries out timer clock calibration needs two clock sources usually, and one is quick clock source; Another is Slow Clock source.Wherein, the frequency of oscillation in quick clock source is generally 13MHz, its precision and stability higher; The frequency of oscillation in Slow Clock source is about 32KHz usually, its precision and stability relatively low.Due to the electric energy that the need of work consumption of quick clock source is a large amount of, so when mobile phone terminal is slept, the Slow Clock source described in usually adopting provides timing for system.But in order to the timing offset in Slow Clock source when ensureing that mobile phone terminal is slept is not more than system requirements, the quick clock source described in usually adopting is that timer clock calibration is carried out in Slow Clock source.
When the processor of mobile phone terminal is in idle condition, first processor judges whether the timer clock calibration of described quick clock source to Slow Clock source completes, if completed, then processor carries out system sleep state; Otherwise processor can not enter system sleep state, until timer clock has been calibrated.Because the precision of the described calibration of timer clock was at a slow speed directly proportional to the time of calibration, so mobile phone terminal is in order to meet different system requirement, need the alignment time of at least 125ms in theory, that is, quick clock source in the 125ms time is at least needed to keep normal work, for timer clock calibration provides standard time clock reference at a slow speed.
In addition, because Slow Clock source stability is relatively low, when variations in temperature, Slow Clock source stability sharply worsens especially.In order to prevent Slow Clock from varying with temperature, frequency deviation occurs, or cause mobile phone terminal off-grid because variations in temperature is excessive due to Slow Clock source, according to the requirement of different system, timer clock calibration is carried out to Slow Clock source in quick clock source.Wherein, the cycle of described timing alignment is generally a few second to tens seconds.
Realizing in process of the present invention, inventor finds at least there is following problem in prior art: in the prior art, in order to ensure the requirement of different system to mobile phone terminal clock precision, the time that quick clock source is calibrated Slow Clock source is longer, make mobile phone terminal can not enter sleep state in time, thus shorten the length of one's sleep of mobile phone terminal, add mobile phone terminal power consumption.
Summary of the invention
Embodiments provide one timer clock calibration steps and device and a kind of terminal at a slow speed, enter sleep state in time to realize mobile phone terminal, save mobile phone terminal power consumption.
For achieving the above object, embodiments of the invention adopt following technical scheme:
On the one hand, embodiments provide one timer clock calibration steps at a slow speed, comprising:
Obtain high-speed clock signal and slow clock signal; Wherein, described high-speed clock signal is higher than 13MHz;
According to described high-speed clock signal, timer clock calibration is carried out to described Slow Clock.
Further, the described calibration steps of timer clock at a slow speed, can also comprise:
The number obtaining described slow clock signal is set.
Further, when described high-speed clock signal is not less than 130MHz, the step of described acquisition high-speed clock signal and slow clock signal, specifically comprises:
Obtain fast clock signal and described slow clock signal;
According to the number of the described slow clock signal of the acquisition of described setting, cumulative described slow clock signal number;
According to described fast clock signal, obtain high-speed clock signal.
Further, when the number of the described slow clock signal of acquisition that described cumulative described slow clock signal number is more than or equal to described setting, the step of described acquisition high-speed clock signal and slow clock signal, specifically can also comprise:
Send spill over.
Further, described according to described high-speed clock signal, described Slow Clock is carried out to the step of timer clock calibration, specifically comprise:
The rising edge number of cumulative described high-speed clock signal;
The trailing edge number of cumulative described high-speed clock signal;
According to described spill over, obtain the rising edge number of described high-speed clock signal and the trailing edge number of described high-speed clock signal and;
According to the rising edge number of described high-speed clock signal and the trailing edge number of described high-speed clock signal and, upgrade fractional frequency division coefficient;
According to described fractional frequency division coefficient and slow clock signal, obtain reference clock signal at a slow speed.
On the other hand, embodiments provide one timer clock calibrating installation at a slow speed, comprising:
Signal acquiring unit, for obtaining high-speed clock signal and slow clock signal; Wherein, described high-speed clock signal is higher than 13MHz;
Alignment unit, for according to described high-speed clock signal, carries out timer clock calibration to described Slow Clock.
Further, the described calibrating installation of timer clock at a slow speed, can also comprise:
Number of times setting unit, for arranging the number obtaining described slow clock signal.
Further, when described high-speed clock signal is not less than 130MHz, described signal acquiring unit, specifically comprises:
Signal acquisition subelement, for obtaining fast clock signal and described slow clock signal;
Signal number of times adds up subelement, for the number according to the described slow clock signal of the acquisition of described setting, and cumulative described slow clock signal number;
High-speed clock signal obtains subelement, for according to described fast clock signal, obtains high-speed clock signal.
Further, when the number of the described slow clock signal of acquisition that described cumulative described slow clock signal number is more than or equal to described setting, described signal acquiring unit, specifically can also comprise:
Spill over sends subelement, for sending spill over.
Further, described alignment unit, specifically comprises:
Rising edge number adds up subelement, for the rising edge number of cumulative described high-speed clock signal;
To add up subelement along number, for the trailing edge number of cumulative described high-speed clock signal down;
Coefficient obtains subelement, for according to described spill over, obtain the rising edge number of described high-speed clock signal and the trailing edge number of described high-speed clock signal with;
Coefficient update subelement, for according to the rising edge number of described high-speed clock signal and the trailing edge number of described high-speed clock signal and, upgrade fractional frequency division coefficient;
Calibrating signal obtains subelement, for according to described fractional frequency division coefficient and slow clock signal, obtains reference clock signal at a slow speed.
Again on the one hand, embodiments provide a kind of terminal, comprising: timer clock calibrating installation at a slow speed as above.
The one that the embodiment of the present invention provides is timer clock calibration steps and device and a kind of terminal at a slow speed, by obtaining high-speed clock signal, timer clock calibration is carried out to described Slow Clock, the alignment time of timer clock at a slow speed of mobile phone terminal is shortened, namely when mobile phone terminal needs to enter dormant, the calibration process of slow clock signal terminates, thus ensure that the length of one's sleep of mobile phone terminal, greatly reduce the power consumption of mobile phone terminal.The embodiment of the present invention can also adopt the bilateral counting along frequency measuring method, the high-speed clock signal of described acquisition being carried out to rising edge and trailing edge, frequency measurement error is made to reduce half, frequency measurement time shorten is 1/2 of the source frequency measurement time, and then shorten the alignment time of described slow clock signal, improve calibration accuracy.
Accompanying drawing explanation
The one timer clock calibration steps flow chart at a slow speed that Fig. 1 provides for the embodiment of the present invention;
The another kind timer clock calibration steps flow chart at a slow speed that Fig. 2 provides for the embodiment of the present invention;
The one timer clock calibrating installation structural representation at a slow speed that Fig. 3 provides for the embodiment of the present invention;
The another kind timer clock calibrating installation structural representation at a slow speed that Fig. 4 provides for the embodiment of the present invention;
A kind of terminal structure schematic diagram that Fig. 5 provides for the embodiment of the present invention;
A kind of calibrating installation of timer clock at a slow speed that Fig. 6 provides for the embodiment of the present invention realize schematic diagram.
Embodiment
The one provided the embodiment of the present invention below in conjunction with accompanying drawing at a slow speed timer clock calibration steps and device and a kind of terminal is described in detail.
As shown in Figure 1, be the one timer clock calibration steps at a slow speed that the embodiment of the present invention provides, the method comprises:
101, high-speed clock signal and slow clock signal is obtained; Wherein, described high-speed clock signal is higher than 13MHz; Described high-speed clock signal can obtain according to the fast clock signal of mobile phone terminal, specifically: described fast clock signal can obtain the high-speed clock signal identical with described fast clock signal precision by phase-locked loop.
102, according to described high-speed clock signal, timer clock calibration is carried out to described Slow Clock.
As shown in Figure 2, be the one timer clock calibration steps at a slow speed that the embodiment of the present invention provides, the method comprises: when described high-speed clock signal is not less than 130MHz,
201: the number obtaining described slow clock signal is set.This step is according to the alignment requirements of system to slow clock signal, alignment time and calibration error are arranged, specifically, because the alignment time is longer, the error of calibration is less, and calibration needs the power consumption of consumption larger, so balance to make calibration power consumption and alignment time and error reach one, namely in order to meet the alignment requirements of system to slow clock signal, the number obtaining described slow clock signal is selected.
202: obtain fast clock signal and described slow clock signal.
203: according to the number of the described slow clock signal of the acquisition of described setting, cumulative described slow clock signal number.
204: according to described fast clock signal, obtain high-speed clock signal.
205: the rising edge number of cumulative described high-speed clock signal;
206: the trailing edge number of cumulative described high-speed clock signal;
207: when the number of the described slow clock signal of acquisition that described cumulative described slow clock signal number is more than or equal to described setting, send spill over.
208: according to described spill over, obtain the summation of the rising edge number of described high-speed clock signal and the trailing edge number of described high-speed clock signal;
209: according to the summation of the rising edge number of described high-speed clock signal and the trailing edge number of described high-speed clock signal, upgrade fractional frequency division coefficient; Wherein, described fractional frequency division coefficient is used for decimal frequency divider and adjusts reference clock signal at a slow speed.
210: according to described fractional frequency division coefficient and slow clock signal, obtain reference clock signal at a slow speed.
As shown in Figure 3, be the one timer clock calibrating installation at a slow speed that the embodiment of the present invention provides, this device, specifically comprises:
Signal acquiring unit 301, for obtaining high-speed clock signal and slow clock signal; Wherein, described high-speed clock signal is higher than 13MHz;
Alignment unit 302, for according to described high-speed clock signal, carries out timer clock calibration to described Slow Clock.
Further, this device can also comprise:
Number of times setting unit 303, for arranging the number obtaining described slow clock signal.
As shown in Figure 4, be the one timer clock calibrating installation at a slow speed that the embodiment of the present invention provides, this device, when described high-speed clock signal is not less than 130MHz, described signal acquiring unit 301, comprises further:
Signal acquisition subelement 401, for obtaining fast clock signal and described slow clock signal;
Signal number of times adds up subelement 402, for the number according to the described slow clock signal of the acquisition of described setting, and cumulative described slow clock signal number;
High-speed clock signal obtains subelement 403, for according to described fast clock signal, obtains high-speed clock signal.
When the number of the described slow clock signal of acquisition that described cumulative described slow clock signal number is more than or equal to described setting, described signal acquiring unit, further comprises:
Spill over sends subelement 404, for sending spill over.
Described alignment unit 302, comprises further:
Rising edge number adds up subelement 405, for the rising edge number of cumulative described high-speed clock signal;
To add up subelement 406 along number, for the trailing edge number of cumulative described high-speed clock signal down;
Coefficient obtains subelement 407, for according to described spill over, obtain the rising edge number of described high-speed clock signal and the trailing edge number of described high-speed clock signal with;
Coefficient update subelement 408, for according to the rising edge number of described high-speed clock signal and the trailing edge number of described high-speed clock signal and, upgrade fractional frequency division coefficient;
Calibrating signal obtains subelement 409, for according to described fractional frequency division coefficient and slow clock signal, obtains reference clock signal at a slow speed.
As shown in Figure 5, be a kind of terminal that the embodiment of the present invention provides, this terminal specifically comprises: the above-mentioned calibrating installation of timer clock at a slow speed.
As shown in Figure 6, a kind of calibration steps of timer clock at a slow speed provided for the embodiment of the present invention realize schematic diagram; If the frequency of this slow clock signal of timer clock calibration steps is at a slow speed: 32KHz; The clock signal of fast clock signal is 13MHz; Specific implementation at a slow speed timer clock calibration process as follows:
When calibrate enable invalid time, 2
ncounter, d type flip flop, M digit counter 0 and M digit counter 1 all reset clearing; Be set to effectively when calibration is enable, 2
nthe input clock gate of counter is opened, and when the 1st 32KHz Slow Clock rising edge, d type flip flop exports high, opens M digit counter 0 input clock gate and M digit counter 1 input clock gate.Hereafter each 32K Slow Clock rising edge triggers 2
ncounter adds 1, and it is low to export overflow indicator signal, until 2
nduring counter overflow, export overflow indicator signal high, close the input clock gate of M digit counter 0 and the input clock gate of M digit counter 1.Input clock gate for M digit counter 0 and M digit counter 1 opens period, fast clock signal gets 130MHz high-speed clock signal by phase-locked loop pll, often carry out one-accumulate 1 through 1 high-frequency clock rising edge M digit counter 0, often carry out one-accumulate 1 through 1 high-frequency clock trailing edge M digit counter 1.
Whenever 2
nduring counter overflow, trigger M digit counter 0 sum counter 1 and be added, result is stored in M+1 register.Decimal frequency divider can calculate based on the value of current M+1 digit counter and upgrade fractional frequency division coefficient, after this, produces reference clock at a slow speed according to new fractional frequency division coefficient.
It should be noted that high-speed clock signal that the above obtains is not less than 130MHz is a comparatively preferred embodiment of the present invention; Therefore, as long as the high-speed clock signal met higher than 13MHz all belongs to protection scope of the present invention.
The one that the embodiment of the present invention provides is timer clock calibration steps and device and a kind of terminal at a slow speed, by obtaining high-speed clock signal, timer clock calibration is carried out to described Slow Clock, the alignment time of timer clock at a slow speed of mobile phone terminal is shortened, namely when mobile phone terminal needs to enter dormant, the calibration process of slow clock signal terminates, thus ensure that the length of one's sleep of mobile phone terminal, greatly reduce the power consumption of mobile phone terminal.The embodiment of the present invention can also adopt the bilateral counting along frequency measuring method, the high-speed clock signal of described acquisition being carried out to rising edge and trailing edge, frequency measurement error is made to reduce half, frequency measurement time shorten is 1/2 of the source frequency measurement time, and then shorten the alignment time of described slow clock signal, improve calibration accuracy.
It should be noted that, the calibration steps of timer clock at a slow speed that the embodiment of the present invention provides and the high-speed clock signal that device adopts are as Slow Clock frequency measurement reference.Because the frequency of described high-speed clock signal is higher, calibration error is reduced greatly, and the alignment time also shortens greatly.Such as: adopt 13MHz fast clock signal to produce high-speed clock signal by phase-locked loop, therefore described high-speed clock signal and 13MHz fast clock signal have identical precision.The higher high-frequency clock of frequency is adopted to do the frequency measurement of signal as slow clock signal with reference to reducing quantization error.Count high-speed clock signal rising edge and trailing edge because the embodiment of the present invention adopts again, therefore frequency measurement error can reduce half, and Measuring Time can shorten half further simultaneously.Thus measure error can be obtained be about 2
14-N/ f
h, wherein N represents the figure place of counter, namely receives the number of slow clock signal, f
hrepresent high-speed clock signal frequency.Such as: set described fast clock signal to get high-speed clock signal frequency as 130MHz, N by PLL and get 8, then the frequency measurement time is 2
n-15s=7.8125ms, calibration accuracy can reach 0.49PPM.Like this, calibrated before the processor free time and complete, therefore adopt the embodiment of the present invention that processor can be made idle, system enters sleep immediately, compared with prior art, the embodiment of the present invention carries out the calibration of slow clock signal without the need to curtailing sleep, thus greatly reduces the power consumption of mobile phone terminal.
Through the above description of the embodiments, one of ordinary skill in the art will appreciate that: all or part of step realized in above-described embodiment method is that the hardware that can carry out instruction relevant by program has come, described program can be stored in a computer read/write memory medium, this program is when performing, comprise the step as above-mentioned embodiment of the method, described storage medium, as: ROM/RAM, magnetic disc, CD etc.
The above; be only the specific embodiment of the present invention, but protection scope of the present invention is not limited thereto, is anyly familiar with those skilled in the art in the technical scope that the present invention discloses; change can be expected easily or replace, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of claim.
Claims (11)
1. a timer clock calibration steps at a slow speed, is characterized in that, comprising:
Obtain high-speed clock signal and slow clock signal; Wherein, described high-speed clock signal is not less than 130MHz;
According to described high-speed clock signal, timer clock calibration is carried out to described Slow Clock;
Wherein, described high-speed clock signal is obtained in the following manner:
Obtain fast clock signal;
The high-speed clock signal identical with described fast clock signal precision is obtained by phase-locked loop.
2. the calibration steps of timer clock at a slow speed according to claim 1, is characterized in that, also comprise:
The number obtaining described slow clock signal is set.
3. the calibration steps of timer clock at a slow speed according to claim 2, is characterized in that, the step of described acquisition high-speed clock signal and slow clock signal, comprises further:
Obtain fast clock signal and described slow clock signal;
According to the number of the described slow clock signal of the acquisition of described setting, cumulative described slow clock signal number;
According to described fast clock signal, obtain high-speed clock signal.
4. the calibration steps of timer clock at a slow speed according to claim 3, it is characterized in that, when the number of the described slow clock signal of acquisition that described cumulative described slow clock signal number is more than or equal to described setting, the step of described acquisition high-speed clock signal and slow clock signal, further comprises:
Send spill over.
5. the calibration steps of timer clock at a slow speed according to claim 4, is characterized in that, described according to described high-speed clock signal, described Slow Clock is carried out to the step of timer clock calibration, comprises further:
The rising edge number of cumulative described high-speed clock signal;
The trailing edge number of cumulative described high-speed clock signal;
According to described spill over, obtain the rising edge number of described high-speed clock signal and the trailing edge number of described high-speed clock signal and;
According to the rising edge number of described high-speed clock signal and the trailing edge number of described high-speed clock signal and, upgrade fractional frequency division coefficient;
According to described fractional frequency division coefficient and slow clock signal, obtain reference clock signal at a slow speed.
6. a timer clock calibrating installation at a slow speed, is characterized in that, comprising:
Signal acquiring unit, for obtaining high-speed clock signal and slow clock signal; Wherein, described high-speed clock signal is not less than 130MHz;
Alignment unit, for according to described high-speed clock signal, carries out timer clock calibration to described Slow Clock;
Wherein, described signal acquiring unit, after acquisition fast clock signal, obtains the high-speed clock signal identical with described fast clock signal precision by phase-locked loop.
7. the calibrating installation of timer clock at a slow speed according to claim 6, is characterized in that, also comprise:
Number of times setting unit, for arranging the number obtaining described slow clock signal.
8. the calibrating installation of timer clock at a slow speed according to claim 7, it is characterized in that, described signal acquiring unit, comprises further:
Signal acquisition subelement, for obtaining fast clock signal and described slow clock signal;
Signal number of times adds up subelement, for the number according to the described slow clock signal of the acquisition of described setting, and cumulative described slow clock signal number;
High-speed clock signal obtains subelement, for according to described fast clock signal, obtains high-speed clock signal.
9. the calibrating installation of timer clock at a slow speed according to claim 8, it is characterized in that, when the number of the described slow clock signal of acquisition that described cumulative described slow clock signal number is more than or equal to described setting, described signal acquiring unit, further comprises:
Spill over sends subelement, for sending spill over.
10. the calibrating installation of timer clock at a slow speed according to claim 9, it is characterized in that, described alignment unit, comprises further:
Rising edge number adds up subelement, for the rising edge number of cumulative described high-speed clock signal;
To add up subelement along number, for the trailing edge number of cumulative described high-speed clock signal down;
Coefficient obtains subelement, for according to described spill over, obtain the rising edge number of described high-speed clock signal and the trailing edge number of described high-speed clock signal with;
Coefficient update subelement, for according to the rising edge number of described high-speed clock signal and the trailing edge number of described high-speed clock signal and, upgrade fractional frequency division coefficient;
Calibrating signal obtains subelement, for according to described fractional frequency division coefficient and slow clock signal, obtains reference clock signal at a slow speed.
11. 1 kinds of terminals, is characterized in that, comprising: as the calibrating installation of timer clock at a slow speed in claim 6 to 10 as described in any one.
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| CN200910055012.3A CN101959298B (en) | 2009-07-17 | 2009-07-17 | Method and device for calibrating slow timing clock and terminal |
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Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103197139B (en) * | 2012-01-06 | 2017-03-15 | 上海华虹集成电路有限责任公司 | Clock rate testing circuit |
| CN103901942B (en) * | 2012-12-28 | 2017-07-04 | 联芯科技有限公司 | For the calibration method and device of the clock accuracy of terminal |
| CN104796978A (en) * | 2014-01-18 | 2015-07-22 | 交通运输部科学研究院 | Synchronous and batch calibration method for time base of WSN (Wireless Sensor Networks) nodes |
| CN105873190B (en) | 2015-01-20 | 2019-04-30 | 深圳市中兴微电子技术有限公司 | A kind of clock correcting method and terminal of closed loop |
| CN105738695A (en) * | 2016-04-14 | 2016-07-06 | 杭州中科微电子有限公司 | Clock frequency tracking measuring and error estimating method and module |
| CN110876178B (en) * | 2018-08-31 | 2023-05-23 | 展讯通信（上海）有限公司 | 32K clock calibration method and device |
| CN109547024B (en) * | 2019-01-09 | 2024-04-16 | 上海艾为电子技术股份有限公司 | Multi-signal detection method and detection control device |
| CN112230711B (en) * | 2020-09-25 | 2023-03-14 | 紫光展锐(重庆)科技有限公司 | Calibration device, method and computer readable storage medium |
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| CN101366188A (en) * | 2005-11-09 | 2009-02-11 | 高通股份有限公司 | Apparatus and methods for estimating a sleep clock frequency |
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Application publication date: 20110126 Assignee: Shanghai Li Ke Semiconductor Technology Co., Ltd. Assignor: Leadcore Technology Co., Ltd. Contract record no.: 2018990000159 Denomination of invention: Method and device for calibrating slow timing clock and terminal Granted publication date: 20150325 License type: Common License Record date: 20180615 |