CN103197139B - Clock rate testing circuit - Google Patents
Clock rate testing circuit Download PDFInfo
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- CN103197139B CN103197139B CN201210004410.4A CN201210004410A CN103197139B CN 103197139 B CN103197139 B CN 103197139B CN 201210004410 A CN201210004410 A CN 201210004410A CN 103197139 B CN103197139 B CN 103197139B
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Abstract
The invention discloses test clock and tested clock are divided into fast clock and slow clock by a kind of clock rate testing method, fast clock counter are set fast clock is counted, slow clock counter is set slow clock is counted；Counting interval during test is counted interval on the basis of the counting interval of slow clock；First start slow clock counter after system start-up test to be counted, slow clock counter is restarted fast clock counter after starting counting and counted；Slow clock counter stops counting after writing all over, then stops fast clock counter counting again；With the test starting position that fast clock counter stops the signal removal system for counting, the frequency for reading the numerical value of fast clock counter, the count value of count value, slow clock counter according to fast clock counter and known test clock calculates the frequency of tested clock.The invention also discloses a kind of clock rate testing circuit.The present invention can obtain more accurate test result within the limited testing time.
Description
Technical field
The present invention relates to a kind of clock rate testing circuit.
Background technology
In current chip design, increasing chip internal is also used in addition to the clock being input into using interface
Built-in clock.The factors such as the design error of process deviation and embedded clock circuit cause designer to have to be carried out to embedded clock
The requirement of test.At present, commonplace method of testing is embedded clock to be tested using interface clock, i.e. interface clock
Start counting simultaneously with embedded clock, in calculating in the count value and known interface-clock-frequency that necessarily count interval
The frequency of clock is built, to determine the deviation between the frequency of embedded clock and design load.Such test circuit does not generally consider
Speed relation between test clock and tested clock, counts interval on the basis of the counting interval of unification test clock, and
And the enumerator directly gone to be respectively started test clock and tested clock with the enabling signal of system.The survey of this test circuit
Examination error often, in units of the cycle of slow clock, can be drawn in the case where test clock and tested clock frequency are widely different
Enter sizable test error, especially in the case where the frequency of tested clock is more much lower than the frequency of test clock.This
If kind of a circuit will reduce test error and can only increase counting interval, but can increase the testing time.
Content of the invention
The technical problem to be solved is to provide a kind of clock rate testing circuit, can be in limited test
In obtain more accurate test result.
For solve above-mentioned technical problem, the present invention clock rate testing circuit, including：Slow clock circuit, fast clock electricity
Road and system clock circuit；
The system clock circuit includes：
One four d flip-flop, its data output end output system start test signal；
One the 3rd two-stage synchronizer, its data output end are connected with the data input pin of the 5th d type flip flop, and the data
Outfan is connected with an input of door with the 4th through a reverser；
One the 5th d type flip flop, its data output end are connected with another input of door with the 4th；
One the 4th and door, its outfan is connected with the synchronous reset end of the four d flip-flop, for detecting fast clock
The synchronized enabling signal trailing edge of enumerator, when the synchronized enabling signal trailing edge for detecting fast clock counter
When, its output signal makes the four d flip-flop reset, and synchronous scavenging system starts test signal；
The input end of clock input system clock letter of the four d flip-flop, the 3rd two-stage synchronizer and the 5th d type flip flop
Number；
The fast clock circuit includes：
The data input pin of one second two-stage synchronizer, its data output end and 3d flip-flop and the 3rd and the one of door
Input is connected；
One 3d flip-flop, its data output end are connected with another input of door with the 3rd through a reverser, and should
The data input pin that data output end enables input and the 3rd two-stage synchronizer with the counting of fast clock counter is connected
Connect；The synchronized enabling signal of output fast clock counter；
One fast clock counter, its terminal count output export fast clock count value；
One the 3rd and door, its outfan is connected with the synchronous reset end of the fast clock counter；
The input end of clock of second two-stage synchronizer, 3d flip-flop and fast clock counter is input into fast clock letter
Number；
The slow clock circuit includes：
One first two-stage synchronizer, its data input pin are connected with the data output end of the four d flip-flop, input
System start-up test signal；Its data output end and first and an input and the data input pin phase of the first d type flip flop of door
Connection；
One first d type flip flop, its data output end are connected with an input of door with second, and the data output end warp
One reverser is connected with another input of door with first；
One slow clock counter, its are counted enable input and are connected with the outfan of door with second, are input into slow clock meter
The enabling signal of number device；
One first and door, its outfan is connected with the synchronous reset end of the slow clock counter；
One comparator, its reverse input end are connected with the terminal count output of slow clock counter, and its positive input is defeated
Enter reference value；
One second and door, its another input is connected with the outfan of the comparator；
One second d type flip flop, its data input pin are connected with the outfan of door with second；Its data output end with described
The data input pin of the second two-stage synchronizer is connected, and exports the startup letter synchronous without fast clock circuit of fast clock counter
Number；
The input end of clock of first two-stage synchronizer, the first d type flip flop, slow clock counter and the second d type flip flop
Input slow clock signal；
First two-stage synchronizer, the second two-stage synchronizer and the 3rd two-stage synchronizer are connected by two d type flip flops
Composition, for synchronizing to asynchronous signal.
Compared with the method for of the invention with traditional testing clock frequency, the test error of clock frequency can be controlled non-
In often little scope, that is, the error of test hour counter can be controlled within two fast clock cycle, and this is in test
It is particularly significant in the case that clock and measured clock frequency difference are larger.
The present invention can be effectively reduced test error, obtain more accurate test result.
Description of the drawings
The present invention is further detailed explanation with specific embodiment below in conjunction with the accompanying drawings：
Fig. 1 is one embodiment of the invention clock rate testing circuit structure diagram；
Fig. 2 is clock rate testing method flow diagram.
Specific embodiment
Many products have built-in clock at present, in order to understand the frequency of embedded clock, are usually connect using contact
The clock of mouth goes to test built-in clock, i.e. test clock and tested clock while being counted, and then passes through certain time
In count value and the frequency of known interface clock calculate the frequency of tested clock.Missed using said method testing clock frequency
Difference is larger, and especially built-in in the project having 100KHz clocks have as many as tens times with contact clock frequency difference, and this will
So that test error cannot receive.
Present invention focuses on accurately the boot sequence of gated counter and the correct counting of selection are interval, so that energy
Test error is enough effectively reduced, more accurate test result is obtained in the short period of time.
Fig. 1 is one embodiment of the invention, shown clock rate testing circuit by system clock circuit, slow clock circuit and
Fast three part of clock circuit composition, there it is contemplated that the completely asynchronous situation of three clocks, therefore signal is from a clock zone
It is required for carrying out two-stage synchronization to another clock zone, and the reference value compared with the count value of slow clock counter is
The counting of test is interval, can be fixed value, or a programmable value.
The system clock circuit includes：
One four d flip-flop DFF4, its input end of clock CLK input system clock sys_clk, data output end Q are exported
System start-up test signal start_test (high level is effective).
One the 3rd two-stage synchronizer 2DFF3, its data output end Q are connected with the data input pin D of the 5th d type flip flop DFF5
Connect, and the data output end Q of the 3rd two-stage synchronizer 2DFF3 is connected with an input of door AND4 with the 4th through a reverser
Connect, its input end of clock CLK input system clock sys_clk.
One the 5th d type flip flop DFF5, its input end of clock CLK input system clock sys_clk, data output end Q and
Four are connected with another input of door AND4.
One the 4th is connected with the synchronous reset end R of the four d flip-flop DFF4, is used for door AND4, its outfan
The synchronized enabling signal start_fastcounter trailing edge of detection fast clock counter KJ, when detecting fast clock meter
During the synchronized enabling signal start_fastcounter trailing edge of number devices, its output signal makes the four d flip-flop
DFF4 resets, and carrys out synchronous scavenging system and starts test signal start_test.
The fast clock circuit includes：
The data input pin D of one second two-stage synchronizer 2DFF2, its data output end Q and 3d flip-flop DFF3 and
Three are connected with an input of door AND3, and its input end of clock CLK is input into fast clock signal fast_clk.
One 3d flip-flop DFF3, its input end of clock CLK are input into fast clock signal fast_clk；Its data output end Q
It is connected with another input of door AND3 with the 3rd through a reverser, and its data output end Q and fast clock counter KJ
Count enable input EN to be connected with the data input pin D of the 3rd two-stage synchronizer 2DFF3 of the system clock circuit, defeated
Go out synchronized enabling signal start_fastcounter of fast clock counter KJ.
One fast clock counter KJ, its input end of clock CLK are input into fast clock signal fast_clk, and terminal count output is exported
Fast clock count value fast_counter.
One the 3rd is connected with the synchronous reset end R of fast clock counter KJ with door AND3, its outfan.
The slow clock circuit includes：
One first two-stage synchronizer 2DFF1, its input end of clock CLK are input into slow clock signal slow_clk, and its data is defeated
Enter to hold D and the data output end Q of the four d flip-flop DFF of the system clock circuit to be connected, input system starts test letter
Number start_test；One input of its data output end Q and first and door AND1 and the data input of the first d type flip flop DFF1
End D is connected.
One first d type flip flop DFF1, its input end of clock CLK are input into slow clock signal slow_clk, its data output end Q
It is connected with an input of door AND2 with second, and the data output end Q of the first d type flip flop DFF1 is through a reverser and first
It is connected with another input of door AND1.
One slow clock counter MJ, its input end of clock CLK are input into slow clock signal slow_clk, and which counts and enables input
End EN is connected with the outfan of door AND2 with second, is input into enabling signal start_slow of slow clock counter
counter；
One first is connected with the synchronous reset end R of slow clock counter MJ with door AND1, its outfan.
One comparator BJ, its reverse input end are connected with the terminal count output of slow clock counter MJ, its forward direction input
End input reference.
One second is connected with the outfan of the comparator BJ with door AND2, its another input.
One second d type flip flop DFF2, its input end of clock CLK are input into slow clock signal slow_clk, its data input pin D
It is connected with the outfan of door AND2 with second；Second two-stage synchronizer of its data output end Q and the fast clock circuit
The data input pin D of 2DFF2 is connected, and exports the enabling signal synchronous without fast clock circuit of fast clock counter
slowclk_start_fastclk.
In conjunction with shown in Fig. 1,2, after system start-up test, slow clock circuit is first to system start-up test signal start_test
Its rising edge is synchronized and detects, after the rising edge of system start-up test signal start_test is detected, first and door
The output of AND1 makes slow clock counter MJ synchronously clear 0, then start slow clock counter MJ and slow clock signal slow_clk is entered
Row is counted.
Start in slow clock counter MJ and count and also do not count between expiry, it is not synchronized that slow clock circuit is produced
Enabling signal slowclk_start_fastclk deactivation fast clock counter KJ is counted.
Fast clock circuit is synchronized to not synchronized enabling signal slowclk_start_fastclk and is detected thereon
Edge is risen, when the rising edge of not synchronized enabling signal slowclk_start_Fastclk is detected, the 3rd with door AND3's
Output makes fast clock counter KJ synchronously clear 0, and the synchronized enabling signal in fast clock counter KJ for producing
Lower startup fast clock counter KJ of start_fastcounter effects is counted.
Slow clock counter MJ write all over after stop count, the second d type flip flop DFF2 output fast clock counter without
Synchronous enabling signal slowclk_start_fastclk of fast clock circuit can automatically become low level, thus fast clock count
Device KJ can also be automatically stopped counting.
System clock circuit is synchronized to enabling signal start_fastcounter of fast clock counter, and is detected
The enabling signal start_fastcounter trailing edge of fast clock counter, when the enabling signal for detecting fast clock counter
During start_fastcounter trailing edges, four d flip-flop DFF4 synchronous resets are made, carry out synchronous scavenging system and start test letter
Number start_test.System reads count value fast_counter of fast clock counter, according to the counting of fast clock counter
The frequency of value, the count value of slow clock counter and known test clock calculates the frequency of tested clock.
The counting of circuit shown in Fig. 1 is interval completely on the basis of the counting interval of slow clock, because speed clock is completely different
Step, in fact it could happen that be the startup and end of fast clock counter where error, but the error for introducing respectively is maximum less than one
Count value of the individual error for the fast clock cycle, therefore introducing altogether less than two fast clock cycle, i.e. fast clock counters
Fast_counter errors are less than 2.
First two-stage synchronizer, the second two-stage synchronizer and the 3rd two-stage synchronizer are connected by two d type flip flops
Composition, effect is that asynchronous signal is synchronized.
The present invention has been described in detail above by specific embodiment and embodiment, but these not constitute right
The restriction of the present invention.Without departing from the principles of the present invention, those skilled in the art can also make many deformations and change
Enter, these also should be regarded as protection scope of the present invention.
Claims (6)
1. a kind of clock rate testing circuit, it is characterised in that include：Slow clock circuit, fast clock circuit and system clock electricity
Road；
The system clock circuit includes：
One four d flip-flop, its data output end output system start test signal；
One the 3rd two-stage synchronizer, its data output end are connected with the data input pin of the 5th d type flip flop, and the data output
End is connected with an input of door with the 4th through a reverser；
One the 5th d type flip flop, its data output end are connected with another input of door with the 4th；
One the 4th and door, its outfan is connected with the synchronous reset end of the four d flip-flop, for detecting fast clock count
The synchronized enabling signal trailing edge of device, when the synchronized enabling signal trailing edge of fast clock counter is detected, its
Output signal makes the four d flip-flop reset, and synchronous scavenging system starts test signal；
The input end of clock input system clock signal of the four d flip-flop, the 3rd two-stage synchronizer and the 5th d type flip flop；
The fast clock circuit includes：
The data input pin of one second two-stage synchronizer, its data output end and 3d flip-flop and the 3rd with an input of door
End is connected；
One 3d flip-flop, its data output end are connected with another input of door with the 3rd through a reverser, and the data
The data input pin that outfan enables input and the 3rd two-stage synchronizer with the counting of fast clock counter is connected；Defeated
Go out the synchronized enabling signal of fast clock counter；
One fast clock counter, its terminal count output export fast clock count value；
One the 3rd and door, its outfan is connected with the synchronous reset end of the fast clock counter；
The input end of clock of second two-stage synchronizer, 3d flip-flop and fast clock counter is input into fast clock signal；
The slow clock circuit includes：
One first two-stage synchronizer, its data input pin are connected with the data output end of the four d flip-flop, input system
Start test signal；Its data output end is connected with the data input pin of an input and the first d type flip flop of door with first；
One first d type flip flop, its data output end are connected with an input of door with second, and the data output end is anti-through one
It is connected with another input of door to device with first；
One slow clock counter, its are counted enable input and are connected with the outfan of door with second, are input into slow clock counter
Enabling signal；
One first and door, its outfan is connected with the synchronous reset end of the slow clock counter；
One comparator, its reverse input end are connected with the terminal count output of slow clock counter, its positive input input ginseng
Examine value；
One second and door, its another input is connected with the outfan of the comparator；
One second d type flip flop, its data input pin are connected with the outfan of door with second；Its data output end and described second
The data input pin of two-stage synchronizer is connected, and exports the enabling signal synchronous without fast clock circuit of fast clock counter；
The input end of clock input of first two-stage synchronizer, the first d type flip flop, slow clock counter and the second d type flip flop
Slow clock signal；
First two-stage synchronizer, the second two-stage synchronizer and the 3rd two-stage synchronizer are composed in series by two d type flip flops,
For synchronizing to asynchronous signal.
2. clock rate testing circuit as claimed in claim 1, it is characterised in that：After system start-up test, the slow clock
Circuit is first synchronized to system start-up test signal and detects its rising edge, when the rising for detecting system start-up test signal
After, described first makes slow clock counter synchronous clear 0 with the output of door, then start slow clock counter and slow clock signal is entered
Row is counted；
Start in the slow clock counter and count and do not count between expiry, slow clock circuit produce fast clock counter without fast
The synchronous enabling signal of clock circuit, starts fast clock counter and is counted.
3. clock rate testing circuit as claimed in claim 2, it is characterised in that：The fast clock circuit is to fast clock count
The not synchronized enabling signal of device is synchronized and detects its rising edge, when detecting the not synchronized enabling signal
During rising edge, the 3rd makes fast clock counter synchronous clear 0, and the synchronized startup in fast clock counter with the output of door
Start fast clock counter to be counted under signal function.
4. clock rate testing circuit as claimed in claim 1 or 2, it is characterised in that：Slow clock counter stops after writing all over
Count, then the enabling signal synchronous without fast clock circuit of fast clock counter automatically becomes low level, fast clock counter
It is automatically stopped counting.
5. clock rate testing circuit as claimed in claim 1, it is characterised in that：System clock circuit is to fast clock counter
Synchronized enabling signal synchronize, and detect the synchronized enabling signal trailing edge, when detecting the trailing edge
When, four d flip-flop synchronous reset is made, the system start-up test signal is synchronously removed.
6. clock rate testing circuit as claimed in claim 1, it is characterised in that：System reads the counting of fast clock counter
The frequency of value, the count value of count value, slow clock counter according to fast clock counter and known test clock calculates quilt
The frequency of test clock.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210004410.4A CN103197139B (en) | 2012-01-06 | 2012-01-06 | Clock rate testing circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210004410.4A CN103197139B (en) | 2012-01-06 | 2012-01-06 | Clock rate testing circuit |
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| CN103197139A CN103197139A (en) | 2013-07-10 |
| CN103197139B true CN103197139B (en) | 2017-03-15 |
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| CN201210004410.4A Active CN103197139B (en) | 2012-01-06 | 2012-01-06 | Clock rate testing circuit |
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Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103698603B (en) * | 2013-12-27 | 2017-03-15 | 深圳芯邦科技股份有限公司 | A kind of chip and its clock test methodology and chip clock test system |
| CN104931779A (en) * | 2015-05-08 | 2015-09-23 | 中国电子科技集团公司第四十一研究所 | Single-channel realized continuous frequency measure method |
| CN104931778B (en) * | 2015-06-09 | 2017-09-12 | 浙江大学 | A kind of clock frequency detection circuit |
| CN107290240B (en) * | 2017-07-27 | 2019-12-10 | 江苏集萃有机光电技术研究所有限公司 | Quartz crystal microbalance and detection method |
| CN109976955B (en) * | 2017-12-28 | 2023-02-21 | 上海坚芯电子科技有限公司 | Clock frequency test circuit and measuring and calculating method |
| CN111026232A (en) * | 2019-11-08 | 2020-04-17 | 深圳市汇顶科技股份有限公司 | Clock calibration method, chip and electronic equipment |
| CN113129991B (en) * | 2021-04-01 | 2023-04-07 | 深圳市纽创信安科技开发有限公司 | Chip safety protection method and circuit for ROMBIST test |
| CN114461009B (en) * | 2022-01-07 | 2024-04-26 | 山东云海国创云计算装备产业创新中心有限公司 | Method for automatically identifying clock domain conversion by using FPGA single bit signal |
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| JPH10190568A (en) * | 1996-12-27 | 1998-07-21 | Matsushita Electric Ind Co Ltd | Radio receiving device |
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| US5742650A (en) * | 1994-02-04 | 1998-04-21 | Motorola, Inc. | Power reduction method and apparatus for phase-locked loop based clocks in a data processing system |
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| CN1767390A (en) * | 2004-10-27 | 2006-05-03 | 中兴通讯股份有限公司 | Multipath clock detecting device |
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